Amplitude and phase adjustable carrier wave generating apparatus and method

Abstract

This invention discloses an amplitude-phase adjustable carrier generation device and method, belonging to the field of precision measurement and signal synthesis. The phase accumulator of this invention incorporates a phase adjuster. The phase adjuster counts the system clock, and when a set count value C is reached, it outputs a phase adjustment value S. At this time, the value of the phase register is simultaneously added to the frequency control word FCW and the phase adjustment value S. Subsequently, the phase register overflows, is cleared to zero, and accumulation restarts. The phase adjuster supplements the decimal part discarded during the rounding of the frequency control word FCW, which helps improve the frequency stability of the carrier. The CORDIC calculator of this invention employs a parallel interpolation structure, which can use n CORDIC cores to calculate the sine values ​​of n consecutive phases in parallel. The interval between two adjacent phases is the frequency control word FCW. The interpolation unit arranges the n data streams and outputs them serially. The parallel interpolation structure improves the speed and accuracy of CORDIC calculation through parallel computation, which can greatly reduce phase truncation errors and help reduce carrier spurious emissions.

Description

Technical Field

[0001] This invention belongs to the field of precision measurement and signal synthesis technology, and more specifically, relates to an amplitude-phase adjustable carrier generation device and method. Background Technology

[0002] In recent years, with the in-depth research on space gravitational wave detection, the performance requirements for related instruments have become increasingly stringent. Space gravitational waves are a novel astronomical observation medium, opening up new avenues for human exploration of space. Conducting space gravitational wave detection requires the construction of high-performance space inertial sensors. As one of the fundamental components of a space inertial sensor, the high-precision capacitive displacement sensing circuit's overall performance largely depends on the stability of its front-end sinusoidal carrier signal. In high-precision capacitive displacement sensors, the amplitude and phase of the four carrier signals need to be continuously corrected according to actual conditions to achieve stable amplitude and phase carrier output, reducing the impact of mutual coupling between channels on measurement accuracy.

[0003] like Figure 1 As shown, when the capacitive displacement sensor is working, the carrier signal V p The differential capacitance signal ΔC (ΔC = C1 - C2) is modulated onto the differential transformer bridge circuit by being injected onto the plates surrounding the inspection quality TM. The demodulation circuit extracts the differential capacitance signal in voltage form and obtains the displacement information of the inspection quality TM through the data acquisition system. The carrier generation unit provides the system with four amplitude- and phase-adjustable sinusoidal carrier signals, and the carrier injection unit injects the carrier signal onto the capacitor plates, such as... Figure 2 As shown.

[0004] Currently, the main methods for generating carrier waves include direct analog frequency synthesis, phase-locked loop (PLL) frequency synthesis, and direct digital frequency synthesis. Direct analog frequency synthesis suffers from drawbacks such as large size, complex structure, and high spurious emissions. PLL frequency synthesis offers good frequency stability, but its frequency resolution is low, making it suitable for generating high-frequency signals but unsuitable for generating 100kHz low-frequency sinusoidal carrier waves. Direct digital frequency synthesis offers advantages such as low phase noise and high frequency resolution, making it suitable for generating low-frequency carrier waves; however, the direct digital synthesis (DDS) method has certain deficiencies in frequency stability. None of the above methods can precisely control the amplitude and phase of the carrier signal, failing to meet the amplitude and phase correction requirements of high-precision capacitive displacement sensors in practical engineering. Therefore, a carrier wave generation method with an adjustable amplitude and phase and a communication interface is needed. Summary of the Invention

[0005] In view of the above-mentioned defects or improvement needs of the prior art, the present invention provides an amplitude-phase adjustable carrier generation device and method, the purpose of which is to accurately control the amplitude and phase of the carrier signal and improve the frequency stability of the carrier.

[0006] To achieve the above objectives, according to one aspect of the present invention, an amplitude-phase adjustable carrier generation device is provided, comprising: a DDS controller; the DDS controller includes a phase accumulator, a phase shifter, a RAM waveform storage table, a CORDIC calculator, a MUX multiplexer, and an attenuator; wherein, the phase accumulator includes a phase adjuster, an adder, and a phase register; the phase adjuster counts the system clock, and when a set count value C is reached, it outputs a phase adjustment value S; the adder superimposes the frequency control word FCW and the phase adjustment value S; the value of the phase register is accumulated with the output value of the adder, then overflows, is cleared to zero, and accumulation restarts;

[0007] The phase shifter adjusts the phase value and then sends it to the RAM waveform storage table or the CORDIC calculator. The CORDIC calculator uses a parallel interpolation structure and can use n CORDIC cores to calculate the sine values ​​of n consecutive phases in parallel. The spacing between two adjacent phases is the frequency control word FCW. The interpolation unit arranges the n data channels and outputs them serially.

[0008] The RAM waveform storage table and the CORDIC calculator obtain the carrier amplitude signal based on the phase value;

[0009] The MUX multiplexer selects one carrier signal and sends it to the attenuator.

[0010] After the attenuator adjusts the amplitude of the carrier signal, it finally outputs the carrier data stream.

[0011] Furthermore, the device also includes an FPGA platform and four DACs; the FPGA platform has a built-in SoC system; the SoC system includes an ARM Cortex-M0 and two UARTs; the DDS controller functions as a peripheral of the SoC system.

[0012] The UART0 interface is connected to an external carrier injection unit. The carrier injection unit sends amplitude and phase feedback information to UART0 in a fixed communication frame format, which is then parsed by the ARM program to obtain the carrier amplitude and phase adjustment values.

[0013] The UART1 interface connects to an external host computer with a display interface. Users can set the amplitude, phase and frequency of the carrier wave through the host computer and send the setting information to the SoC system through UART1.

[0014] The DDS controller generates four carrier data streams based on the set carrier parameters, and outputs them to four DACs to obtain carrier signals.

[0015] Furthermore, the SoC system also includes an LVDS communication interface for communicating with other FPGA devices.

[0016] Furthermore, the RAM waveform storage table and the CORDIC calculator are connected via a single-pole double-throw switch.

[0017] Furthermore, the SoC system bus adopts the AHB and APB bus protocols.

[0018] Furthermore, the AHB bus includes two master devices and five slave devices. The master devices are the Cortex-M0 core and the DMA controller, respectively, and the slave devices are the ROM, RAM, TIMER timer, GPIO and APB bus bridge, respectively. The APB bus is connected to seven slave devices, namely UART0, UART1, LVDS and four DDS controllers.

[0019] The present invention also provides a method for generating an amplitude-phase adjustable carrier based on the above-mentioned amplitude-phase adjustable carrier generating device, comprising:

[0020] S1. Determine the required carrier waveform, and use the host computer to send the waveform data to the SoC system via UART1. The DMA controller reads the data received from UART1 and then writes it into the RAM waveform storage table in the DDS controller; the ARM program parses the frame to obtain the carrier frequency f. out Phase P out and amplitude A out parameter;

[0021] S2. If the output is a sinusoidal signal, use the CORDIC calculator to calculate the sinusoidal amplitude; if the output is another periodic signal, use the RAM waveform storage table to find the carrier amplitude; based on the required carrier signal parameters, the ARM calculates the frequency control word FCW, count value C, adjustment value S, phase shift value ΔP, and attenuation value.

[0022] In this calculation, the results of FCW and C are both rounded down; FCW = f out *2 N / f clk f out Where N is the carrier signal frequency, N is the bit width of the phase register, and f clk The operating clock frequency of the DDS controller; C = 2 N / FCW; S=2 N %FCW, % represents the modulo operation; △P = P out *2 N / 360; P out The set phase value;

[0023] S3. If you choose to use a CORDIC calculator, then modify the frequency control word of the phase accumulator to 2*FCW, and modify the operating clock frequency of the phase accumulator to f. clk / 2; If you choose to use the RAM waveform lookup table, there is no need to modify the relevant parameters;

[0024] S4.ARM writes the calculated control parameters into the register of the DDS controller, completing the initialization operation of the DDS controller;

[0025] The S54 DDS controller outputs a continuous data stream to four DACs, converting digital signals into analog signals and generating carrier signals.

[0026] Overall, the above-described technical solutions conceived by this invention can achieve the following beneficial effects compared with the prior art.

[0027] (1) An additional phase adjuster is added inside the phase accumulator of the present invention. The phase adjuster counts the system clock, and when the set count value C is reached, it outputs the phase adjustment value S. At this time, the value of the phase register is simultaneously added to the frequency control word FCW and the phase adjustment value S. Then the phase register overflows, is cleared to zero, and starts accumulating again. The phase adjuster supplements the decimal part discarded when the frequency control word FCW is rounded down, which is beneficial to improving the frequency stability of the carrier.

[0028] (2) The CORDIC calculator of the present invention adopts a parallel interpolation structure, which can use n CORDIC cores to calculate the sine values ​​of n consecutive phases in parallel. The interval between two adjacent phases is the frequency control word FCW. The interpolation unit arranges the n data channels and outputs them serially. The parallel interpolation structure improves the CORDIC calculation speed and accuracy through parallel operation, which can greatly reduce the phase truncation error and help reduce carrier spurious.

[0029] (3) The SoC-based design enables the carrier generation unit to have better flexibility and scalability, and the overall structure is simpler. The system operation status can be controlled by programming, which is beneficial for technical personnel to develop and maintain. Attached Figure Description

[0030] Figure 1 This is the main circuit schematic of a capacitive displacement sensor;

[0031] Figure 2 This is a schematic diagram of carrier generation and injection.

[0032] Figure 3 This is a hardware block diagram of the carrier generation method of the present invention;

[0033] Figure 4 This is a bus architecture diagram of the SoC design for this invention;

[0034] Figure 5 This is a diagram of the internal structure of the DDS controller of the present invention. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0036] This invention provides an amplitude-phase adjustable carrier generation device based on SoC design. The hardware structure of the device is as follows: Figure 3 As shown, it mainly includes an FPGA platform and four DACs. The FPGA platform houses a SoC system with an ARM Cortex-M0 core, and also includes two UARTs and one LVDS communication interface. The DDS controller functions as a peripheral of the SoC system.

[0037] The UART0 interface is connected to an external carrier injection unit. The carrier injection unit sends amplitude and phase feedback information to UART0 in a fixed communication frame format, which is then parsed by the ARM program to obtain the carrier amplitude and phase adjustment values.

[0038] The UART1 interface connects to an external host computer with a display interface. The host computer can set the amplitude, phase, and frequency of the carrier wave and send the setting information to the SoC system via UART1.

[0039] The LVDS interface is a reserved communication interface used to communicate with other FPGA devices.

[0040] The DDS controller generates four carrier data streams based on the set carrier parameters, and outputs them to four DACs to obtain carrier signals. Simultaneously, various settings can be configured through the ARM program to configure the registers in the DDS controller.

[0041] The SoC system bus design of this invention is based on the AHB and APB bus protocols, and the architecture is as follows: Figure 4 As shown. The AHB bus includes two master devices and five slave devices. The master devices are the Cortex-M0 core and the DMA controller, while the slave devices are ROM, RAM, TIMER, GPIO, and the APB bus bridge. The APB bus has seven slave devices connected: UART0, UART1, LVDS, and four DDS controllers. For the Cortex-M0 core, the accessible memory address range is 0x00000000 to 0xFFFFFFFF. To determine which peripheral the processor needs to access, a memory region is allocated for each peripheral. The AHB bus decodes this region to ultimately select the desired peripheral. Figure 4 The memory addresses allocated to each peripheral are indicated in the code.

[0042] The DMA controller enables high-speed data read and write operations. If it is necessary to update the waveform data controlled by the DDS, the DMA controller can be used to read the waveform data received by the UART and then write the data into the RAM waveform storage table.

[0043] ROM and RAM store user program instructions and variables respectively, and are implemented using the FPGA's BRAM resources;

[0044] The TIMER generates a timed trigger signal to trigger critical events; GPIO generates level signals to control peripheral chips.

[0045] The structure of the DDS controller is as follows: Figure 5 As shown, this includes a phase accumulator, a phase shifter, a RAM waveform storage table, a CORDIC calculator, a MUX multiplexer, and an attenuator. The phase accumulator accumulates the frequency control word (FCW) and sends the accumulated result to the phase shifter. The phase shifter adjusts the phase value and then sends it to either the RAM waveform storage table or the CORDIC calculator, which is selected by a single-pole double-throw switch. The RAM waveform storage table and the CORDIC calculator obtain the carrier amplitude signal based on the phase value. The MUX multiplexer selects one carrier signal and sends it to the attenuator. After the attenuator adjusts the amplitude of the carrier signal, it finally outputs the carrier data stream to the DAC.

[0046] In the existing DDS architecture, the phase accumulator includes an adder and a phase register. The phase accumulator has N bits, the frequency control word is FCW, and each reference clock f... clk When the FCW arrives, the value of the phase register will be added until the value of the phase register is greater than or equal to 2. N Overflow occurs, at which point the DDS outputs a sinusoidal signal for one cycle, with the frequency f of the output sinusoidal signal. out =FCW*f clk / 2 N In an FPGA, the frequency control word (FCW) must be a positive integer, and less than 2. N The frequency f of the sinusoidal signal output using the DDS method is then... out There will be certain limitations:

[0047]

[0048] The frequency control word FCW can be expressed as: FCW = f out *2 N / f clk If FCW is a positive integer, then the frequency f of the output sine wave signal is... out With reference clock f clk The following relationship must be satisfied:

[0049]

[0050] In formula (2), x is a positive integer and must satisfy x≤N. In this case, the frequency control word FCW can be expressed as:

[0051] FCW=2 N-x (x∈{1,2,3,……,2 N-1}) (3)

[0052] Based on the above analysis, when actually using the DDS method to generate a carrier, two cases need to be discussed:

[0053] 1) When the reference clock frequency f clk and the output sine wave frequency f out It satisfies formula (2), and the frequency control word FCW satisfies formula (3). For example, N = 32, f clk =128MHz, f out =1MHz, at which point the frequency control word is a positive integer FCW = 33554432. In this case, after the phase register overflows once, the phase can return to its initial value in the next cycle, and the number of all sampling points in each cycle will coincide. The sinusoidal carrier frequency f output by the DDS... out It is highly accurate and stable.

[0054] 2) When the reference clock frequency f clk and the output sine wave frequency f out Formula (2) is not satisfied. In this case, the frequency control word FCW needs to retain the decimal part, and the value of the phase register can only return to the initial value in the next loop after overflow. However, the frequency control word FCW must be a positive integer due to its own definition. For example, N=32, f clk =100MHz, f out =1MHz, at this time the frequency control word is FCW = 42949672 (the calculated result of the frequency control word FCW is 42949672.96, which is rounded to get 42949672). The frequency of the generated carrier signal is approximately 0.99999997765MHz. Under these circumstances, it is impossible to generate an accurate and stable 1MHz signal. The initial values ​​of the phase registers in two adjacent cycles are different, and the number of all sampling points in each cycle cannot coincide, which leads to poor frequency stability of the generated carrier.

[0055] The phase accumulator of this invention includes an additional phase adjuster. This phase adjuster counts the system clock, and when the count reaches a set value C, it outputs a phase adjustment value S. At this point, the value of the phase register is simultaneously increased by the frequency control word FCW and the phase adjustment value S. The phase register then overflows, is cleared, and the accumulation process restarts. The phase adjuster compensates for the decimal part discarded during the rounding of the frequency control word FCW, which helps improve the frequency stability of the carrier.

[0056] In existing DDS systems, due to storage resource limitations, the output value of the phase accumulator typically discards the lower B bits and uses the higher A bits (A = N – B) as the address for ROM lookup table addressing. For example, if the phase accumulator has N = 32 bits, and all N bits are used for ROM addressing, then the length of the ROM table would need to reach 2^32 bits. 32 This is obviously impossible to implement in an FPGA. Therefore, phase truncation is required, taking the high A bits of the phase accumulator output and discarding the low B bits.

[0057] The phase truncation error is expressed as:

[0058]

[0059] In the formula, F[] represents the integer part, mod() is the modulo function, and the modulo function represents the amount to be discarded. The result is equal to n*FCW divided by 2. B The remainder. The expression for the stepped wave after phase truncation is:

[0060]

[0061] Then perform a Fourier transform on equation (5) to obtain S p The spectral distribution characteristics of (t) are as follows:

[0062] f=±nf clk ±f0±mf k (6)

[0063] Where f k =mod(FCW,2) B )f c / 2 B The ratio of the dominant frequency amplitude to the maximum spurious amplitude is:

[0064]

[0065] According to equation (7), for every bit decrease in the phase cutoff number B, the stray power decreases by 6.02 dB. Therefore, it is necessary to increase the ROM table storage space or improve the DDS phase-to-amplitude conversion method.

[0066] The CORDIC calculator of this invention employs a parallel interpolation structure, which can use n CORDIC cores to calculate the sine values ​​of n consecutive phases in parallel. The interval between two adjacent phases is the frequency control word (FCW). The interpolation unit arranges the n data streams and outputs them serially. The parallel interpolation structure improves the speed and accuracy of CORDIC calculations through parallel computation, which can greatly reduce phase truncation errors and is beneficial for reducing carrier spurious emissions.

[0067] The workflow of this invention is described below. This embodiment mainly includes the following steps:

[0068] Step 1: Determine the required carrier waveform. Use the host computer to send the waveform data to this SoC system via UART1. The DMA controller reads the data received from UART1 and then writes it into the RAM waveform storage table in the DDS controller. The ARM program parses the frame to obtain the carrier frequency f. out Phase P out and amplitude A out parameter.

[0069] Step 2: The carrier signal is a sinusoidal signal by default, but it can also be set to other periodic signals. If the output is a sinusoidal signal, the amplitude can be calculated using the CORDIC calculator; if the output is another periodic signal, the carrier amplitude can be found using the RAM waveform storage table. The ARM processor selects between the RAM waveform storage table and the CORDIC calculator by setting the MUX multiplexer. Based on the required carrier signal parameters, the ARM processor calculates control parameters such as the frequency control word FCW, count value C, adjustment value S, phase shift value, and attenuation value. The specific process is as follows:

[0070] 1) Calculate the frequency control word FCW according to the formula: FCW = f out *2 N / f clk , where f out Where N is the carrier signal frequency, N is the bit width of the phase register, and f clk This is the operating clock frequency of the DDS controller. The calculated FCW needs to be rounded down, discarding all decimal parts.

[0071] 2) Calculate the count value C of the phase adjuster. According to the formula: C = 2 N / FCW, the calculation result is also rounded down. The count value C indicates that the phase accumulator needs to accumulate C times within one carrier cycle.

[0072] 3) Calculate the adjustment value S of the phase adjuster, according to the formula: S = 2 N %FCW, where % represents the remainder operation, and the calculated remainder is the adjustment value S, which represents the accumulated remainder of the phase accumulator in one cycle.

[0073] 4) Calculate the phase shift value ΔP, according to the formula: ΔP = P out *2 N / 360, where P out The initial phase of all four carrier waves is 180°, and the phase adjustment accuracy is 1. o The phase shift value ΔP is stored in the phase shifter. The output value of the phase accumulator is increased by the phase shift value ΔP after passing through the phase shifter, and then the phase-amplitude conversion is performed.

[0074] 5) According to the set amplitude parameter A out The attenuation parameters of the attenuator are calculated, and the amplitude of the carrier signal is adjusted by the attenuator.

[0075] Step 3: If you choose to use the CORDIC calculator, then modify the frequency control word of the phase accumulator to 2*FCW, and modify the operating clock frequency of the phase accumulator to f. clk The value is / 2, which is due to the parallel interpolation structure of the CORDIC calculator. If you choose to use a RAM waveform lookup table, no modification to the relevant parameters is required.

[0076] Step 4: The ARM writes the control parameters calculated above into the register of the DDS controller, thus completing the initialization operation of the DDS controller.

[0077] Step 5: The four DDS controllers output a continuous data stream to the four DACs, realizing the conversion of digital signals into analog signals for output, thus completing the generation of the carrier signal.

[0078] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An amplitude and phase adjustable carrier generation device, characterized by comprising: include: DDS controller; The DDS controller includes a phase accumulator, a phase shifter, a RAM waveform storage table, a CORDIC calculator, a MUX multiplexer, and an attenuator. The phase accumulator includes a phase adjuster, an adder, and a phase register. The phase adjuster counts the system clock and outputs a phase adjustment value S when the set count value C is reached. The adder superimposes the frequency control word FCW and the phase adjustment value S. The value of the phase register is added to the output value of the adder, then overflows, is cleared, and the accumulation restarts. The phase shifter adjusts the phase value and then sends it to the RAM waveform storage table or the CORDIC calculator. The CORDIC calculator uses a parallel interpolation structure and can use n CORDIC cores to calculate the sine values ​​of n consecutive phases in parallel. The spacing between two adjacent phases is the frequency control word FCW. The interpolation unit arranges the n data channels and outputs them serially. The RAM waveform storage table and the CORDIC calculator obtain the carrier amplitude signal based on the phase value; The MUX multiplexer selects one carrier signal and sends it to the attenuator. After the attenuator adjusts the amplitude of the carrier signal, it finally outputs the carrier data stream. The carrier signal is generated based on the following steps: S1. Determine the required carrier waveform, and use the host computer to send the waveform data to the SoC system via UART1. The DMA controller reads the data received from UART1 and then writes it into the RAM waveform storage table in the DDS controller; the ARM program parses the frame to obtain the carrier frequency f. out Phase P out and amplitude A out parameter; S2. If the output is a sine wave signal, use the CORDIC calculator to calculate the sine wave amplitude; if the output is another periodic signal, use the RAM waveform storage table to find the carrier amplitude; based on the required carrier signal parameters, the ARM calculates the frequency control word FCW, count value C, adjustment value S, phase shift value ΔP, and attenuation value. In this calculation, both FCW and C are rounded down to the nearest integer; FCW = f out * 2 N / f clk f out Where N is the carrier signal frequency, N is the bit width of the phase register, and f clk Where C is the operating clock frequency of the DDS controller; C = 2 N / FCW; S = 2 N %FCW, % indicates the modulo operation; △P = P out * 2 N / 360; P out The set phase value; S3. If you choose to use a CORDIC calculator, then modify the frequency control word of the phase accumulator to 2*FCW, and modify the operating clock frequency of the phase accumulator to f. clk / 2; If you choose to use the RAM waveform lookup table, there is no need to modify the relevant parameters; S4.ARM writes the calculated control parameters into the register of the DDS controller, completing the initialization operation of the DDS controller; The S54 DDS controller outputs a continuous data stream to four DACs, converting digital signals into analog signals and generating carrier signals.

2. A phase and amplitude adjustable carrier generation device according to claim 1, characterized in that The device also includes an FPGA platform and four DACs; the FPGA platform has a built-in SoC system; the SoC system includes an ARM Cortex-M0 and two UARTs; the DDS controller functions as a peripheral of the SoC system. The UART0 interface is connected to an external carrier injection unit. The carrier injection unit sends amplitude and phase feedback information to UART0 in a fixed communication frame format, which is then parsed by the ARM program to obtain the carrier amplitude and phase adjustment values. The UART1 interface connects to an external host computer with a display interface. Users can set the amplitude, phase and frequency of the carrier wave through the host computer and send the setting information to the SoC system through UART1. The DDS controller generates four carrier data streams based on the set carrier parameters, and outputs them to four DACs to obtain carrier signals.

3. A phase and amplitude adjustable carrier generation device according to claim 2, characterized in that The SoC system also includes an LVDS communication interface for communicating with other FPGA devices.

4. A phase and amplitude adjustable carrier generation device according to claim 2, characterized in that The RAM waveform storage table and the CORDIC calculator are connected via a single-pole double-throw switch.

5. The amplitude-phase adjustable carrier generation device according to claim 2, characterized in that, The SoC system bus adopts the AHB and APB bus protocols.

6. A phase and amplitude adjustable carrier generation device according to claim 5, characterized in that AHB bus includes two master devices and five slave devices, the master devices are Cortex-M0 core and DMA controller, and the slave devices are ROM, RAM, TIMER timer, GPIO and APB bus bridge; APB bus is mounted with seven slave devices, which are UART0, UART1, LVDS and four DDS controllers.

Images