A DBB bus to TileLink bus conversion system, method, and hardware device

Abstract

The application discloses a DBB bus to TileLink bus conversion system, method and hardware equipment, and relates to the technical field of bus interface conversion. The conversion system comprises a DBBToAXI4 module, an AXI4Buffer module, an AXI4UserYanker module, an AXI4ToTL module and a TLFragmenter module, and the modules are sequentially connected. The DBBToAXI4 module is used for mapping the signals of the DBB bus to the AXI4 bus, comprising assigning the request signal combination logic of the DBB to the corresponding AXI4 signal, and performing the assignment operation on the arsize signal or the awsize signal. The AXI4Buffer module is used for buffering the response message on the AXI4 bus. The AXI4UserYanker module is used for converting the AXI4 bus with the user field into the AXI4 bus without the user field. The AXI4ToTL module is used for matching and mapping the information on the AXI4 bus to the TileLink bus. The TLFragmenter module is used for cutting the larger transaction into multiple smaller transactions, so as to reduce the maximum logical transmission of the TileLink. The application realizes the conversion from the DBB bus to the TileLink bus, and is particularly suitable for the application scene of the module adopting the DBB interface as the data interface in the TileLink bus architecture.

Description

Technical Field

[0001] This invention relates to the field of bus interface conversion technology, and more specifically, to a DBB bus to TileLink bus conversion system, method and hardware device. Background Technology

[0002] NVIDIA Deep Learning Accelerator (NVDLA) is a free and open architecture that facilitates standard approaches to designing deep learning inference accelerators. (See [link to relevant documentation]). Figure 1 It adopts a modular architecture that is scalable and highly configurable, designed to simplify integration and portability, and supports a wide range of performance levels and easily scalable applications, from smaller, cost-sensitive Internet of Things (IoT) devices to performance-oriented IoT devices.

[0003] The DBB (Data Backbone) bus interface is the data interface for the NVDLA module. (See also...) Figure 2 The DBB bus is a high-performance, high-bandwidth, low-latency on-chip bus. NVDLA reads and writes data in memory through the DBB bus. The DBB interface protocol defines the AW (Write request) channel, W (Write data) channel, B (Write response) channel, AR (Read request) channel, and R (Read data) channel, similar to the AXI4 interface protocol, but not entirely the same.

[0004] The TileLink bus, designed in 2014 by UC Berkeley and SiFive, is an alternative bus for RISC-V instruction set CPUs that provides coherent memory-mapped access to memory and other slave devices for multiple master devices. Supporting various communication agents, TileLink is designed for use in System-on-Chip (SoC) applications to connect general-purpose multiprocessors, coprocessors, accelerators, DMA engines, and simple or complex devices. It uses fast, scalable interconnects to provide low-latency and high-throughput data transfer.

[0005] A TileLink network consists of a link between a master interface and a slave interface. Within each network link, the TileLink protocol defines logically independent channels through which brokers can send messages. These channels are directional, as each channel transmits messages from the master interface to the slave interface, or vice versa. Most channels include transaction control signals and a bus for exchanging data. To perform operations on shared memory, the master device sends a request message to the slave device on the request channel and waits for an acknowledgment message on the response channel.

[0006] In the existing technology, there is no relevant method for converting the DBB bus to the TileLink bus, which is not conducive to the application of NVDLA within the TileLink bus architecture and affects the widespread application of NVIDIA deep learning accelerators in the future. Summary of the Invention

[0007] To overcome the shortcomings of the prior art in that NVDLA cannot be applied within the TileLink bus architecture, this invention provides a DBB bus to TileLink bus conversion system, method, and hardware device.

[0008] To solve the above-mentioned technical problems, the technical solution of the present invention is as follows:

[0009] In the first aspect, a DBB bus to TileLink bus conversion system includes a DBBToAXI4 module, as well as an AXI4Buffer module, an AXI4UserYanker module, an AXI4ToTL module and a TLFragmenter module, which are connected in sequence.

[0010] The DBBToAXI4 module maps DBB bus signals to the AXI4 bus, including assigning the DBB request signal combination logic to the corresponding AXI4 signals and performing value assignment operations on the arsize or awsize signals; the AXI4Buffer module buffers response messages on the AXI4 bus; the AXI4UserYanker module converts an AXI4 bus with a user field into an AXI4 bus without a user field; the AXI4ToTL module maps information on the AXI4 bus to the TileLink bus; and the TLFragmenter module divides larger transactions into multiple smaller transactions to reduce the maximum logical transmission of TileLink.

[0011] In this technical solution, the DBB bus is first mapped to the AXI4 bus through the DBBToAXI4 module, and then the AXI4 bus is mapped to the TileLink bus through the AXI4ToTL module. This ultimately realizes the conversion from DBB bus to TileLink bus, which helps to enable the use of hardware modules that use the DBB interface as the data interface within the TileLink bus architecture.

[0012] Secondly, a method for converting a DBB bus to a TileLink bus, using a DBB bus to TileLink bus conversion system proposed in the first aspect, includes:

[0013] The Slave initiates a request message on the DBB bus, and the DBBToAXI4 module maps the request message from the DBB bus to the AXI4 bus; wherein, the request message is a read data request signal or a write data request signal.

[0014] The AXI4Buffer module buffers response messages on the AXI4 bus;

[0015] The AXI4UserYanker module converts an AXI4 bus with a user field into an AXI4 bus without a user field.

[0016] The AXI4ToTL module maps response message matching on the AXI4 bus to the TileLink bus.

[0017] The TLFragmenter module splits a large TileLink bus request into multiple smaller TileLink bus requests;

[0018] The Master responds to requests on the TileLink bus.

[0019] Thirdly, a hardware device includes an NVDLA module, the NVDLA module having a DBB interface, the DBB interface being connected to a DBB bus to TileLink bus conversion system proposed in the first aspect, for data conversion with an external TileLink interface.

[0020] Compared with the prior art, the beneficial effects of the technical solution of the present invention are:

[0021] This invention addresses the difference in read / write channels between the DBB bus and the TileLink bus. To achieve data conversion from DBB to TileLink, a DBB-to-TileLink bus conversion system is designed, including a DBBToAXI4 module, as well as AXI4Buffer, AXI4UserYanker, AXI4ToTL, and TLFragmenter modules. By mapping the DBB bus to the AXI4 bus and then to the TileLink bus, the DBB-to-TileLink bus conversion is achieved. This system is particularly suitable for applications using DBB interfaces as data interfaces within the TileLink bus architecture, such as NVDLA. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the NVDLA system architecture;

[0023] Figure 2 This is a schematic diagram of the internal architecture of NVDLA;

[0024] Figure 3 This is a schematic diagram of a TileLink network;

[0025] Figure 4 This is a system architecture diagram of the DBB bus to TileLink bus conversion in Example 1;

[0026] Figure 5 This is a data flow diagram between the DBB bus and the AXI4 bus in Example 1;

[0027] Figure 6 This is a flowchart of the DBB bus to TileLink bus conversion method in Example 2;

[0028] Figure 7 This is a data flow diagram between the DBB bus and the TileLink bus in Example 2;

[0029] Figure 8 This is a flowchart of the signal operation of the conversion method described in Example 2;

[0030] Figure 9 The waveform diagram is from the simulation experiment in Example 3. Detailed Implementation

[0031] The accompanying drawings are for illustrative purposes only and should not be construed as limiting the scope of this patent.

[0032] To better illustrate this embodiment, some parts in the accompanying drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions;

[0033] It will be understood by those skilled in the art that certain well-known structures and their descriptions may be omitted in the accompanying drawings.

[0034] To facilitate understanding and implementation, the DBB bus and TileLink bus in this invention will be described in detail.

[0035] I. DBB Bus

[0036] The DBB interface is similar to the AXI4 interface protocol, but not entirely the same. (See [link / reference]). Figure 5 It includes five channels: AW (Writer request) channel, W (Write data) channel, B (Write response) channel, AR (Read request) channel, and R (Read data) channel. The data fields for each channel are shown in Tables 1-5 below:

[0037] Table 1 AW Channel Fields

[0038]

[0039] Table 2 W Channel Fields

[0040]

[0041] Table 3 B Channel Fields

[0042]

[0043] Table 4 AR Channel Fields

[0044]

[0045] Table 5 R Channel Fields

[0046]

[0047] II. TileLink Bus

[0048] The TileLink network can support multiple communication agents, each supporting different subsets of protocols. The TileLink specification includes three Conformity levels for additional agents: TL-UL (TileLink Uncached Lightweight), TL-UH (TileLink Uncached Heavyweight), and TL-C (TileLink Cached).

[0049] TileLink includes five channels: A, B, C, D, and E. (See attached document.) Figure 3 The functions of each channel are as follows:

[0050] Channel A: Transmits requests to perform operations, access, or cache data on a specified address range.

[0051] Channel D: Sends a data response or confirmation message to the original requester.

[0052] The highest protocol conformance level (TL-C) adds three additional channels that provide the ability to manage permissions for cached data blocks:

[0053] Channel B: Sends a request to perform an operation at the address cached by the master proxy, to access or write back the cached data.

[0054] Channel C: Transmits data or acknowledgment messages in response to requests.

[0055] Channel E: Transmits the final acknowledgment of the cache block transmission from the original requester, used for serialization.

[0056] The priorities of cross-channel messages are A < B < C < D < E, in ascending order of priority. The priority ensures that messages flowing through the TileLink network never enter a routing or waiting loop.

[0057] Channel A flows from the master interface to the slave interface, carrying request messages sent to a specific address. This channel is used by all TileLink conformance levels and is mandatory.

[0058] Channel D flows from the slave interface to the master interface. It carries response messages for requests on Channel A sent to a specific address. It also carries acknowledgments for voluntary write-backs on Channel C. This channel is used by all TileLink conformance levels and is mandatory.

[0059] In the embodiment, only TL-UL is involved, and only Channels A and D need to be considered.

[0060] The technical solution of the present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0061] Embodiment 1

[0062] This embodiment provides a conversion system from a DBB bus to a TileLink bus. Refer to Figure 4 , including a DBBToAXI4 module, an AXI4Buffer module, an AXI4UserYanker module, an AXI4ToTL module, and a TLFragmenter module, which are connected in sequence;

[0063] Among them, the DBBToAXI4 module is used to map the signals of the DBB bus to the AXI4 bus, including assigning the combined logic of the DBB request signal to the corresponding AXI4 signal and performing an assignment operation on the arsize signal or the awsize signal; the AXI4Buffer module is used to cache the response messages on the AXI4 bus; the AXI4UserYanker module is used to convert the AXI4 bus with a user field into an AXI4 bus without a user field; the AXI4ToTL module is used to map the information on the AXI4 bus to the TileLink bus; the TLFragmenter module is used to split a larger transaction into multiple smaller transactions to reduce the maximum logical transmission of TileLink.

[0064] In a specific implementation process, after the DBBToAXI4 module receives the signal output through the DBB interface, it responds and maps it to the AXI4 bus. Refer to Figure 5The AXI4Buffer module buffers response messages on the AXI4 bus; the AXI4UserYanker module converts an AXI4 bus with a user field into an AXI4 bus without a user field; the AXI4ToTL module then maps the AXI4 bus without a user field to the TileLink bus. (See also...) Figure 7 Since the DBB interface does not support burst transmission, the large TileLink bus request from the TLFragmenter module is divided into multiple smaller TileLink bus requests to reduce the maximum logical transmission of TileLink.

[0065] In a preferred embodiment, the DBBToAXI4 module assigns the signal combination logic of DBB to the corresponding signal of AXI4, and performs a value assignment operation on the arsize signal or awsize signal according to the type of the received request message, specifically in any of the following ways:

[0066] (1) If the request message is a read data request signal, assign the arvalid, already, arrid, arlen and aradir read data request signal combination logic of DBB to the arvalid, already, arrid, arlen and aradir signals of AXI4; assign the rvalid, rready, arrid, rlast and rdata read data request signal combination logic of DBB to the rvalid, rready, arrid, rlast and rdata signals of AXI4, and perform an assignment operation on the arsize signal of AXI4;

[0067] (2) If the request message is a write data request signal, assign the combined logic of the DBB's awvalid, awready, awid, awlen and awaddr write data request signals to the AXI4's awvalid, awready, awid, awlen and awaddr signals; assign the combined logic of the DBB's wvalid, wready, wdata and wlast write data request signals to the AXI4's wvalid, wready, wdata and wlast signals; and perform an assignment operation on the AXI4's awsize according to the wstrb signal value.

[0068] Example 2

[0069] This embodiment provides a method for converting from a DBB bus to a TileLink bus. (See attached document.) Figure 4 , Figure 6 , Figure 7An application example 1 proposes a DBB bus to TileLink bus conversion system, comprising:

[0070] The Slave initiates a request message on the DBB bus, and the DBBToAXI4 module maps the request message from the DBB bus to the AXI4 bus; wherein, the request message is a read data request signal or a write data request signal.

[0071] The AXI4Buffer module buffers response messages on the AXI4 bus;

[0072] The AXI4UserYanker module converts an AXI4 bus with a user field into an AXI4 bus without a user field.

[0073] The AXI4ToTL module maps response message matching on the AXI4 bus to the TileLink bus.

[0074] The TLFragmenter module splits a large TileLink bus request into multiple smaller TileLink bus requests;

[0075] The Master responds to requests on the TileLink bus.

[0076] In a preferred embodiment, see Figure 8 If the request message is a read data request signal, the Slave initiates a request on the DBB bus, and the DBBToAXI4 module maps the request message from the DBB bus to the AXI4 bus, including:

[0077] The slave sends a read data request signal on the DBB bus by pulling up the arvalid and arready signals. The slave also sends the request address information through the araddr signal.

[0078] The DBBToAXI4 module assigns the combined logic of the DBB read data request signal to the corresponding signal of AXI4, and performs a value assignment operation on the arsize signal of AXI4.

[0079] Because the TileLink protocol specifies that the size value needs to be determined when transmitting data, the arsize signal can be directly connected to the TileLink size signal by assigning a value to it, which conforms to the TileLink protocol.

[0080] In an optional embodiment, the request address information is 64 bits; the DBBToAXI4 module assigns the read data request signal combination logic of DBB to the corresponding signal of AXI4, and performs an assignment operation on the arsize signal of AXI4, specifically: the DBBToAXI4 module assigns the read data request signal combination logic of DBB's arvalid, awakened, arrid, arlen, and aradir to the arvalid, awakened, arrid, arlen, and aradir signals of AXI4, assigns the read data request signal combination logic of DBB's rvalid, rready, rid, rlast, and rdata to the rvalid, rready, rid, rlast, and rdata signals of AXI4, and sets the arsize signal value on the AXI4 bus to 3'b110.

[0081] In an optional embodiment, if the request message is a read data request signal, the Master responds to the request on the TileLink bus, including:

[0082] After receiving a read data request signal on the TileLink bus and sending back a response message, the Master pulls up the rvalid and rready signals of the DBB. The Master then returns the data within the corresponding requested address to the Slave via the rdata signal.

[0083] In another preferred embodiment, if the request message is a write data request signal, the Slave initiates a request message on the DBB bus, and the DBBToAXI4 module maps the request message from the DBB bus to the AXI4 bus, including:

[0084] The slave sends a write data request signal on the DBB bus by pulling up the awvalid and awready signals. The slave also sends address information via the awaddr signal. The write data request signal types include Putfulldata and / or Putpartialdata.

[0085] The DBBToAXI4 module assigns the DBB write data request signal combination logic to the corresponding AXI4 signal, and selects to directly assign a value to the AXI4 awsize signal based on the wstrb signal value, or to first assign a value to the AXI4 awaddr signal and then assign a value to the awsize signal.

[0086] Similarly, since the TileLink protocol specifies that the value of `size` needs to be determined when transmitting data, assigning a value to `awsize` allows it to directly connect to the `size` signal of TileLink, thus conforming to the TileLink protocol. Furthermore, to enable DBB to interface with the TileLink protocol, assigning a value to the `awsize` signal based on the `wstrb` signal value ensures that the `size` signal in TileLink corresponds to the `wstrb` signal in DBB.

[0087] In one optional embodiment, the address information is 64 bits; the step of selecting to directly assign a value to the awsize signal of AXI4 based on the wstrb signal value, or to first assign a value to the awaddr signal of AXI4 and then assign a value to the awsize signal, specifically involves:

[0088] If the wstrb signal value is 64'hffff_ffff_0000_0000, first set the awaddr of AXI4 to {nvdla_core2dbb_aw_awaddr_c[63:6],1'd1,nvdla_core2dbb_aw_awaddr_c[4:0]}, and then set the awsize signal value of AXI4 to 3'b101;

[0089] If the wstrb signal value is 64'hffff_ffff_ffff_ffff, then let the awsize signal value be 3'b110;

[0090] If the wstrb signal value is 64'h0000_0000_ffff_ffff, then let the awsize signal value be 3'b101;

[0091] If the wstrb signal value is any other value, set the awsize signal value to 3'b0.

[0092] In the Tilelink protocol, the MaskGen implementation rules specify two write data request methods: Putfulldata and Putpartialdata. In this optional embodiment, the wstrb signal value corresponds to the generation of the mask in TileLink. When the wstrb signal value is 64'hffff_ffff_ffff_ffff, it indicates that the current write data request method is Putfulldata. When the wstrb signal value is 64'h0000_0000_ffff_ffff or 64'hffff_ffff_0000_0000, it indicates that the current write data request method is Putpartialdata.

[0093] Furthermore, if the request message is a write data request signal, the Master responds to the request on the TileLink bus, including:

[0094] If the wstrb signal value is any of 64'hffff_ffff_0000_0000, 64'hffff_ffff_ffff_ffff, or 64'h0000_0000_ffff_ffff, the Master receives the write data request signal on the TileLink bus and sends back a response message, pulling the valid and bready signals high. The Slave sends the data through the wdata signal. Otherwise, the Master does not send back a response message after receiving the write data request signal on the TileLink bus.

[0095] Example 3

[0096] To verify the feasibility of the DBB bus to TileLink bus conversion method provided in Example 2, this example conducts a simulation experiment on the DBB bus to TileLink bus conversion method proposed in Example 2. (See attached document for details.) Figure 9 .

[0097] When the slave sends a read data request signal to the master: on the rising edge of the clock CLK, the slave pulls ARVALID high via the DBB bus. Upon receiving the ARVALID signal, the master pulls ARREADY high, maintaining this high until one burst_len data transfer is complete. Upon receiving the high ARREADY signal, the slave pulls ARVALID low. ARADDR assigns the corresponding address when ARVALID is high. The ARREADY signal is pulled high upon receiving a high ARREADY signal, maintaining this high position for one cycle, during which data is read. The ARREADY signal is controlled by the slave; when the last data packet of a read operation is read, RLAST is pulled high, indicating that a burst read operation is complete.

[0098] When the slave sends a write data request signal to the master: on the rising edge of the clock CLK, the slave pulls AWVALID high via the DBB bus. Upon receiving the AWVALID signal, the master pulls AWREADY high, maintaining it until a burst_len write operation is completed. Upon receiving the high AWREADY signal, the slave pulls AWVALID low. AWADDR assigns the corresponding address when AWVALID is high. The WREADY signal is pulled high upon receiving a high WVALID signal, maintains it for one cycle, and data is written via the WDATA signal. The WVALID signal is controlled by the slave; when the last data packet of a write operation is read, WLAST is pulled high, indicating that a write operation is complete. BRESP and BVALID are both controlled by the slave; when the WLAST signal is received, BVALID is pulled high. Optionally, BREADY can remain high until the BVALID signal is high, at which point it can be pulled low; alternatively, BREADY can remain high after the AWREADY signal is high, until the BVALID signal is high, at which point it can be pulled low.

[0099] Example 4

[0100] This embodiment provides a hardware device, including an NVDLA module. The NVDLA module is provided with a DBB interface, which is connected to the conversion system proposed in Embodiment 1 for data conversion with an external TileLink interface.

[0101] The same or similar labels correspond to the same or similar parts;

[0102] The terms used to describe positional relationships in the accompanying drawings are for illustrative purposes only and should not be construed as limiting this patent.

[0103] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively describe all embodiments here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A DBB bus to TileLink bus conversion system, characterized in that, It includes the DBBToAXI4 module, as well as the AXI4Buffer module, AXI4UserYanker module, AXI4ToTL module and TLFragmenter module, with each module connected in sequence; The DBBToAXI4 module maps DBB bus signals to the AXI4 bus, including assigning the DBB request signal combination logic to the corresponding AXI4 signal and performing value assignment operations on the arsize or awsize signal; the AXI4Buffer module buffers response messages on the AXI4 bus; the AXI4UserYanker module converts an AXI4 bus with a user field into an AXI4 bus without a user field; the AXI4ToTL module maps information on the AXI4 bus to the TileLink bus; and the TLFragmenter module divides larger transactions into multiple smaller transactions to reduce the maximum logical transmission of TileLink. In the DBBToAXI4 module, the signal combination logic of DBB is assigned to the corresponding signal of AXI4, and the arsize signal or awsize signal is assigned a value according to the type of the received request message, specifically any of the following: (1) If the request message is a read data request signal, assign the arvalid, already, arrid, arlen and aradir read data request signal combination logic of DBB to the arvalid, already, arrid, arlen and aradir signals of AXI4; assign the rvalid, rready, arrid, rlast and rdata read data request signal combination logic of DBB to the rvalid, rready, arrid, rlast and rdata signals of AXI4, and perform an assignment operation on the arsize signal of AXI4; (2) If the request message is a write data request signal, assign the combined logic of the DBB's awvalid, awready, awid, awlen and awaddr write data request signals to the AXI4's awvalid, awready, awid, awlen and awaddr signals; assign the combined logic of the DBB's wvalid, wready, wdata and wlast write data request signals to the AXI4's wvalid, wready, wdata and wlast signals; and perform an assignment operation on the AXI4's awsize according to the wstrb signal value.

2. A method for converting a DBB bus to a TileLink bus, using the DBB bus to TileLink bus conversion system described in claim 1, characterized in that, include: The Slave initiates a request message on the DBB bus, and the DBBToAXI4 module maps the request message from the DBB bus to the AXI4 bus; wherein, the request message is a read data request signal or a write data request signal. The AXI4Buffer module buffers response messages on the AXI4 bus; The AXI4UserYanker module converts an AXI4 bus with a user field into an AXI4 bus without a user field. The AXI4ToTL module maps response message matching on the AXI4 bus to the TileLink bus. The TLFragmenter module splits a large TileLink bus request into multiple smaller TileLink bus requests; The Master responds to the request on the TileLink bus; Wherein, if the request message is a read data request signal, the Slave initiates a request on the DBB bus, and the DBBToAXI4 module maps the request message from the DBB bus to the AXI4 bus, including: The slave sends a read data request signal on the DBB bus by pulling up the arvalid and arready signals. The slave also sends the request address information through the araddr signal. The DBBToAXI4 module assigns the combined logic of the DBB read data request signal to the corresponding signal of AXI4, and performs a value assignment operation on the arsize signal of AXI4. Furthermore, if the request message is a write data request signal, the Slave initiates a request message on the DBB bus, and the DBBToAXI4 module maps the request message from the DBB bus to the AXI4 bus, including: The slave sends a write data request signal on the DBB bus by pulling up the awvalid and awready signals. The slave also sends address information via the awaddr signal. The write data request signal types include Putfulldata and / or Putpartialdata. The DBBToAXI4 module assigns the DBB write data request signal combination logic to the corresponding AXI4 signal, and selects to directly assign a value to the AXI4 awsize signal based on the wstrb signal value, or to first assign a value to the AXI4 awaddr signal and then assign a value to the awsize signal.

3. The method for converting a DBB bus to a TileLink bus according to claim 2, characterized in that, The requested address information is 64 bits; The DBBToAXI4 module assigns the read data request signal combination logic of DBB to the corresponding signals of AXI4, and performs an assignment operation on the arsize signal of AXI4. Specifically, the DBBToAXI4 module assigns the arvalid, awakened, arrid, arlen, and aradir read data request signal combination logic of DBB to the arvalid, awakened, arrid, arlen, and aradir signals of AXI4, and assigns the rvalid, rready, rid, rlast, and rdata read data request signal combination logic of DBB to the rvalid, rready, rid, rlast, and rdata signals of AXI4, and sets the arsize signal value on the AXI4 bus to 3'b110.

4. The method for converting a DBB bus to a TileLink bus according to claim 2, characterized in that, If the request message is a read data request signal, the Master responds to the request on the TileLink bus, including: After receiving a read data request signal on the TileLink bus and sending back a response message, the Master pulls up the rvalid and rready signals of the DBB. The Master then returns the data within the corresponding requested address to the Slave via the rdata signal.

5. The method for converting a DBB bus to a TileLink bus according to claim 4, characterized in that, The address information is 64 bits; The specific steps are as follows: First, assign a value directly to the AXI4's awsize signal based on the wstrb signal value; second, assign a value to the AXI4's awaddr signal first, and then assign a value to the awsize signal. If the wstrb signal value is 64'hffff_ffff_0000_0000, first set the awaddr of AXI4 to {nvdla_core2dbb_aw_awaddr_c[63:6],1'd1,nvdla_core2dbb_aw_awaddr_c[4:0]}, and then set the awsize signal value of AXI4 to 3'b101; If the wstrb signal value is 64'hffff_ffff_ffff_ffff, then let the awsize signal value be 3'b110; If the wstrb signal value is 64'h0000_0000_ffff_ffff, then let the awsize signal value be 3'b101; If the wstrb signal value is any other value, set the awsize signal value to 3'b0.

6. The method for converting a DBB bus to a TileLink bus according to claim 5, characterized in that, If the request message is a write data request signal, the Master responds to the request on the TileLink bus, including: If the wstrb signal value is any of 64'hffff_ffff_0000_0000, 64'hffff_ffff_ffff_ffff, or 64'h0000_0000_ffff_ffff, the Master receives the write data request signal on the TileLink bus and sends back a response message, pulling the valid and bready signals high. The Slave sends the data through the wdata signal. Otherwise, the Master does not send back a response message after receiving the write data request signal on the TileLink bus.

7. A hardware device, comprising an NVDLA module, characterized in that, The NVDLA module is equipped with a DBB interface, which is connected to the conversion system as described in claim 1, for data conversion with an external TileLink interface.

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