PAM-4 DFE architecture with DFE tap values dependent on symbol conversion

Abstract

The present disclosure relates to a PAM-4 DFE architecture with symbol conversion-dependent DFE tap values. Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from data signals received via a band-limited (or non-ideal) channel. A first PAM-4 DFE architecture has low latency from the output of a sampler to applying a first DFE tap feedback to an input signal. This is achieved by not decoding the sampler output to generate a feedback signal for the first DFE tap. Instead, a weighted version of the original sampler output is directly applied to the input signal without further analog or digital processing. An additional PAM-4 DFE architecture uses the current symbol in addition to (one or more) previous symbols to determine the DFE feedback signal. Another architecture uses non-uniform pre-emphasis to transmit PAM-4 signaling. Non-uniform pre-emphasis allows a speculative DFE receiver to resolve the transmitted PAM-4 signal with fewer comparators / samplers.

Description

[0001] This application is a divisional application of the invention patent application with the application date of October 12, 2016, application number 201680051179.0 (202110458051.9), and invention title "PAM-4 DFE Architecture with DFE Tap Values Dependent on Symbol Transitions". BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Figure 1 FIG. is a diagram illustrating a communication system having a decision feedback equalizer (DFE).

[0003] Figure 2 FIG. is a diagram illustrating a memory system.

[0004] Figure 3A FIG. illustrates a non-speculative DFE four-level pulse amplitude modulation (PAM-4) receiver having an analog feed-forward equalizer (FFE).

[0005] Figure 3B FIG. illustrates a non-speculative DFE two-level pulse amplitude modulation (PAM-2) receiver having an analog FFE.

[0006] Figure 4A FIG. illustrates a non-speculative DFE PAM-4 receiver having a combined receive FFE and first tap DFE loop.

[0007] Figure 4B FIG. illustrates a non-speculative DFE PAM-2 receiver having a combined receive FFE and first tap DFE loop.

[0008] Figure 5 FIG. illustrates a non-speculative DFE receiver having an analog FFE and higher-order DFE taps.

[0009] Figure 6 FIG. illustrates a non-speculative DFE receiver having a receive FFE and higher-order DFE taps.

[0010] Figure 7 FIG. illustrates a non-speculative DFE receiver having a low-latency DFE tap feedback.

[0011] Figure 8 FIG. illustrates a PAM-4 receiver having a low-latency DFE feedback.

[0012] Figure 9 FIG. illustrates a PAM-4 receiver having a DFE feedback.

[0013] Figure 10 FIG. illustrates a receiver having a DFE feedback.

[0014] Figure 11 FIG. illustrates a receiver having a higher-order DFE feedback.

[0015] Figure 12 Illustrates a communication system with non-uniform transmit equalization and a speculative DFE.

[0016] Figures 13A to 13C Illustrates an example of non-uniform transmit equalization.

[0017] Figure 14A Illustrates a PAM-4 data eye for non-uniform equalization transition from a positive-sign previous symbol.

[0018] Figure 14B Illustrates a PAM-4 data eye for non-uniform equalization transition from a negative-sign previous symbol.

[0019] Figure 15 Illustrates a PAM-4 speculative DFE receiver with five comparators.

[0020] Figure 16 Illustrates a PAM-4 speculative DFE receiver with second-tap feedback.

[0021] Figure 17 Illustrates a PAM-4 speculative DFE receiver with second-tap feedback without subtraction.

[0022] Figure 18 Is a flowchart illustrating a non-speculative no-decoder method of decision feedback equalization.

[0023] Figures 19A to 19B Is a flowchart illustrating a non-speculative method of decision feedback equalization.

[0024] Figure 20 Is a flowchart illustrating a non-speculative DFE using an analog FFE.

[0025] Figure 21 Is a flowchart illustrating a non-speculative DFE using a combined receive FFE and first-tap DFE loop.

[0026] Figure 22 Illustrates a communication system with a receiver based on an analog-to-digital converter (ADC).

[0027] Figure 23 Illustrates a receiver with higher-order DFE feedback in the digital domain.

[0028] Figure 24 Is a flowchart illustrating a method of equalizing a data signal.

[0029] Figure 25 Is a block diagram of a computer system. Detailed Description

[0030] Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from data signals received via a band-limited (or non-ideal) channel. In one embodiment, the PAM-4 DFE architecture has low latency from the output of the sampler to applying the first DFE tap feedback to the input signal. This is achieved by not decoding the sampler output to generate the feedback signal for the first DFE tap. Instead, a weighted version of the original sampler output is directly applied to the input signal without further analog or digital processing.

[0031] In other embodiments, in addition to the previous symbol(s), the additional PAM-4 DFE architecture also uses the current symbol to determine the DFE feedback signal. For example, an analog sample and hold circuit is used to capture the voltage level of the symbol when the symbol is the current symbol. This captured voltage is held until the next symbol period, weighted, and then analog added to a weighted version of the current input voltage. This implements an analog feed-forward equalizer using the current symbol. In another example, a weighted version of the current input voltage is added to the first DFE tap voltage. The sum of these inputs is sampled to produce the first DFE tap voltage for the next symbol period.

[0032] A finite impulse response (FIR) filter is used to provide non-uniform pre-emphasis to the PAM-4 output signal. The non-uniform pre-emphasis values are selected such that after passing through the channel, several received voltage levels approximately have the same value. In other words, the non-uniform pre-emphasis is combined with the ISI caused by the channel to allow sampling of a particular transition using the same reference voltage rather than using different reference voltages. This allows using fewer comparators (e.g., five instead of twelve) to presumptively sample the received PAM-4 signal.

[0033] Figure 1 is a diagram of a communication system with decision feedback equalization (DFE). Communication system 100 includes a driver integrated circuit, a receiver integrated circuit, and the interconnection therebetween. The driver integrated circuit includes a transmitter circuit 110 (also referred to as a driver). The transmitter circuit 110 may use finite impulse response (FIR)-based equalization. The transmitter circuit 110 may include a tap driver 113. The tap driver 113 may include one or more pre-tap FFE drivers, one or more post-tap FFE drivers, and a main tap driver.

[0034] The receiver integrated circuit includes a receiver circuit 150. The interconnection between the driver integrated circuit and the receiver integrated circuit includes an interconnection system 140. The interconnection system 140 will generally include a printed circuit (PC) board, connectors, cables, flexible circuits, other substrates, and / or combinations thereof. The interconnection system 140 may be and / or include one or more transmission lines.

[0035] The receiver circuit 150 will typically be part of an integrated circuit that receives signals sent by a driver integrated circuit. It should be understood that termination (not shown in Figure 1 ) can be part of the integrated circuit or the interconnect system 140. It should also be understood that although the system 100 is illustrated as transmitting a single-ended signal, the signal sent by the driver integrated circuit of the system 100 can represent one signal in a pair of differential signals, or one signal in a set of signals that transmit multi-line encoded data.

[0036] In Figure 1 , the output of the transmitter circuit 110 is connected to the first end of the interconnect system 140. The second end of the interconnect system 140 is connected to the input of the receiver 150. In one embodiment, the transmitter circuit 110 can be configured to drive PAM-4 signal levels. In another embodiment, the transmitter circuit 110 can be configured to drive PAM-2 (non-return-to-zero - NRZ) signaling levels.

[0037] In one embodiment, the receiver 150 uses a PAM-4 DFE architecture with low latency from the output of the sampler to applying the first DFE tap feedback to the input signal. An appropriately weighted version of the original sampler output is directly applied to the input signal without further analog or digital processing. By directly applying the weighted version of the original sampler output to the input signal, the latency associated with processing the sampler output into a single DFE tap value is reduced.

[0038] In one embodiment, the receiver 150 uses a DFE architecture that uses the current input voltage (symbol) received via the interconnect system 140 as an input to help determine the DFE feedback signal. The receiver 150 adds the current input symbol to the higher (i.e., greater than 1) DFE feedback taps (if any) to produce a first input voltage. The receiver 150 can use an analog sample and hold circuit to capture the first input voltage during the current symbol period. The receiver 150 holds the captured first input voltage during the next symbol period. The receiver 150 weights the captured first input voltage. The receiver 150 adds the weighted version of this analogously to the analog weighted version of the current input voltage (i.e., the next symbol). Thus, the receiver 150 implements an analog feed-forward equalizer that utilizes the current symbol.

[0039] In one embodiment, the receiver 150 adds the current input symbol to the higher (i.e., greater than 1) DFE feedback taps (if any) to generate a first input voltage. The receiver 150 analogously weights the first input voltage to produce a weighted version of the first input voltage. The receiver 150 analogously adds the weighted version of the first input voltage to the first DFE tap voltage generated from the sampled (digital) version of the previous symbol. The sum of these two inputs is sampled by the receiver 150 to produce the first DFE tap voltage for the next (i.e., subsequent) symbol period.

[0040] In one embodiment, the receiver 150 is a speculative DFE receiver. The transmitter circuit 110 uses a finite impulse response (FIR) filter to apply non-uniform pre-emphasis to the PAM-4 output signal. The non-uniform pre-emphasis applied by the transmitter circuit 110 is selected such that after passing through the interconnect system 140, several of the received PAM-4 voltage levels effectively have the same value. The non-uniform pre-emphasis applied by the transmitter circuit 110, in combination with the ISI introduced by the interconnect system 140, allows a particular PAM-4 transition transmitted by the transmitter circuit 110 to be accurately sampled by the speculative DFE receiver 150 using five comparators.

[0041] Values -3, -1, +1, and +3 may be assigned to the PAM-4 voltage levels. These values are assumed for the purposes of this discussion. Additionally, for the purposes of this discussion, the letter "a" is used to denote these symbol values in digital / integer form (i.e., -3, -1, +1, and +3), while the letter "v" is used to denote these symbol values and other voltages in their analog form (e.g., -30 mV, -10 mV, +10 mV, +30 mV).

[0042] A desired non-speculative DFE receiver (e.g., receiver 150) implements the first DFE tap based on the current symbol according to Equation 1 below:

[0043] dfe1 = -0.5α1(a -1 - a0) Equation 1

[0044] where dfe1 is the desired DFE tap value for the first post-cursor DFE tap; a -1 is the previous symbol; a0 is the current symbol; and α1 is the amount of ISI associated with the transition between two adjacent PAM-4 levels with respect to the signal / voltage for the first post-cursor ISI (e.g., from +1 to -1, -3 to -1, etc.). Thus, the desired non-speculative DFE receiver (e.g., receiver 150) implements the first DFE tap according to Table 1.

[0045]

[0046]

[0047] For the second and higher DFE tap values (e.g., DFE tap #n, where n = 2, 3, 4...), the previous symbol a can be shown -n The amount of ISI present on the current symbol a0 depends on two adjacent symbols a -n and a -(n-1) between the trajectories. Thus, the expected value for a higher DFE tap can be expressed according to Equation 2:

[0048]

[0049] where dfe n is the expected DFE tap value for the nth post - symbol DFE tap; a -(n-1) is the previous symbol immediately preceding the nth symbol; a -n is the current symbol; and a n is the amount of ISI associated with the transition magnitude of a single PAM - 4 level (e.g., from +1 to -1, -3 to -1, etc.) for the nth post - symbol ISI.

[0050] According to Equation 1 and Equation 2, the equations in Table 2 summarize the expected DFE tap values for all taps. In Table 2, v m is the received voltage; m is the time index; h0, h1, h2, etc. are the discrete - time voltage values of the single - bit response of the channel (e.g., the interconnect system 140); and a m is the mth transmitted symbol.

[0051]

[0052] It should be understood that, as used herein, h is the single - bit response (SBR). In other words, when the single - bit response is plotted such that the Y - axis is in volts and the x - axis is in time, the single - bit response is obtained by convolving the channel impulse response (e.g., the impulse response of the interconnect 140) with an ideal bit (i.e., a square signal). To find the effect of ISI on each symbol (bit), the single - bit response is needed. When h has a subscript (i.e., h0, h1, h2...h mWhen used together, it refers to the sampling of the continuous waveform h obtained at evenly spaced instants, where the separation between every two adjacent samplings is 1 UI - unit interval - equal to 1 / (data rate). The point where h has its maximum amplitude can be called a cursor, or h0. The subscript zero (0) refers to the fact that the cursor is used as a time reference. The sampling that arrives 1 UI after h0 (to the right of the time axis from left to right) is called the first post-cursor or h1. The sampling before h0 (to the left) is called the first pre-cursor or h -1 . To illustrate how to calculate the effect of ISI on the current bit voltage amplitude v0, assume a simplified channel with only 1 pre-cursor and 1 post-cursor. In this case, for example:

[0053] v0 = (current symbol) × h0 + (next symbol) × h -1 + (previous symbol) × h1

[0054] Note that the symbols in NRZ (i.e., PAM-2) signaling can have values of -1 or +1. For PAM-4 signaling, the symbols can have values of -1, -1 / 3, +1 / 3, or +1.

[0055] Figure 2 is a block diagram illustrating a memory system. In Figure 2 , the memory system 200 includes a memory controller 210 and a memory 220. The memory controller 210 includes a driver 213 and a receiver 214. The memory controller 210 also includes N signal ports Q[1:N], and the N signal ports Q[1:N] can be driven by one or more of the drivers in the driver 213 and can receive signals to be sampled by one or more of the receivers in the receiver 214. The memory 220 includes a driver 223 and a receiver 224. The memory 220 also includes N signal ports Q[1:N], and the N signal ports Q[1:N] can be driven by one or more of the drivers in the driver 223 and can receive signals to be sampled by one or more of the receivers in the receiver 224. The signal ports Q[1:N] of the memory controller 210 are operatively coupled to the ports Q[1:N] of the memory 220 respectively. The receiver 224 of the memory 220 can receive one or more of the Q[1:N] signals from the memory controller 210. The receiver 214 of the memory controller 210 can receive one or more of the Q[1:N] signals from the memory 220.

[0056] One or more of the drivers 213 in the driver 213 can form a PAM-2 signaling system or a PAM-4 signaling system when configured and coupled to corresponding one or more receivers 224. Thus, one or more of the drivers 213 in the driver 213 of the memory controller 210 can correspond to the transmitter circuit 110 discussed previously, or to the transmitter circuit discussed subsequently herein. One or more of the drivers 213 in the driver 213 of the memory controller 210 can apply pre-emphasis to drive (two-level or four-level) signals. One or more of the receivers 214 in the receiver 214 of the memory controller 210 can correspond to the receiver 150 discussed previously, or to the receiver circuit discussed subsequently herein. One or more of the receivers 214 in the receiver 214 of the memory controller 210 can use a DFE architecture that uses the current input voltage (symbol) received via the memory 220 as an input to help determine the DFE feedback signal.

[0057] One or more of the drivers 223 in the driver 223 can form a PAM-2 signaling system or a PAM-4 signaling system when configured and coupled to corresponding one or more receivers 214. Thus, one or more of the drivers 223 in the driver 223 of the memory 220 can correspond to the transmitter circuit 110 discussed previously, or to the transmitter circuit discussed subsequently herein. One or more of the drivers 223 in the driver 223 of the memory 220 can apply pre-emphasis to drive (two-level or four-level) signals. One or more of the receivers 224 in the receiver 224 of the memory 220 can correspond to the receiver 150 discussed previously, or to the receiver circuit discussed subsequently herein. One or more of the receivers 224 in the receiver 224 of the memory 220 can use a DFE architecture that uses the current input voltage (symbol) received from the memory controller 210 as an input to help determine the DFE feedback signal.

[0058] The memory controller 210 and the memory 220 are integrated circuit type devices, such as devices commonly referred to as "chips". A memory controller such as the memory controller 210 manages the data stream to and from a memory device such as the memory 220. For example, the memory controller can be a northbridge chip, an application specific integrated circuit (ASIC) device, a graphics processing unit (GPU), a system on a chip (SoC), or an integrated circuit device including many circuit blocks selected from, for example, a graphics core, a processor core, and an MPEG encoder / decoder. The memory 220 can include a dynamic random access memory (DRAM) core or other types of memory cores, for example, a static random access memory (SRAM) core or a non-volatile memory core such as a flash memory. Additionally, although the embodiments presented herein describe a memory controller and components, the apparatus and method can also be applied to a chip interface that accomplishes signal transmission between separate integrated circuit devices.

[0059] It should be understood that the signal ports Q[1:N] of both the memory controller 210 and the memory 220 can correspond to any input or output pin (or ball pin) of the memory controller 210 or the memory 220 that transmits information between the memory controller 210 and the memory 220. For example, the signal ports Q[1:N] can correspond to bidirectional data pins (or pad components) that are used to transfer read and write data between the memory controller 210 and the memory 220. The data pins can also be referred to as "DQ" pins. Thus, for a memory 220 that reads and writes data up to 16 bits at a time, the signal ports Q[1:N] can be considered to correspond to the pins DQ[0:15]. In another example, the signal ports Q[1:N] can correspond to one or more unidirectional command / address (C / A) buses. The signal ports Q[1:N] can correspond to one or more unidirectional control pins. Thus, the signal ports Q[1:N] on the memory controller 210 and the memory 220 can correspond to pins such as CS (chip select), including a command interface with timing control strobes such as RAS and CAS, address pins A[0:P] (i.e., address pins that carry address bits), DQ[0:X] (i.e., data pins that carry data bits), etc., and other pins in past, present, or future devices.

[0060] Figure 3A Illustrated is a non-speculative DFE four-level pulse amplitude modulation (PAM-4) receiver with analog feed-forward equalization (FFE). Figure 3AThe receiver 300 illustrated therein may correspond to one or more of the receivers 150, 214, and / or 224. In one embodiment, the receiver 300 may be configured to implement the DFE tap values as described herein. In particular, the receiver 300 may implement the DFE tap values given in one or more of Equation 1, Equation 2, Table 1, and / or Table 2.

[0061] The receiver 300 includes an analog adder 311, a sample and hold (S / H) circuit 340, weighted buffers 341, 342, and a PAM-4 sampler 320. The PAM-4 sampler 320 includes samplers 321, 322, and 323. The samplers 321 - 323 output digital signals that can be interpreted as +1 or -1. The weighted buffers 341 - 342 receive and output analog signals that do not require interpretation.

[0062] An input signal (IN) is operatively coupled to the input of the S / H 340 and the input of the weighted buffer 342. For example, the input signal (IN) may be received from the interconnect system 140. The weighted buffer 342 multiplies the analog voltage at the input of the weighted buffer 342 by a factor K0 and outputs it. In one embodiment, K0 = 1 + 0.5α1, where α1 may be adapted or selected to remove the first post - marker ISI component. When α1 is dynamically adapted, it should be understood that K0 may be variable during the adaptation (i.e., training) period, but is typically constant during normal operation.

[0063] The sample and hold 340 samples and holds according to a timing reference (CK) synchronized with the symbol period such that the S / H 340 will take an analog sample of the voltage on the input of the S / H 340 while the PAM-4 sampler 320 is controlled to sample. This analog sample is held at the output of the S / H 340 until a new analog sample is taken during the next symbol period.

[0064] The output of the S / H 340 is input to the weighted buffer 341. The weighted buffer 341 multiplies the analog voltage at the input of the weighted buffer 341 by a factor K1 and outputs it. In one embodiment, K1 = -0.5α1. Similar to K0, it should be understood that K1 may be variable during the adaptation (i.e., training) period, but is typically constant during normal operation.

[0065] The outputs of weighted buffers 341 and 342 are input to analog adder 311. The output of analog adder 311 is input to PAM-4 sampler 320. The output of analog adder 311 is input to the non-inverting inputs of samplers 321-323. The inverting input of sampler 321 receives reference voltage Vref1. The inverting input of sampler 322 receives reference voltage Vref2. The inverting input of sampler 323 receives reference voltage Vref3. Reference voltages Vref1, Vref2, and Vref3 are typically selected between the PAM-4 voltage levels. For example, if the four PAM-4 levels are -3V, -1V, +1V, and +3V, then Vref1 can be selected as -2V, Vref2 = 0V, and Vref3 = +2V.

[0066] Samplers 321-323 each receive timing reference CK. CK determines the timing at which samplers 321-323 compare the input (i.e., the output of adder 311) with their respective reference voltages (e.g., Vref1, etc.) to produce their respective digital output signals.

[0067] The voltage at the input of PAM-4 sampler 320 can be represented by the equations in Table 3. In Table 3, v m is the received voltage; m is the time index; h0, h1, h2, etc. are the discrete-time voltage values of the single-bit response of the channel (e.g., interconnect system 140); a m is the m-th transmitted symbol; and β is the ISI at the output of S / H 340.

[0068]

[0069] Figure 3B Illustrates a non-speculative DFE two-level pulse amplitude modulation (PAM-2) receiver with analog FFE. The receiver 302 illustrated in Figure 3B can correspond to one or more of receivers 150, 214, and / or 224. In one embodiment, receiver 302 can be configured to implement the DFE tap values as described herein. In particular, receiver 302 can implement the DFE tap values given in one or more of Equation 1, Equation 2, Table 1, and / or Table 2.

[0070] Receiver 302 includes analog adder 311, sample and hold (S / H) circuit 340, weighted buffer 341, weighted buffer 342, and sampler 322. Thus, from Figure 3BIt should be apparent that receiver 302 is similar to receiver 300, but without samplers 321 and 323. Moreover, receiver 302 has the inverting input of sampler 322 coupled to Vref4. In one embodiment, Vref4 = Vref2 = 0V.

[0071] Figure 4A Illustrated is a non-speculative DFE PAM-4 receiver having a combined receive FFE and first tap DFE loop. In Figure 4A The receiver 400 illustrated therein may correspond to one or more of receivers 150, 214, and / or 224. In one embodiment, receiver 400 may be configured to implement the DFE tap values as described herein. In particular, receiver 400 may implement the DFE tap values given in one or more of Equation 1, Equation 2, Table 1, and / or Table 2.

[0072] Receiver 400 includes analog adder 411, weighted buffer 441, weighted buffers 435, 436, 437, and PAM-4 sampler 420. PAM-4 sampler 420 includes samplers 421, 422, and 423. The outputs of samplers 421 - 423 are digital signals that can be interpreted as +1 or -1. Weighted buffer 441 receives an analog signal that does not need to be interpreted.

[0073] The input signal (IN) is operatively coupled to the input of weighted buffer 441. For example, the input signal (IN) may be received from interconnect system 140. Weighted buffer 441 multiplies the analog voltage at the input of weighted buffer 441 by a factor K0 and outputs it. In one embodiment, K0 = 1 + 0.5α1, where α1 is adapted or selected to remove the first post-mark ISI component. When α1 is dynamically adapted, it should be understood that K0 may be variable during the adaptation (i.e., training) period, but it is typically constant during normal operation.

[0074] The outputs of weighted buffer 441 and weighted buffers 435 - 437 are input to analog adder 411. The output of analog adder 411 is input to PAM-4 sampler 420. The output of analog adder 411 is input to the non-inverting inputs of samplers 421 - 423. The inverting input of sampler 421 receives reference voltage Vref1. The inverting input of sampler 422 receives reference voltage Vref2. The inverting input of sampler 423 receives reference voltage Vref3. The reference voltages Vref1, Vref2, and Vref3 are typically selected to be between the PAM-4 voltage levels. For example, if the four PAM-4 levels are -3V, -1V, +1V, and +3V, then Vref1 may be selected as -2V, Vref2 = 0V, and Vref3 = +2V.

[0075] Samplers 421 - 423 each receive a timing reference CK. CK determines the timing at which samplers 421 - 423 compare an input (i.e., the output of adder 411) with their respective reference voltages (e.g., Vref1, etc.) to produce their respective digital output signals. Weighted buffers 441, adder 411, PAM - 4 sampler 420, and weighted buffers 435 - 437 form a combined ISI pre - filter and first DFE tap loop.

[0076] The voltage at the input of PAM - 4 sampler 420 can be represented by the equations in Table 4. In Table 4, v m is the received voltage; m is the time index; h0, h1, h2, etc. are the discrete - time voltage values of the single - bit response of the channel (e.g., interconnect system 140); a m is the mth transmitted symbol. Note that the equations in Table 4 are written for a sampled single - tap (i.e., h0 is the main tap, h1 is the first post - cursor) channel.

[0077]

[0078]

[0079] Figure 4B Illustrated is a non - speculative DFE PAM - 2 receiver with a combined receive FFE and first - tap DFE loop. Figure 4B The receiver 402 shown in can correspond to one or more of receivers 150, 214, and / or 224. In one embodiment, receiver 402 can be configured to implement DFE tap values as described herein. In particular, receiver 402 can implement the DFE tap values given in one or more of Equation 1, Equation 2, Table 1, and / or Table 2.

[0080] Receiver 402 includes analog adder 411, weighted buffer 441, weighted buffer 436, and sampler 422. Thus, it should be Figure 4B apparent that receiver 402 is similar to receiver 400, but without samplers 421, 423, weighted buffers 435, and weighted buffer 437. Additionally, receiver 402 has the inverting input of sampler 322 coupled to Vref4. In one embodiment, Vref4 = Vref2 = 0V.

[0081] Figure 5 Illustrated is a non - speculative DFE receiver with an analog FFE and higher - order DFE taps. Figure 5The receiver 500 shown in [description] can correspond to one or more of the receivers 150, 214, and / or 224. In one embodiment, the receiver 500 can be configured to implement the DFE tap values as described herein. In particular, the receiver 500 can implement the DFE tap values given in one or more of Equation 1, Equation 2, Table 1, and / or Table 2.

[0082] The receiver 500 includes an analog adder 510, a receiver feed - forward equalizer (RxFFE) 545, a sampler 520, weighted buffers 532, 533, 534, tap logics 552, 553, 554, registers 562, 563, and 564. In an embodiment, the sampler 520 is a PAM - 4 sampler (e.g., similar or identical to the PAM - 4 sampler 320 or 420) and accordingly outputs a plurality of decision bits. In another embodiment, the sampler 520 is a PAM - 2 sampler that outputs a single decision bit (e.g., similar or identical to the sampler 322 or sampler 422). The RxFFE 545 includes a sample - and - hold (S / H) circuit 540, weighted buffers 541, 542, and an analog adder 511.

[0083] An input signal (IN) is operably coupled to the input of the adder 510. For example, the input signal (IN) can be received from the interconnect system 140. The output of the adder 510 is input to the sample - and - hold circuit 540 and the weighted buffer 542. The weighted buffer 542 multiplies the analog voltage at the input of the weighted buffer 542 by a factor K0 and outputs it. In one embodiment, K0 = 1 + 0.5α1, where α1 is adapted or selected to remove the first post - marker ISI component. When α1 is dynamically adapted, it should be understood that K0 can be variable during the adaptation (i.e., training) period, but it is typically constant during normal operation.

[0084] The output of the S / H 540 is input to the weighted buffer 541. The weighted buffer 541 multiplies the analog voltage at the input of the weighted buffer 541 by a factor K1 and outputs it. In one embodiment, K1 = - 0.5α1. Similar to K0, it should be understood that K1 can be variable during the adaptation (i.e., training) period, but it is typically constant during normal operation.

[0085] The outputs of the weighted buffer 541 and the weighted buffer 542 are input to the analog adder 511. The output of the analog adder 511 is input to the sampler 520. The sampler 520 and each of the registers 562 - 564 receive a timing reference (not shown in [description]). This timing reference (e.g., Figure 5 in [description] Figure 3A and Figure 3BThe CK) determines the timing at which the sampler 520 compares its input (i.e., the output of the adder 511) with a reference (or threshold) voltage to produce a corresponding digital output signal(s). The timing reference also determines when each register latches and propagates the value on its input to its output. The register 562 receives the output of the sampler 520. The registers 563 - 564 each serially receive the output of the previous registers 562 - 564, thereby forming a serial shift register that holds the previous value sampled by the sampler 520 for each successive stage.

[0086] The output of the sampler 520 is also input to the tap logic 552. The tap logic 552 subtracts the output of the sampler 520 from the output of the register 562. The output of the tap logic 552 is input to the weighted buffer 532. The weighted buffer 532 multiplies the analog voltage at the input of the weighted buffer 532 by a factor -K2 and outputs it. In one embodiment, K2 = 0.5α2. The output of the weighted buffer 532 is input to the adder 510, thereby completing the second DFE tap loop. The output of the register 562 is also input to the tap logic 553. The tap logic 553 subtracts the output of the register 562 from the output of the register 563. The output of the tap logic 553 is input to the weighted buffer 533. The weighted buffer 533 multiplies the analog voltage at the input of the weighted buffer 533 by a factor -K3 and outputs it. In one embodiment, K3 = 0.5α3. The output of the weighted buffer 533 is input to the adder 510, thereby completing the third DFE tap loop. The output of the register 563 is also input to the tap logic 554. The tap logic 554 subtracts the output of the register 563 from the output of the register 564. The output of the tap logic 554 is input to the weighted buffer 534. The weighted buffer 534 multiplies the analog voltage at the input of the weighted buffer 534 by a factor -K4 and outputs it. In one embodiment, K4 = 0.5α4. The output of the weighted buffer 534 is input to the adder 510, thereby completing the fourth DFE tap loop. Additional higher-order DFE tap loops can be formed in a similar manner.

[0087] Figure 6 Illustrated is a non-speculative DFE receiver having a receiving FFE and higher-order DFE taps. Figure 6 The receiver 600 illustrated in can correspond to one or more of the receivers 150, receiver 214, and / or receiver 224. In one embodiment, the receiver 600 can be configured to implement the DFE tap values as described herein. In particular, the receiver 600 can implement the DFE tap values given in one or more of Equation 1, Equation 2, Table 1, and / or Table 2.

[0088] The receiver 600 includes an analog adder 610, an ISI pre-filter / first DFE tap 646, weighted buffers 632, 633, 634, tap logics 652, 653, 654, registers 662, 663, and 664. The ISI pre-filter / first DFE tap 646 includes weighted buffers 641, 642, an analog adder 611, and a sampler 620. In one embodiment, the sampler 620 is a PAM-4 sampler (e.g., similar to or the same as the PAM-4 sampler 320 or 420) and outputs a plurality of decision bits accordingly. In another embodiment, the sampler 620 is a PAM-2 sampler that outputs a single decision bit (e.g., similar to or the same as the sampler 322 or sampler 422).

[0089] The input signal (IN) is operably coupled to the input of the adder 610. For example, the input signal (IN) can be received from the interconnect system 140. The output of the adder 610 is input to the ISI pre-filter / first DFE tap 646. Specifically, the output of the adder 610 is input to the weighted buffer 641. The weighted buffer 641 multiplies the analog voltage at the input of the weighted buffer 641 by a factor K0 and outputs it. In one embodiment, K0 = 1 + 0.5α1, where α1 is adapted or selected to remove the first post-mark ISI component. When α1 is dynamically adapted, it should be understood that K0 can be variable during the adjustment (i.e., training) period, but it is usually constant during normal operation.

[0090] The outputs of the weighted buffer 641 and the weighted buffer 642 are input to the analog adder 611. The output of the analog adder 611 is input to the sampler 620. The output of the sampler 620 is input to the weighted buffer 642. The weighted buffer 642 multiplies the analog voltage at the input of the weighted buffer 642 by a factor -K1 and outputs it. In one embodiment, K1 = 0.5α1. Similar to K0, it should be understood that K1 can be variable during the adaptation (i.e., training) period, but it is usually constant during normal operation.

[0091] Each of the sampler 620 and the registers 662 - 664 receives a timing reference (not shown in Figure 6 ). This timing reference (e.g., Figure 3A and Figure 3BThe CK) determines the timing for the sampler 620 to compare its input (i.e., the output of the adder 611) with a reference (or threshold) voltage to generate a corresponding digital output signal. The register 662 receives the output of the sampler 620. The registers 663 - 664 serially receive the outputs of the previous registers 662 - 664, thereby forming a serial shift register that holds the previous values sampled by the sampler 620 for each successive stage.

[0092] The output of the sampler 620 is also input to the tap logic 652. The tap logic 652 subtracts the output of the sampler 620 from the output of the register 662. The output of the tap logic 652 is input to the weighted buffer 632. The weighted buffer 632 multiplies the analog voltage at the input of the weighted buffer 632 by the factor -K2 and outputs it. In one embodiment, K2 = 0.5α2. The output of the weighted buffer 633 is input to the adder 610, thereby completing the second DFE tap loop. The output of the register 662 is also input to the tap logic 653. The tap logic 653 subtracts the output of the register 662 from the output of the register 663. The output of the tap logic 653 is input to the weighted buffer 633. The weighted buffer 633 multiplies the analog voltage at the input of the weighted buffer 633 by the factor -K3 and outputs it. In one embodiment, K3 = 0.5α3. The output of the weighted buffer 633 is input to the adder 610, thereby completing the third DFE tap loop. The output of the register 663 is also input to the tap logic 654. The tap logic 654 subtracts the output of the register 663 from the output of the register 664. The output of the tap logic 654 is input to the weighted buffer 634. The weighted buffer 634 multiplies the analog voltage at the input of the weighted buffer 634 by the factor -K4 and outputs it. In one embodiment, K4 = 0.5α4. The output of the weighted buffer 634 is input to the adder 610, thereby completing the fourth DFE tap loop. Additional higher-order DFE tap loops can be formed in a similar manner.

[0093] Figure 7 Illustrated is a non-speculative DFE receiver with low-latency DFE tap feedback. Figure 7 The receiver 700 illustrated in can correspond to one or more of the receivers 150, receiver 214, and / or receiver 224. In one embodiment, the receiver 700 can be configured to implement the DFE tap values as described herein. In particular, the receiver 700 can implement the DFE tap values given in one or more of Equation 1, Equation 2, Table 1, and / or Table 2.

[0094] The receiver 700 includes an analog adder 710, an ISI pre-filter / first DFE tap 746, weighted buffers 732, 733, 734, 735, registers 762 and 763. The ISI pre-filter / first DFE tap 746 includes weighted buffers 741, 742, an analog adder 711, and a sampler 720. In an embodiment, the sampler 720 is a PAM-4 sampler (e.g., similar or identical to the PAM-4 sampler 320 or 420) and accordingly outputs a plurality of decision bits. In another embodiment, the sampler 720 is a PAM-2 sampler that outputs a single decision bit (e.g., similar or identical to the sampler 322 or the sampler 422).

[0095] The input signal (IN) is operatively coupled to the input of the adder 710. For example, the input signal (IN) can be received from the interconnect system 140. The output of the adder 710 is input to the ISI pre-filter / first DFE tap 746. In particular, the output of the adder 710 is input to the weighted buffer 741. The weighted buffer 741 multiplies the analog voltage at the input of the weighted buffer 741 by a factor K0 and outputs it. In one embodiment, K0 = 1 + 0.5α1, where α1 is adapted or selected to remove the first post-mark ISI component. When α1 is dynamically adapted, it should be understood that K0 can be variable during the adaptation (i.e., training) period, but it is typically constant during normal operation.

[0096] The outputs of the weighted buffer 741 and the weighted buffer 742 are input to the analog adder 711. The output of the analog adder 711 is input to the sampler 720. The output of the sampler 720 is input to the weighted buffer 742. In one embodiment, K1 = 0.5α1. Similar to K0, it should be understood that K1 can be variable during the adaptation (i.e., training) period, but it is typically constant during normal operation.

[0097] The sampler 720 and each of the registers 762 - 764 receive a timing reference (not shown in Figure 7 ). This timing reference (e.g., Figure 3A and Figure 3B CK) determines the timing at which the sampler 720 compares its input (i.e., the output of the adder 711) with a (one or more) reference (or threshold) voltage to produce a corresponding digital output signal. The register 762 receives the output of the sampler 720. The register 763 etc. each serially receive the outputs of the previous registers 762 - 763, thereby forming a serial shift register that holds the previous values sampled by the sampler 720 for each successive stage.

[0098] The output of sampler 720 is also input to weighted buffer 732. Weighted buffer 732 multiplies the analog voltage at the input of weighted buffer 732 by factor +K2 and outputs it. The output of register 762 is input to weighted buffer 733. Weighted buffer 733 multiplies the analog voltage at the input of weighted buffer 733 by factor -K2 and outputs it. In one embodiment, K2 = 0.5α2. The output of weighted buffer 732 and the output of weighted buffer 732 are input to adder 710, thereby completing the second DFE tap loop. The output of register 762 is also input to weighted buffer 734. Weighted buffer 734 multiplies the analog voltage at the input of weighted buffer 734 by factor +K3 and outputs it. The output of weighted buffer 734 and the output of weighted buffer 735 (weighted buffer 735 receives the output of register 763, not shown in Figure 7 and is input to adder 710, thereby completing the third DFE tap loop. Additional higher-order DFE tap loops can be formed in a similar manner.

[0099] Figure 8 FIG. illustrates a PAM-4 receiver with low-latency DFE feedback. Figure 8 The receiver 800 illustrated in can correspond to one or more of receivers 150, 214, and / or 224. In one embodiment, receiver 800 can be configured to implement the DFE tap values as described herein. In particular, receiver 800 can implement the DFE tap values given in one or more of Equation 1, Equation 2, Table 1, and / or Table 2.

[0100] Receiver 800 includes analog adder 810, samplers 821, 822, 823, weighted buffers 831, 832, and 833. Weighted buffers 831 - 833 receive digital signals decoded as +1 or -1. Weighted buffers 831 - 833 apply (e.g., multiply) a weighting factor (-α) to the input value and output an analog voltage corresponding to the weighted input signal. For example, when weighted buffer 831 receives a logic "0" (decoded as referring to -1), weighted buffer 831 applies a weighting factor of -α and outputs an analog signal corresponding to -1 × -α = α volts. When weighted buffer 831 receives a logic "1" (which is decoded as referring to +1), weighted buffer 831 applies a weighting factor of -α and outputs an analog signal corresponding to +1 × -α = -αV.

[0101] The input signal (IN) is operatively coupled to the input of adder 810. For example, the input signal (IN) may be received from the interconnect system 140. The output of adder 810 is input to the PAM-4 sampler 820. The output of analog adder 810 is input to the non-inverting inputs of samplers 821-823. The inverting input of sampler 821 receives the reference voltage Vref1. The inverting input of sampler 822 receives the reference voltage Vref2. The inverting input of sampler 823 receives the reference voltage Vref3. The reference voltages Vref1, Vref2, and Vref3 are typically selected to be between the PAM-4 voltage levels. For example, if the four PAM-4 levels are -3V, -1V, +1V, and +3V, then Vref1 may be selected to be -2V, Vref2 = 0V, and Vref3 = +2V.

[0102] Samplers 821-823 each receive the timing reference CK. CK determines the timing at which samplers 821-823 compare the input (i.e., the output of adder 811) with their respective reference voltages (e.g., Vref1, etc.) to produce their respective digital output signals. The output of sampler 821 is input to the weighted buffer 831. The output of sampler 822 is input to the weighted buffer 832. The output of sampler 823 is input to the weighted buffer 833. Weighted buffers 831-833 each apply (e.g., multiply) the same weighting factor (i.e., -α) to their respective input values and output the corresponding analog voltages corresponding to the weighted input signals. Note that when Vref3 > Vref2 > Vref1, the output OUT[1:3] of the PAM-4 sampler 820 is encoded as a 3-bit thermometer code. This 3-bit thermometer code is not decoded before being applied to the inputs of weighted buffers 831-833. The lack of this decoding logic helps to reduce the latency from the CK timing reference that causes samplers 821-823 to sample to applying the DFE tap values to adder 810.

[0103] Figure 9 Illustrated is a PAM-4 receiver with DFE feedback. Figure 9 The receiver 900 illustrated in may correspond to one or more of receivers 150, 214, and / or 224. In one embodiment, the receiver 900 may be configured to implement the DFE tap values as described herein. In particular, the receiver 900 may implement the DFE tap values given in one or more of Equation 1, Equation 2, Table 1, and / or Table 2.

[0104] The receiver 900 includes an analog adder 910, samplers 921, 922, 923, 924, 925, 926, weighted buffers 931, 932, 933, 935, 936, 937, and a sample and hold (S / H) 990.

[0105] The input signal (IN) is operatively coupled to the input of the S / H 990 and the non-inverting inputs of the samplers 925 - 927. For example, the input signal (IN) can be received from the interconnect system 140. The output of the S / H 990 is input to the adder 910. The output of the analog adder 910 is input to the non-inverting inputs of the samplers 921 - 923. The inverting input of the sampler 921 receives the reference voltage Vref1. The inverting input of the sampler 922 receives the reference voltage Vref2. The inverting input of the sampler 923 receives the reference voltage Vref3. The inverting input of the sampler 925 receives the reference voltage Vref5. The inverting input of the sampler 926 receives the reference voltage Vref6. The inverting input of the sampler 923 receives the reference voltage Vref7. The reference voltages Vref1, Vref2, Vref3, Vref5, Vref6, and Vref7 are typically selected to be between the PAM-4 voltage levels. For example, if the four PAM-4 levels are -3V, -1V, +1V, and +3V, then Vref1 and Vref5 can be selected to be -2V, Vref2 = Vref6 = 0V, and Vref3 = Vref7 = +2V.

[0106] The samplers 921 - 923 and 925 - 927 each receive a timing reference CK. CK determines the timing at which the samplers 921 - 923 and 925 - 927 compare their inputs (i.e., the input voltage and output of the adder 910) with their respective reference voltages (e.g., Vref1, etc.) to produce their respective digital output signals. The output of the sampler 921 is input to the weighted buffer 931. The output of the sampler 922 is input to the weighted buffer 932. The output of the sampler 923 is input to the weighted buffer 933. The output of the sampler 925 is input to the weighted buffer 935. The output of the sampler 926 is input to the weighted buffer 936. The output of the sampler 927 is input to the weighted buffer 937. The weighted buffers 931 - 933 each apply (e.g., multiply) the same weighting factor (i.e., -K1) to their respective input values and output the corresponding analog voltages corresponding to the weighted input signals. In Figure 9In [the figure], each of weighted buffers 935 - 937 applies (e.g., multiplies) the same weighting factor (i.e., +Kc) to their respective input values and outputs a corresponding analog voltage corresponding to the weighted input signal. However, it should be understood that in some embodiments, weighted buffers 935 - 937 apply (e.g., multiply) different weighting factors. Additionally, in one embodiment, Kc = K1. In another embodiment, Kc ≠ K1.

[0107] The voltages at the inputs of samplers 931 - 933 can be represented by the equations in Table 5. In Table 5, v m is the received voltage; m is the time index; h0, h1, h2, etc. are the discrete - time voltage values of the single - bit response of the channel (e.g., interconnect system 140); a m is the m - th transmitted symbol.

[0108]

[0109] Figure 10 The figure illustrates a receiver with DFE feedback. In Figure 10 The receiver 1000 illustrated in [the figure] can correspond to one or more of receiver 150, receiver 214, and / or receiver 224. Receiver 1000 includes analog adder 1010, sampler 1021, sampler 1022, weighted buffer 1031, weighted buffer 1032, and sample - and - hold (S / H) 1090. In one embodiment, samplers 1021 - 1022 can be PAM - 2 samplers. In another embodiment, samplers 1021 - 1022 can be PAM - 4 samplers.

[0110] The input signal (IN) is operably coupled to the input of S / H 1090 and the input of sampler 1021. For example, the input signal (IN) can be received from interconnect system 140. The output of S / H 1090 is input to adder 1010. The output of analog adder 1010 is input to sampler 1022.

[0111] Samplers 1021 - 1023 and 1025 - 1027 each receive a timing reference (not shown in Figure 10 ). The output of sampler 1021 is input to weighted buffer 1031. The output of sampler 1022 is input to weighted buffer 1032. The output of sampler 1022 is the output OUT of receiver 1000. Weighted buffer 1031 applies (e.g., multiplies) a first weighting factor (i.e., +K) to its respective input value and outputs a corresponding analog voltage corresponding to the weighted input signal. Weighted buffer 1032 applies (e.g., multiplies) a second weighting factor (i.e., -K) to its respective input value and outputs a corresponding analog voltage corresponding to the weighted input signal.

[0112] Figure 11 Illustrates a receiver with higher-order DFE feedback. Figure 11 The illustrated receiver 1100 may correspond to one or more of receivers 150, 214, and / or 224. Receiver 1100 includes analog adder 1110, first DFE tap 1146, weighted buffers 1132, 1133, 1134, tap logic 1152, 1153, 1154, registers 1162, 1163, and 1164. First DFE tap 1146 includes analog adder 1111, samplers 1121, 1122, weighted buffers 1131, 1132, and sample-and-hold (S / H) 1190. In one embodiment, sampler 1120 is a PAM-4 sampler (e.g., similar or identical to PAM-4 sampler 320 or 420) and outputs multiple decision bits accordingly. In another embodiment, sampler 1120 is a PAM-2 sampler that outputs a single decision bit (e.g., similar or identical to sampler 322 or sampler 422).

[0113] Input signal (IN) is operably coupled to the input of adder 1110. For example, input signal (IN) may be received from interconnect system 140. The output of adder 1110 is input to first DFE tap 1146. In particular, the output of adder 1110 is input to S / H 1190 and sampler 1121.

[0114] The outputs of weighted buffers 1131 and 1132 are input to analog adder 1111. The output of analog adder 1111 is input to sampler 1122. The output of sampler 1122 is input to tap logic 1152.

[0115] Samplers 1122, 1121, and each of registers 1162 - 1164 receive a timing reference (not shown Figure 11 in the Figure 3A figure). This timing reference (e.g., Figure 3B CK of

[0116] The output of sampler 1122 is also input to tap logic 1152. Tap logic 1152 subtracts the output of register 1162 from the output of sampler 1122. The output of tap logic 1152 is input to weighted buffer 1132. Weighted buffer 1132 multiplies the analog voltage at the input of weighted buffer 1132 by factor -K2 and outputs it. In one embodiment, K2 = 0.5α2. The output of weighted buffer 1132 is input to adder 1110, thus completing the second DFE tap loop. The output of register 1162 is also input to tap logic 1153. Tap logic 1153 subtracts the output of register 1163 from the output of register 1162. The output of tap logic 1153 is input to weighted buffer 1133. Weighted buffer 1133 multiplies the analog voltage at the input of weighted buffer 1133 by factor -K3 and outputs it. In one embodiment, K3 = 0.5α3. The output of weighted buffer 1133 is input to adder 1110, thus completing the third DFE tap loop. The output of register 1163 is also input to tap logic 1154. Tap logic 1154 subtracts the output of register 1164 from the output of register 1163. The output of tap logic 1154 is input to weighted buffer 1134. Weighted buffer 1134 multiplies the analog voltage at the input of weighted buffer 1132 by factor -K4 and outputs it. In one embodiment, K4 = 0.5α4. The output of weighted buffer 1134 is input to adder 1110, thus completing the fourth DFE tap loop. Additional higher-order DFE tap loops can be formed in a similar manner.

[0117] Figure 12 A communication system with non-uniform transmit equalization and speculative DFE is illustrated. Communication system 1200 includes a driver integrated circuit, a receiver integrated circuit, and an interconnect therebetween. The driver integrated circuit includes transmitter circuit 1210 (also referred to as a driver). Transmit finite impulse response (FIR) logic 1275 controls transmitter circuit 1210 to achieve non-uniform transmit equalization.

[0118] The receiver integrated circuit includes receiver circuit 1250. The interconnect between the driver integrated circuit and the receiver integrated circuit includes interconnect system 1240. Interconnect system 1240 will generally include a printed circuit (PC) board, connectors, cables, flexible circuits, other substrates, and / or combinations thereof. Interconnect system 1240 can be and / or include one or more transmission lines.

[0119] Receiver circuit 1250 will generally be part of an integrated circuit that receives signals transmitted by the driver integrated circuit. It should be understood that termination (not shown in Figure 12as shown) may be part of integrated circuit or interconnect system 1240. It should also be understood that although system 1200 is shown as transmitting single-ended signals, the signals transmitted by the driver integrated circuit of system 1200 may represent one signal of a pair of differential signals, or one signal of a set of signals transmitting multi-line encoded data.

[0120] In Figure 12 it, the output of transmitter circuit 1210 is connected to the first end of interconnect system 1240. The second end of interconnect system 1240 is connected to the input of receiver 1250. Transmitter circuit 1210 is configured to drive PAM-4 signal levels.

[0121] In one embodiment, receiver 1250 is a speculative DFE receiver. FIR logic 1275 applies non-uniform pre-emphasis to the PAM-4 output signal. The non-uniform pre-emphasis output by transmitter circuit 1210 under the control of FIR logic 1275 is selected such that after passing through interconnect system 1420, even if the previous symbols are different, multiple received PAM-4 voltage levels effectively have the same value. For example, through uniform pre-emphasis (or no pre-emphasis), non-ideal characteristics of interconnect system 1240 (e.g., ISI) may cause up to 13 voltage levels (but still only representing 4 PAM-4 symbols) to reach receiver 1250. The non-uniform emphasis applied by FIR logic 1275 reduces the number of different voltage levels at the input to receiver 1250. Thus, in one embodiment, non-uniform pre-emphasis allows speculative DFE receiver 1250 to accurately sample a particular PAM-4 transition transmitted by transmitter circuit 1210 by using a reduced number of comparators. For example, by applying appropriate non-uniform pre-emphasis, the number of voltage levels reaching receiver 1250 can be reduced from 13 voltage levels (which require 12 comparators to sample) to 6 voltage levels (which can be sampled with 5 comparators).

[0122] Figure 13A illustrates an example of non-uniform transmit equalization. In Figure 13A it, for two example PAM-4 transitions - from -1 to +3 and from -3 to +3, a piecewise linear approximation of the signal output by transmitter 1210 (under the control of FIR logic 1275) is shown. The equalized PAM-4 transition from -3 to +3 is shown as a transition from -3 voltage levels to a +3 + α voltage levels. The equalized PAM-4 transition from -1 to +3 is shown as a simple transition from -1 voltage levels to +3 voltage levels. Thus, since the symbol after these two transitions is the +3 PAM-4 symbol, it can be seen that FIR logic 1275 is applying non-uniform pre-emphasis.

[0123] After passing through the channel (i.e., the interconnect system 1240), the bandwidth limitations, non-linearity, and other non-ideal properties of the interconnect system 1240 result in Figure 13A the graphical sketches shown on the right side. Although both sketches illustrate the same waveform, one of the waveforms is depicted as a piecewise linear approximation. This is done to better illustrate the results of non-linear equalization at the receiver. In particular, even though both transitions start from different states (-1 and -3) in the previous symbol period, both transitions (i.e., -1 to +3 and -3 to +3) result in substantially the same voltage at the sampling time in the next symbol period. In Figure 13A this case, the voltage is +3 - 2α.

[0124] Also as Figure 13A shown in +2b is the appropriate reference (or threshold) voltage (V +2b ) that will be used to determine whether the resulting symbol corresponds to the PAM-4 +3 level. V

[0125] Figure 13B is depicted as +2 - 2α. Figure 13B illustrates another example of non-uniform transmit equalization. In

[0126] this case, for two additional example PAM-4 transitions - from -1 to +1 and from -3 to +1, a piecewise linear approximation of the signal output by the transmitter 1210 (under the control of the FIR logic 1275) is shown. The equalized PAM-4 transition from -3 to +1 is shown as a transition from the -3 voltage level to the +1 + 2α voltage level. The equalized PAM-4 transition from -1 to +1 is shown as a transition from the -1 voltage level to the a + 1 + α voltage level. Thus, since the symbol after these two transitions is the +3 PAM-4 symbol, it can be seen that the FIR logic 1275 is applying non-uniform pre-emphasis.

[0126] After passing through the channel (i.e., the interconnect system 1240), the bandwidth limitations, non-linearity, and other non-ideal properties of the interconnect system 1240 result in Figure 13B the graphical sketches shown on the right side. Even though both transitions start from different states (-1 and -3) in the previous symbol period, both transitions (i.e., -1 to +3 and -3 to +3) result in substantially the same voltage at the sampling time for the next symbol period. In Figure 13B this case, the voltage is +1. Also shown in Figure 13B is the appropriate reference (or threshold) voltage (V0) for determining whether the resulting symbol corresponds to a positive (+1 or +3) or negative (-1 or -3) PAM-4 level. V0 is depicted as 0V.

[0127] Figure 13Cis a diagram showing the transmit level (voltage) obtained from all possible PAM-4 conversions, the corresponding received levels, and the appropriate threshold levels for distinguishing the received levels. In Figure 13C the conversions and levels illustrated are also given in Table 6. From Figure 13C and Table 6, it can be seen that the appropriate number of threshold levels is five. Therefore, for these signals with non-uniform pre-emphasis, only five comparators / samplers will be required to implement the speculative PAM-4 DFE receiver.

[0128]

[0129] It should be noted that for positive previous symbols (i.e., +1 or +3), only three appropriate threshold voltages are given: V -2b =-2 + 2α; V0 = 0, while V +2 = +2. Figure 14A illustrates the PAM-4 data eye converted from non-uniform equalization of the previous symbol of the positive sign. For negative previous symbols (i.e., -1 or -3), only three appropriate threshold voltages are given: V -2 = -2, V0 = 0 and V -2b = +2 - 2α. Figure 14B illustrates the PAM-4 data eye converted from non-uniform equalization of the previous symbol of the negative sign. It should also be noted that the threshold voltage V0 = 0 is used for both positive and negative previous symbols. Therefore, a sampler with a threshold voltage of V0 = 0 can be used to determine which set of samplers or threshold voltages (i.e., the set with V -2b , V0 and V -2 , or the set with V -2 , V0 and V +2b ) should be used to determine the current symbol.

[0130] Figure 15 illustrates a PAM-4 speculative DFE receiver with five comparators. Figure 15 The receiver 1500 illustrated in Figure 15 can correspond to one or more of receivers 150, 214, and / or 224. Receiver 1500 includes samplers 1523 - 1527, register 1560, multiplexer (MUX) 1580, MUX 1581, and decoding logic 1585. In Figure 15 , the input signal (IN) is operatively coupled to the non-inverting inputs of samplers 1523 - 1527. The inverting input of sampler 1523 (i.e., the reference or threshold voltage input) receives the reference voltage V -2 . The inverting input of sampler 1524 receives the reference voltage V -2b . The inverting input of sampler 1525 receives the reference voltage V0. The inverting input of sampler 1526 receives the reference voltage V +2b。The inverting input of sampler 1527 receives the reference voltage V +2 。

[0131] Each of samplers 1523 - 1527 receives the timing reference CK. CK determines the timing at which samplers 1523 - 1527 compare the input (i.e., IN) with their respective reference voltages (e.g., V -2 、V -2b etc.) to produce the timing of their respective digital output signals. The timing reference also determines when register 1560 latches and propagates the value on its input to its output. The output (OUT - 2) of sampler 1523 is input to the “0” input of MUX 1580. The output (OUT - 2B) of sampler 1524 is input to the “1” input of MUX 1580. The output (OUT0) of sampler 1525 is input to the input of logic 1585 and register 1560. The output (OUT + 2B) of sampler 1526 is input to the “0” input of MUX 1581. The output (OUT + 2) of sampler 1527 is input to the “1” input of MUX1581.

[0132] The select inputs (“S”) of MUX 1580 and MUX 1581 are received from the output of register 1560. Thus, the output of register 1560 is the result of comparing the input signal with the reference voltage V0 by sampler 1525. Since V0 is between the PAM - 4 levels of +1 and - 1, the output of register 1560 corresponds to the symbol of the previous symbol. In other words, when the previous symbol is a - 1 or a - 3, the output of register 1560 controls MUX 1580 - 1581 to select their “0” inputs. When the previous symbol is a + 1 or a + 3, the output of register 1560 controls MUX 1580 - 1581 to select their “1” inputs. The outputs of MUX 1580 - 1581 are received by logic 1585 to produce the received value OUT[0:1].

[0133] When the previous symbol is a - 1 or a - 3 (based on the output of register 1560), logic 1585 decodes the comparison result between IN and the reference voltages V -2 、V0 and V +2b When the previous symbol is a - 1 or a - 3 (based on the output of register 1560), logic 1585 decodes the comparison result between IN and the reference voltages V -2b 、V0 and V +2 In one embodiment, according to V -2 =-2, V -2b =-2 + 2α; V0 = 0, V -2b =+2 - 2α and V +2 =+2, the relative (to each other) voltage levels are used to select V-2b and V -2 and V0, V +2b and V -2 .

[0134] Figure 16 Illustrated is a PAM-4 speculative DFE receiver with second tap feedback. Figure 16 The illustrated receiver 1600 may correspond to one or more of receivers 150, 214, and / or 224. Receiver 1600 includes analog adder 1611, samplers 1623 - 1627, tap logic 1652, weighted buffer 1651, registers 1660, 1661, multiplexer (MUX) 1680, MUX 1681, and decoding logic 1685. In Figure 16 , an input signal (IN) is input to analog adder 1611. The output of analog adder 1611 is input to the non-inverting inputs of samplers 1623 - 1627. The inverting input of sampler 1623 (i.e., the reference or threshold voltage input) receives reference voltage V -2 . The inverting input of sampler 1624 receives reference voltage V -2b . The inverting input of sampler 1625 receives reference voltage V0. The inverting input of sampler 1626 receives reference voltage V +2b . The inverting input of sampler 1627 receives reference voltage V +2 .

[0135] Samplers 1623 - 1627 each receive timing reference CK. CK determines the timing at which samplers 1623 - 1627 compare an input (i.e., IN) with their respective reference voltages (e.g., V -2 , V -2b , etc.) to produce their respective digital output signals. The timing reference also determines when registers 1660 and 1661 latch the values on their respective inputs and propagate them to their respective outputs. The output of sampler 1623 (OUT-2) is input to the "0" input of MUX 1680. The output of sampler 1624 (OUT-2B) is input to the "1" input of MUX 1680. The output of sampler 1625 (OUT0) is input to logic 1685 and the input of register 1660. The output of sampler 1626 (OUT+2B) is input to the "0" input of MUX 1681. The output of sampler 1627 (OUT+2) is input to the "1" input of MUX 1681.

[0136] The select inputs (“S”) of MUX 1680 and MUX 1681 receive the output from register 1660. Thus, the output of register 1660 is the result of the sampler 1625 comparing the input signal with the reference voltage V0. Since V0 is between the PAM-4 levels of +1 and -1, the output of register 1660 corresponds to the symbol of the previous symbol. In other words, when the previous symbol is a-1 or a-3, the output of register 1660 controls MUX 1680-1581 to select their “0” inputs. When the previous symbol is a+1 or a+3, the output of register 1660 controls MUX 1680-1681 to select their “1” inputs. Logic 1685 receives the output of MUX1680-1681 to generate the received value OUT[0:1].

[0137] The output OUT[0:1] of logic 1685 is input to register 1661 and tap logic 1652. The output of register 1661 is input to tap logic 1652. Tap logic 1652 subtracts the output of register 1661 from the output of logic 1685. The output of tap logic 1652 is input to weighted buffer 1651. The output of weighted buffer 1651 is input to adder 1611, thus completing the second tap DFE loop. In one embodiment, according to V -2 =-2, V -2b =-2 + 2α; V0 = 0, V -2b =+2 - 2α and V +2 =+2, the relative (to each other) voltage levels of V -2b , V -2 , V0, V +2b and V -2 are selected.

[0138] Figure 17 The figure shows a PAM-4 speculative DFE receiver with a second tap feedback without subtraction. Figure 17 The receiver 1700 shown in can correspond to one or more of receivers 150, 214, and / or 224. Receiver 1700 includes an analog adder 1711, samplers 1723-1727, registers 1763, 1765, 1767, 1768, multiplexers (MUX) 1780, MUX 1781, decoder logic 1785, tap logic 1788, and (one or more) digital-to-analog converters 1798. In Figure 17 the input signal (IN) is input to analog adder 1711. The output of analog adder 1711 is input to the non-inverting inputs of samplers 1723-1727. The inverting input (i.e., the reference or threshold voltage input) of sampler 1723 receives the reference voltage V -2。The inverting input of sampler 1724 receives the reference voltage V -2b 。The inverting input of sampler 1725 receives the reference voltage V0. The inverting input of sampler 1726 receives the reference voltage V +2b 。The inverting input of sampler 1727 receives the reference voltage V +2 。

[0139] Each of samplers 1723 - 1727 receives the timing reference CK. CK determines the timing at which samplers 1723 - 1727 compare an input (i.e., IN) with their respective reference voltages (e.g., V -2 、V -2b etc.) to produce the timing of their respective digital output signals. The timing reference also determines when register 1760 latches and propagates the value on its input to its output. The output (OUT-2) of sampler 1723 is input to the "0" input of MUX 1780. The output (OUT-2B) of sampler 1724 is input to the "1" input of MUX 1780. The output (OUT0) of sampler 1725 is input to the input of logic 1785 and register 1765. The output (OUT+2B) of sampler 1726 is input to the "0" input of MUX 1781. The output (OUT+2) of sampler 1727 is input to the "1" input of MUX1781.

[0140] The select inputs ("S") of MUX 1780 and MUX 1781 are received from the output of register 1765. Thus, the output of register 1765 is the result of sampler 1725 comparing the input signal with the reference voltage V0. Since V0 is between the PAM-4 levels of +1 and -1, the output of register 1760 corresponds to the symbol of the previous symbol. In other words, when the previous symbol is a-1 or a-3, the output of register 1760 controls MUX 1780 - 1781 to select their "0" inputs. When the previous symbol is a+1 or a+3, the output of register 1760 controls MUX 1780 - 1781 to select their "1" inputs.

[0141] When the previous symbol is a-1 or a-3 (based on the output of register 1760), logic 1785 decodes the comparison result between IN and the reference voltages V -2 、V0 and V +2b 。When the previous symbol is a-1 or a-3 (based on the output of register 1765), logic 1785 decodes the comparison result (delayed by one symbol period by registers 1763, 1765, and 1767) between IN and the reference voltages V -2b 、V0 and V +2 。In one embodiment, according to V -2 =-2, V-2b = -2 + 2α; V0 = 0, V -2b = +2 - 2α and V +2 = +2 are selected for V with respect to (to each other) voltage levels -2b 、V -2 、V0、V +2b and V -2 。

[0142] The output of MUX 1780 is input to register 1763. The output of MUX 1781 is input to register 1767. The output of sampler 1725 is input to register 1765. Thus, the outputs of register 1763, register 1765, and register 1767 correspond to (in thermometer code) the previous PAM-4 symbol received via IN. The outputs of register 1763, register 1765, and register 1767 received by logic 1785 produce the received value OUT[0:1]. The outputs of register 1763, register 1765, and register 1767 are also received by tap logic 1788 to produce tap values from the current sampled result and the previous symbol. The tap values from logic 1788 are input to register 1768. The output of register 1768 is input to DAC 1798. The analog output of DAC 1798 is input to analog adder 1711, thus completing at least the second tap DFE loop.

[0143] Figure 18 is a flowchart illustrating a method of a non-speculative non-decoder for decision feedback equalization. Figure 18 The steps illustrated in can be performed by one or more elements of communication system 100, memory system 200, and / or communication system 1200. A first sampler decision indicator is generated based on a comparison between the equalized data signal and a first reference voltage (1802). For example, sampler 821 can compare the output of adder 810 with a threshold or reference voltage Vref1 to produce a value on OUT[1].

[0144] A second sampler decision indicator is generated based on a comparison between the equalized data signal and a second reference voltage (1804). For example, sampler 822 can compare the output of adder 810 with a threshold or reference voltage Vref2 to produce a value on OUT[2]. A third sampler decision indicator is generated based on a comparison between the equalized data signal and a third reference voltage (1806). For example, sampler 823 can compare the output of adder 810 with a threshold or reference voltage Vref3 to produce a value on OUT[3].

[0145] Based on the first sampler decision indicator, a first error removal voltage (1808) is generated. For example, based on OUT[1], the weighted buffer 831 can generate an analog error removal voltage that is provided to the adder 810. Based on the second sampler decision indicator, a second error removal voltage (1810) is generated. For example, based on OUT[2], the weighted buffer 831 can generate an analog error removal voltage that is provided to the adder 810. Based on the third sampler decision indicator, a third error removal voltage (1812) is generated. For example, based on OUT[3], the weighted buffer 831 can generate an analog error removal voltage that is provided to the adder 810.

[0146] The received data signal is added to the first removal error voltage, the second removal error voltage, and the third removal error voltage to generate an equalized data signal (1814). For example, the outputs of the weighted buffer 831, the weighted buffer 832, and the weighted buffer 833 are added to the input IN to generate an equalized data signal that is provided to the samplers 821 - 823.

[0147] Figures 19A to 19B is a flowchart illustrating a non - speculative method of decision feedback equalization. The steps illustrated in Figures 19A to 19B can be performed by one or more elements of the communication system 100 and / or the memory system 200. A first previous symbol sampler decision indicator is generated based on a comparison between the equalized data signal and a first reference voltage (1902). For example, the sampler 921 can compare the output of the adder 910 with a threshold or reference voltage Vref1 to generate a value on OUT[1]. A second previous symbol sampler decision indicator is generated based on a comparison between the equalized data signal and a second reference voltage (1904). For example, the sampler 922 can compare the output of the adder 910 with a threshold or reference voltage Vref2 to generate a value on OUT[2]. A third previous symbol sampler decision indicator is generated based on a comparison between the equalized data signal and a third reference voltage (1906). For example, the sampler 923 can compare the output of the adder 910 with a threshold or reference voltage Vref3 to generate a value on OUT[3].

[0148] Generate a first current symbol sampler decision indicator (1908) based on a comparison between a received data signal and a first reference voltage. For example, sampler 925 may compare the input voltage IN with a threshold or reference voltage Vref1 to generate a value that is input to weighted buffer 935. Generate a second current symbol sampler decision indicator (1910) based on a comparison between the received data signal and a second reference voltage. For example, sampler 926 may compare the input voltage IN with a threshold or reference voltage Vref2 to generate a value that is input to weighted buffer 936. Generate a third current symbol sampler decision indicator (1912) based on a comparison between the received data signal and a third reference voltage. For example, sampler 927 may compare the input voltage IN with a threshold or reference voltage Vref3 to generate a value that is input to weighted buffer 937.

[0149] Generate a first previous symbol error removal voltage (1914) based on the first previous symbol sampler decision indicator. By way of example, based on the input from sampler 921, weighted buffer 931 may generate an error removal voltage to be provided to adder 910. Generate a second previous symbol error removal voltage (1916) based on the second previous symbol sampler decision indicator. For example, based on the input from sampler 922, weighted buffer 932 may generate an error removal voltage to be provided to adder 910. Generate a third previous symbol error removal voltage (1918) based on the third previous symbol sampler decision indicator. For example, based on the input from sampler 923, weighted buffer 933 may generate an error removal voltage to be provided to adder 910.

[0150] Generate a first current symbol error removal voltage (1920) based on the first current symbol sampler decision indicator. For example, based on the input from sampler 921, weighted buffer 931 may generate an error removal voltage to be provided to adder 910. Generate a second current symbol error removal voltage (1922) based on the second current symbol sampler decision indicator. For example, based on the input from sampler 922, weighted buffer 932 may generate an error removal voltage to be provided to adder 910. Generate a third current symbol error removal voltage (1924) based on the third current symbol sampler decision indicator. For example, based on the input from sampler 923, weighted buffer 933 may generate an error removal voltage to be provided to adder 910.

[0151] The delayed version of the received data signal is added to the first previous symbol error removal voltage, the second previous symbol error removal voltage, the third previous symbol error removal voltage, the first current symbol error removal voltage, the second current symbol removal error voltage, and the third current symbol error removal voltage to produce an equalized data signal (1926). For example, adder 910 adds the inputs from S / H 990, weighted buffers 931 - 933, and weighted buffers 935 - 937 to produce the equalized data signal that is provided to samplers 921 - 933.

[0152] It should be understood that the received data signal IN is not sufficiently equalized when it is input to samplers 925 - 937. In one embodiment, the signal "IN" can already be equalized using a continuous time linear equalizer (CTLE) and a variable gain amplifier (VGA), both of which are present in the receiver analog front end (AFE) (not shown Figure 9 in the figure). Thus, the outputs of weighted buffers 935 - 937 can be based on incorrect decisions of samplers 925 - 927. However, the outputs of samplers 925 - 927 can be regarded as estimates of the current symbol and the selection of the weighting for the corresponding selected weighted buffers 935 - 937.

[0153] Figure 20 is a flowchart illustrating a non - speculative DFE using an analog FFE. Figure 20 The steps illustrated in the figure can be performed by one or more elements of communication system 100, memory system 200, and / or communication system 1200. A first sampler decision (2002) is generated by sampling a first analog output by an analog feed - forward equalizer that receives the equalized data signal. For example, the RxFFE 545 formed by S / H 540, weighted buffer 541, weighted buffer 542, and adder 511 can be sampled by sampler 522 to produce a sampler decision.

[0154] A first error removal voltage is generated by weighting the first sampler decision (2004). For example, weighted buffer 532 can weight the output of tap logic 552 to produce the error removal voltage that is input to adder 510, and the output of tap logic 552 is based on subtracting the sampler decision from sampler 520.

[0155] The received data signal and the first error removal voltage are added to produce an equalized data signal (2006). For example, adder 510 can add IN and the output of weighted buffer 532 to produce the input to S / H 540 and weighted buffer 542.

[0156] Figure 21 FIG. is a flow chart illustrating a non-speculative DFE using a combined receive FFE and first tap DFE loop. Figure 21 The steps illustrated in can be performed by one or more elements of communication system 100, memory system 200, and / or communication system 1200. By using the first DFE loop, a first sampler decision (2102) is generated based on a first error cancellation voltage and a weighted equalized data signal. For example, sampler 620 can generate a sampler decision based on the error cancellation voltage from weighted buffer 642, where weighted buffer 642 is part of a DFE loop formed by adder 611, sampler 620, and weighted buffer 642.

[0157] A weighted equalized data signal is generated by weighting the equalized data signal (2104). For example, weighted buffer 641 can weight the equalized data signal output by adder 610. A second error cancellation voltage is generated by weighting the first sampler decision (2106). For example, based on the output of tap logic 652, weighted buffer 632 can generate an error cancellation voltage that is input to adder 610, where the output of tap logic 652 is based on subtracting the sampler decision from sampler 620.

[0158] The input data signal and the second error cancellation voltage are added together to generate an equalized data signal (2108). For example, adder 610 can receive the output of weighted buffer 632 and add it to input signal IN to generate the input to weighted buffer 641.

[0159] Figure 22 FIG. illustrates a communication system having a receiver based on an analog-to-digital converter (ADC). Communication system 2200 includes a driver integrated circuit, a receiver integrated circuit, and an interconnect therebetween. The driver integrated circuit includes a transmitter circuit 2210 (also referred to as a driver). The receiver integrated circuit includes a variable gain amplifier (VGA) 2251, a continuous time linear equalizer (CTLE) 2252, an analog-to-digital converter 2290, a digital FFE+DFE 2295, a clock data recovery 2291, a phase adjuster 2293, and a phase locked loop 2292. The interconnect between the driver integrated circuit and the receiver integrated circuit includes an interconnect system 2240. Interconnect system 2240 will typically include a printed circuit (PC) board, connectors, cables, flexible circuits, other substrates, and / or combinations thereof. Interconnect system 2240 can be and / or include one or more transmission lines.

[0160] The receiver integrated circuit will typically be part of an integrated circuit that receives signals transmitted by the driver integrated circuit. It should be understood that termination (not shown in Figure 22as shown) can be part of integrated circuit or interconnect system 2240. It should also be understood that although system 2200 is shown as transmitting a single-ended signal, the driver integrated circuit of system 2200 can represent one signal of a pair of differential signals or one signal of a set of signals that transmit multi-line encoded data.

[0161] In Figure 22 the output of transmitter circuit 2210 is connected to the first end of interconnect system 2240. The second end of interconnect system 2240 is connected to the input of VGA 2251. The output of VGA 2251 is input to CTLE 2252. The output of CTLE 2252 is input to ADC 2290. The multi-bit and / or multi-sampled digital output of ADC 2290 is input to digital FFE+DFE 2295. Digital FFE+DFE 2295 is multi-bit decision OUT[1:N]. The output of digital FFE+DFE 2295 is input to CDR 2291. The recovered clock output by CDR 2291 is input to phase adjuster 2293. Phase adjuster 2293 also receives a clock signal from PLL 2292. The output of phase adjuster 2293 is used to control the timing of ADC 2290 to sample the output of CTLE 2290. Transmitter circuit 2210 can be configured to drive PAM-4 signaling levels.

[0162] Figure 23 illustrates a receiver with higher-order DFE feedback in the digital domain. Figure 23 The digital FFE+DFE 2300 shown can correspond to digital FFE+DFE 2295. Digital FFE+DFE 2300 includes digital adder 2310, FFE 2346, first DFE tap 2347, weighted buffers 2332, 2333, 2334, tap logics 2352, 2353, 2354, registers 2362, 2363, and 2364. FFE 2346 includes digital adder 2311, discrete-time derivative 2371, and weighted buffer 2331. First DFE tap 2347 includes sampler register 2361 and weighted buffer 2332. In one embodiment, digital FFE+DFE 2300 is configured to process samples of PAM-4 signals and thus receive multiple digital bits / samples (from, for example, ADC 2290) via IN and correspondingly output multiple decision bits. In another embodiment, digital FFE+DFE 2300 is configured to process samples of PAM-2 signals and thus can output only a single decision bit (e.g., OUT[1]).

[0163] A digital input signal (IN) that can be multiple bits and / or multiple samples is operably coupled to the input of adder 2310. The output of adder 2310 is input to FFE 2346. In particular, the output of adder 2310 is input to adder 2311 and discrete-time derivative 2371. In one embodiment, discrete-time derivative 2371 implements a delay and a subtraction such that discrete-time derivative 2371 outputs according to the following equation: ffe out = 1 - z -1 , where z -1 is the value at the input to discrete-time derivative 2371 during the previous iteration (i.e., z -1 represents the previous symbol input to discrete-time derivative 2371). In one embodiment, K1 = 0.5α1. Thus, it should be understood that K1 can be variable during the adaptation (i.e., training) period, but it is typically constant during normal operation.

[0164] The outputs of weighted buffer 2331, weighted buffer 2332, and adder 2310 are input to digital adder 2311. The output of adder 2311 is input to register 2361. The output of register 2361 is input to tap logic 2352 and weighted buffer 2332.

[0165] Discrete-time derivative 2371 and each of registers 2361 - 2364 receive a timing reference (not shown in Figure 23 ). Registers 2362 - 2364 each serially receive the outputs of the previous registers 2361 - 2264, thereby forming a serial shift register that holds the previous value output by adder 2311 for each successive stage.

[0166] The output of register 2361 is also input to tap logic 2352. Tap logic 2352 subtracts the output of register 2362 from the output of register 2361. The output of tap logic 2352 is input to weighted buffer 2332. Weighted buffer 2332 outputs the value at the input of weighted buffer 2332 multiplied by factor -K2. In one embodiment, K2 = 0.5α2. The output of weighted buffer 2332 is input to adder 2310, thus completing the second DFE tap loop. The output of register 2362 is also input to tap logic 2353. Tap logic 2353 subtracts the output of register 2363 from the output of register 2362. The output of tap logic 2353 is input to weighted buffer 2333. Weighted buffer 2333 outputs the value at the input of weighted buffer 2333 multiplied by factor -K3. In one embodiment, K3 = 0.5α3. The output of weighted buffer 2333 is input to adder 2310, thus completing the third DFE tap loop. The output of register 2363 is also input to tap logic 2354. Tap logic 2354 subtracts the output of register 2364 from the output of register 2363. The output of tap logic 2354 is input to weighted buffer 2334. Weighted buffer 2334 outputs the value at the input of weighted buffer 2334 multiplied by factor -K4. In one embodiment, K4 = 0.5α4. The output of weighted buffer 2334 is input to adder 2310, thereby completing the fourth DFE tap loop. Additional higher-order DFE tap loops can be formed in a similar manner.

[0167] Figure 24 is a flowchart illustrating a method for equalizing a data signal. In Figure 24 The steps illustrated can be performed by one or more elements of communication system 100, memory system 200, and / or communication system 1200. A data signal is received (2402). For example, receiver 300 can receive an input data signal at node IN. The data signal can be received by the S / H 340 and weighted buffer 342 of receiver 300.

[0168] Based on the current symbol received via the data signal and the previous symbol received via the data signal, an equalized data signal is generated (2404). For example, based on the current symbol received at node IN and based on the output of S / H 340 (which corresponds to the previous symbol received at node IN), adder 311 can output an equalized data signal to be sampled by PAM-4 sampler 320.

[0169] In one embodiment, a circuit for receiving a data signal and outputting an equalized data signal includes an adder that receives the data signal and outputs the equalized data signal. The circuit further includes a first error signal generator that provides a first error removal signal to the adder such that the equalized data signal is based on a current symbol received via the data signal and a previous symbol received via the data signal. The equalized data signal can be based on a difference between the current symbol and the previous symbol. The first error signal generator and the adder can be configured to form an analog feedforward equalization circuit. The first error signal generator and the adder can be configured to form an analog inter-symbol interference pre-filter and a first post-symbol decision feedback equalization loop. The first error signal generator and the adder can be configured to form an analog feedforward equalization circuit and a first post-symbol decision feedback equalization loop.

[0170] The circuit can further include a second error signal generator that provides a second error removal signal to the adder such that the equalized data signal is further based on a first prior symbol received via the data signal before the current symbol and a second prior symbol received continuously after the first prior symbol. The second error signal generator can be configured to make the second error removal signal based on the first prior symbol and the second prior symbol without using combinational logic between a first storage element storing the first prior symbol and the adder. The data signal can be received by the adder in digital form, and the first error signal generator and the adder can be configured to form a discrete-time digital feedforward equalization circuit.

[0171] In one embodiment, a method of equalizing a data signal includes: receiving the data signal and generating an equalized data signal based on a current symbol received via the data signal and a previous symbol received via the data signal. The equalized data signal can be based on a difference between the current symbol and the previous symbol. The equalized data signal can be generated by an analog feedforward equalization circuit. The equalized data signal can be generated by a circuit configured to form an analog inter-symbol interference pre-filter and a first post-symbol decision feedback equalization loop. The equalized data signal can be generated by a circuit configured to form an analog feedforward equalization circuit and a first post-symbol decision feedback equalization loop. The equalized data signal can be further based on a first prior symbol received via the data signal before the current symbol and a second prior symbol received continuously after the first prior symbol.

[0172] The equalized data signal can be further based on the first prior symbol and the second prior symbol without using combinational logic between an adder for generating the equalized data signal and a plurality of storage elements that store at least the first prior symbol and the second prior symbol. A discrete-time digital feed-forward equalization circuit can receive a data signal in digital form and can generate an equalized data signal in digital form.

[0173] In one embodiment, a communication system includes a transmitter that transmits a data signal with non-uniform pre-emphasis. The non-uniform pre-emphasis is applied to transitions from a first plurality of output states to a first output state. The non-uniform pre-emphasis is also applied to transitions from a second plurality of output states to a second output state. The non-uniform pre-emphasis is applied such that transitions of the data signal from corresponding states in the first plurality of first output states are to be received at a substantially first voltage level at a receiver sampling time after passing through a band-limited channel. Similarly, the non-uniform pre-emphasis is further applied such that transitions of the data signal from corresponding states in the second plurality of output states are to be received at a substantially second voltage level at the receiver sampling time after passing through the band-limited channel. The communication system further includes a receiver for receiving the data signal with non-uniform pre-emphasis after the data signal has passed through the band-limited channel. The receiver selects between a first set of comparator outputs and a second set of comparator outputs based on a first comparator output sampled at a previous receiver sampling time. The selected set of comparator outputs is used to determine the output of the receiver corresponding to the receiver sampling time.

[0174] There can be three comparator outputs in each of the first set of comparator outputs and the second set of comparator outputs. The first comparator output can be based on a first reference voltage. The first comparator output in the selected set of comparator outputs can be based on the first reference voltage. The second comparator output in the selected set of comparator outputs can be based on a second reference voltage. The third comparator output in the selected set of comparator outputs can be based on a third reference voltage. The third reference voltage can be greater than the first reference voltage. The second reference voltage can be less than the first reference voltage.

[0175] In one embodiment, a communication system includes a transmitter that transmits a data signal with non-uniform pre-emphasis. The non-uniform pre-emphasis is applied to transitions from a first output state, a second output state, and a third output state to a fourth output state. The non-uniform pre-emphasis is applied such that transitions of the data signal from at least the first output state and the second output state to the fourth output state will be received at substantially the same voltage level at a receiver sampling time after passing through a band-limited channel. The communication system further includes a receiver. After the data signal has passed through the band-limited channel, the receiver is configured to receive the data signal with non-uniform pre-emphasis. The receiver uses a first reference voltage to detect the fourth output state after a transition from the first output state and the second output state to the fourth output state. The receiver also uses the second reference voltage to detect the fourth output state after a transition from the third output state to the fourth output state.

[0176] The receiver may include a first sampler configured to generate a previous symbol sampler decision indicator based on a comparison of the data signal with a first reference voltage during a previous symbol time. The first sampler also generates a first sampler decision based on a comparison of the data signal with the first reference voltage during a current symbol time. The receiver may further include a second sampler configured to generate a second sampler decision based on a comparison of the data signal with a second reference voltage during the current symbol time. The receiver may further include a third sampler configured to generate a first sampler decision based on a comparison of the data signal with a third reference voltage during the current symbol time. The receiver may further include a fourth sampler configured to generate a second sampler decision based on a comparison of the data signal with a fourth reference voltage during the current symbol time. The receiver may further include a fifth sampler configured to generate a second sampler decision based on a comparison of the data signal with a fifth reference voltage during the current symbol time. The receiver may further include a selection logic configured to generate an output bit using the second sampler decision and the fourth sampler decision based on a first value of the previous symbol sampler decision indicator, and to generate the output bit using the third sampler decision and the fifth sampler decision based on a second value of the previous symbol sampler decision indicator.

[0177] The third reference voltage may be greater than the second reference voltage. The first reference voltage may be greater than the third reference voltage. The fourth reference voltage may be greater than the first reference voltage. The fifth reference voltage may be greater than the fourth reference voltage. The selection logic may include a first multiplexer that selects between the second sampler decision and the third sampler decision and a second multiplexer that selects between the fourth sampler decision and the fifth sampler decision. The output bit may correspond to a four-level pulse amplitude modulation (PAM-4) signaling level. The non-uniform pre-emphasis may be applied to the transmitted data signal such that the transmitted data signal will be received at substantially the same voltage level at the receiver sampling time for transitions from at least a first output state and a second output state to a third output state.

[0178] In one embodiment, a receiver circuit may include: a data signal input for receiving a data signal transmitted with non-uniform pre-emphasis; a first sampler for generating a previous symbol sampler decision indicator based on a comparison of the data signal with a first reference voltage during a previous symbol time, wherein the first sampler also generates a first sampler decision based on a comparison of the data signal with the first reference voltage during a current symbol time; a second sampler for generating a second sampler decision based on a comparison of the data signal with a second reference voltage during the current symbol time; a third sampler for generating a first sampler decision based on a comparison of the data signal with a third reference voltage during the current symbol time; a fourth sampler for generating a second sampler decision based on a comparison of the data signal with a fourth reference voltage during the current symbol time; a fifth sampler for generating a second sampler decision based on a comparison of the data signal with a fifth reference voltage during the current symbol time; and selection logic for generating an output bit using the second sampler decision and the fourth sampler decision based on a first value of the previous symbol sampler decision indicator. The selection logic also generates an output bit using the third sampler decision and the fifth sampler decision based on a second value of the previous symbol sampler decision indicator.

[0179] The third reference voltage may be greater than the second reference voltage. The first reference voltage may be greater than the third reference voltage. The fourth reference voltage may be greater than the first reference voltage. The fifth reference voltage may be greater than the fourth reference voltage. The selection logic may include a first multiplexer for selecting between the second sampler decision and the third sampler decision and a second multiplexer for selecting between the fourth sampler decision and the fifth sampler decision. The output bit may correspond to a four-level pulse amplitude modulation (PAM-4) signaling level.

[0180] The non-uniform pre-emphasis can be applied to the transmitted data signal such that transitions of the transmitted data signal from at least a first output state and a second output state to a third output state will be received at substantially the same voltage level at the receiver sampling time after passing through a band-limited channel. The non-uniform pre-emphasis can be applied by a transmit integrated circuit using a finite impulse response filter. The non-uniform pre-emphasis can be applied by the transmit integrated circuit to four-level pulse amplitude modulation (PAM-4) signaling levels. The receiver circuit can be included in a memory device. The receiver circuit can be included in a memory controller.

[0181] In one embodiment, an integrated circuit can include an output for coupling to a band-limited channel; and a transmitter for transmitting a data signal via the band-limited channel. The data signal has non-uniform pre-emphasis. The non-uniform pre-emphasis is applied to transitions from a first output state, a second output state, and a third output state to a fourth output state. Applying the non-uniform pre-emphasis by the transmitter causes transitions of the data signal from at least the first output state and the second output state to the fourth output state to be received at substantially the same voltage level at the receiver sampling time after passing through the band-limited channel.

[0182] The data signal can be received by a receive integrated circuit that uses a first reference voltage to detect the fourth output state after transitions from the first output state and the second output state to the fourth output state. The integrated circuit also uses a second reference voltage to detect the fourth output state after transitions from the third output state to the fourth output state.

[0183] The integrated circuit may further include a first sampler for generating a previous symbol sampler decision indicator based on a comparison of the data signal with a first reference voltage during a previous symbol time. The first sampler also generates a first sampler decision based on a comparison of the data signal with the first reference voltage during a current symbol time. The integrated circuit may further include a second sampler for generating a second sampler decision based on a comparison of the data signal with a second reference voltage during the current symbol time. The integrated circuit may further include a third sampler for generating a first sampler decision based on a comparison of the data signal with a third reference voltage during the current symbol time. A fourth sampler is for generating a second sampler decision based on a comparison of the data signal with a fourth reference voltage during the current symbol time. The integrated circuit may further include a fifth sampler for generating a second sampler decision based on a comparison of the data signal with a fifth reference voltage during the current symbol time. The integrated circuit may further include selection logic for generating an output bit using the second sampler decision and the fourth sampler decision based on a first value of the previous symbol sampler decision indicator, and for generating the output bit using the third sampler decision and the fifth sampler decision based on a second value of the previous symbol sampler decision indicator.

[0184] The third reference voltage may be greater than the second reference voltage. The first reference voltage may be greater than the third reference voltage. The fourth reference voltage may be greater than the first reference voltage. The fifth reference voltage may be greater than the fourth reference voltage. The receiving integrated circuit may be a memory device.

[0185] In one embodiment, a decision feedback equalizer includes: a first previous symbol sampler configured to compare an equalized data signal with a first reference voltage to generate a first previous symbol sampler decision; a second previous symbol sampler configured to compare the equalized data signal with a second reference voltage to generate a second previous symbol sampler decision; a first current symbol sampler configured to compare a received data signal with a first reference voltage to generate a first current symbol sampler decision; a second current symbol sampler configured to compare the received data signal with a second reference voltage to generate a second current symbol sampler decision; and an analog adder circuit configured to receive a first previous symbol error cancellation voltage based on the first previous symbol sampler decision, and to receive a second previous symbol error cancellation voltage based on the second previous symbol sampler decision, and to receive a first current symbol error cancellation voltage based on the first current symbol sampler decision, and to receive a second current symbol error cancellation voltage based on the second current symbol sampler decision, and to generate the equalized data signal based on a delayed version of the received data signal, the first previous symbol error cancellation voltage, the second previous symbol error cancellation voltage, the first current symbol error cancellation voltage, and the second current symbol error cancellation voltage.

[0186] The first data sampler and the second data sampler may be part of a PAM-4 sampler. The first previous symbol error cancellation voltage, the second previous symbol error cancellation voltage, the first current symbol error cancellation voltage, and the second current symbol error cancellation voltage may have substantially equal magnitudes. The first previous symbol sampler decision may determine a first sign of the first previous symbol error cancellation voltage. The first current symbol sampler decision may determine a second sign of the first current symbol error cancellation voltage. The first sign and the second sign may be opposite signs when the first previous symbol sampler decision and the first current symbol sampler decision indicate the same comparison result with the respective first reference voltage. The delayed version of the received data signal may be generated by an analog sample and hold circuit that receives the received data signal.

[0187] The decision feedback equalizer may further include: a third previous symbol sampler for comparing the equalized data signal with a third reference voltage to generate a third previous symbol sampler decision; a third current symbol sampler for comparing the received data signal with the third reference voltage to generate a third current symbol sampler decision, wherein an analog adder is further configured to receive a third previous symbol error cancellation voltage based on the third previous symbol sampler decision, and receive a third current symbol error cancellation voltage based on the third current symbol sampler decision, and the equalized data signal is further based on the third previous symbol error cancellation voltage and the third current symbol error cancellation voltage.

[0188] The first previous symbol error cancellation voltage, the second previous symbol error cancellation voltage, and the third previous symbol error cancellation voltage, the first current symbol error cancellation voltage, the second current symbol error cancellation voltage, and the third current symbol error cancellation voltage may have substantially equal magnitudes. A first difference between the first reference voltage and the second reference voltage and a second difference between the second reference voltage and the third reference voltage may be approximately equal. The first previous symbol error cancellation voltage and the second previous symbol error cancellation voltage may have substantially different magnitudes, thereby achieving unique decision feedback weighting for the first previous symbol sampler decision and the second previous sampler decision. The first current symbol error cancellation voltage and the second current symbol error cancellation voltage may have substantially different magnitudes, thereby achieving unique decision feedback weighting for the first current symbol sampler decision and the second current symbol sampler decision.

[0189] A method for receiving a data signal includes: generating a first previous symbol sampler decision indicator based on a comparison between an equalized data signal and a first reference voltage; generating a second previous symbol sampler decision indicator based on a comparison between the equalized data signal and a second reference voltage; generating a first current symbol sampler decision indicator based on a comparison between a received data signal and the first reference voltage; generating a second current symbol sampler decision indicator based on a comparison between the received data signal and the second reference voltage; generating a first previous symbol error cancellation voltage based on the first previous symbol sampler decision indicator; generating a second previous symbol error cancellation voltage based on the second previous symbol sampler decision indicator; generating a second previous symbol error cancellation voltage based on the first current symbol sampler decision indicator; generating a second current symbol error cancellation voltage based on the second current symbol sampler decision indicator; and adding at least one delayed version of the received data signal to the first previous symbol error cancellation voltage, the second previous symbol error cancellation voltage, the first current symbol error cancellation voltage, and the second current symbol error cancellation voltage to generate the equalized data signal.

[0190] The first previous symbol error cancellation voltage and the second previous symbol error cancellation voltage may have substantially different magnitudes, thereby achieving unique decision feedback weighting for the first previous symbol sampler decision indicator and the second previous symbol sampler decision indicator. The first previous symbol error cancellation voltage and the second previous symbol error cancellation voltage may have magnitudes that are substantially different from the first current symbol error cancellation voltage and the second current symbol error cancellation voltage.

[0191] The method may further include: generating a third previous symbol sampler decision indicator based on a comparison between the equalized data signal and a third reference voltage; generating a third current symbol sampler decision indicator based on a comparison between the received data signal and the third reference voltage; generating a third previous symbol error cancellation voltage based on the third previous symbol sampler decision indicator; and generating a third current symbol error cancellation voltage based on the third current symbol sampler decision indicator; adding the third previous symbol error cancellation voltage and the third current symbol error cancellation voltage to the received data signal, the first previous symbol error cancellation voltage, the second previous symbol error cancellation voltage, the first current symbol error cancellation voltage, and the second current error cancellation voltage to generate the equalized data signal.

[0192] The first difference between the first reference voltage and the second reference voltage and the second difference between the second reference voltage and the third reference voltage may be substantially equal. The first previous symbol error cancellation voltage, the second previous symbol error cancellation, and the third previous symbol error cancellation voltage may have substantially unequal magnitudes, thereby achieving unique decision feedback weighting for the first previous symbol sampler decision indicator, the second previous symbol sampler decision indicator, and the third previous symbol sampler decision indicator. The first current symbol error cancellation voltage, the second current symbol error cancellation, and the third current symbol error cancellation voltage have substantially unequal magnitudes, thereby achieving unique decision feedback weighting for the first current symbol sampler decision indicator, the second current symbol sampler decision indicator, and the third current symbol sampler decision indicator. The method may further include delaying the received data signal by one symbol time to produce a delayed version of the received data signal.

[0193] In one embodiment, an integrated circuit includes: a first prior symbol sampler configured to compare an equalized data signal with a first reference voltage to generate a first prior symbol sampler decision; a second prior symbol sampler configured to compare the equalized data signal with a second reference voltage to generate a second prior symbol sampler decision; a third prior symbol sampler configured to compare the equalized data signal with the second reference voltage to generate a second prior symbol sampler decision; a first current symbol sampler configured to compare a received data signal with the first reference voltage to generate a first current symbol sampler decision; a second current symbol sampler configured to compare the received data signal with the second reference voltage to generate a second current symbol sampler decision; a third current symbol sampler configured to compare the received data signal with the second reference voltage to generate a second current symbol sampler decision; an analog adder circuit configured to receive a first prior symbol error cancellation voltage based on the first prior symbol sampler decision, and receive a second prior symbol error cancellation voltage based on the second prior symbol sampler decision, and receive a third prior symbol error cancellation voltage based on the third prior symbol sampler decision, and receive a first current symbol error cancellation voltage based on the first current symbol sampler decision, and receive a second current symbol error cancellation voltage based on the second current symbol sampler decision, and receive a third current symbol error cancellation voltage based on the third current symbol sampler decision, and generate the equalized data signal based on a delayed version of the received data signal, the first prior symbol error cancellation voltage, the second prior symbol error cancellation voltage, the third prior symbol error cancellation voltage, the first current symbol error cancellation voltage, the second current symbol error cancellation voltage, and the third current symbol error cancellation voltage. The first prior symbol sampler, the second prior symbol sampler, and the second prior symbol sampler may be configured as PAM-4 samplers.

[0194] In one embodiment, a circuit for receiving a data signal includes: a first data sampler configured to compare an equalized data signal with a first reference voltage to generate a first sampler decision; a second data sampler configured to compare the equalized data signal with a second reference voltage to generate a second sampler decision; an analog adder circuit configured to receive a first error cancellation voltage based on the first sampler decision, and receive a second error cancellation voltage based on the second sampler decision, and generate the equalized data signal based on the received data signal, the first error cancellation voltage, and the second error cancellation voltage.

[0195] The first data sampler and the second data sampler may be part of a PAM-4 sampler. The first error removal voltage and the second error removal voltage may have substantially equal magnitudes. The first sampler decision may determine a first sign of the first error removal voltage, and the second sampler decision may determine a second sign of the second error removal voltage.

[0196] The integrated circuit may further include: a third data sampler for comparing the equalized data signal with a third reference voltage to generate a third sampler decision; and the adder circuit for further receiving a third error removal voltage based on the third sampler decision and generating the equalized data signal based on the third error removal voltage. The first error removal voltage, the second error removal voltage, and the third error removal voltage may have substantially equal magnitudes. The first sampler decision, the second sampler decision, and the third sampler decision may determine signs of the respective first error removal voltage, second error removal voltage, and third error removal voltage. A first difference between the first reference voltage and the second reference voltage and a second difference between the second reference voltage and the third reference voltage may be approximately equal.

[0197] In one embodiment, a method of receiving a data signal includes: generating a first sampler decision indicator based on a comparison between an equalized data signal and a first reference voltage; generating a second sampler decision indicator based on a comparison between the equalized data signal and a second reference voltage; generating a first error removal voltage based on the first sampler decision indicator; generating a second error removal voltage based on the second sampler decision indicator; and at least adding the received data signal to the first error removal voltage and the second error removal voltage to generate the equalized data signal.

[0198] The first error removal voltage and the second error removal voltage may have substantially different magnitudes, thereby achieving unique decision feedback weighting for the first sampler decision indicator and the second sampler decision indicator. A first value of the first sampler decision indicator may cause the first error removal voltage to contribute to increasing the voltage of the received data signal to generate the equalized data signal. A second value of the first sampler decision indicator may cause the first error removal voltage to contribute to decreasing the voltage of the received data signal to generate the equalized data signal.

[0199] The method may further include: generating a third sampler decision indicator based on a comparison between the equalized data signal and a third reference voltage; generating a third error cancellation voltage based on the third sampler decision indicator; and adding the third error cancellation voltage to the received data signal, the first error cancellation voltage, and the second error cancellation voltage to generate the equalized data signal.

[0200] A first difference between the first reference voltage and the second reference voltage and a second difference between the second reference voltage and the third reference voltage may be substantially equal. The first error cancellation voltage, the second error cancellation voltage, and the third error cancellation voltage may have substantially unequal magnitudes, thereby achieving unique decision feedback weighting for the first sampler decision indicator, the second sampler decision indicator, and the third sampler decision indicator. The first decision indicator, the second decision indicator, and the third decision indicator may determine whether the corresponding first error cancellation voltage, second error cancellation voltage, and third error cancellation voltage respectively contribute to increasing or decreasing the equalized data signal.

[0201] In one embodiment, an integrated circuit includes: a first data sampler for comparing an equalized data signal with a first reference voltage to generate a first sampler decision; a second data sampler for comparing the equalized data signal with a second reference voltage to generate a second sampler decision; a third data sampler for comparing the equalized data signal with a third reference voltage to generate a third sampler decision; an analog adder circuit for receiving a first error cancellation voltage based on the first sampler decision, receiving a second error cancellation voltage based on the second sampler decision, receiving a third error cancellation voltage based on the third sampler decision, and generating the equalized data signal based on the received data signal, the first error cancellation voltage, and the second error cancellation voltage.

[0202] The first error cancellation voltage, the second error cancellation voltage, and the third error cancellation voltage may have substantially equal magnitudes. The first sampler decision, the second sampler decision, and the third sampler decision may determine the signs of the corresponding first error cancellation voltage, second error cancellation voltage, and third error cancellation voltage. A first difference between the first reference voltage and the second reference voltage and a second difference between the second reference voltage and the third reference voltage may be approximately equal. The first data sampler and the second data sampler may include PAM-4 samplers.

[0203] In one embodiment, a decision feedback equalizer (DFE) includes: an analog feed-forward equalizer (FFE) configured to receive an equalized data signal and generate a first analog tap output; a first sampler configured to receive the first analog tap output and generate a first sampler decision; and an analog adder configured to receive at least the received data signal and a first error cancellation voltage based on the first sampler decision, the adder being configured to generate the equalized data signal.

[0204] The FFE may further include: an analog sample and hold configured to generate a delayed version of the equalized data signal; and an adder configured to generate the first analog tap output, the adder being configured to receive a current symbol error cancellation voltage and a previous symbol error cancellation voltage, the current symbol error cancellation voltage being based on the equalized data signal and the previous symbol error cancellation voltage being based on the delayed version of the equalized data signal.

[0205] The decision feedback equalizer may further include a tap feedback circuitry configured to receive at least the first sampler decision and generate the first error cancellation voltage. The tap feedback circuitry may receive a plurality of sampler decisions including the first sampler decision and generate a corresponding plurality of error cancellation voltages corresponding to the plurality of sampler decisions, the plurality of sampler decisions corresponding to previous values of the first sampler decision.

[0206] In one embodiment, a method of receiving a data signal includes: generating a first sampler decision by sampling a first analog output by an analog feed-forward equalizer that receives an equalized data signal; generating a first error cancellation voltage by weighting the first sampler decision; and adding at least the received data signal and the first error cancellation voltage to generate the equalized data signal.

[0207] The method may further include: holding the equalized data signal to generate a delayed analog version of the equalized data signal; weighting the delayed analog version of the equalized data signal to generate a previous symbol error cancellation voltage; weighting the equalized data signal to generate a current symbol error cancellation voltage; and generating the first analog output by adding the current symbol error cancellation voltage and the previous symbol error cancellation voltage.

[0208] The method may further include: weighting a second sampler decision to generate a corresponding second error cancellation voltage corresponding to a previous value of the first sampler decision, wherein the second sampler decision is added to at least the received data signal and the first error cancellation voltage to generate the equalized data signal.

[0209] In one embodiment, a decision feedback equalizer (DFE) includes: a first tap DFE loop that receives to receive an equalized data signal and generates a first sampler decision based on a previous symbol sampler decision and the equalized data signal; and a first analog adder that receives at least the received data signal and a first error cancellation voltage based on the first sampler decision, the adder being configured to generate the equalized data signal.

[0210] The first tap DFE loop may further include: a first tap weighting circuitry that receives the previous sampler decision and generates a first tap error cancellation voltage; an equalized data signal weighting circuitry that receives the equalized data signal and generates a weighted current symbol voltage; a second analog adder that receives the weighted current symbol voltage and the first tap error cancellation voltage; and a sampler that receives the output of the second analog adder and generates the first sampler decision.

[0211] The decision feedback equalizer may further include: a tap feedback circuitry that receives a plurality of sampler decisions including the first sampler decision and generates a corresponding plurality of error cancellation voltages corresponding to the plurality of sampler decisions. The plurality of sampler decisions may correspond to previous values of the first sampler decision.

[0212] The decision feedback equalizer may further include: a tap feedback circuitry that receives a plurality of sampler decisions not including the first sampler decision and generates a corresponding plurality of error cancellation voltages corresponding to the plurality of sampler decisions. The plurality of sampler decisions correspond to previous values of the first sampler decision.

[0213] In one embodiment, a decision feedback equalizer (DFE) includes: a first tap DFE loop that receives to receive an equalized data signal and generates a first sampler decision based on a previous symbol sampler decision and the equalized data signal; and a first analog adder that receives at least the received data signal and a first error cancellation voltage based on the first sampler decision, the adder being configured to generate the equalized data signal.

[0214] The first tap DFE circuit may further include: a first tap weighting circuit device for receiving the previous sampler decision and generating a first tap error cancellation voltage; an equalized data signal weighting circuit device for receiving the equalized data signal and generating a weighted current symbol voltage; a second analog adder for receiving the weighted current symbol voltage and the first tap error cancellation voltage; and a sampler for receiving the output of the second analog adder and generating the first sampler decision.

[0215] The decision feedback equalizer may further include: a tap feedback circuit device for receiving a plurality of sampler decisions including the first sampler decision and generating corresponding multiple error cancellation voltages corresponding to the plurality of sampler decisions, the plurality of sampler decisions corresponding to previous values of the first sampler decision. The decision feedback may further include: a tap feedback circuit device for receiving a plurality of sampler decisions not including the first sampler decision and generating corresponding multiple error cancellation voltages corresponding to the plurality of sampler decisions, the plurality of sampler decisions corresponding to previous values of the first sampler decision.

[0216] The above systems and devices may be implemented in a computer system, an integrated circuit, or stored by a computer system. The above systems may also be stored on a non-transitory computer-readable medium. The devices, circuits, and systems described herein may be implemented using computer-aided design tools available in the art and embodied by computer-readable files described by software including such circuits. This includes one or more of the following elements: System 100, System 200, Receiver 300, Receiver 302, Receiver 400, Receiver 402, Receiver 500, Receiver 600, Receiver 700, Receiver 800, Receiver 900, Receiver 1000, Receiver 1100, System 1200, Receiver 1500, Receiver 1600, Receiver 1700, System 2200, Digital FFE+DFE 2295, and its components. These software descriptions may be: behavioral, register transfer, logic component, transistor, and layout geometry level descriptions. Moreover, the software descriptions may be stored on a non-transitory storage medium or transmitted via a carrier wave.

[0217] Data formats in which such a description can be implemented include, but are not limited to: formats that support a behavioral language like C, formats that support register transfer level (RTL) languages like Verilog and VHDL, formats that support geometric description languages (such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. In addition, the data transfer of these files on a machine-readable medium can be done electronically via various media on the Internet, or, for example, via email. Note that physical files can be implemented on a machine-readable medium such as: 4mm tape, 8mm tape, 3-1 / 2 inch floppy disk media, CD, DVD, Blu-ray, etc.

[0218] Figure 25 The figure shows a block diagram of a computer system. The computer system 2500 includes a communication interface 2520, a processing system 2530, a storage system 2540, and a user interface 2560. The processing system 2530 is operatively coupled to the storage system 2540. The storage system 2540 stores software 2550 and data 2570. The computer system 2500 may include one or more of the following: system 100, system 200, receiver 300, receiver 302, receiver 400, receiver 402, receiver 500, receiver 600, receiver 700, receiver 800, receiver 900, receiver 1000, receiver 1100, system 1200, receiver 1500, receiver 1600, 1700, system 2200, digital FFE+DFE 2295, or components that implement the methods, circuits, and / or waveforms described herein. The processing system 2530 is operatively coupled to the communication interface 2520 and the user interface 2560. The computer system 2500 may include a programmed general-purpose computer. The computer system 2500 may include a microprocessor. The computer system 2500 may include programmable or dedicated circuitry. The computer system 2500 may be distributed among multiple devices, processors, storage devices, and / or interfaces that together include elements 2520 - 2570.

[0219] The communication interface 2520 may include a network interface, a modem, a port, a bus, a link, a transceiver, or other communication devices. The communication interface 2520 may be distributed among multiple communication devices. The processing system 2530 may include a microprocessor, a microcontroller, logic circuitry, or other processing devices. The processing system 2530 may be distributed among multiple processing devices. The user interface 2560 may include a keyboard, a mouse, a voice recognition interface, a microphone and speaker, a graphical display, a touch screen, or other types of user interface devices. The user interface 2560 may be distributed among multiple interface devices. The storage system 2540 may include a disk, a tape, an integrated circuit, RAM, ROM, EEPROM, flash memory, a network storage device, a server, or other memory functions. The storage system 2540 may include a computer-readable medium. The storage system 2540 may be distributed among multiple memory devices.

[0220] The processing system 2530 obtains the software 2550 from the storage system 2540 and executes the software 2550. The processing system 2530 may obtain the data 2570 and store the data 2570. The processing system 2530 may also obtain and store data via the communication interface 2520. The processing system 2530 may create or modify the software 2550 or the data 2570 to achieve a tangible result. The processing system 2530 may control the communication interface 2520 or the user interface 2560 to achieve a tangible result. The processing system 2530 may obtain and execute remotely stored software via the communication interface 2520.

[0221] The software 2550 and the remotely stored software may include an operating system, utilities, drivers, networking software, and other software typically executed by a computer system. The software 2550 may include application programs, applets, firmware, or other forms of machine-readable processing instructions typically executed by a computer system. When executed by the processing system 2530, the software 2550 or the remotely stored software may boot the computer system 2500 into operation.

[0222] The foregoing description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and other modifications and variations are possible in light of the above teachings. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention in various embodiments and with various modifications suited to the particular use contemplated. It is intended that the appended claims be construed to include alternative embodiments of the invention except as limited by the prior art.

Claims

1. A receiver circuit, comprising: An analog adder circuit for receiving a first input signal and generating an output data signal based on a first error removal voltage generated during a symbol period and a second error removal voltage generated during the symbol period; A first data sampler for sampling a first sampler input signal using a first reference voltage based on the output data signal to generate a first sampler decision; And A second data sampler for sampling a second sampler input signal using a second reference voltage based on the output data signal to generate a second sampler decision, wherein the first error removal voltage is generated from the first sampler decision, and the second error removal voltage is generated from the second sampler decision; Wherein the first input signal is generated by applying decision feedback equalization to a second input signal.

2. The receiver circuit according to claim 1, wherein the first sampler decision is multiplied by a first scaling factor to generate the first error removal voltage.

3. The receiver circuit according to claim 1, wherein the second sampler decision is multiplied by a second scaling factor to generate the second error removal voltage.

4. The receiver circuit according to claim 1, wherein the first sampler decision is multiplied by a first scaling factor to generate the first error removal voltage, the second sampler decision is multiplied by a second scaling factor to generate the second error removal voltage, and the first scaling factor is equal to the second scaling factor.

5. The receiver circuit according to claim 1, wherein the decision feedback equalization applied to the second sampler input signal is based on a third sampler decision generated by the first data sampler.

6. The receiver circuit according to claim 1, wherein the decision feedback equalization applied to the second sampler input signal is based on a third sampler decision generated by the second data sampler.

7. A method for receiving a data signal, comprising: Generating a first sampler decision based on a comparison between a first equalized data signal and a first reference voltage during a symbol period; Generating a second sampler decision based on a comparison between the first equalized data signal and a second reference voltage during the symbol period; Generating a first error removal voltage based on the first sampler decision; Generating a second error removal voltage based on the second sampler decision; And Adding the received data signal, the first error removal voltage, and the second error removal voltage, and generating a second equalized data signal.

8. The method according to claim 7, wherein the first sampler decision is scaled by a first scaling factor to generate the first error removal voltage.

9. The method according to claim 7, wherein the second sampler decision is scaled by a first scaling factor to generate the second error removal voltage.

10. The method according to claim 8, wherein the second sampler decision is scaled by a second scaling factor to generate the second error removal voltage, and the first scaling factor is equal to the second scaling factor.

11. The method according to claim 8, further comprising: Equalizing the second input signal to generate the first equalized data signal.

12. A receiver circuit, comprising: A first symbol sampler for comparing a first input signal with a first reference voltage during a symbol period to generate a first symbol sampler decision; A second symbol sampler for comparing the first input signal with a second reference voltage during the symbol period to generate a second symbol sampler decision; And An analog adder circuit for receiving a first symbol error cancellation voltage based on the first symbol sampler decision, and receiving a second symbol error cancellation voltage based on the second symbol sampler decision, and generating the first input signal based on the first symbol error cancellation voltage, the second symbol error cancellation voltage, and a second input signal; Wherein the second input signal is an equalized version of a third input signal.

13. The receiver circuit according to claim 12, wherein the first symbol sampler decision is scaled by a first scaling factor to generate the first symbol error cancellation voltage.

14. The receiver circuit according to claim 12, wherein the second symbol sampler decision is scaled by a second scaling factor to generate the second symbol error cancellation voltage.

15. The receiver circuit according to claim 13, wherein the second symbol sampler decision is scaled by a second scaling factor to generate the second symbol error cancellation voltage, and the first scaling factor is equal to the second scaling factor.

16. The receiver circuit according to claim 12, wherein the first symbol sampler decision determines a first symbol of the first symbol error cancellation voltage.

17. The receiver circuit according to claim 12, wherein the third input signal is equalized based on a first previous decision of the first symbol sampler.

18. The receiver circuit according to claim 17, wherein the third input signal is further equalized based on a second previous decision of the second symbol sampler.

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