Priority-based encoder-based technique for computing minimum or maximum of multiple values

Abstract

Priority encoder based techniques for computing a minimum or maximum of a plurality of values are disclosed. In various embodiments, a maximum or minimum of a plurality of input values is determined. For each of a set of possible values, a corresponding detection result is set to indicate whether at least one of the input values matches the possible value. The detection results are used to determine the maximum or minimum of the plurality of input values.

Description

Technical Field

[0001] The various embodiments generally relate to computer processing systems, and more specifically to techniques for calculating the minimum or maximum value among a plurality of values ​​using a priority encoder. Background Technology

[0002] Floating-point matrix multiplication is a fundamental building block of many machine learning algorithms. The matrix multiplication of an m×n matrix A and an n×p matrix B produces an m×p matrix C, where the elements c of C are... ij It is the dot product of row i of A and column j of B, and therefore can be expressed as In order to perform floating-point matrix multiplication at high throughput, some processors include a collection of dedicated hardware components known as the "floating-point matrix multiplication data path".

[0003] In many floating-point matrix multiplication data paths, each floating-point value is multiplied by 2 (mantissa). 指数 The format is as follows: The mantissa is an integer represented by a sequence of bits, while the exponent is an integer represented by a shorter sequence of bits. This is used to calculate the sum of multiple floating-point values ​​(e.g., n products a). ik b kj To effectively calibrate the decimal point in the mantissa, the data path typically calculates the largest exponent among multiple values ​​and right-shifts each value by the difference between the largest exponent and the exponent of that value.

[0004] One approach to compute the maximum of n exponents involves implementing a tree-based maximization circuit with n inputs in a floating-point matrix multiplication data path. The tree-based maximization circuit is a binary tree of sub-circuits, each of which includes, but is not limited to: a comparator that compares two inputs; and a multiplexer that selects and outputs the maximum of the two inputs. The outputs of all sub-circuits except the last one are the inputs to the sub-circuits in the next level. For example, a four-input tree-based maximization circuit includes, but is not limited to, two sub-circuits at the top level and a single sub-circuit at the bottom level. Each sub-circuit at the top level computes the two maximum values ​​for different input value pairs. The sub-circuit in the last level computes and outputs the maximum of the two maximum values.

[0005] One drawback of tree-based maximization circuits is that, due to the increasing depth of dot products with advancements in semiconductor technology and architecture, they have become a performance bottleneck for some floating-point matrix multiplication data paths. More specifically, the number of inputs to many tree-based maximization circuits roughly doubles with each design generation (e.g., from 4 to 8 to 16, and even to 32). Doubling the number of input values ​​requires adding additional layers to the binary tree, and adding layers to the binary tree significantly increases the latency of the tree-based maximization circuit, thus limiting the achievable design clock frequency. Therefore, this limits the overall performance of the floating-point matrix multiplication data path.

[0006] Another drawback of tree-based maximization circuits is their unsuitability for pipelined operations. As used herein, "pipelining" refers to dividing logic into multiple stages via pipeline registers (e.g., flip-flops). Pipeline registers store signals between stages, allowing each stage to perform operations on different data in parallel. In the context of floating-point matrix multiplication data paths, exponents are typically stored in registers for subsequent shift operations, and thus the number of additional registers required for a partial maximization circuit with a pipelined design corresponds to the internal structure of the maximization circuit. For tree-based maximization circuits, the relatively large number of pipeline registers required to store the internal state of the binary tree can be a barrier to pipelined design.

[0007] For illustrative purposes, the above describes, in the context of tree-based maximization circuits, the scaling problems typically associated with existing maximization circuits implemented in floating-point matrix multiplication data paths. However, other types of existing maximization circuits also exhibit undesirable high latency, latency that increases excessively with the number of exponents, difficulty in pipelinedization, or arbitrary combinations thereof.

[0008] As stated above, what is needed in the art is a more efficient technique for calculating the maximum exponent in a floating-point dot product pipeline. Summary of the Invention

[0009] This invention provides a circuit. The circuit includes a set of detection sub-circuits, each of which calculates different detection results included in a set of detection results and indicates whether at least one input value included in a set of input values ​​is equal to a different integer; and an encoder coupled to the set of detection sub-circuits, the encoder determining an active bit from encoder input data, including each detection result in the set of detection results being a different bit in the encoder input data, and encoding the bit position associated with the active bit to generate a maximum value.

[0010] At least one technical advantage of the disclosed technique compared to the prior art is that it reduces the latency caused by doubling the number of exponents when calculating the maximum exponent. In this respect, with the disclosed technique, because the comparison is performed between each exponent and a possible value rather than between exponents, the increase in latency attributable to doubling the number of exponents is approximately the latency of a two-input OR gate, rather than the sum of the latency of a comparator and a multiplexer. Furthermore, because adding a pipeline level to the hierarchical maximum circuitry in the pipelined floating-point matrix multiplication data path involves storing only a portion of a single exponent, the hierarchical maximum circuitry is well-suited for pipelined applications. These technical advantages provide one or more technical improvements over prior art methods. Attached Figure Description

[0011] To gain a detailed understanding of the features described above in the various embodiments, a more specific description of the inventive concept briefly outlined above can be obtained by referring to the various embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings only show typical embodiments of the inventive concept and should not be construed as limiting the scope in any way, and other equally effective embodiments exist.

[0012] Figure 1 It is a block diagram of the maximum value circuit according to various embodiments;

[0013] Figure 2 This involves operating on 32 4-bit input values ​​according to various embodiments. Figure 1 Block diagram of the circuit with the maximum value;

[0014] Figure 3 It is a block diagram of the layered maximum value circuit according to various embodiments;

[0015] Figure 4 This involves operating on 32 8-bit input values ​​according to various embodiments. Figure 3 Block diagram of the layered maximum value circuit;

[0016] Figure 5 It is a block diagram of the minimum / maximum value circuit according to various embodiments;

[0017] Figure 6 This is a flowchart of method steps for calculating the minimum or maximum value among multiple values ​​according to various embodiments; and

[0018] Figure 7 This is a block diagram illustrating a system configured to implement one or more aspects of various embodiments. Detailed Implementation

[0019] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the various embodiments. However, it will be apparent to those skilled in the art that the inventive concept can be practiced without one or more of these specific details. For illustrative purposes only, multiple instances of the same object are referred to herein by reference numerals consistent with the objects and by alphanumeric characters in brackets consistent with the examples, where necessary.

[0020] As described earlier, many methods for calculating the sum of multiple floating-point values ​​involve calculating the maximum exponent among these values. One approach to determining the maximum value among n integer input values ​​(such as exponents) involves implementing a tree-based maximization circuit. A tree-based maximization circuit is a binary tree of paired maximization sub-circuits, where each pair of maximization sub-circuits calculates the maximum of the two inputs via a comparator and a multiplexer. One drawback of tree-based maximization circuits is that doubling the number of input values ​​increases the latency by the sum of the comparator and multiplexer latency. Therefore, for some floating-point dot product calculations, paired maximization trees have become a performance bottleneck. Another drawback of tree-based maximization circuits is the large area required to incrementally apply pipelined design. Incrementally applying pipelined design of tree-based maximization circuits becomes impractical when the area available for implementing them is limited.

[0021] Detect the maximum value among multiple input values

[0022] To address the aforementioned issues, in some embodiments, the maximization circuit does not directly compare input values ​​to determine the maximum value. Instead, the maximization circuit detects the maximum possible value that is equal to or "matches" at least one input value. The following combines... Figure 1 The parameterized form of the maximum value circuit implemented in some embodiments is described in more detail.

[0023] Figure 1 This is a block diagram of the maximum value circuit 100 according to various embodiments. As shown, the maximum value circuit 100 calculates a maximum value 190 based on input values ​​110(n-1)–110(0), where n can be any positive integer. The maximum value 190 is the maximum value among the input values ​​110(n-1)–110(0). For illustrative purposes, the input values ​​110(n-1)–110(0) are also referred to herein separately as “input value 110” and collectively as “input value 110”. Each input value 110 is represented by r bits, where r can be any positive integer, and therefore the maximum value 190 is represented by r bits.

[0024] The input values ​​110(n-1)–110(0) are also represented here as I. n-1-I0. The maximum value of 190 is also represented here as "Max". For illustrative purposes, Figures 1 to 7 Zero-based indexing and the bus notation format "B[j:k]" are used to represent the portions of the multi-bit value B corresponding to the bits at positions j to k. Therefore, the input value 110(n-1)–110(0) and the maximum value 190 are also represented here as I. n-1 [(r-1):0]–I0[(r-1):0] and Max[(r-1):0]. For illustrative purposes, in Figures 1 to 5 In this context, routes with multiple bits are represented by thicker lines than routes with a single bit value.

[0025] In operation, the maximum value circuit 100 sets the maximum value 190 to be equal to the maximum value among one or more possible values ​​that match at least one of the input values ​​110. These possible values ​​are values ​​that can be represented in r bits according to the integer representation associated with the input values ​​110. In some embodiments, including Figures 1 to 7 In the embodiment depicted, input value 110 and maximum value 190 are unsigned integer values ​​(e.g., exponents). In such an embodiment, r bits in each input value of input value 110 can represent values ​​from 0 to (2^r). r -1)(including 0 and (2) r -1)) possible values. The maximum value circuit 100 is capable of determining the maximum value among one or more values ​​based on possible values ​​that match at least one of the input values ​​110 in any technically feasible manner. Determining the maximum value among one or more values ​​is also referred to herein as performing a “maximum calculation”.

[0026] As shown in the figure, in some embodiments, the maximum value circuit 100 includes, but is not limited to, the detection sub-circuit 120 (2 r -1)–120(1) and priority encoder 180. For illustrative purposes, detection sub-circuit 120(2) r -1)–120(1) is also referred to here separately as “detection sub-circuit 120” and collectively as “detection sub-circuit 120”. Detection sub-circuit 120(2) r -1)–120(1) respectively generate detection results 170(2) based on input values ​​110(n-1)–110(0). r -1)–170(1). For illustrative purposes, the test result is 170(2). r -1)–170(1) is also referred to here separately as “detection result 170” and collectively as “detection result 170”.

[0027] More precisely, regarding (2) rFor an integer variable p from -1 to 1, the detection subcircuit 120(p) generates a detection result 170(p), which indicates whether at least one of the input values ​​110(n-1)–110(0) is equal to p. In some embodiments, if at least one of the input values ​​110(n-1)–110(0) is equal to p, the detection subcircuit 120(p) generates a detection result 170(p) of '1'. Otherwise, the detection subcircuit 120(p) generates a detection result 170(p) of '0'. Detection subcircuit 120(2 r -1)–120(1) can perform any number and / or type of detection operations to generate detection results separately in any technically feasible manner 170(2 r -1)–170(1).

[0028] In some embodiments, each detection sub-circuit 120 includes, but is not limited to, a set of n matching detectors and an OR (or) component of width n (e.g., an n-input OR gate, an OR tree, etc.). For (2 r An integer variable p from -1 to 1 is used to detect whether each of the matching detectors in the sub-circuit 120(p) generates a different matching value for p indicating whether a different input value in the input value 110 is equal to a different matching value for p. In some embodiments, if the matching detector determines that the relevant input value 110 matches the relevant possible value p, then the matching detector outputs the matching value '1'.

[0029] For illustrative purposes, including in the detection sub-circuit 120 (2 r The three matching detectors in -1) and corresponding to the input values ​​110(n-1), 110(1), and 110(0) are represented by "I n-1 ==2 r -1? "I1==2 r -1? and "I0==2" r -1? ” is used as a comment box to indicate the associated function. The three matching detectors included in the detection sub-circuit 120(2) and corresponding to the input values ​​110(n-1), 110(1), and 110(0) are respectively represented by “I”. n-1 ==2?", "I1==2?", and "I0==2?" are used as annotation boxes to indicate the associated functions. Furthermore, the three matched detectors included in the detection sub-circuit 120(1) and corresponding to the input values ​​110(n-1), 110(1), and 110(0) are respectively represented by boxes labeled "I1==2?", "I2==2?", and "I0==2?". n-1 The boxes “I1==1?”, “I0==1?” are used as comments to indicate the relevant functions.

[0030] Each matching detector can determine whether an associated input value 110 matches an associated possible value p in any technically feasible manner. For example, in some embodiments, this includes a detection sub-circuit 120 (2 r Each match detector in the match detectors of -1) is an AND component (not shown) of width r that generates and outputs a match value of '1' if all bits of the corresponding input value 110 are equal to '1', and otherwise generates and outputs a match value of '0'. In the same or other embodiments, n comparators in one or more of the detection sub-circuits 120 are implemented via r exclusive NOR ("XNOR") components and an AND component of width r.

[0031] For from (2) r An integer variable p from -1 to 1, within each detection subcircuit 120(p), has n matching values ​​associated with that possible value p as inputs (represented by a wide box annotated with "OR") to an OR component of width n, and the output of the OR component of width n is the detection result 170(p). Therefore, if at least one of the input values ​​110(n-1)–110(0) equals p, at least one of the matching detectors in detection subcircuit 120(p) generates a matching value '1', and thus the OR component of width n in detection subcircuit 120(p) generates a detection result 170(p) of '1'. Otherwise, each matching detector in detection subcircuit 120(p) generates a matching value of '0', and thus the OR component of width n in detection subcircuit 120(p) generates a detection result 170(p) of '0'.

[0032] In some embodiments, the priority encoder 180 is denoted as D[(2 r -1):0] of 2 r The bit input port receives 2 r A parallel priority encoder for bit input data, wherein the most significant bit (MSB) in the input data corresponds to D[2]. r -1], and the least significant bit (LSB) in the input data corresponds to D[0]. Priority encoder 180 encoding 2 r The position of the most significant '1' bit in the input data is used to generate an r-bit binary value. The priority encoder 180 outputs the r-bit binary value via an r-bit output port denoted as Q[(r-1):0].

[0033] In some embodiments, the detection result 170(2) r -1)–170(1) are connected to D[(2) respectively. r -1):1], and therefore the position in the input data (2r The bits at -1)–1 are respectively equal to the detection result 170(2) r -1)–170(1). Although not shown, in some embodiments, the zero-detection subcircuit generates a “zero-detection result” that indicates whether at least one of the input values ​​110(n-1)–110(0) is equal to 0, the zero-detection result is connected to D[0], and therefore the LSB of the input data is equal to the zero-detection result.

[0034] Q[(r-1):0] is connected to Max[(r-1):0], and therefore the maximum value 190 is equal to the r-bit binary value generated by the priority encoder 180. In operation, because the position of the most significant '1' bit of the input data is equal to the position of the bit from (2... r The maximum value among one or more values ​​of -1)–0 is used, so the priority encoder 180 sets the maximum value 190 to be equal to the maximum value among the input values ​​110.

[0035] As shown in the figure, in some embodiments, to reduce the area of ​​the maximum value circuit 100, the maximum value circuit 100 does not include the zero-detection sub-circuit and therefore does not produce a zero-detection result. Instead, D[0] is restricted to a high level, so the LSB of the input data is '1', and if all input values ​​110(n-1)–110(0) are equal to 0, the priority encoder 180 is enabled to output an r-bit binary value of 0 via the output port Q[(r-1):0]. More specifically, if all input values ​​110(n-1)–110(0) are equal to 0, the detection sub-circuit 120(2 r -1)–120(1) Output the detection results 170(2) respectively r -1)–170(1), all of these results are equal to zero, corresponding to the maximum value of 0 among all input values ​​of 0.

[0036] Advantageously, because the maximization circuit 100 does not perform comparisons between the input values ​​110, the adverse effects associated with the increased number of input values ​​110 can be reduced. More specifically, in some embodiments, if the number of input values ​​110 is doubled, the wide OR gates included in the detection sub-circuit 120(p) are the primary factor causing an increase in the delay of the maximization circuit 100. Because doubling the number of input values ​​110 requires adding 2-input OR gates to each wide OR gate, the increase in delay of the maximization circuit 100 is approximately the delay of 2-input OR gates. In contrast, as previously described herein, doubling the number of input values ​​in an existing tree-based maximization circuit can increase the delay of the existing tree-based maximization circuit by at least the sum of the delays of the comparator and the multiplexer. As those skilled in the art will recognize, the delay of the comparator itself is significantly greater than the delay of a 2-input AND gate.

[0037] Note that the techniques described herein are illustrative and not restrictive, and can be modified without departing from the broader spirit and scope of the invention. Many modifications and variations to the functionality described herein within the context of the maximum value circuit 100, the detection sub-circuit 120, the matching detector, the OR component with width n, and the priority encoder 180 will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

[0038] Specifically, in some embodiments, the functions described herein are modified to implement a minimum value circuit, either as an alternative to or in addition to the maximum value circuit 100. For example, in some embodiments, the minimum value circuit includes, but is not limited to, the detection sub-circuit 120 (2 r -2)–120(1), zeroth detection sub-circuit and trailing one detector. Relative to the maximum value circuit 100, detection sub-circuit 120(2) r -1) is replaced by the zeroth detection subcircuit, and the priority encoder 180 is associated with the tail 1 detector. The zeroth detection subcircuit generates a "zero detection result", which indicates whether at least one of the input values ​​110(n-1)–110(0) is equal to 0.

[0039] In some embodiments, the trailing detector 1 is an inverted or overridden form of the priority encoder 180, which is relative to 2. r The position of the most significant '1' bit in the "inverted input data" is encoded to generate an r-bit binary value, the r-bit binary value is inverted, and the r-bit binary value is output via an r-bit output port referred to herein as Qbar[(r-1):0]. In the same or other embodiments, the bit at position 0 in the input data and the position (2) of the inverted input data are encoded to generate an r-bit binary value, the r-bit binary value is inverted, and the r-bit binary value is output via an r-bit output port referred to herein as Qbar[(r-1):0]. r -1) Driven by the zeroth detection result. Based on detection results 170(1)–170(2) respectively. r -2) Drive at position 1–(2) of the input data r The bit at position -2) and therefore at position (2) when the input data is inverted. r -2)–1. And at the position of the input data (2 r The bit at -1) and therefore at position 0 in the inverse input data are restricted to a high level or by the detection result 170(2) r -1) Driver.

[0040] Any number of techniques described herein can be implemented in any amount and / or type of software, hardware, or any combination thereof. In some embodiments, any number of maximum value circuits can be implemented in any technically feasible manner by any number and / or type of other circuits, data paths, pipelines, functional units, execution units, or any other component of the processor. In some embodiments, each maximum value circuit may be the same as and may be different from zero or more other maximum value circuits. In the same or other embodiments, each parameter value associated with a maximum value circuit (e.g., the value of n or r) may be the same as and may be different from the corresponding parameter value associated with zero or more other maximum value circuits.

[0041] Specifically, the maximum value circuit 100 and the detection sub-circuit 120 (2) can be implemented in any technically feasible manner. r -1)–120(1), a matching detector, an OR component with a width of n, and a priority encoder 180. For example, in some embodiments, the maximum value circuit 100 and the detection sub-circuit 120(2) are synthesized based on the functional behavioral description described herein. r -1)–120(1), a matching detector, an n-wide OR component, a priority encoder 180, a follow-one detector, or any combination thereof. For example, in some embodiments, truth tables encoding the leading 1 position or the trailing 1 position in the input data are used to synthesize the priority encoder or the trailing 1 detector, respectively. In the same or other embodiments, one or more components from any number of standard cell libraries, any number of field-programmable gate array (FPGA) libraries, any number of other discrete components, any amount and / or type of custom logic and / or layout, or any combination thereof are used to implement the maximum value circuit 100, the detection sub-circuit 120(2), and other components. r -1)–120(1), a match detector, an OR component with a width of n, a priority encoder 180, or any combination thereof.

[0042] Figure 2 It operates on 32 4-bit input values ​​according to various embodiments. Figure 1 A block diagram of the maximum value circuit 100. More specifically, in some embodiments, the maximum value circuit 100 calculates a maximum value 190, which is the maximum value of the input values ​​110(31)–110(0). Each of the input values ​​110(31)–110(0) and the maximum value 190 is an unsigned integer value, each represented by four bits. See also Figure 1 , Figure 2 It describes where n is 32, r is 4, and (2 r-1) is an embodiment of 15. Therefore, the input values ​​110(31)–110(0) are also represented as I respectively. 31 [3:0]–I0[3:0], and respectively represent being I 31 –I0. The maximum value of 190 is also represented as Max[3:0].

[0043] In operation, the maximum value circuit 100 sets the maximum value 190 to be equal to the maximum of one or more values ​​from 15 to 0 that match at least one of the input values ​​110. As shown, in some embodiments, the maximum value circuit 100 includes, but is not limited to, detection sub-circuits 120(3)–120(0) and a priority encoder 180. The detection sub-circuits 120(3)–120(0) generate detection results 170(3)–170(0) based on the input values ​​110(31)–110(0), respectively.

[0044] For illustrative purposes, in Figure 2 The diagram clearly describes the detection sub-circuits 120(15), 120(1), and 120(0). As shown, if any of the input values ​​110(31)–110(0) equals 15, then the detection sub-circuit 120(15) sets the detection result 170(15) to '1'. Otherwise, the detection sub-circuit 120(15) sets the detection result 170(15) to '0'. If any of the input values ​​110(31)–110(0) equals 2, then the detection sub-circuit 120(2) sets the detection result 170(2) to '1'. Otherwise, the detection sub-circuit 120(2) sets the detection result 170(2) to '0'. If any of the input values ​​110(31)–110(0) equals 1, then the detection sub-circuit 120(1) sets the detection result 170(1) to '1'. Otherwise, the detection sub-circuit 120(1) sets the detection result 170(1) to '0'.

[0045] As shown in the figure, in some embodiments, the priority encoder 180 is a parallel priority encoder that receives 16-bit input data via a 16-bit input port denoted as D[15:0]. The priority encoder 180 encodes the position of the most significant '1' bit in the 16-bit input data to generate a 4-bit binary value. The priority encoder 180 outputs a 4-bit binary value via a 4-bit output port denoted as Q[3:0].

[0046] In some embodiments, detection results 170(15)–170(1) are connected to D[15:1], and therefore the bits at positions 15–1 in the input data are equal to detection results 170(15)–170(1), respectively. D[0] is restricted to a high level, and therefore the LSB of the input data is '1'. Q[3:0] is connected to Max[3:0], and therefore the maximum value 190 is equal to the 4-bit binary value generated by the priority encoder 180. In operation, because the position of the most significant '1' bit in the input data is equal to the maximum value among one or more values ​​of 15–0 that match at least one input value 110, the priority encoder 180 sets the maximum value 190 to be equal to the maximum value among the input values ​​110.

[0047] The maximum value calculation is divided into multiple lower-order maximum value calculations.

[0048] Typically, different approaches to problem-solving (e.g., determining the maximum of multiple indices) are associated with different trade-offs between any number and / or type of design characteristics. Some examples of design characteristics include, but are not limited to, latency, throughput, power, and scalability. (See also: [link to relevant documentation]) Figure 1 In some embodiments, the number of detection sub-circuits 120 and therefore the area of ​​the maximum value circuit 100 increase exponentially with the number of bits in each input value 110. Thus, in some embodiments, if the number of bits on each input value 110 exceeds a bit threshold (e.g., 3 or 4), it may be difficult, if not impossible, to meet and / or optimize any number and / or type of design criteria related to area.

[0049] For this reason, in some embodiments, a hierarchical maximization circuit breaks down a maximum value calculation into interdependent subproblems and solves these subproblems sequentially via multiple maximization circuits. As combined below... Figure 3 More specifically, in some embodiments, the hierarchical maximization circuitry configures each maximization circuit to compute different portions of the maximum value based on a subset of corresponding portions of the input value. In some embodiments, because the number of bits in the personalized input of each constituent maximization circuit is reduced, the total area of ​​the hierarchical maximization circuitry is significantly reduced relative to a single maximization circuitry that computes the entire maximum value. In the same or other embodiments, the delay of the hierarchical maximization circuitry is greater than the sum of the delays of the constituent maximization circuitry, and therefore greater than the delay of a comparable single maximization circuitry.

[0050] In some embodiments, the inherent trade-offs in the structures of the maximum maximization circuit and the hierarchical maximum maximization circuit provide opportunities to optimize the maximum maximization computation in any technically feasible manner based on any number and / or type of design requirements, design criteria, etc. For example, in some embodiments, and as previously noted, if the number of bits in each input of the maximum computation is greater than a bit threshold, the maximum computation is performed via the hierarchical maximum maximization circuit. Otherwise, the maximum computation is performed via the maximum maximization circuit.

[0051] Figure 3 This is a block diagram of the hierarchical maximum value circuit 300 according to various embodiments. As shown, the hierarchical maximum value circuit 300 calculates a maximum value 190 based on the input values ​​110(n-1)–110(0), where n can be any positive integer. The maximum value 190 is the maximum value of the input values ​​110(n-1)–110(0). Each input value 110 is represented by r bits, where r can be any positive integer, and therefore the maximum value 190 is represented by r bits.

[0052] As shown in the figure, in some embodiments, the layered maximum value circuit 300 includes, but is not limited to, a maximum value circuit 100(1), a mask sub-circuit 370, and a maximum value circuit 100(0). In some embodiments, the maximum value circuit 100(1) and the maximum value circuit 100(0) are Figure 1 Different instances of the maximum value circuit 100. The maximum value circuit 100(1) and the maximum value circuit 100(0) can be the same or different.

[0053] In some embodiments, the maximum value circuit 100(1) calculates the maximum value of (rk) bits among n values ​​received via n (rk) bit input ports, where k is a positive integer less than r. In the same or other embodiments, the maximum value circuit 100(0) calculates the maximum value of k bits among n values ​​received via n k bit input ports. In some embodiments, (rk) may be equal to or different from k, and therefore the maximum value circuit 100(1) and the maximum value circuit 100(0) may generate the same number or different number of bits for the maximum value 190.

[0054] In some embodiments, the hierarchical maximum circuit 300 takes the input value 110(n-1)–110(0) (represented herein as I) as input value 110(n-1)–110(0). n-1 The (rk) MSBs of each of [(r-1):k]–I0[(r-1):k]) are routed to the n (rk) bit input ports of the maximum circuit 100(1). In response, the maximum circuit 100(1) generates (rk) MSBs of a maximum value of 190, denoted here as Max[(r-1):k].

[0055] As shown in the figure, in the same or other embodiments, the mask sub-circuit 370 drives the n (rk) bit input ports of the maximum value circuit 100 (0) based on the (rk) MSBs in the maximum value 190 and the input value 110(n-1)–110(0). For an integer variable i from (n-1) to 0, if the (rk) MSBs in the input value 110(i) (represented here as I) i [(r-1):k]) equals (rk) MSBs of the maximum value 190 (represented as Max[(r-1):k]), then the mask sub-circuit 370 will I i [(k-1):0] is routed to the i-th input port of the maximum value circuit 100(0). Otherwise, the masking sub-circuit 370 routes k-bit 0 values ​​to the i-th input port of the maximum value circuit 100(0). In this way, the masking sub-circuit 370 removes or “masks” zero or more input values ​​110 that have MSBs that do not match the MSBs in the maximum value 190 previously calculated by the maximum value circuit 100(1). The masking sub-circuit 370 can generate values ​​that drive the input ports of the maximum value circuit 100(0) in any technically feasible manner.

[0056] In some embodiments, the mask sub-circuit 370 includes, but is not limited to, n comparator / AND pairs. For an integer variable i from (n-1) to 0, the i-th comparator / AND pair will... i [(k-1):0] or k-bit 0 is routed to the i-th input port of the maximum value circuit 100(0). More precisely, the comparator pair I in the i-th comparator / AND pair. i [(r-1):k] is compared with Max[(r-1):k] to produce the i-th matching value. If I i If [(r-1):k] equals Max[(r-1):k], then the i-th match is '1'; otherwise, it is '0'. For I i Each bit in the k bits of [(k-1):0] represents the AND component in the i-th comparator / AND pair at the i-th matched value and I. i Perform a logical AND operation between each of the k bits in [(k-1):0] to generate a value represented as J. i The k-bit output value of [(k-1):0]. As shown in the figure, it is represented as J. i The k-bit output value of [(k-1):0] is routed to the i-th input port of the maximum value circuit 100(0).

[0057] For illustrative purposes, the comparators corresponding to the input values ​​110(0), 110(1), and 110(N-1) are in Figure 3The box is explicitly described as being annotated with "MSB match?". The AND components corresponding to the input values ​​110(0), 110(1), and 110(N-1) are in... Figure 3 The text explicitly describes it as a box annotated with "and".

[0058] As shown in the figure, in response to n k-bit values ​​received via the input port of the maximum value circuit 100(0), the maximum value circuit 100(0) generates k LSBs of the maximum value 190, denoted here as Max[(k-1):0]. Therefore, Max[(k-1):0] is equal to the maximum value in a subset of the input value 110, which has (rk) MSBs equal to the (rk) MSB of the maximum value 190. The hierarchical maximum value circuit 300 then outputs the maximum value 190.

[0059] In some other embodiments, instead of sequentially solving two sub-problems via two maximum value circuits to generate a maximum value of 190, the hierarchical maximum value circuit 300 sequentially solves m sub-problems via m maximum value circuits to generate a maximum value of 190, where m is greater than 2. In the same or other embodiments, the hierarchical maximum value circuit 300 includes, but is not limited to, m maximum value circuits and (m-1) mask sub-circuits.

[0060] Each of the m maximum-value circuits generates a distinct portion of the maximum value 190, where each portion of the maximum value corresponds to a distinct, non-overlapping sequence of bit positions. Simultaneously, the bit position sequence spans from the MSB to the LSB of the maximum value 190. Each bit position sequence may have the same number of bits as zero or more other bit position sequences, and may have a different number of bits than zero or more other bit position sequences. For illustrative purposes, the (m-1)th maximum-value circuit is associated with the (m-1)th bit position sequence of the bit positions including the MSB of the maximum value 190, the (m-2)th maximum-value circuit is associated with the next highest bit position sequence, and so on. The 0th maximum-value circuit is associated with the 0th bit position sequence of the bit positions including the LSB of the maximum value 190.

[0061] In some embodiments, the (m-1)th maximization circuit calculates the (m-1)th portion of the maximum value 190, including the MSB, based on the corresponding portions of the input values ​​110(n-1) to 110(0). For integers j from (m-2) to 0, the j-th masking sub-circuit routes the j-th portion of each input value 110 in the j-th matching subset of the input values ​​110 to the corresponding input of the j-th maximization circuit, and routes zero values ​​to each of the other input ports of the j-th maximization circuit. The j-th matching subset of the input values ​​110 includes one or more input values ​​110 having an MSB that matches the MSB of the maximum value 190 calculated by one or more previous maximization circuits. The j-th maximization circuit calculates the j-th portion of the maximum value 190 based on the j-th portion of one or more input values ​​110 in the j-th matching subset of the input values ​​110. After the 0th maximization circuit calculates the LSB in the maximum value 190, the hierarchical maximization circuit 300 outputs the maximum value 190.

[0062] In some embodiments, each of the hierarchical maximization circuits in any number of hierarchical maximization circuits may divide the corresponding bit position of the maximum value into multiple bit position sequences in any technically feasible manner and based on any number and / or type of criteria. In some embodiments, to optimize the tradeoff between delay and area, each hierarchical maximization circuit divides the corresponding bit position into a minimum number of bit position sequences, each having four bits or fewer. In the same or other embodiments, the hierarchical maximization circuits compute the nine-bit maximum value, denoted herein as Max[8:0], via three maximization circuits that compute Max[8:6], Max[5,3], and Max[2:0], respectively.

[0063] Advantageously, because the input value of each maximum circuit in a hierarchical maximum circuit is determined by the input value of the hierarchical maximum circuit and any previously calculated MSB of the maximum value, the hierarchical maximum circuit is particularly suitable for pipelining when the input value of the hierarchical maximum circuit has already been stored. For example, in some embodiments, in order to add a pipeline level to a hierarchical maximum circuit following the maximum circuit, a register is used to store the output of the maximum circuit. Thus, adding a pipeline level involves storing only a portion of the maximum value. For example, and as depicted via dashed lines, in some embodiments, the input values ​​110(1)–110(n) have already been stored for floating-point sums, and the hierarchical maximum circuit 300 is piped via an optional incremental pipelining trigger 418 storing Max[(r-1):k].

[0064] In some other embodiments, although the input values ​​of each maximization circuit in the hierarchical maximization circuit are not yet stored, the regular structure of the hierarchical maximization circuit facilitates efficient pipelined operation at any number of locations. For example, as depicted via dashed lines, in some embodiments, the hierarchical maximization circuit 300 is connected via a storage J... n-1 The optional pipelined trigger 438 of [k:0]–J0[k:0] is pipelined.

[0065] The hierarchical maximum circuit 300, zero or more other hierarchical maximum circuits, maximum circuits 110(1) and 110(0), comparator / AND pairs, comparators, and AND components can be implemented in any technically feasible manner. For example, in some embodiments, the hierarchical maximum circuit 300, zero or more other hierarchical maximum circuits, maximum circuits 110(1) and 110(0), zero or more other maximum circuits, comparator / AND pairs, comparators, AND components, or any combination thereof are synthesized based on the behavioral description of the functions described herein. In the same or other embodiments, the hierarchical maximum circuit 300, zero or more other hierarchical maximum circuits, maximum circuits 110(1) and 110(0), zero or more other maximum circuits, comparator / AND pairs, comparators, AND components, or any combination thereof are implemented using one or more components from any number of standard cell libraries, any number of FPGA libraries, any number of other discrete components, any amount and / or type of custom logic and / or layout, or any combination thereof.

[0066] Note that the techniques described herein are illustrative and not restrictive, and may be modified without departing from the broader spirit and scope of the invention. Many modifications and variations to the functions described herein, within the context of the layered maximum circuit 300, maximum circuits 110(1) and 110(0), comparator / AND pairs, comparators, and AND components, will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

[0067] Specifically, the functionality described herein can be modified to implement a hierarchical minimum circuit (not shown) as an alternative to or in addition to the hierarchical maximum circuit 300. For example, in some embodiments, the hierarchical minimum circuit is a modified form of the hierarchical maximum circuit 300, wherein the maximum circuit 100(1) and the maximum circuit 100(0) are replaced by a first minimum circuit and a zeroth minimum circuit, respectively, but the mask sub-circuit 370 and the routing remain unchanged. In operation, the first minimum circuit and the zeroth minimum circuit generate (rk) MSBs and k LSBs of the minimum value in the input values ​​110(n-1)–110(0), respectively.

[0068] Any number of techniques described herein can be implemented in any amount and / or type of software, hardware, or any combination thereof. In some embodiments, any number of hierarchical maximum circuits, including any number of maximum circuits and zero or more other maximum circuits, can be implemented in any technically feasible manner in any number and / or type of other circuits, data paths, pipelines, functional units, execution units, or any other component of the processor. In some embodiments, each hierarchical maximum circuit may be the same as, and may be different from, zero or more other hierarchical maximum circuits. In the same or other embodiments, each maximum circuit may be the same as, and may be different from, zero or more other maximum circuits.

[0069] Figure 4 This involves operating on 32 8-bit input values ​​according to various embodiments. Figure 3 A block diagram of the hierarchical maximization circuit 300. More specifically, in some embodiments, the hierarchical maximization circuit 300 calculates a maximum value 190, which is the maximum value among the input values ​​110(31)–110(0). Each of the input values ​​110(31)–110(0) and the maximum value 190 is an unsigned integer value, each represented by eight bits. Regarding Figure 3 , Figure 4 An example is described where n is 32 and r is 8. Therefore, the input values ​​110(31)–110(0) are also represented as I. 31 [7:0]–I0[7:0], and respectively represented as I 31 –I0. The maximum value of 190 is also represented as Max[7:0].

[0070] As shown in the figure, in some embodiments, the layered maximum circuit 300 includes, but is not limited to, maximum circuit 100(1), mask sub-circuit 370, and maximum circuit 100(0). Each of the maximum circuits 110(1) and 110(0) calculates the 4-bit maximum value of the 32 values ​​received via 32 4-bit input ports.

[0071] In some embodiments, the layered maximum circuit 300 will input the values ​​110(31)–110(0) (represented herein as I). 31The four MSBs of each of [7:4]–I0[7:4]) are routed to the input ports of the maximum circuit 100(1). In response, the maximum circuit 100(1) generates four MSBs of the maximum value 190, denoted here as Max[7:4]. As shown, the masking subcircuit 370 drives the 32 four-bit input ports of the maximum circuit 100(0) based on Max[7:4] and the input values ​​110(n-1)–110(0). For an integer variable i from (n-1) to 0, the masking subcircuit 370 generates a value denoted as J. i The output value of [3:0] is routed to the i-th input port of the maximum value circuit 100(0). If I i [7:4] equals Max[7:4], then J i [3:0] equals I i [3:0]. Otherwise, J i [3:0] equals '0000'. In response, the maximum circuit 100(0) generates Max[3:0]. Then the layered maximum circuit 300 outputs a maximum value of 190.

[0072] In some embodiments, and as depicted via dashed lines, the input values ​​110(1)–110(31) have been stored for floating-point sums, and the hierarchical maximum circuit 300 is piped via an optional incremental pipeline flip-flop 418 storing Max[7:4]. In some other embodiments, the hierarchical maximum circuit 300 is piped via a storage J 31 The optional pipelined trigger 438 of [3:0]–J0[3:0] is pipelined.

[0073] Execute minimum / maximum value command

[0074] Figure 5 This is a block diagram of a minimum / maximum value circuit 500 according to various embodiments. In some embodiments, the minimum / maximum value circuit 500 calculates an output value 590 based on a minimum value selection 520 and a source value 510(n-1)–510(0), where n can be any positive integer. In the same or other embodiments, the minimum / maximum value circuit 500 calculates the output value 590 in response to a minimum / maximum value instruction specifying, but not limited to, a minimum value selection 520 and a source value 510.

[0075] Although Figure 5Not shown, but each of the source values ​​510(n-1)–510(0) and the output value 590 is represented by r bits, where r can be any positive integer. In the same or other embodiments, the r bits of each of the source values ​​510(n-1)–510(0) and the output value 590 represent an unsigned integer value (e.g., an exponent). If minimum selection 520 is enabled (e.g., equal to '1'), then the minimum / maximum circuit 500 sets the output value 590 to be equal to the minimum value among the source values ​​510(n-1)–510(0). Otherwise, the minimum / maximum circuit 500 sets the output value 590 to be equal to the maximum value among the source values ​​510(n-1)–510(0). The maximum and minimum values ​​among the source values ​​510(n-1)–510(0) are also referred to herein as the "maximum value" and "minimum value" of the source values ​​510(n-1)–510(0), respectively.

[0076] As shown in the figure, in some embodiments, the minimum / maximum value circuit 500 includes, but is not limited to, conditional inverter sub-circuits 530(n)–530(0) and Figure 1 The maximum value circuit 100 or Figure 3 The hierarchical maximum circuit 300. Each of the conditional inverter sub-circuits 530(n)–530(0) includes, but is not limited to, one or more inverters and one or more multiplexers, wherein each multiplexer is denoted as “MUX”.

[0077] In some embodiments, if minimum selection 520 is enabled, the conditional inverting sub-circuit 530(n-1)–530(0) inverts the source values ​​510(n-1)–510(0) to generate the previously combined Figure 1 and Figure 3 The input value described is 110(n-1)–110(0). Otherwise, the conditional inverter sub-circuit 530(n-1)–530(0) sets the input value 110(n-1)–110(0) to be equal to the source value 510(n-1)–510(0).

[0078] As shown in the figure, the maximum value circuit 100 or the hierarchical maximum value circuit 300 calculates a maximum value of 190, which is equal to the maximum value of the input values ​​110(n-1)–110(0). If minimum value selection 520 is enabled, the conditional inverting sub-circuit 530(n) inverts the maximum value 190 to generate an output value 590 equal to the minimum value among the source values ​​510(n-1)–510(0). Otherwise, the conditional inverting sub-circuit 530(n) sets the output value 590 to be equal to the maximum value 190, which is equal to the maximum value among the source values ​​510(n-1)–510(0).

[0079] Note that the techniques described herein are illustrative and not restrictive, and may be modified without departing from the broader spirit and scope of the invention. In some other embodiments, any number and / or type of circuitry may be used with any number of maximizing circuits, any number of hierarchical maximizing circuits, or any combination thereof to generate the minimum or maximum value of any number of source values ​​in any technically feasible manner.

[0080] Figure 6 This is a flowchart of method steps for calculating the minimum or maximum value among multiple values ​​according to various embodiments. (See also...) Figure 1 The system described in –5 describes these method steps, but those skilled in the art will understand that any system configured to perform these method steps in any order is within the scope of this invention.

[0081] As shown in the figure, method 600 begins at step 602, where a component implemented in software, hardware, or any combination thereof determines an input value 110 for maximum value calculation. In some embodiments, the component may be a maximum value circuit 100, a hierarchical maximum value circuit 300, a minimum / maximum value circuit 500, etc., and the component may determine the input value in any technically feasible manner. In step 604, the component selects the most significant bit position sequence from one or more bit position sequences spanning the MSB to LSB of each of the input values ​​110. In step 606, for each input value 110, the component sets the current input equal to the portion of the input value 110 corresponding to the selected bit position sequence.

[0082] In step 608, for each positive integer value that can be represented by the number of bits in the selected bit position sequence, the component generates a detection result of the integer value, indicating whether at least one of the current inputs is equal to the integer value. In step 610, the component sets the MSB to LSB of the data input to be equal to the detection results of the highest to lowest possible integer values ​​and zero, respectively. In step 612, the component encodes the bit position of the most significant '1' bit of the data input to generate a portion of the selected bit position sequence corresponding to the maximum value.

[0083] In step 614, the component determines whether the selected bit position sequence is the last bit position sequence. If, in step 614, the component determines that the selected bit position sequence is not the last bit position sequence, then method 600 proceeds to step 616. In step 616, the component selects the next highest bit position sequence and sets the current input equal to the corresponding portion of the input value. In step 618, for each input value with a computed portion of the mismatched maximum value in the MSB, the component updates the current input to zero. Method 600 then returns to step 608, where the component generates a new detection result for each integer value based on the current input.

[0084] However, if in step 614 the component determines that the selected bit position sequence is the last bit position sequence, then method 600 proceeds directly to step 620. In step 620, the component determines the output value based on the maximum value. Method 600 then terminates.

[0085] Exemplary System Overview

[0086] Figure 7 This is a block diagram illustrating a system 700 configured to implement one or more aspects of various embodiments. As shown, system 700 includes, but is not limited to, a central programming unit (CPU) 702 and system memory 704 coupled to a parallel processing subsystem 712 via a memory bridge 705 and a communication path 713. In some embodiments, at least a portion of system memory 704 is host memory associated with CPU 702. Memory bridge 705 is further coupled to an input / output (I / O) bridge 707 via a communication path 706, and I / O bridge 707 is further coupled to a switch 716.

[0087] In operation, I / O bridge 707 is configured to receive user input from input device 708 (such as a keyboard or mouse) and forward the input to CPU 702 for processing via communication path 706 and memory bridge 705. Switch 716 is configured to provide connectivity between I / O bridge 707 and other components of system 700, such as network adapter 718 and add-on cards 720 and 721.

[0088] As shown in the figure, I / O bridge 707 is coupled to system disk 714, which can be configured to store content, applications, and data used by CPU 702 and parallel processing subsystem 712. Generally, system disk 714 provides non-volatile storage for applications and data and may include fixed or removable hard disk drives, flash memory devices, optical disc read-only memory, digital universal disk read-only memory, Blu-ray, high-definition digital universal disk, or other magnetic, optical, or solid-state storage devices. Although not explicitly shown, other components (such as universal serial bus or other port connections, optical disc drives, digital universal disk drives, film recording devices, etc.) may also be connected to I / O bridge 707.

[0089] In various embodiments, memory bridge 705 may be a northbridge chip, and I / O bridge 707 may be a southbridge chip. Furthermore, any technically suitable protocol may be used to implement communication paths 706 and 713, as well as other communication paths within system 700. Protocols include, but are not limited to, high-speed peripheral component interconnects, accelerated graphics ports, HyperTransport, or any other bus or point-to-point communication protocol known in the art.

[0090] In some embodiments, CPU 702 is the main processor of system 700, controlling and coordinating the operation of other system components. In the same or other embodiments, CPU 702 issues instructions controlling the operation of one or more parallel processors (not shown) included in parallel processing subsystem 712. As mentioned herein, a “parallel processor” can be any computing system, including but not limited to multiple physical units (e.g., processor cores, streaming multiprocessors, etc.) that can be configured to perform any number and / or type of computation simultaneously.

[0091] In some embodiments, each parallel processor may be a parallel processing unit (PPU), a graphics processing unit (GPU), a tensor processing unit, a multi-core central processing unit (CPU), an intelligent processing unit, a neural processing unit, a neural network processor, a data processing unit, a vision processing unit, or any other type of processor or accelerator that currently or in the future can support the parallel execution of multiple threads.

[0092] In some embodiments, the parallel processors may be the same or different, and each parallel processor may be associated with a dedicated parallel processing memory or not. In some embodiments, the parallel processing memory associated with a given parallel processor includes, but is not limited to, one or more types of dynamic random access memory (DRAM). In the same or other embodiments, each set of instructions (e.g., programs, functions, etc.) or "kernel" executed on a given parallel processor resides in the parallel processing memory within the parallel processor.

[0093] In some embodiments, the parallel processing subsystem 712 incorporates circuitry optimized for general-purpose processing. Such circuitry can be incorporated into one or more parallel processors, which can be configured to perform general-purpose processing operations. In the same or other embodiments, the parallel processing subsystem 712 further incorporates circuitry optimized for graphics processing. Such circuitry can be incorporated into one or more parallel processors, which can be configured to perform graphics processing operations. In the same or other embodiments, any number of parallel processors can output data to any number of display devices 710. In some embodiments, zero or more of the parallel processors can be configured to perform general-purpose processing operations instead of graphics processing operations, and zero or more of the parallel processors can be configured to perform both general-purpose processing operations and / or graphics processing operations.

[0094] In some embodiments, the parallel processing subsystem 712 can be coupled with... Figure 7One or more other components may be integrated to form a single system. For example, the parallel processing subsystem 712 may be integrated with the CPU 702 and other interconnect circuitry on a single chip to form a system on the chip. In the same or other embodiments, any number of CPUs 702 and any number of parallel processing subsystems 712 may be distributed across any number of shared geographic locations and / or any number of different geographic locations, and / or implemented in any combination within one or more cloud computing environments (i.e., encapsulated shared resources, software, data, etc.).

[0095] System memory 704 may include, but is not limited to, any number and / or type of system software (e.g., operating systems, device drivers, libraries, utilities, etc.), any number and / or type of software applications, or any combination thereof. The system software and software applications included in system memory 704 can be organized in any technically feasible manner.

[0096] As shown in the figures, in some embodiments, system memory 704 includes, but is not limited to, a programming platform software stack 760 and software applications 790. The programming platform software stack 760 is associated with a programming platform for accelerating computational tasks using hardware in the parallel processing subsystem 712. In some embodiments, the programming platform may be accessible to software developers through, but not limited to, libraries, compiler instructions, and / or extensions to programming languages. In the same or other embodiments, the programming platform may be, but is not limited to, a unified computing device architecture (CUDA). Developed by NVIDIA in Santa Clara, California, the Radeon Open Computing Platform (ROCm) and OpenCL (OpenCL... TM It is developed by the Khronos group, SYCL, or IntelOne application programming interface.

[0097] In some embodiments, the programming platform software stack 760 provides an execution environment for software application 790 and zero or more other software applications (not shown). In the same or other embodiments, software application 790 may include, but is not limited to, any computer software capable of being launched on the programming platform software stack 760. In some embodiments, software application 790 may be, but is not limited to, artificial intelligence applications or workloads, machine learning applications or workloads, deep learning applications or workloads, high-performance computing applications or workloads, virtual desktop infrastructure, or data center workloads.

[0098] In some embodiments, the software application 790 and the programming platform software stack 760 execute under the control of the CPU 702. In the same or other embodiments, the software application 790 may access one or more parallel processors included in the parallel processing subsystem 712 via the programming platform software stack 760. For illustrative purposes, the CPU 702 and any number of parallel processors included in the parallel processing subsystem 712 are... Figure 7 In the context of [the processor], it is referred to as a "processor".

[0099] In operation, software application 790 and / or any number of other software applications cause one or more of these processors to execute any number of instructions sequentially, simultaneously, or in any combination thereof. Each instruction may specify, but is not limited to, an opcode specifying the instruction to be executed, zero or more operands, and any amount of (including none) additional data (e.g., instruction options, operand formats, etc.).

[0100] In some embodiments, as part of executing any number of instructions, one or more processors communicate via one or more maximum value circuits (e.g., Figure 1 The maximum value circuit 100), one or more hierarchical maximum value circuits (e.g., Figure 3 Hierarchical maximum value circuit 300), one or more minimum / maximum value circuits (e.g., Figure 5 The minimum / maximum value circuit (500), or any combination thereof, is used to calculate the maximum value among multiple multi-digit integer values.

[0101] Note that the techniques described herein are illustrative and not restrictive, and can be modified without departing from the broader spirit and scope of the invention. Many modifications and variations to the functionality provided by the software application 790, the programming platform software stack 760, the CPU 702, the parallel processing subsystem 712, one or more parallel processors, one or more computing engines, and the resource manager will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

[0102] It should be understood that the system shown herein is illustrative and variations and modifications are possible. The connection topology (including the number and arrangement of bridges, the number of CPUs 702, and the number of parallel processing subsystems 712) can be modified as needed. For example, in some embodiments, system memory 704 may be directly connected to CPU 702 instead of via memory bridge 705, and other devices may communicate with system memory 704 via memory bridge 705 and CPU 702. In some other alternative topologies, parallel processing subsystems 712 may be connected to I / O bridge 707 or directly to CPU 702 instead of via memory bridge 705. In other embodiments, I / O bridge 707 and memory bridge 705 may be integrated into a single chip rather than existing as one or more discrete devices. Finally, in some embodiments, Figure 7 One or more components shown may be omitted. For example, switch 716 may be omitted, and network adapter 718 and add-on cards 720, 721 will be directly connected to I / O bridge 707. In another example, parallel processing subsystem 712 may be omitted from system 700.

[0103] In summary, the disclosed technique can be used to efficiently calculate the maximum value among multiple values, such as the exponent of a product in a floating-point dot product unit. In some embodiments, the maximum value circuit is implemented via (2 r -1) different detection sub-circuits and a parallel priority encoder calculate the maximum value among n r-bit input values. For (2 r The possible values ​​i range from -1 to 1. If any of the n input values ​​equals i, the i-th detection sub-circuit outputs the i-th detection result as '1'; otherwise, it outputs the i-th detection result as '0'. The i-th detection result is input to the parallel priority encoder as (2... r -1) The i-th bit of the data, and the 0th bit of the data input is restricted to a high level. The parallel priority encoder encodes the bit position of the most significant '1' bit of the data input to determine the maximum value among n input values.

[0104] In the same or other embodiments, the hierarchical maximization circuit computes the maximum value among n r-bit input values ​​via m maximization circuits and (m-1) masking sub-circuits, where m is an integer greater than 1. The hierarchical maximization circuit divides the r-bit positions into a sequence of m-bit positions, where each bit position sequence is associated with a different maximization circuit. In some embodiments, the (m-1)th maximization circuit computes the (m-1)th portion of the maximum value 190, including the MSB, based on the corresponding portion in the input value. For an integer j from (m-2) to 0, the j-th masking sub-circuit routes the j-th portion of each input value in the j-th matching subset of the input values ​​to the corresponding input of the j-th maximization circuit, and routes zero values ​​to each of the other input ports of the j-th maximization circuit. The j-th matching subset of the input values ​​includes one or more input values ​​having an MSB that matches the MSB of the maximum value computed by one or more previous maximization circuits. Therefore, the j-th maximization circuit computes the j-th portion of the maximum value based on the j-th portion of one or more input values ​​in the j-th matching subset of the input values. After the 0th maximum circuit calculates the LSB in the maximum value, the hierarchical maximum circuit outputs the maximum value.

[0105] At least one technical advantage of the disclosed technique over the prior art is that it reduces the latency caused by doubling the number of exponents when calculating the maximum exponent. In this respect, using the disclosed technique, because the comparison is performed between each exponent and a possible value rather than between exponents, the increase in latency attributable to doubling the number of exponents is approximately the latency of the two-input OR gate, rather than the sum of the latency of the comparator and the multiplexer. Furthermore, because adding a pipeline level to the hierarchical maximum circuitry in the pipelined floating-point matrix multiplication data path involves storing only a portion of a single exponent, the hierarchical maximum circuitry is well-suited for pipelined applications. These technical advantages provide one or more technical improvements over prior art methods.

[0106] Any and all combinations of any element of any claim recited in any claim and / or any element described in any way in this application are within the intended scope of these embodiments and protections.

[0107] Various embodiments have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

[0108] Various aspects of this embodiment can be embodied as systems, methods, or computer program products. Therefore, aspects of this disclosure can take the form of entirely hardware embodiments, entirely software embodiments (including firmware, resident software, microcode, etc.), or embodiments combining software and hardware aspects, all of which are collectively referred to herein as “modules,” “systems,” or “computers.” Furthermore, any hardware and / or software techniques, processes, functions, components, engines, modules, or systems described in this disclosure can be implemented as circuits or sets of circuits. Additionally, aspects of this disclosure can take the form of computer program products embodied in one or more computer-readable media having a computer-readable program codec implemented therein.

[0109] Any combination of one or more computer-readable media may be used. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. For example, a computer-readable storage medium can be, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination thereof. More specific examples of computer-readable storage media (a non-exhaustive list) will include the following: an electrical connection having one or more wires, a portable computer disk, a hard disk, a random access memory, a read-only memory, an erasable programmable read-only memory, flash memory, optical fiber, a portable optical disc read-only memory, an optical storage device, a magnetic storage device, or any suitable combination thereof. In the context of this document, a computer-readable storage medium can be any tangible medium that can contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0110] The aspects of this disclosure have been described above with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine. When executed via a processor in a computer or other programmable data processing apparatus, the instructions enable the implementation of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a dedicated processor, or a field-programmable gate array (FPGA).

[0111] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. Each block in a flowchart or block diagram may represent a module, segment, or portion of code, including executable instructions for implementing one or more specified logical functions. It should also be noted that in some alternative embodiments, the functions indicated in the blocks may occur in a different order than indicated in the figures. For example, depending on the functions involved, two consecutively shown blocks may actually execute substantially simultaneously, or these blocks may sometimes execute in reverse order. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware system or a combination of dedicated hardware and computer instructions that performs a specific function or behavior.

[0112] While the foregoing description is directed to embodiments of this disclosure, other and further embodiments of this disclosure may be devised without departing from the basic scope of this disclosure, and the scope of protection is determined by the appended claims.

Claims

1. A circuit comprising: The first plurality of detection sub-circuits include each detection sub-circuit receiving a plurality of r-bit input values ​​and calculating different detection results included in a first plurality of detection results, wherein each detection result included in the first plurality of detection results indicates whether at least one input value included in the plurality of r-bit input values ​​is equal to an integer associated with an index of the corresponding detection sub-circuit, wherein the number of detection sub-circuits is 2. r -1, r is a positive integer, the index is from (2... r -1) to 1; as well as A first encoder, coupled to the plurality of detection sub-circuits, is used for: Determining a first active bit or a last active bit from the first encoder input data, wherein the first active bit corresponds to the most significant bit of the first encoder input data, and the last active bit corresponds to the least significant bit of the first encoder input data, including that each of the first plurality of detection results includes a distinct bit from the first encoder input data; and The bit positions associated with the first active bit or the last active bit are encoded to generate a maximum or minimum value.

2. The circuit of claim 1, wherein the first encoder generates the maximum value, and the circuit further comprises: A plurality of inverters are coupled to a plurality of detection sub-circuits, the plurality of inverters inverting a plurality of source values ​​to generate the plurality of input values; as well as A second plurality of inverters, coupled to the first encoder, invert the maximum value to generate the minimum value.

3. The circuit according to claim 1, wherein the first encoder comprises a parallel priority encoder or a tail detector, wherein the tail detector is an inverted or overridden form of the parallel priority encoder.

4. The circuit of claim 1, wherein the first detection sub-circuit in the plurality of detection sub-circuits comprises: Multiple matching detectors; as well as The OR component is coupled to the plurality of matching detectors.

5. The circuit according to claim 1, further comprising: Multiple pipelined triggers coupled to the first encoder, the multiple pipelined triggers storing the maximum value or the minimum value.

6. The circuit of claim 1, wherein the plurality of input values ​​correspond to a sequence of the most significant bit positions among a plurality of all input values, the maximum value or the minimum value is represented by the sequence of the most significant bit positions of all maximum values ​​or all minimum values, and the circuit further comprises: A masking subcircuit, coupled to the first encoder, generates a plurality of next values ​​associated with the next position sequence based on the plurality of all input values ​​and the maximum or minimum value; A second plurality of detection sub-circuits are coupled to the mask sub-circuit, and the second plurality of detection sub-circuits calculate a second plurality of detection results; as well as A second encoder, coupled to the second plurality of detection sub-circuits, determines the next maximum or next minimum value represented by the next bit position sequence of the total maximum or the total minimum values.

7. The circuit according to claim 6, further comprising: Multiple pipelined flip-flops are coupled to the mask subcircuit, and the multiple pipelined flip-flops store the multiple next values.

8. The circuit of claim 6, wherein the total maximum value or the total minimum value includes the maximum or minimum value among the plurality of total input values.

9. The circuit according to claim 1, wherein the least significant bit or most significant bit of the first encoder input data includes the binary value 1.

10. The circuit of claim 1, wherein the number of detection sub-circuits in the first plurality of detection sub-circuits is 2 raised to the power of the number of bits included in each of the plurality of input values ​​minus 1.

11. The circuit of claim 1, wherein the circuit includes a maximum value circuit, the maximum value circuit being included in the floating-point matrix multiplication data path.

12. A method for performing a maximum value calculation or a minimum value calculation, the method comprising: Receives multiple r-bit input values; Perform one or more detection operations on the plurality of r-bit input values ​​to compute a first plurality of detection results, wherein each of the first plurality of detection results indicates whether at least one input value among the plurality of r-bit input values ​​is equal to an integer associated with the index of the corresponding detection operation, wherein the number of detection operations is 2. r -1, r is a positive integer, the index is from (2... r -1) to 1; Detecting a first active bit or a last active bit from the first encoder input data, the first active bit corresponding to the most significant bit of the first encoder input data, the last active bit corresponding to the least significant bit of the first encoder input data, including each of the first plurality of detection results including a distinct bit from the first encoder input data; and The first or last position associated with the first or last active bit is encoded to generate a maximum or minimum value.

13. The method of claim 12, wherein the first position is encoded to generate the maximum value, and the method further comprises: Invert multiple source values ​​to generate the multiple input values; as well as The maximum value is inverted to generate the minimum value.

14. The method of claim 12, further comprising: Store the maximum or minimum value to implement one or more pipelined operations.

15. The method of claim 12, wherein the plurality of input values ​​correspond to a sequence of the most significant bits of a plurality of all input values, the maximum value or the minimum value is represented by the sequence of the most significant bits of all maximum values ​​or all minimum values, and the method further comprises: Generate multiple next values ​​associated with the next position sequence based on the multiple input values ​​and the maximum or minimum value; Perform one or more detection operations on the plurality of next values ​​to generate a second plurality of detection results; Detecting a second active bit from the second encoder input data, including each of the second plurality of detection results including a different bit of the second encoder input data; as well as The second position associated with the second active position is encoded to generate the next maximum or the next minimum value represented by the next position sequence of the all maximum or the all minimum values.

16. The method of claim 12, wherein the maximum value or the minimum value includes the maximum or minimum value among the plurality of input values.

17. The method of claim 12, wherein the least significant bit of the first encoder input data includes the binary value 1.

18. The method of claim 12, wherein the first plurality of detection results are associated with a range of integers spanning from 1 to 2, which is a power of the number of bits included in each of the plurality of input values ​​minus 1.

19. The method of claim 12, wherein the plurality of input values ​​comprises a plurality of indices.

20. One or more non-transitory computer-readable media comprising instructions that, when executed by one or more processors, cause the one or more processors to perform a maximum or minimum value calculation by performing the following steps: Receives multiple r-bit input values; Perform one or more detection operations on the plurality of r-bit input values ​​to compute a first plurality of detection results, wherein each of the first plurality of detection results indicates whether at least one input value among the plurality of r-bit input values ​​is equal to an integer associated with the index of the corresponding detection operation, wherein the number of detection operations is 2. r -1, r is a positive integer, the index is from (2... r -1) to 1; Detecting a first active bit or a last active bit from the first encoder input data, the first active bit corresponding to the most significant bit of the first encoder input data, the last active bit corresponding to the least significant bit of the first encoder input data, including each of the first plurality of detection results including a distinct bit from the first encoder input data; and The first or last position associated with the first or last active bit is encoded to generate a maximum or minimum value.

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