HQOS rate limiting methods, devices, boards, and storage media

Abstract

This application relates to the field of communication transmission, and particularly to a rate limiting method, apparatus, board, and storage medium for HQOS. The method includes: obtaining a rate limiting configuration; wherein the rate limiting configuration includes: load sharing of each path, egress port type, and initial rate limiting value of each node on the HQOS scheduling tree; calculating a weight factor for each node based on the load sharing and the egress port type; and obtaining the actual rate limiting value of each node based on the weight factor and the initial rate limiting value of each node. In the embodiments of this application, obtaining the rate limiting configuration, acquiring the weight factor of each node on the HQOS scheduling tree based on the port type and load sharing in the rate limiting configuration, and adjusting the initial rate limiting value of each node based on the weight factor to obtain a personalized actual rate limiting value for each node, is beneficial for adjusting the actual rate limiting value and rationally allocating forwarding resources.

Description

Technical Field

[0001] This application relates to the field of communication transmission, and in particular to a rate limiting method, apparatus, board, and storage medium for HQOS. Background Technology

[0002] In a distributed system, when the pseudowire (PW) egress deployed on a single board is an equal cost multi-path route (ECMP), the ECMP egress port belongs to multiple egress boards. When the PW uses hierarchical quality of service (HQOS) to perform information transmission, HQOS rate limiting is performed on each egress board. Each node on the HQOS scheduling tree corresponds to a different egress board. The traditional method is to set the same rate limit value for each egress board, or to divide it equally among all egress boards. For example, if the PW rate limit is 100M, then the rate limit for each egress board is 100M, or 100M divided by the total number of egress boards.

[0003] However, in actual network deployments, after PW traffic is distributed via ECMP, the final traffic volume distributed across each egress board is often uneven. Setting the same rate limit for each egress board will lead to unreasonable allocation of traffic resources. Summary of the Invention

[0004] The main objective of this application is to propose a rate limiting method, device, board, and storage medium for HQOS, so as to reasonably allocate PW interface traffic resources when using HQOS for traffic transmission.

[0005] To achieve the above objectives, this application provides an HQOS rate limiting method applied to a board supporting pseudowires, comprising: obtaining a rate limiting configuration; wherein the rate limiting configuration includes: load sharing of each path, egress type, and initial rate limiting value of each node on the HQOS scheduling tree; calculating a weight factor for each node based on the load sharing and egress type; and obtaining the actual rate limiting value of each node based on the weight factor and the initial rate limiting value of each node.

[0006] To achieve the above objectives, embodiments of this application also provide an HQOS speed limiting device that supports pseudolines, including:

[0007] An acquisition unit is used to acquire a rate limiting configuration, wherein the rate limiting configuration includes: load sharing of each path, egress type, and initial rate limiting value of each node on the HQOS scheduling tree; a calculation unit is used to calculate the weight factor of each node based on the load sharing and egress type; and an execution unit is used to obtain the actual rate limiting value of each node based on the weight factor of each node and the initial rate limiting value of each node.

[0008] To achieve the above objectives, this application also provides a single-board unit, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to execute the above-described HQOS rate limiting method.

[0009] To achieve the above objectives, a computer-readable storage medium is provided, storing a computer program that, when executed by a processor, implements the HQOS rate limiting method described above.

[0010] In some embodiments, the HQOS rate limiting device proposed in this application obtains the rate limiting configuration, acquires the weight factor of each node on the HQOS scheduling tree based on the port type and load sharing in the rate limiting configuration, adjusts the initial rate limiting value of each node based on the weight factor, and obtains the personalized actual rate limiting value of each node, which is beneficial for adjusting the actual rate limiting value and rationally allocating forwarding resources. Attached Figure Description

[0011] Figure 1 This is a flowchart of an HQOS speed limiting method according to one embodiment of this application;

[0012] Figure 2 This is a schematic diagram of the HQOS speed limiting method according to one embodiment of this application;

[0013] Figure 3 This is a schematic diagram of an HQOS speed limiting method according to one embodiment of this application;

[0014] Figure 4 This is a reference schematic diagram of an HQOS speed limiting method according to one embodiment of this application;

[0015] Figure 5 This is a schematic diagram of a reference module for an HQOS speed limiting method according to one embodiment of this application;

[0016] Figure 6 This is a schematic diagram of an HQOS speed limiting device according to one embodiment of this application;

[0017] Figure 7This is a schematic diagram of a single board according to one embodiment of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the various embodiments of this application will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the various embodiments of this application to help readers better understand this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various changes and modifications based on the following embodiments. The division of the various embodiments below is for the convenience of description and should not constitute any limitation on the specific implementation of this application. The various embodiments can be combined with and referenced by each other without contradiction.

[0019] The terms "first" and "second" used in the embodiments of this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a system, product, or device that includes a series of components or units is not limited to the listed components or units, but may optionally include unlisted components or units, or may optionally include other components or units inherent to such products or devices. In the description of this application, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0020] One embodiment of the present invention relates to an HQOS rate limiting method. It is applied to a single-board system that supports pseudowires, and the specific process is as follows: Figure 1 As shown.

[0021] Step 101: Obtain the rate limiting configuration; wherein, the rate limiting configuration includes: load sharing of each path, egress type, and initial rate limiting value of each node on the HQOS scheduling tree;

[0022] Step 102: Calculate the weighting factor for each node based on load sharing and output type;

[0023] Step 103: Based on the weight factor of each node and the initial speed limit value of each node, obtain the actual speed limit value of each node.

[0024] In this embodiment, the rate limiting configuration is obtained, and the weight factor of each node on the HQOS scheduling tree is obtained based on the port type and load sharing in the rate limiting configuration. The initial rate limiting value of each node is adjusted according to the weight factor to obtain the personalized actual rate limiting value of each node, which is beneficial for adjusting the actual rate limiting value and reasonably allocating forwarding resources.

[0025] The implementation details of the HQOS rate limiting method in this embodiment are described below. The following content is only for the convenience of understanding and is not necessary for implementing this solution.

[0026] In step 101, the rate limiting configuration is obtained; wherein, the rate limiting configuration includes: load sharing of each path, egress type and initial rate limiting value of each node on the HQOS scheduling tree.

[0027] Specifically, the Power Controller (PW) runs on a single board. The PW's egress is in ECMP mode, and in ECMP mode, the PW's egress ports belong to multiple egress boards, with some cases where multiple egress ports belong to a single egress board. HQOS is used for information transmission within the PW, and HQOS rate limiting is executed on each egress board. Each node in the HQOS scheduling tree within the PW corresponds to a specific egress board. The HQOS location rate limiting configuration includes: load sharing for each path, egress type, and the initial rate limit value for each node in the HQOS scheduling tree. The load sharing for each path refers to the load of each egress port in ECMP mode; the initial rate limit value for each node in the HQOS scheduling tree is the initial rate limit value on each egress board.

[0028] In one example, obtaining the rate limiting configuration may involve receiving a rate limiting configuration sent by the motherboard. Upon receiving the rate limiting configuration from the motherboard, if it is not a direct plaintext data transmission, the board may also perform local data parsing to obtain the required rate limiting configuration. The received rate limiting configuration may be stored locally on the board or in a TM chip that is communicatively connected to the board. The motherboard may also be a main control module.

[0029] In step 102, the weighting factor of each node is calculated based on the load sharing and the type of the output terminal. Specifically, in this embodiment, the weighting factor of each node is obtained based on the initial load sharing and the type of the output terminal, thereby adaptively adjusting the speed limiting configuration of each node according to the weighting factor.

[0030] In one example, the egress port type includes: physical port or link aggregation port. Based on load balancing and egress port type, the weighting factor for each node is calculated. For example, the bandwidth ratio of each member in the link aggregation port is calculated. The weighting factor for each node is calculated based on the load balancing of the physical port and link aggregation port corresponding to each node, and the bandwidth ratio of each member in the link aggregation port corresponding to each node. The link aggregation port can be a link aggregation segment routing (SR) port, used to handle the forwarding path of the tunnel, reducing the use of complex forwarding control protocols. The weighting factor for each node is calculated based on load balancing and egress port type. For example, real-time network congestion detection is performed by classifying or prioritizing physical ports and link aggregation ports. Based on the detection status of each port compared with the total data traffic, the actual weight and rate limiting required for each port are calculated.

[0031] In one example, the weighting factor of each node is calculated based on the load sharing of the physical ports and link aggregation ports corresponding to each node, as well as the bandwidth ratio of each member in the link aggregation port corresponding to each node. For example, the load sharing of the link aggregation port is updated according to the bandwidth ratio of each member; for each node, the load sharing of the physical port corresponding to the node and the updated load sharing of the members in the link aggregation port corresponding to the node are added together to obtain a first sum, and the ratio of the first sum to the total load sharing is obtained. The ratio is the weighting factor of the node; where the total load sharing is obtained by adding the load sharing of all paths. That is, the initial load sharing of the physical port is not processed, the load sharing of the link aggregation port is updated according to the bandwidth of the members, and the weighting factor of each node is calculated based on the updated load sharing of the members in the link aggregation port and the initial load sharing of the physical port.

[0032] In step 103, the actual rate limit value for each node is obtained based on the weight factor of each node and the initial rate limit value of each node. For example, the actual rate limit value for each node is obtained by multiplying the initial rate limit value of each node by the calculated weight factor, which makes the allocation of forwarding resources more reasonable and improves the user experience.

[0033] In one example, the initial rate limit value for each node includes at least the initial rate limit value of each node and the initial rate limit value of the first priority message in each node. The actual rate limit value for each node is obtained based on the node's weight factor and its initial rate limit value, including: obtaining the actual rate limit value of each node based on its weight factor and its initial rate limit value; and obtaining the actual rate limit value of the first priority message in each node based on its weight factor and the initial rate limit value of the first priority message in each node. For example, the first priority message is a cos7 message, and the second priority message is a default message. After obtaining the weight factor for the node, the initial rate limit value and the cos7 message are assigned the weight value respectively, i.e., both types of messages are adjusted according to the weight factor. When the original rate limits for the two types of messages are inconsistent, they are calculated separately using the weight factor to maintain the proportional relationship of message transmission in the current node, avoiding additional adaptive adjustments due to changes in the proportion, and reducing unnecessary system resource consumption.

[0034] In one example, after obtaining the actual speed limit value of each node, the process further includes: writing the actual speed limit value into the TM chip in the single board to update the speed limit configuration. That is, after obtaining the actual speed limit value, the actual speed limit value is saved to the TM chip in the single board, updating the originally obtained speed limit configuration in the single board. This facilitates direct invocation when the same conditions exist during subsequent HQOS data transmission, avoiding duplicate calculations and wasting computing resources.

[0035] In one example, one implementation of this application can be described as being achieved through configuring a control plane and a data forwarding plane. For the control plane, the "Master Control PW HQOS Configuration Module" receives HQOS rate limiting configurations. The "Board PW HQOS Parsing Module" parses the received non-plaintext data. The "Board ECMP Weight Factor Calculation Module" calculates the weight factors of each node in the HQOS scheduling tree based on the load sharing and egress type in the rate limiting configuration. Combining these weight factors, a new rate limiting value is obtained, and the updated HQOS scheduling tree is written to the TM chip according to the new rate limiting value. For the data forwarding plane, data traffic passes through the "Board PW Traffic Forwarding Module" and is delivered to the egress boards of each path according to the load sharing weights of each ECMP path. On the egress boards, the TM chip is invoked to perform HQOS rate limiting and scheduling according to the rate limiting values ​​of each node in the configured HQOS scheduling tree. In some embodiments, after the "Single Board ECMP Weight Factor Calculation Module" calculates the ECMP weight factor of the single board based on the ECMP load sharing path and outgoing port type, it returns the result to the "Single Board PW HQOS Parsing Module." The "Single Board PW HQOS Parsing Module" multiplies the rate limiting value of each node in the HQOS scheduling tree by the weight factor of the node and writes the updated HQOS scheduling tree into the TM chip. In this embodiment, when the PW outgoing port is ECMP, the HQOS rate limiting result matches the load sharing, resulting in more accurate rate limiting and making it easier for users to plan network traffic. The TM chip is referred to as the "Single Board TM Chip Traffic Management Module."

[0036] To facilitate understanding, numerical examples are provided to illustrate the above implementation methods. It should be understood that the following descriptions are merely implementation details for ease of understanding and are not essential for implementing this solution. (Refer to...) Figure 2 .

[0037] S1: Obtain the rate limiting configuration; the rate limiting configuration includes: load sharing of each path, egress type, and initial rate limiting value of each node on the HQOS scheduling tree; for example, receive the rate limiting configuration issued by the "Master Control PW HQOS Configuration Module", PW rate limit 100M, PW is divided into two priorities, cos7 is high priority with a rate limit of 20M, and default is low priority with no rate limit.

[0038] S2: Calculate the weighting factor for each node based on load sharing and egress type; for example, the "Board PW HQOS Parsing Module" receives and parses the rate limiting configuration, calls the "Board ECMP Weighting Factor Calculation Module," and calculates the weighting factor slot_divisor. An example of the calculation process is as follows:

[0039] S21: Obtain the total load sharing (total_ecmp_weight), and sum up the load sharing (w) of all ECMP paths (p) to obtain total_ecmp_weight.

[0040] S22: Calculate the load sharing of each node, local_ecmp_weight, traverse each ECMP path p, determine the outgoing port of path p, if it is a physical port PhyPort, then jump to step S23, if the outgoing port of path p is a link aggregation SG port, then jump to step S24.

[0041] S23: The exit of path P is PhyPort. Determine the board slot number to which PhyPort belongs. If it is the same as the board slot number corresponding to this node, then it is the PhyPort of this node. Add the load sharing w of this path p to local_ecmp_weight.

[0042] S24: The exit point of path p is the link aggregation SG. Iterate through the member ports (PhyPort) of the SG, obtain the bandwidth of each PhyPort, and add this bandwidth to the total bandwidth (total_sg_rate) of the SG. If a member port corresponds to the local node's PhyPort, also add this bandwidth to the local node's bandwidth (local_sg_rate) of the SG. After the iteration is complete, obtain the total_sg_rate and local_sg_rate of the SG. Then, the load sharing of path p (w*(local_sg_rate / total_sg_rate)) is added to local_ecmp_weight.

[0043] S25: Calculate the weight factor slot_divisor for this node:

[0044] slot_divisor=(local_ecmp_weight / total_ecmp_weight).

[0045] S3: Based on the weight factor of each node and the initial rate limit value of each node, the actual rate limit value of each node is obtained; for example, the "single board PW HQOS parsing module" multiplies each rate limit value of the HQOS scheduling tree by the slot_divisor as the rate limit value of this single board and writes it into the TM chip.

[0046] The calculation steps and parameters for S21 to S25 above are shown in the appendix. Figure 3 ,

[0047] total_ecmp_weight = 10 + 30 + 20 + 40 + 15 + 10 = 125, which is the sum of w for p1 to p6.

[0048] The local_ecmp_weight of slot1 on board is obtained by summing the w values ​​of p1, p2, and p4. The exit of p1 is PhyPort, and its w10 can be used directly. The exits of p2 and p4 are SG, and the w value belonging to this board needs to be calculated based on the bandwidth ratio of the member ports of SG. The w value for p2 is 30*(1 / (1+10)) and for p4 it is 40*(10 / (10+10)). Finally, the local_ecmp_weight of slot1 on board is 10+30*(1 / (1+10))+40*(10 / (10+10))=32.7.

[0049] Using the same calculation method: local_ecmp_weight for single board slot2 = 30*(10 / (1+10))+20 = 47.3, local_ecmp_weight for single board slot3 = 40*(10 / (10+10))+15+10 = 45.

[0050] Then, the weight factor slot_divisor of each of the board slots 1 to 3 (i.e., each node on the HQOS scheduling tree) is obtained. The slot_divisor of board slot 1 is 32.7 / 125, the slot_divisor of board slot 2 is 47.3 / 125, and the slot_divisor of board slot 3 is 45 / 125.

[0051] The rate limit value for each board (each node in the HQOS scheduling tree) = initial rate limit value * slot_divisor. The PW rate limit for board slot1 is 100M * (32.7 / 125) = 26.16M, and the cos7 rate limit for board slot1 is 20M * (32.7 / 125) = 5.232M; the PW rate limit for board slot2 is 100M * (47.3 / 125) = 37.84M, and the cos7 rate limit for board slot2 is 20M * (47.3 / 125) = 7.568M; the PW rate limit for board slot3 is 100M * (45 / 125) = 36M, and the cos7 rate limit for board slot3 is 20M * (45 / 125) = 7.2M.

[0052] For hardware module processing, please refer to the appendix. Figure 3 Traffic enters from slot0 of the single board, passes through ECMP and SG two-layer load sharing, and is forwarded to the egress single board slots 1 to 3. HQOS rate limiting is performed according to the TM chip in the single board. The actual rate limiting value of each single board is calculated based on the weight factor of the single board (the node on the HQOS scheduling tree), so it matches the traffic sharing size, which can achieve more accurate rate limiting and scheduling.

[0053] In one example, if the method proposed in the embodiments of this application is not used, the resulting speed limiting will be as follows: Figure 4 As shown. The speed limit values ​​for each export board are equal, and the hardware structure can be referenced. Figure 5 .

[0054] It is understood that the implementation of the present invention is not limited to the above data values. For example, the number of ECMP paths can be more, the number of single-board slots can be more, the number of SG member ports and bandwidth types can be more, and the HQOS policy template can also have more variations.

[0055] In this embodiment, by receiving the rate limiting configuration sent by the motherboard, the weight factors of each node on the HQOS scheduling tree are obtained according to the port type and load sharing in the rate limiting configuration. The initial rate limiting value of each node is adjusted according to the weight factors to obtain the personalized actual rate limiting value of each node. This is beneficial for adjusting the actual rate limiting value and reasonably allocating forwarding resources. It makes the rate limiting value of each board match the traffic sharing of the board, making the rate limiting more accurate and more convenient for users to calculate and allocate network bandwidth.

[0056] The steps of the various methods described above are only for clarity. In practice, they can be combined into one step or some steps can be split into multiple steps. As long as they include the same logical relationship, they are all within the scope of protection of this patent. Adding insignificant modifications or introducing insignificant designs to the algorithm or process, but without changing the core design of the algorithm and process, are also within the scope of protection of this patent.

[0057] One embodiment of the present invention relates to an HQOS speed limiting device, such as... Figure 6 As shown, it includes:

[0058] The acquisition unit 201 is used to acquire the rate limiting configuration; wherein, the rate limiting configuration includes: load sharing of each path, exit type and initial rate limiting value of each node on the HQOS scheduling tree;

[0059] The calculation unit 202 is used to calculate the weighting factor of each node based on the load sharing and the type of the output terminal;

[0060] The execution unit 203 is used to obtain the actual speed limit value of each node based on the weight factor of each node and the initial speed limit value of each node.

[0061] In one example, for the acquisition unit 201, the acquisition of the speed limit configuration includes: receiving the speed limit configuration sent by the motherboard.

[0062] In one example, for computing unit 202, the egress port type includes: physical port or link aggregation port; the step of calculating the weight factor of each node based on the load sharing and egress port type includes: calculating the bandwidth ratio of each member in the link aggregation port; and calculating the weight factor of each node based on the load sharing of the physical port and link aggregation port corresponding to each node, and the bandwidth ratio of each member in the link aggregation port corresponding to each node.

[0063] In one example, calculating the weight factor of each node based on the load sharing of the physical ports and link aggregation ports corresponding to each node, and the bandwidth ratio of each member in the link aggregation ports corresponding to each node, includes: updating the load sharing of the link aggregation ports according to the bandwidth ratio of each member; for each node, adding the load sharing of the physical port corresponding to the node and the updated load sharing of the members in the aggregated link ports corresponding to the node to obtain a first sum; obtaining the ratio of the first sum to the total load sharing, where the ratio is the weight factor of the node; wherein the total load sharing is obtained by adding the load sharing of all paths.

[0064] In one example, for execution unit 203, the initial rate limit value of each node includes at least the initial rate limit value of each node and the initial rate limit value of the first priority message in each node; obtaining the actual rate limit value of each node based on the weight factor of each node and the initial rate limit value of each node includes: obtaining the actual rate limit value of each node based on the weight factor of each node and the initial rate limit value of each node; obtaining the actual rate limit value of the first priority message of each node based on the weight factor of each node and the initial rate limit value of the first priority message in each node.

[0065] In addition, after obtaining the actual speed limit value of each node, the method further includes: writing the actual speed limit value into the TM chip in the single board.

[0066] In this implementation, the rate limiting configuration is obtained, and the weight factor of each node on the HQOS scheduling tree is obtained based on the port type and load sharing in the rate limiting configuration. The initial rate limiting value of each node is adjusted according to the weight factor to obtain the personalized actual rate limiting value of each node, which is beneficial for adjusting the actual rate limiting value and rationally allocating forwarding resources.

[0067] It is not difficult to see that this embodiment is a system embodiment corresponding to the above embodiments, and this embodiment can be implemented in conjunction with the above embodiments. The relevant technical details mentioned in the above embodiments are still valid in this embodiment, and will not be repeated here to reduce repetition. Accordingly, the relevant technical details mentioned in this embodiment can also be applied to the above embodiments.

[0068] It is worth mentioning that all modules involved in this embodiment are logical modules. In practical applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. Furthermore, to highlight the innovative aspects of this invention, this embodiment does not introduce units that are not closely related to solving the technical problem proposed by this invention; however, this does not mean that other units are absent from this embodiment.

[0069] One embodiment of the present invention relates to a single board, such as Figure 7 As shown, it includes at least one processor 301; and,

[0070] The memory 302 is communicatively connected to the at least one processor 301; wherein,

[0071] The memory 302 stores instructions that can be executed by the at least one processor 301, which, when executed by the at least one processor 301, enables the at least one processor 301 to perform the method embodiments described above.

[0072] The memory and processor are connected via a bus, which can include any number of interconnecting buses and bridges, connecting various circuits of one or more processors and memories. The bus can also connect various other circuits, such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and will not be described further herein. The bus interface provides an interface between the bus and the transceiver. The transceiver can be a single element or multiple elements, such as multiple receivers and transmitters, providing a unit for communicating with various other devices over a transmission medium. Data processed by the processor is transmitted over the wireless medium via an antenna, which further receives data and transmits it to the processor.

[0073] The processor manages the bus and general processing, and also provides various functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions. Memory is used to store data used by the processor during operation.

[0074] One embodiment of the present invention relates to a computer-readable storage medium storing a computer program. When executed by a processor, the computer program implements the method embodiments described above.

[0075] That is, those skilled in the art will understand that all or part of the steps in the methods of the above embodiments can be implemented by a program instructing related hardware. This program is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0076] Those skilled in the art will understand that the above embodiments are specific examples of implementing the present invention, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the present invention.

Claims

1. An HQOS speed limiting method, characterized in that, Applications to single-board systems that support pseudo-lines include: Obtain the rate limiting configuration; wherein the rate limiting configuration includes: load sharing of each path, egress type and initial rate limiting value of each node on the HQOS scheduling tree, wherein the initial rate limiting value of each node includes at least the initial rate limiting value of each node and the initial rate limiting value of the first priority packet in each node. Calculate the weighting factor for each node based on the load sharing and the type of the output terminal; Based on the weight factors of each node and the initial speed limit value of each node, the actual speed limit value of each node is obtained; Based on the weight factors of each node and the initial rate limit value of the first priority message of each node, the actual rate limit value of the first priority message of each node is obtained.

2. The HQOS speed limiting method according to claim 1, characterized in that, The egress port type includes: physical port or link aggregation port; The step of calculating the weighting factor for each node based on the load sharing and the outgoing terminal type includes: Calculate the bandwidth ratio of each member in the link aggregation port; The weighting factor of each node is calculated based on the load sharing of the physical ports and link aggregation ports corresponding to each node, and the bandwidth ratio of each member in the link aggregation ports corresponding to each node.

3. The HQOS speed limiting method according to claim 2, characterized in that, The calculation of the weighting factor for each node based on the load sharing of the physical ports and link aggregation ports corresponding to each node, and the bandwidth ratio of each member in the link aggregation ports corresponding to each node, includes: The load balancing of the link aggregation port is updated according to the bandwidth ratio of each member; For each node, the load sharing of the physical port corresponding to the node and the updated load sharing of the aggregated link port corresponding to the node are added together to obtain a first sum; the ratio of the first sum to the total load sharing is obtained, and the ratio is the weighting factor of the node; wherein, the total load sharing is obtained by adding the load sharing of all paths.

4. The HQOS speed limiting method according to claim 1, characterized in that, After obtaining the actual speed limit values ​​for each node, the process further includes: The actual speed limit value is written into the TM chip in the single board.

5. The HQOS speed limiting method according to claim 1, characterized in that, The process of obtaining the speed limit configuration includes: Receive the speed limit configuration sent by the motherboard.

6. An HQOS speed limiting device, characterized in that, Supports pseudolines, including: An acquisition unit is used to acquire a rate limiting configuration; wherein the rate limiting configuration includes: load sharing of each path, egress type and initial rate limiting value of each node on the HQOS scheduling tree, wherein the initial rate limiting value of each node includes at least the initial rate limiting value of each node and the initial rate limiting value of the first priority packet in each node. A calculation unit is used to calculate the weighting factor of each node based on the load sharing and the type of the output terminal; The execution unit is configured to obtain the actual rate limit value of each node based on the weight factor of each node and the initial rate limit value of each node; and to obtain the actual rate limit value of the first priority message of each node based on the weight factor of each node and the initial rate limit value of the first priority message of each node.

7. A single-board unit, characterized in that, include: At least one processor; as well as, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the HQOS rate limiting method as described in any one of claims 1 to 5.

8. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the HQOS rate limiting method as described in any one of claims 1 to 5.

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