A page table modification method, a verification method, a device, and an electronic device

Abstract

Embodiments of the present application disclose a page table modification method, a verification method, a device and an electronic device, and relate to the technical field of processors. The method is provided to improve the efficiency of verifying the characteristics of a processor and / or the attributes of a page table. The method comprises: applying a first virtual address space and a second virtual address space; wherein the first virtual address space is mapped to a first physical address space by a first page table, and the second virtual address space is mapped to a second physical address space by a second page table; writing the base address of an mth-level page table in the first page table into a page table entry of an nth-level page table of the second page table to form a third page table; wherein m is an integer greater than or equal to 1 and less than or equal to the number of levels of the first page table; n is an integer greater than or equal to m and less than or equal to the number of levels of the second page table; and modifying the first page table according to the third page table. The present application is suitable for verifying a processor and / or a page table.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of processors, and in particular to a page table modification method and device, a page table verification method and device, an electronic device, and a readable storage medium. BACKGROUND

[0002] Paging plays an important role in modern processors and operating systems. Most processors have supported paging mechanisms for a long time. The basic task of paging is to map virtual addresses in a process to physical addresses. This mapping is controlled by an operating system and provides a continuous virtual address space for user applications, which can achieve memory isolation and security between processes.

[0003] In processor feature or page table attribute verification work, problems such as changing page tables may be encountered. Page tables are stored in physical memory and managed by an operating system. Therefore, the modification process of page tables is relatively complex in verification work, which leads to low verification efficiency. SUMMARY

[0004] Therefore, embodiments of the present application provide a page table modification method and device, a page table verification method and device, an electronic device, and a readable storage medium, which facilitate improving the efficiency of processor feature and / or page table attribute verification.

[0005] In a first aspect, embodiments of the present application provide a page table modification method, including: applying for a first virtual address space and a second virtual address space; wherein the first virtual address space is mapped to a first physical address space through a first page table, and the second virtual address space is mapped to a second physical address space through a second page table; writing a base address of an mth-level page table in the first page table into a page table entry of an nth-level page table in the second page table to form a third page table; wherein m is an integer greater than or equal to 1 and less than or equal to the number of levels of the first page table; n is an integer greater than or equal to m and less than or equal to the number of levels of the second page table; and modifying the first page table according to the third page table.

[0006] According to a specific implementation manner of embodiments of the present application, the applying for a first virtual address space and a second virtual address space includes: applying for the first virtual address space and the second virtual address space through a dynamic memory allocation function.

[0007] According to a specific implementation manner of the embodiment of the present application, the method further includes: obtaining the base address of the mth-level page table in the first page table; and writing the base address of the mth-level page table into the page table entry of the n th-level page table of the second page table to form the third page table; the third page table sequentially includes the first-level page table to the n th-level page table of the second page table, the mth-level page table of the first page table, and the t-level page table after the mth-level page table in the first page table; t is a difference value greater than or equal to 0 and less than or equal to the number of levels of the second page table minus n minus 1; and the modifying the first page table according to the third page table includes: writing data into the page table entry in the mth-level page table plus t plus 1th-level page table of the first page table according to the third page table to modify the first page table.

[0008] According to a specific implementation manner of the embodiment of the present application, the obtaining the base address of the mth-level page table in the first page table includes: obtaining the base address of the first page table through a kernel driver module; and obtaining the base address of the mth-level page table in the first page table according to the base address of the first page table; and the writing the base address of the mth-level page table into the page table entry of the n th-level page table of the second page table includes: obtaining the base address of the second page table through the kernel driver module; obtaining the address of the page table entry of the n th-level page table in the second page table according to the base address of the second page table; and writing the base address of the mth-level page table into the page table entry of the n th-level page table of the second page table according to the address of the page table entry of the n th-level page table.

[0009] According to a specific implementation manner of the embodiment of the present application, the number of levels of the first page table is 4, the number of levels of the second page table is four, m and n are equal to three, and the writing the base address of the mth-level page table into the page table entry of the n th-level page table of the second page table includes: writing the base address of the third-level page table of the first page table into the page table entry of the third-level page table of the second page table.

[0010] According to a specific implementation manner of the embodiment of the present application, the writing data into the page table entry in the mth-level page table plus t plus 1th-level page table of the first page table according to the third page table includes: determining a first virtual address range; the first virtual address range corresponds to the mth-level page table plus t plus 1th-level page table of the first page table on the third page table; obtaining the page table entry of the mth-level page table plus t plus 1th-level page table according to the first virtual address range and the third page table; modifying the page table entry of the mth-level page table plus t plus 1th-level page table, and writing the modified page table entry of the mth-level page table plus t plus 1th-level page table into a corresponding position of the mth-level page table plus t plus 1th-level page table.

[0011] According to a specific implementation manner of the embodiment of the present application, the determining the first virtual address range comprises: determining a target bit corresponding to the m+t+1th level page table in a base address of the second virtual address space; determining a first value on a bit equal to the target bit in a base address of the first virtual address space; determining a base address of the first virtual address range according to the first value and the base address of the second virtual address space; determining a size of the first virtual address range; and determining the first virtual address range according to the base address of the first virtual address range and the size of the first virtual address range.

[0012] According to a specific implementation manner of the embodiment of the present application, the determining the size of the first virtual address range comprises: determining the size of the first virtual address range according to a number of entries of the page table entry of the m+t+1th level page table and a size of each page table entry.

[0013] According to a specific implementation manner of the embodiment of the present application, before the writing the base address of the mth level page table into the page table entry of the n th level page table of the second page table, the method further comprises: judging whether a number of entries of the page table entry of the n th level page table is 1; and if yes, performing the step of writing the base address of the mth level page table into the page table entry of the n th level page table of the second page table.

[0014] According to a specific implementation manner of the embodiment of the present application, before the obtaining the base address of the mth level page table in the first page table, the method further comprises: traversing the first page table and the second page table to determine that the first page table and the second page table have no page fault.

[0015] According to a specific implementation manner of the embodiment of the present application, after the determining that the first page table and the second page table have no page fault, the method further comprises: saving a page table entry of an n th level page table of the second page table; and / or, saving a page table entry in an m+t+1th level page table of the first page table.

[0016] According to a specific implementation manner of the embodiment of the present application, after the saving the page table entry of the n th level page table of the second page table; and / or, the saving the page table entry in the m+t+1th level page table of the first page table, the method further comprises: restoring the page table entry of the n th level page table of the second page table using the saved page table entry; and / or, restoring the page table entry in the m+t+1th level page table of the first page table using the saved page table entry in the m+t+1th level page table of the first page table.

[0017] In a second aspect, the embodiments of the present application provide a verification method, comprising: obtaining target data by a test code through a page table; wherein the test code is used to verify a feature of a processor and / or an attribute of the page table; the page table is created according to the modification method of the page table in any of the above embodiments; the test code runs on the processor; and the feature of the processor and / or the attribute of the page table are verified according to the target data.

[0018] In a third aspect, the embodiments of the present application provide a modification device of a page table, comprising: an application module, configured to apply a first virtual address space and a second virtual address space; wherein the first virtual address space is mapped to a first physical address space through a first page table, and the second virtual address space is mapped to a second physical address space through a second page table; a writing module, configured to write a base address of an mth-level page table in the first page table into a page table entry of an nth-level page table of the second page table, to form a third page table; wherein m is an integer greater than or equal to 1 and less than or equal to a number of levels of the first page table; n is an integer greater than or equal to m and less than or equal to a number of levels of the second page table; and a modification module, configured to modify the first page table according to the third page table.

[0019] According to a specific implementation of the embodiments of the present application, the application module is specifically configured to apply the first virtual address space and the second virtual address space through a dynamic memory allocation function.

[0020] According to a specific implementation of the embodiments of the present application, the writing module comprises: an obtaining submodule, configured to obtain the base address of the mth-level page table in the first page table; and a writing submodule, configured to write the base address of the mth-level page table into the page table entry of the nth-level page table of the second page table, to form the third page table; wherein the third page table comprises, in sequence, a first-level page table to an nth-level page table of the second page table, an mth-level page table of the first page table, and t-level page tables after the mth-level page table in the first page table; wherein t is an integer greater than or equal to 0 and less than or equal to a difference between a number of levels of the second page table minus n and 1; and the modification module comprises a modification submodule, configured to write data into a page table entry in an m+t+1th-level page table of the first page table according to the third page table, to modify the first page table.

[0021] According to a specific implementation manner of the embodiment of the present application, the obtaining sub-module is specifically configured to: obtain the base address of the first page table through a kernel driver module; and obtain the base address of the mth-level page table in the first page table according to the base address of the first page table. The modifying sub-module is specifically configured to: obtain the base address of the second page table through the kernel driver module; obtain the address of the page table entry of the nth-level page table in the second page table according to the base address of the second page table; and write the base address of the mth-level page table into the page table entry of the nth-level page table of the second page table according to the address of the page table entry of the nth-level page table.

[0022] According to a specific implementation manner of the embodiment of the present application, the number of levels of the first page table is four, and the number of levels of the second page table is four; m and n are equal to three; and the writing sub-module is specifically configured to: write the base address of the third-level page table of the first page table into the page table entry of the third-level page table of the second page table.

[0023] According to a specific implementation manner of the embodiment of the present application, the modifying sub-module is specifically configured to: determine a first virtual address range; wherein the first virtual address range corresponds to the mth+t+1th-level page table of the first page table on the third page table; obtain the page table entry of the mth+t+1th-level page table according to the first virtual address range and the third page table; modify the page table entry of the mth+t+1th-level page table, and write the modified page table entry of the mth+t+1th-level page table into a corresponding position of the mth+t+1th-level page table.

[0024] According to a specific implementation manner of the embodiment of the present application, the modifying sub-module is specifically configured to: determine a target bit corresponding to the mth+t+1th-level page table in the base address of the second virtual address space; determine a first value on a bit equal to the target bit in the base address of the first virtual address space; determine the base address of the first virtual address range according to the first value and the base address of the second virtual address space; determine the size of the first virtual address range; and determine the first virtual address range according to the base address of the first virtual address range and the size of the first virtual address range.

[0025] According to a specific implementation manner of the embodiment of the present application, the modifying sub-module is specifically configured to: determine the size of the first virtual address range according to the number of entries of the page table entry of the mth+t+1th-level page table and the size of each page table entry.

[0026] According to a specific implementation manner of the embodiment of the present application, the device further comprises: a judging module, configured to judge whether the number of entries of the entry of the (n)th level page table of the second page table is 1 before the writing module writes the base address of the (m)th level page table into the entry of the (n)th level page table of the second page table; and an executing module, configured to execute the step of writing the base address of the (m)th level page table into the entry of the (n)th level page table of the second page table if the number of entries is 1.

[0027] According to a specific implementation manner of the embodiment of the present application, the device further comprises: a traversing module, configured to traverse the first page table and the second page table to determine that the first page table and the second page table have no missing pages before the obtaining submodule obtains the base address of the (m)th level page table in the first page table.

[0028] According to a specific implementation manner of the embodiment of the present application, the device further comprises: a saving module, configured to save the entry of the (n)th level page table of the second page table and / or the entry of the (m+t+1)th level page table of the first page table after the traversing module determines that the first page table and the second page table have no missing pages.

[0029] According to a specific implementation manner of the embodiment of the present application, the device further comprises: a restoring module, configured to restore the entry of the (n)th level page table of the second page table and / or the entry of the (m+t+1)th level page table of the first page table after the saving module saves the entry of the (n)th level page table of the second page table and / or the entry of the (m+t+1)th level page table of the first page table.

[0030] In a fourth aspect, an embodiment of the present application provides a verification device, comprising: an obtaining module, configured to obtain target data by a test code; wherein the test code is used to verify a characteristic of a processor and / or an attribute of a page table; the page table is created according to the modification method of the page table in any of the preceding embodiments; and the test code runs on the processor; and a verifying module, configured to verify the characteristic of the processor and / or the attribute of the page table according to the target data.

[0031] In a fifth aspect, an electronic device is provided, and the electronic device comprises a housing, a processor, a memory, a circuit board and a power supply circuit, wherein the circuit board is arranged inside a space enclosed by the housing, the processor and the memory are arranged on the circuit board; the power supply circuit is configured to supply power to each circuit or device of the electronic device; the memory is configured to store executable program codes; and the processor is configured to run a program corresponding to the executable program codes by reading the executable program codes stored in the memory, so as to execute the page table modification method and / or the verification method according to any one of the preceding embodiments.

[0032] In a sixth aspect, a computer readable storage medium is provided, and the computer readable storage medium stores one or more programs, and the one or more programs are executable by one or more processors to implement the page table modification method and / or the verification method according to any one of the preceding embodiments.

[0033] The page table modification method, the processor verification method, the device, the electronic device and the readable storage medium provided by the embodiments of the present application apply for a first virtual address space and a second virtual address space; the first virtual address space is mapped to a first physical address space through a first page table, and the second virtual address space is mapped to a second physical address space through a second page table; a base address of an mth-level page table in the first page table is written into a page table entry of an nth-level page table in the second page table to form a third page table; and then the first page table is modified according to the third page table, so as to facilitate improving the efficiency of verifying the characteristics of the processor and / or the attributes of the page table. BRIEF DESCRIPTION OF DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0035] Figure 1 A flowchart of the page table modification method provided by an embodiment of the present application is shown in the figure;

[0036] Figure 2 A schematic diagram of the third page table provided by a specific embodiment of the present application is shown in the figure;

[0037] Figure 3 A flowchart of the page table modification method provided by a specific embodiment of the present application is shown in the figure;

[0038] Figure 4 A flowchart of the verification method provided by an embodiment of the present application is shown in the figure;

[0039] Figure 5 A flowchart of a verification method provided by an embodiment of the present application is shown in FIG. 1.

[0040] Figure 6 A structure diagram of a page table modification device provided by an embodiment of the present application is shown in FIG. 2.

[0041] Figure 7 A structure diagram of a verification device provided by an embodiment of the present application is shown in FIG. 3.

[0042] Figure 8 A structure diagram of an electronic device provided by an embodiment of the present application is shown in FIG. 4. DETAILED DESCRIPTION

[0043] The embodiments of the present application are described in detail below with reference to the accompanying drawings. It should be noted that the described embodiments are only some of the embodiments of the present application, but not all of the embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of the present application.

[0044] In order for those skilled in the art to better understand the technical concepts, implementation schemes and beneficial effects of the embodiments of the present application, the embodiments are described in detail below.

[0045] A page table modification method provided by an embodiment of the present application facilitates improving the efficiency of verifying the characteristics of a processor and / or the attributes of a page table.

[0046] Figure 1 A flowchart of a page table modification method provided by an embodiment of the present application is shown in FIG. 1. Figure 1 As shown in FIG. 1, the page table modification method of the present embodiment can include:

[0047] S101, a first virtual address space and a second virtual address space are applied for.

[0048] The virtual address space is applied for from an operating system, and a page table is allocated for the virtual address space to complete mapping of a virtual address to a physical address.

[0049] In the present embodiment, the first virtual address space is mapped to a first physical address space through a first page table, and the second virtual address space is mapped to a second physical address space through a second page table.

[0050] The first virtual address space and the second virtual address space of the present embodiment can be of the same size or different sizes.

[0051] The number of levels of the first page table can be equal to the number of levels of the second page table.

[0052] In some examples, the first virtual address space and the second virtual address space are applied for through a dynamic memory allocation function.

[0053] In the embodiment, the dynamic memory allocation function can be malloc function.

[0054] S102, write the base address of the mth level page table in the first page table into the page table entry of the nth level page table of the second page table to form a third page table.

[0055] In the embodiment, m is an integer greater than or equal to 1 and less than or equal to the number of levels of the first page table; n is an integer greater than or equal to m and less than or equal to the number of levels of the second page table.

[0056] If the first page table and the second page table are four-level page tables and the mth level page table in the first page table is the second level page table, the nth level page table of the second page table can be the second level, the third level or the fourth level.

[0057] The number of levels of the third page table can be equal to the number of levels of the first page table and the second page table.

[0058] In the page table, the page table entry in the previous level page table points to or indexes to the next level page table, so that the base address of the mth level page table in the first page table is written into the page table entry of the nth level page table of the second page table, and the mth level page table in the first page table can be indexed by the page table entry of the nth level page table of the second page table.

[0059] S103, modify the first page table according to the third page table.

[0060] In the embodiment, the first page table can be modified according to the formed third page table, and the modified first page table can be used for processor verification.

[0061] In the embodiment, the first virtual address space and the second virtual address space are applied; the first virtual address space is mapped to the first physical address space through the first page table, the second virtual address space is mapped to the second physical address space through the second page table, the base address of the mth level page table in the first page table is written into the page table entry of the nth level page table of the second page table to form a third page table, and the first page table is modified according to the third page table, so that the efficiency of verifying the characteristics of the processor and / or the attributes of the page table is improved, and the problem of low verification efficiency caused by the operating system managing the page table in the prior art is avoided.

[0062] It can be understood that the above process can be completed by the user state process, that is, the first page table can be modified in the user state.

[0063] Another embodiment of the present application is basically the same as the above embodiment, except that the embodiment writes the base address of the mth level page table in the first page table into the page table entry of the nth level page table of the second page table to form a third page table (S102), which can include:

[0064] S102a, obtaining a base address of an m-level page table in the first page table.

[0065] In some examples, obtaining the base address of the m-level page table in the first page table (S102a) can include:

[0066] A1, obtaining the base address of the first page table by a kernel driver module.

[0067] The kernel driver module can interact with the kernel state or the operating system, so that the base address of the first page table stored in the kernel state can be obtained by the kernel driver module. In some examples, the base address of the first page table is stored in the CR3 register, that is, the value in the CR3 register is obtained by the kernel driver module.

[0068] The base address of the first page table can be a base address of a first-level page table in the first page table.

[0069] A2, obtaining the base address of the m-level page table in the first page table according to the base address of the first page table.

[0070] By obtaining the base address of the first page table, that is, the value of the CR3 register, the page table translation process of each page in the first virtual address space can be obtained, that is, the base address of the m-level page table in the first page table can be obtained.

[0071] S102b, writing the base address of the m-level page table into a page table entry of an n-level page table of the second page table to form a third page table.

[0072] The third page table in the embodiment includes the first-level page table to the n-level page table of the second page table, the m-level page table of the first page table, and the t-level page table after the m-level page table in the first page table in turn; wherein t is a difference value greater than or equal to 0 and less than or equal to the number of levels of the second page table minus n minus 1, that is, the total number of page table levels from the first-level page table to the n-level page table of the second page table, the m-level page table of the first page table, and the t-level page table after the m-level page table in the first page table is equal to the number of levels of the first page table or the number of levels of the second page table.

[0073] The base address of the m-level page table is written into the page table entry of the n-level page table of the second page table, so that in the formed third page table, the m-level page table of the first page table can be indexed from the page table entry of the n-level page table of the second page table.

[0074] Referring to Figure 2For example, the base address of the first-level page table of the first page table can be written into the page table entry of the first-level page table, the second-level page table, the third-level page table or the fourth-level page table of the second page table; the base address of the second-level page table of the first page table can be written into the page table entry of the second-level page table, the third-level page table or the fourth-level page table of the second page table; the base address of the third-level page table of the first page table can be written into the page table entry of the third-level page table of the second page table; and the base address of the fourth-level page table of the first page table can be written into the page table entry of the fourth-level page table of the second page table.

[0075] Referring to Figure 2 , the base address of the third-level page table of the first page table is written into the page table entry of the third-level page table of the second page table, the third page table comprises the first-level page table to the third-level page table of the second page table and the third-level page table of the second page table in sequence, and the fourth-level page table of the first page table is the physical address corresponding to the third page table.

[0076] It can be understood that, in some examples, writing the base address of the mth-level page table into the page table entry of the nth-level page table of the second page table (S102b) can comprise:

[0077] B1, obtaining the base address of the second page table through a kernel driver module.

[0078] The kernel driver module can interact with the kernel state or the operating system, so that the base address of the second page table stored in the kernel state can be obtained through the kernel driver module. In some examples, the base address of the second page table is stored in the CR3 register, that is, the value in the CR3 register is obtained through the kernel driver module. In this embodiment, the base addresses of the first page table corresponding to the first virtual address space and the second page table corresponding to the second virtual address space are the same.

[0079] The base address of the second page table can be the base address of the first-level page table in the second page table.

[0080] B2, obtaining the address of the page table entry of the nth-level page table in the second page table according to the base address of the second page table.

[0081] The base address of the second page table obtained, that is, the value of the CR3 register, can obtain the page table translation process of each page in the second virtual address space, that is, the address of the page table entry of the nth-level page table in the second page table can be obtained.

[0082] B3, writing the base address of the mth-level page table into the page table entry of the nth-level page table of the second page table according to the address of the page table entry of the nth-level page table.

[0083] The base address of the mth-level page table is written into the page table entry of the nth-level page table of the second page table, so that the address in the page table entry of the nth-level page table of the second page table can index the mth-level page table of the first page table.

[0084] According to the third page table, modifying the first page table (S103) can include:

[0085] S103a, according to the third page table, writing data to the page table entry in the m+t+1 level page table of the first page table to modify the first page table.

[0086] The base address of the m level page table is written into the page table entry of the n level page table of the second page table to form the third page table, and the last level of the third page table is the m+t level page table of the first page table. In this way, the page table entry in the m+t+1 level page table of the first page table can be used as the corresponding physical address of the third page table. In this way, data can be written to the page table entry in the m+t+1 level page table of the first page table through the third page table. In this way, the page table entry in the m+t+1 level page table of the first page table is changed. Correspondingly, the m+t+1 level page table including the changed page table entry in the first page table is modified.

[0087] Another embodiment of the present application is basically the same as the above-mentioned embodiments, except that in the present embodiment, according to the third page table, writing data to the page table entry in the n+t+1 level page table of the first page table (S103a) can include:

[0088] C1, determining a first virtual address range.

[0089] In the present embodiment, the first virtual address range corresponds to the m+t+1 level page table of the first page table on the third page table, and the page table entry in the m+t+1 level page table of the first page table can be used as the corresponding physical address of the third page table. In this way, the first virtual address range can be mapped to the m+t+1 level page table of the first page table through the third page table.

[0090] The first virtual address range can be determined by a base address and the size of the virtual address range. In some examples, determining the first virtual address range can include:

[0091] C11, determining a target bit in the base address of the second virtual address space corresponding to the m+t+1 level page table.

[0092] The base address of the second virtual address space includes a plurality of bit positions, including a target bit corresponding to the m+t+1 level page table.

[0093] C12, determining a first value on the bit equal to the target bit in the base address of the first virtual address space.

[0094] In the base address of the first virtual address space, the value on the bit equal to the target bit is found, which is the first value.

[0095] C13, determining a base address of the first virtual address range according to the first value and a base address of the second virtual address space.

[0096] The base address of the first virtual address range needs to be equal to the base address of the m+t+1th level page table. If the value of the target bit corresponding to the m+t+1th level page table in the base address of the second virtual address space is a, and the first value of the bit equal to the target bit in the base address of the first virtual address space is b, then the base address of the first virtual address range is the difference between b*8 byte and a.

[0097] C14, determining the size of the first virtual address range.

[0098] In some examples, the size of the first virtual address range is determined according to the number of entries of the page table entry of the m+t+1th level page table and the size of each page table entry.

[0099] The size of the first virtual address range can be the product of the number of entries of the page table entry of the m+t+1th level page table and the size of each page table entry, for example, the size of each page table entry is 8 byte, and the size of the first virtual address range is the product of the number of entries of the page table entry of the m+t+1th level page table and 8 byte.

[0100] C15, determining the first virtual address range according to the base address of the first virtual address range and the size of the first virtual address range.

[0101] C2, obtaining the page table entry of the m+t+1th level page table according to the first virtual address range and the third page table.

[0102] The first virtual address range can be mapped to the m+t+1th level page table of the first page table through the third page table, so that the page table entry of the m+t+1th level page table is obtained according to the first virtual address range and the third page table.

[0103] C3, modifying the page table entry of the m+t+1th level page table, and writing the modified page table entry of the m+t+1th level page table to the corresponding position of the m+t+1th level page table.

[0104] The obtained page table entry of the m+t+1th level page table is modified, and the modified page table entry of the m+t+1th level page table is written to the corresponding position of the m+t+1th level page table, that is, the modification of the page table entry of the m+t+1th level page table is realized, so that the m+t+1th level page table including the changed page table entry is included in the first page table, that is, the first page table is modified.

[0105] An embodiment of the present application is basically the same as the above embodiments, except that the method of the embodiment can further include, before writing the base address of the mth level page table of the first page table into the page table entry of the nth level page table of the second page table:

[0106] S104, determining whether the number of entries of the page table entry of the nth level page table is 1.

[0107] Since the base address of the mth level page table of the first page table is one address, and the page table entry of the nth level page table of the second page table is a storage address, in order to correspond to the one address, it is required that the page table entry of the nth level page table of the second page table is one entry.

[0108] S105, if it is 1, performing the step of writing the base address of the mth level page table into the page table entry of the nth level page table of the second page table.

[0109] In the case that the number of entries of the page table entry of the nth level page table is 1, the base address of the mth level page table is written into the page table entry of the nth level page table of the second page table.

[0110] An embodiment of the present application is basically the same as the above embodiments, except that the method of the embodiment can further include, before obtaining the base address of the mth level page table in the first page table:

[0111] S106, traversing the first page table and the second page table to determine that the first page table and the second page table have no page faults.

[0112] According to the obtained value of the CR3 register, that is, the base addresses of the first page table and the second page table, the first page table and the second page table can be traversed to determine that the first page table and the second page table have no page faults.

[0113] In some examples, after determining that the first page table and the second page table have no page faults, the method can further include:

[0114] S107, saving the page table entry of the nth level page table of the second page table.

[0115] Before writing the base address of the mth level page table of the first page table into the page table entry of the nth level page table of the second page table, the page table entry of the nth level page table of the second page table can be saved, so as to subsequently restore the page table entry of the nth level page table of the second page table.

[0116] In order not to affect the system operation and system security, after verification, it is required to restore the original page table, and in some examples, after saving the page table entry of the nth level page table of the second page table, the method can further include:

[0117] S108, using the saved page table entry of the nth level page table of the second page table to restore the page table entry of the nth level page table of the second page table.

[0118] In some examples, after determining that the first page table and the second page table are not missing pages, the method can further include:

[0119] S 109, saving the page table entry in the m+t+1 level page table of the first page table.

[0120] In some examples, before modifying the page table entry in the m+t+1 level page table of the first page table, the page table entry in the m+t+1 level page table of the first page table can be saved for subsequent recovery of the page table entry in the m+t+1 level page table of the first page table.

[0121] In order not to affect the system operation and system security, after verification, the original page table needs to be restored, and in some examples, after saving the page table entry in the m+t+1 level page table of the first page table, the method can further include:

[0122] S110, using the saved page table entry in the m+t+1 level page table of the first page table to restore the page table entry in the m+t+1 level page table of the first page table.

[0123] Referring to Figure 3 , the scheme of the present application will be described in detail using a four-level page table in a specific embodiment.

[0124] In the user state program of the operating system, two pieces of virtual address space V1_space and V2_space are applied, and the addresses of the two pieces of virtual space are mapped to different physical address spaces through the respective corresponding page tables. Obtaining the page table base address can traverse the entire process of the page table conversion of the two pieces of virtual space addresses.

[0125] Since each level of page table entry has the same Bit meaning, so that the third level page table entry in the virtual address V2_space can be written into the third level page table entry in the virtual address V1_space, so as to constitute a new page table conversion process, and the physical space address corresponding to the virtual address in V2_space is the fourth level page table entry in V1_space space. By the value of the virtual address in the user state V2_space, the fourth level page table corresponding to the virtual address in V1_space can be modified, and then the page table mapping relationship corresponding to the virtual address in V1_space can be changed, wherein the fourth level page table includes a first level page table, a second level page table, a third level page table and a fourth level page table, wherein the first level page table is also called 4-level page mapping table (PML4E: Page-Map Level-4 Entry), the second level page table is also called page table directory pointer table (PDPE, Page-Directory Pointer Entry), the third level page table is also called page table directory table (PDE: Page-Directory Entry), and the fourth level page table is also called page table (PTE, Page Table Entry).

[0126] The specific steps of the embodiment are as follows:

[0127] 1. A user-level program applies for virtual address space V1_space and virtual address space V2_space.

[0128] In the user-level program of the operating system, two virtual address spaces V1_space and V2_space are applied for, and the page table of V1_space space needs to be changed, and the V2_space space address is used to change the page table of V1_space space.

[0129] 2. Traverse the page table surface of the virtual address space V1_space and V2_space to ensure that no page fault exception occurs in the conversion of each level of page table.

[0130] Ensuring that no page fault exception occurs in the conversion of each level of page table means that all pages can be normally converted without page fault exception.

[0131] Here, the value of the page table base address register CR3 needs to be obtained, which needs to be written by a kernel driver.

[0132] 3. Fill the base address of the third level page table corresponding to the virtual address in V1_space virtual space into the third level page table entry corresponding to the virtual address in V2_space virtual space.

[0133] The base address of the third level page table corresponding to the virtual address in the V1_space virtual space is filled into the third level page table item corresponding to the virtual address in the V2_space virtual space, so that the physical space address corresponding to the virtual address in the V2_space virtual space is the fourth level page table item corresponding to the virtual address in the V1_space.

[0134] 4. The original fourth level page table item in the V1_space virtual space and the original third level page table item in the V2_space virtual space are saved.

[0135] 5. The page table corresponding to the virtual address in the V1_space is modified.

[0136] The value of the virtual address in the V2_space virtual space is used to modify the page table mapping relationship of the virtual address in the V1_space through an instruction in the user level.

[0137] 6. Before the user state program exits, the original fourth level page table item in the V1_space virtual space and the original third level page table item in the V2_space virtual space are restored.

[0138] In the embodiment, the change of the page table mapping relationship of the specific virtual address space is realized in the user state of the operating system, the last level page table in all pages of the specific virtual address space in the user state process is modified, and the page table mapping relationship of the original virtual address space needs to be restored before the process exits, so that the system operation and the system security are not affected.

[0139] In the embodiment, the page table mapping relationship of the virtual address space in the user state program is quickly changed through an instruction in the user state by relying on the processor paging mechanism and the operating system page table management system, and the hardware resources such as CR3 and TLB are not affected, a method for quickly changing the page table in the user state is provided, which can be used for verifying the page attribute and processing the processor verification.

[0140] The verification method provided in the embodiment of the application can improve the efficiency of verifying the properties of the processor and / or the page table.

[0141] Figure 4 The flowchart of the verification method provided in the embodiment of the application is shown in FIG. 1. Figure 4 The page table modification method in the embodiment can include the following steps.

[0142] S201, the test code obtains target data through a page table.

[0143] The test code in the embodiment runs on a processor.

[0144] The test code is used to verify the properties of the processor and / or the attributes of the page table. When verifying the properties of the processor, the target data is a physical address obtained through the page table. When verifying the attributes of the page table, the target data can be the attributes of the page table.

[0145] The page table in the embodiment is created according to the modification method of the page table in any of the above embodiments.

[0146] S202, verifying the properties of the processor and / or the attributes of the page table according to the target data.

[0147] According to the obtained target data, the properties of the processor and / or the attributes of the page table are verified.

[0148] In the embodiment, the test code obtains the target data through the page table, and verifies the properties of the processor and / or the attributes of the page table according to the target data. Since the page table used in the verification process is determined according to the modification method of the page table in any of the above embodiments, and the modification of the page table in any of the above embodiments is performed in the user mode, the efficiency of verifying the properties of the processor and / or the attributes of the page table can be improved.

[0149] Referring to Figure 5 , an embodiment of modifying the page table mapping relationship through an instruction in the user mode of the Linux operating system is introduced below, which is used to verify the processor page attributes. The page table of the embodiment is a four-level page table, and the specific execution process is as follows:

[0150] 1. Obtain the base address of the current process page table through the kernel driver.

[0151] In the Linux operating system, a kernel driver program needs to be written to obtain the base address of the current process page table, that is, the value of the CR3 register.

[0152] 2. Apply for 4M virtual address space V1_space and 16K virtual address space V2_space through the malloc function.

[0153] The Linux operating system generally uses a 4K page size, so a 1024*4K size virtual address space and a 4*4K size virtual address space V2_space are applied for through the malloc function.

[0154] 3. Traverse the 1024 pages in V1_space.

[0155] Through the obtained value of the CR3 register, the page table conversion process of the 1024 pages in the virtual address space V1_space can be obtained, and all page tables are traversed to ensure that no page fault occurs.

[0156] 4. save the third level page table of V2_space space and map it to the third level page table of V1_space space at corresponding address.

[0157] fill the base address of the third level page table of V1_space space corresponding page table into the third level page table of V2_space space corresponding page table, that is, the virtual address of V2_space space maps to the fourth level page table of V1_space space corresponding page table.

[0158] 5. determine the fourth level page table of V1_space space all pages corresponding virtual address range of V2_space space and save the fourth level page table item of V1_space space all pages.

[0159] obtain the base virtual address Vaddr of V2_space space corresponding to the fourth level page table of 1024 pages of V1_space space, the virtual address range of V2_space space corresponding to the fourth level page table of V1_space space all pages is [Vaddr-Vaddr+8K]. Save the fourth level page table item of V1_space space all pages. Wherein, 8K is obtained according to the product of the fourth level page table item number 1024 of V1_space space corresponding page table and the size of each item 8 byte.

[0160] 6. modify the page table of V1_space space virtual address.

[0161] select a value from the virtual address [Vaddr-Vaddr+8K] of V2_space space, that is, the corresponding physical address can be read, that is, the fourth level page table item of V1_space space corresponding page is obtained, and the modified page table item is written to the corresponding position, so as to modify the page table of V1_space space virtual address.

[0162] 7. verify the test code.

[0163] 8. before exiting the user mode program, restore the third level page table of V2_space space and the fourth level page table of V1_space space.

[0164] In the embodiment, the consistency of the page table item in the processor 4K paging mechanism is utilized, the change of the page table conversion is realized by modifying the third level page table item in the virtual address space, and then the page table mapping of another virtual address space is affected, in addition, without changing the page and without affecting the TLB, the page table is quickly changed through the instruction in the user mode program.

[0165] The page table modification device provided by the embodiment of the application facilitates improving the efficiency of verifying the characteristics of the processor and / or the attributes of the page table.

[0166] Figure 6 A structure diagram of the page table modification device provided by an embodiment of the present application is shown in the figure, and the page table modification device of the embodiment comprises an application module 11 configured to apply for a first virtual address space and a second virtual address space; wherein the first virtual address space is mapped to a first physical address space through a first page table, and the second virtual address space is mapped to a second physical address space through a second page table; a writing module 12 configured to write a base address of an mth-level page table in the first page table into a page table entry of an nth-level page table of the second page table to form a third page table; wherein m is an integer greater than or equal to 1 and less than or equal to a number of levels of the first page table; n is an integer greater than or equal to m and less than or equal to a number of levels of the second page table; and a modification module 13 configured to modify the first page table according to the third page table. Figure 6

[0167] The device of the embodiment can be used to execute the technical solution of the method embodiment, and the implementation principle and technical effects are similar, which will not be described herein. Figure 1

[0168] The device of the embodiment applies for a first virtual address space and a second virtual address space; wherein the first virtual address space is mapped to a first physical address space through a first page table, and the second virtual address space is mapped to a second physical address space through a second page table; a base address of an mth-level page table in the first page table is written into a page table entry of an nth-level page table of the second page table to form a third page table; and then the first page table is modified according to the third page table, so that the efficiency of verifying the characteristics of the processor and / or the attributes of the page table is improved, and the problem of low verification efficiency caused by the management of the page table by the operating system in the prior art is avoided.

[0169] As an optional implementation, the application module is specifically configured to apply for the first virtual address space and the second virtual address space through a dynamic memory allocation function.

[0170] As an optional implementation, the writing module comprises an acquisition submodule configured to acquire the base address of the mth-level page table in the first page table; and a writing submodule configured to write the base address of the mth-level page table into the page table entry of the nth-level page table of the second page table to form the third page table; the third page table comprises, in sequence, a first-level page table to the nth-level page table of the second page table, the mth-level page table of the first page table, and a tth-level page table after the mth-level page table in the first page table; wherein t is an integer greater than or equal to 0 and less than or equal to a difference between a number of levels of the second page table minus n and 1; and the modification module comprises a modification submodule configured to write data into a page table entry of an mth+tth+1-level page table of the first page table according to the third page table to modify the first page table.

[0171] ​​As an optional implementation, the obtaining submodule is specifically configured to: obtain the base address of the first page table through a kernel driver module; and obtain the base address of the mth-level page table in the first page table according to the base address of the first page table; and the modifying submodule is specifically configured to: obtain the base address of the second page table through the kernel driver module; obtain the address of the nth-level page table entry in the second page table according to the base address of the second page table; and write the base address of the mth-level page table into the nth-level page table entry of the second page table according to the address of the nth-level page table entry.

[0172] As an optional implementation, the number of levels of the first page table is four, and the number of levels of the second page table is four; m and n are equal to three; and the writing submodule is specifically configured to: write the base address of the third-level page table of the first page table into the third-level page table entry of the second page table.

[0173] As an optional implementation, the modifying submodule is specifically configured to: determine a first virtual address range; wherein the first virtual address range corresponds to the mth+t+1th-level page table of the first page table on the third page table; obtain the mth+t+1th-level page table entry according to the first virtual address range and the third page table; modify the mth+t+1th-level page table entry, and write the modified mth+t+1th-level page table entry into a corresponding position of the mth+t+1th-level page table.

[0174] As an optional implementation, the modifying submodule is specifically configured to: determine a target bit corresponding to the mth+t+1th-level page table in the base address of the second virtual address space; determine a first value on a bit equal to the target bit in the base address of the first virtual address space; determine a base address of the first virtual address range according to the first value and the base address of the second virtual address space; determine a size of the first virtual address range; and determine the first virtual address range according to the base address of the first virtual address range and the size of the first virtual address range.

[0175] As an optional implementation, the modifying submodule is specifically configured to: determine the size of the first virtual address range according to the number of entries of the mth+t+1th-level page table entry and the size of each page table entry.

[0176] As an optional implementation, the apparatus further includes: a judging module configured to judge whether the number of entries of the nth-level page table entry is 1 before the writing module writes the base address of the mth-level page table into the nth-level page table entry of the second page table; and an executing module configured to execute the step of writing the base address of the mth-level page table into the nth-level page table entry of the second page table if the number of entries of the nth-level page table entry is 1.

[0177] As an optional implementation, the apparatus further comprises a traversing module configured to traverse the first page table and the second page table to determine that the first page table and the second page table have no page fault before the obtaining submodule obtains the base address of the mth-level page table in the first page table.

[0178] As an optional implementation, the apparatus further comprises a saving module configured to save the page table entry of the nth-level page table of the second page table and / or the page table entry in the m+t+1th-level page table of the first page table after the traversing module determines that the first page table and the second page table have no page fault.

[0179] As an optional implementation, the apparatus further comprises a restoring module configured to restore the page table entry of the nth-level page table of the second page table and / or the page table entry in the m+t+1th-level page table of the first page table after the saving module saves the page table entry of the nth-level page table of the second page table and / or the page table entry in the m+t+1th-level page table of the first page table.

[0180] The apparatuses in the above embodiments can be used to execute the technical solutions of the above method embodiments, and have similar implementation principles and technical effects, which will not be described here.

[0181] The processor verification apparatus provided by an embodiment of the present application can improve the efficiency of verifying the characteristics of a processor and / or the attributes of a page table.

[0182] Figure 7 As shown in a structural diagram of the verification apparatus provided by an embodiment of the present application, Figure 7 the verification apparatus comprises an obtaining module 21 configured to obtain target data by a page table through a test code; the test code is used to verify the characteristics of a processor and / or the attributes of a page table; the page table is created according to the modification method of the page table in any of the above embodiments; and the test code runs on the processor; and a verification module 22 configured to verify the characteristics of the processor and / or the attributes of the page table according to the target data.

[0183] The apparatus in the embodiment can be used to execute the technical solutions of the method embodiments shown in Figure 4 , and has similar implementation principles and technical effects, which will not be described here.

[0184] The device of the embodiment, the test code obtains target data through the page table, and verifies the characteristics of the processor and / or the attributes of the page table according to the target data. Since the page table used in the verification process is determined according to the modification method of the page table in any of the above embodiments, and the modification of the page table in any of the above embodiments is performed in the user mode, the efficiency of the verification of the characteristics of the processor and / or the attributes of the page table can be improved.

[0185] The device of the above embodiment can be used to implement the technical solutions of the above method embodiments, and has similar implementation principles and technical effects, which will not be described here.

[0186] Figure 8 The structural schematic diagram of the electronic device provided by an embodiment of the present application, as shown in Figure 8 The structural schematic diagram of the electronic device provided by an embodiment of the present application, as shown in The power supply circuit 65 is used to supply power to each circuit or device of the above electronic device; the memory 63 is used to store executable program codes; the processor 62 runs the program corresponding to the executable program codes by reading the executable program codes stored in the memory 63, and is used to execute any of the modification methods or verification methods of the page table provided by the above embodiments, so that the corresponding beneficial technical effects can also be achieved, which has been described in detail above and will not be described here.

[0187] The above electronic device exists in various forms, including but not limited to:

[0188] (1) Mobile communication device: the feature of this kind of device is to have mobile communication function, and to provide voice and data communication as the main target. This kind of terminal includes: smart phone (such as iPhone), multimedia phone, functional phone, and low-end phone, etc.

[0189] (2) Ultra-mobile personal computer device: this kind of device belongs to the category of personal computer, has computing and processing functions, and generally has the feature of mobile Internet. This kind of terminal includes: PDA, MID and UMPC device, such as iPad.

[0190] (3) Portable entertainment device: this kind of device can display and play multimedia content. This kind of device includes: audio and video player (such as iPod), handheld game console, electronic book, and smart toy and portable car navigation device.

[0191] (4) Server: a device providing computing services, the configuration of the server includes a processor, a hard disk, a memory, a system bus, etc., the server is similar to a general computer architecture, but since it needs to provide high-reliable services, it has higher requirements in processing capability, stability, reliability, security, scalability, manageability, etc.

[0192] (5) Other electronic devices with data interaction function.

[0193] Correspondingly, the embodiment of the application also provides a computer readable storage medium, the computer readable storage medium stores one or more programs, the one or more programs can be executed by one or more processors to implement the page table modification method or verification method provided by any of the foregoing embodiments, so as to also achieve the corresponding technical effects, which have been described in detail in the foregoing, and will not be described here.

[0194] It should be noted that, in this document, relational terms such as first and second and the like can only be used to distinguish one entity or action from another entity or action, without necessarily requiring or implying that there is any such actual relationship or order between these entities or actions. Moreover, the terms "comprising", "including", or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or apparatus that includes a list of elements does not only include those elements, but also includes other elements not explicitly listed or other elements inherent to such process, method, article or apparatus. Without more limitations, an element defined by the statement "including a..." does not exclude the presence of additional identical elements in the process, method, article or apparatus that includes the element.

[0195] Each embodiment in the specification is described in a relevant manner, and the same and similar parts between each embodiment can be referred to each other, and each embodiment mainly explains the difference from other embodiments.

[0196] Especially, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the part of the method embodiment.

[0197] For the convenience of description, the above device is described as various units / modules respectively described in function. Of course, in the implementation of the present application, the functions of each unit / module can be implemented in the same or multiple software and / or hardware.

[0198] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by a computer program instructing relevant hardware, and the program can be stored in a computer readable storage medium. When the program is executed, the program can include the processes of the above-mentioned embodiment methods. The storage medium can be a magnetic disc, an optical disc, a read-only memory (ROM), a random access memory (RAM), or the like.

[0199] The above merely provides the specific implementation of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of the changes or replacements within the technical range disclosed in the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method of modifying a page table, characterized by, The method comprises the following steps: applying a first virtual address space and a second virtual address space; wherein the first virtual address space is mapped to a first physical address space through a first page table, and the second virtual address space is mapped to a second physical address space through a second page table; the number of levels of the first page table is equal to the number of levels of the second page table; writing the base address of the mth level page table in the first page table into the page table entry of the nth level page table of the second page table to form a third page table; wherein the third page table comprises, in sequence, the first level page table to the nth level page table of the second page table, the mth level page table of the first page table, and the t level page tables after the mth level page table in the first page table; wherein t is equal to the difference between the number of levels of the second page table minus n and 1; m is an integer greater than or equal to 1 and less than the number of levels of the first page table; n is an integer greater than or equal to m and less than the number of levels of the second page table; modifying the first page table according to the third page table; wherein modifying the first page table according to the third page table comprises: writing data into the page table entry of the mth+t+1 level page table of the first page table according to the third page table to modify the first page table.

2. The method of claim 1, wherein, The method of applying a first virtual address space and a second virtual address space comprises: applying the first virtual address space and the second virtual address space through a dynamic memory allocation function.

3. The method of claim 1, wherein, The method of writing the base address of the mth level page table in the first page table into the page table entry of the nth level page table of the second page table to form a third page table comprises: obtaining the base address of the mth level page table in the first page table; writing the base address of the mth level page table into the page table entry of the nth level page table of the second page table to form the third page table.

4. The method of claim 3, wherein, The method of obtaining the base address of the mth level page table in the first page table comprises: obtaining the base address of the first page table through a kernel driver module; obtaining the base address of the mth level page table in the first page table according to the base address of the first page table; The method of writing the base address of the mth level page table into the page table entry of the nth level page table of the second page table comprises: obtaining the base address of the second page table through the kernel driver module; obtaining the address of the page table entry of the nth level page table of the second page table according to the base address of the second page table; writing the base address of the mth level page table into the page table entry of the nth level page table of the second page table according to the address of the page table entry of the nth level page table.

5. The method of claim 1, wherein, The method of writing data into the page table entry of the mth+t+1 level page table of the first page table according to the third page table comprises: determining a first virtual address range; wherein the first virtual address range corresponds to the mth+t+1 level page table of the first page table on the third page table; obtaining the page table entry of the mth+t+1 level page table according to the first virtual address range and the third page table; modifying the page table entry of the mth+t+1 level page table and writing the modified page table entry of the mth+t+1 level page table into the corresponding position of the mth+t+1 level page table.

6. The method of claim 5, wherein, The method of determining a first virtual address range comprises: determining a target bit corresponding to the m+t+1th level page table in a base address of the second virtual address space; determining a first value on a bit equal to the target bit in a base address of the first virtual address space; determining a base address of the first virtual address range according to the first value and the base address of the second virtual address space; determining a size of the first virtual address range; determining the first virtual address range according to the base address of the first virtual address range and the size of the first virtual address range.

7. The method of claim 6, wherein, The determining the size of the first virtual address range comprises: determining the size of the first virtual address range according to a number of entries of the page table entry of the m+t+1th level page table and a size of each page table entry.

8. The method of claim 3, wherein, Before writing the base address of the mth level page table into the page table entry of the n th level page table of the second page table, the method further comprises: determining whether the number of entries of the page table entry of the n th level page table is 1; if 1, then performing the step of writing the base address of the mth level page table into the page table entry of the n th level page table of the second page table.

9. The method of claim 3, wherein, Before obtaining the base address of the mth level page table in the first page table, the method further comprises: traversing the first page table and the second page table to determine that the first page table and the second page table have no page fault.

10. The method of claim 9, wherein, After determining that the first page table and the second page table have no page fault, the method further comprises: saving the page table entry of the n th level page table of the second page table; and / or, saving the page table entry in the m+t+1th level page table of the first page table.

11. The method of claim 10, wherein, After saving the page table entry of the n th level page table of the second page table; and / or, saving the page table entry in the m+t+1th level page table of the first page table, the method further comprises: restoring the page table entry of the n th level page table of the second page table using the saved page table entry; and / or, restoring the page table entry in the m+t+1th level page table of the first page table using the saved page table entry in the m+t+1th level page table of the first page table.

12. A method of authentication, characterized by comprising: a test code acquires target data through a page table; wherein, the test code is used to verify a characteristic of a processor and / or an attribute of the page table; the page table is created according to the modification method of the page table in any one of claims 1-11; the test code runs on the processor; according to the target data, verifying the characteristic of the processor and / or the attribute of the page table.

13. An apparatus for modifying a page table, characterized by: comprising: an application module, configured to apply a first virtual address space and a second virtual address space; wherein, the first virtual address space is mapped to a first physical address space through a first page table, and the second virtual address space is mapped to a second physical address space through a second page table; a number of levels of the first page table is equal to a number of levels of the second page table; The write module is configured to write a base address of an mth-level page table in the first page table into a page table entry of an nth-level page table of the second page table to form a third page table; wherein the third page table comprises, in sequence, a first-level page table to the nth-level page table of the second page table, the mth-level page table of the first page table, and t-level page tables after the mth-level page table in the first page table; wherein t is equal to a difference between a number of levels of the second page table minus n and minus 1; m is an integer greater than or equal to 1 and less than a number of levels of the first page table; and n is an integer greater than or equal to m and less than a number of levels of the second page table; The modification module is configured to modify the first page table according to the third page table. The modification module comprises: The modification submodule is configured to write data into a page table entry of an mth+t+1-level page table of the first page table to modify the first page table according to the third page table.

14. The apparatus of claim 13, wherein, The write module comprises: The acquisition submodule is configured to acquire a base address of an mth-level page table in the first page table; The write submodule is configured to write the base address of the mth-level page table into a page table entry of an nth-level page table of the second page table to form the third page table.

15. The apparatus of claim 14, wherein, The acquisition submodule is specifically configured to: acquire the base address of the first page table through a kernel driver module; acquire the base address of the mth-level page table in the first page table according to the base address of the first page table; The modification submodule is specifically configured to: acquire the base address of the second page table through the kernel driver module; acquire an address of a page table entry of an nth-level page table in the second page table according to the base address of the second page table; write the base address of the mth-level page table into the page table entry of the nth-level page table of the second page table according to the address of the page table entry of the nth-level page table.

16. The apparatus of claim 13, wherein The modification submodule is specifically configured to: determine a first virtual address range; wherein the first virtual address range corresponds to an mth+t+1-level page table of the first page table on the third page table; acquire a page table entry of the mth+t+1-level page table according to the first virtual address range and the third page table; modify the page table entry of the mth+t+1-level page table and write the modified page table entry of the mth+t+1-level page table into a corresponding position of the mth+t+1-level page table.

17. A verification device, characterized by The acquisition module is configured to acquire target data by a page table; wherein a test code is configured to verify a feature of a processor and / or an attribute of the page table; the page table is created according to the modification method of the page table in any one of claims 1 to 11; and the test code runs on the processor; The verification module is configured to verify the feature of the processor and / or the attribute of the page table according to the target data. ​ 18. An electronic device, comprising: The electronic device comprises a housing, a processor, a memory, a circuit board and a power supply circuit, wherein the circuit board is arranged inside a space enclosed by the housing, the processor and the memory are arranged on the circuit board; the power supply circuit is used to supply power to each circuit or device of the electronic device; the memory is used to store executable program codes; the processor runs programs corresponding to the executable program codes by reading the executable program codes stored in the memory, and is used to execute the page table modification method of any one of the preceding claims 1-11 and / or the verification method of the preceding claim 12.

19. A computer-readable storage medium, characterized in that, The computer readable storage medium stores one or more programs, which can be executed by one or more processors to implement the page table modification method of any one of the preceding claims 1-11 and / or the verification method of the preceding claim 12.

Images