Communication tag and electronic device

Abstract

The application provides a communication tag and an electronic device. The communication tag can include a circuit board and a chip disposed on the circuit board. The circuit board can form two coils. The two coils can be disposed on two different conductive layers of the circuit board, respectively. Optionally, the two coils can be disposed crosswise. In addition, the lines for feeding the two coils can be disposed close to each other. The communication tag provided by the application can have a relatively large inductive area and can radiate a relatively strong magnetic field, which is beneficial to improving the inductive performance of the communication tag.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of electronic devices, and more particularly, to a communication tag and an electronic device. BACKGROUND

[0002] Electronic devices are close to each other to achieve short-distance communication interaction between multiple electronic devices. Near field communication (NFC) is a common short-distance communication method. Taking NFC interaction as an example, an electronic device can have a coil for radiating an NFC signal. The electronic device can perform NFC interaction with other electronic devices through the coil. How to improve the performance of the electronic device to sense a short-distance communication signal is a problem to be solved by the present application. SUMMARY

[0003] The present application provides a communication tag and an electronic device, which aims to improve the performance of the communication tag and the electronic device to sense a short-distance communication signal.

[0004] In a first aspect, a communication tag is provided, comprising:

[0005] A circuit board, the circuit board comprising a first coil and a second coil, the first coil and the second coil being located on different conductive layers on the circuit board, the directions of currents on the first coil and the second coil being the same;

[0006] A chip, the chip being disposed on the circuit board, the chip comprising a first port and a second port, the polarities of the first port and the second port being opposite;

[0007] The circuit board comprises a first conductive layer and a second conductive layer, the chip, the first conductive layer and the second conductive layer forming a coil feed circuit;

[0008] The coil feed circuit comprises a first feed end, a second feed end, a third feed end and a fourth feed end;

[0009] The first feed end is located on the first conductive layer and is electrically connected to the first port;

[0010] The second feed end is located on the first conductive layer and is electrically connected to the second port;

[0011] The third feed end is located on the second conductive layer and is oppositely disposed to the first feed end, and the third feed end is electrically connected to the second port;

[0012] The fourth feed end is located on the second conductive layer and is oppositely disposed to the second feed end, and the fourth feed end is electrically connected to the first port;

[0013] The first coil is electrically connected between the first feeding terminal and the third feeding terminal, and the second coil is electrically connected between the second feeding terminal and the fourth feeding terminal.

[0014] The coil feeding circuit can be used to feed the first coil and the second coil. Since the communication tag can include two coils, the signal strength, the inductive area, etc. of the communication tag can be increased accordingly. By reasonably wiring on the circuit board, it is beneficial to make the first coil and the second coil share the same port of the chip. The coil feeding circuit can form two 180° reversed differential ports on two sides of the chip, so as to facilitate reducing the signal interference of the feeding circuit to the first coil and the second coil while feeding the first coil and the second coil.

[0015] With reference to the first aspect, in some implementations of the first aspect, the coil feeding circuit further includes a first via hole and a second via hole,

[0016] The first via hole is electrically connected between the second feeding terminal on the first conductive layer and the third feeding terminal on the second conductive layer,

[0017] The second via hole is electrically connected between the first feeding terminal on the first conductive layer and the fourth feeding terminal on the second conductive layer.

[0018] Through the via hole, the first conductive layer and the second conductive layer can be electrically connected, so as to facilitate arranging the reversed differential ports close to each other and reducing the signal interference of the feeding circuit to the first coil and the second coil.

[0019] With reference to the first aspect, in some implementations of the first aspect, the coil feeding circuit includes a first line, the first line is located on the first conductive layer, and the first line is electrically connected between the first port and the first feeding terminal;

[0020] The coil feeding circuit further includes a second line, the second line is located on the first conductive layer, and the second line is electrically connected between the second port and the second feeding terminal;

[0021] The coil feeding circuit further includes a third line, the third line is located on the second conductive layer, the third line is oppositely arranged with the first line, the third line is electrically connected between the first via hole and the third feeding terminal, and the third line is electrically connected with the second port through the first via hole and the second line;

[0022] The coil feeding circuit further comprises a fourth line, the fourth line is located on the second conductive layer, the fourth line and the second line are oppositely arranged, the fourth line is electrically connected between the second through hole and the fourth feeding end, and the fourth line is electrically connected with the first port through the second through hole and the first line.

[0023] Since the current direction of the first line can be substantially opposite to the current direction of the third line, and the current direction of the second line can be substantially opposite to the current direction of the fourth line, by arranging the first line and the third line close to each other and arranging the second line and the fourth line close to each other, the magnetic field generated by the fourth line can be used to offset part of the magnetic field generated by the second line, and the magnetic field generated by the first line can be used to offset part of the magnetic field generated by the third line, thereby facilitating reduction of the influence of the feeding lines of the coil on the magnetic field generated by the coil.

[0024] With reference to the first aspect, in some implementations of the first aspect, the third line and the fourth line are located on two sides of the chip, the first through hole is located on a side of the chip close to the third line, and the second through hole is located on a side of the chip close to the fourth line.

[0025] The first line comprises a first part, and the first part of the first line is oppositely arranged with the third line; and the second line comprises a first part, and the first part of the second line is oppositely arranged with the fourth line.

[0026] The first line further comprises a second part and a third part, one end of the second part of the first line is connected with the second through hole, and the third part of the first line is connected between the first part and the second part of the first line and surrounds the first through hole.

[0027] The second line further comprises a second part and a third part, one end of the second part of the second line is connected with the first through hole, and the third part of the second line is connected between the first part and the second part of the second line and surrounds the second through hole.

[0028] The distance between the second part of the first line and the second part of the second line is less than a preset distance.

[0029] Since the current direction of the first part of the first line can be substantially opposite to the current direction of the second part of the second line, by arranging the first part of the first line and the second part of the second line close to each other, the magnetic field generated by the first part of the first line can be used to offset part of the magnetic field generated by the second part of the second line, thereby facilitating reduction of the influence of the feeding lines of the coil on the magnetic field generated by the coil.

[0030] With reference to the first aspect, in some implementations of the first aspect, the first port of the chip is located between the second portion and the third portion of the first line, and the second port of the chip is located between the second portion and the third portion of the second line.

[0031] The first port and the second port of the chip can be located at two ends of the chip, and the connection directions of the first port and the second port can be arranged perpendicularly relative to the first line or the second line, and the chip can span the spacing space between the first line and the second line. This is conducive to reducing the lines between the ports of the chip and the lines arranged close to each other.

[0032] With reference to the first aspect, in some implementations of the first aspect, the first line and the second line are located on two sides of the chip, the first via is located on a side of the chip close to the second line, and the second via is located on a side of the chip close to the first line.

[0033] The third line includes a first portion, and the first portion of the third line is arranged opposite to the first line. The fourth line includes a first portion, and the first portion of the fourth line is arranged opposite to the second line.

[0034] The third line further includes a second portion and a third portion. One end of the second portion of the third line is connected to the first via, the second portion of the third line is arranged opposite to the first line or the second line, and the third portion of the third line is connected between the first portion and the second portion of the third line and surrounds the second via.

[0035] The fourth line further includes a second portion and a third portion. One end of the second portion of the fourth line is connected to the second via, the second portion of the fourth line is arranged opposite to the first line or the second line, and the third portion of the fourth line is connected between the first portion and the second portion of the fourth line and surrounds the first via.

[0036] Since the current direction of the second portion of the third line can be substantially opposite to the current direction of the first line or the second line, and the current direction of the second portion of the fourth line can be substantially opposite to the current direction of the first line or the second line, by arranging the second portion of the third line close to the first line or the second line and arranging the second portion of the fourth line close to the first line or the second line, the magnetic field generated by the second portion of the third line can be used to offset part of the magnetic field generated by the first line or the second line, which is conducive to reducing the influence of the feeding line of the coil on the magnetic field generated by the coil.

[0037] With reference to the first aspect, in some implementations of the first aspect, the first port of the chip is connected at one end of the first line, and the second port of the chip is connected at one end of the second line.

[0038] The first port and the second port of the chip can be located at two ends of the chip, and the connection directions of the first port and the second port can be arranged in parallel with respect to the first line or the second line. The chip can span the spacing space between the two ends of the first line and the second line close to each other, which is conducive to reducing the lengths of the first line and the second line.

[0039] With reference to the first aspect, in some implementations of the first aspect, the first conductive layer further includes a fifth line electrically connected between the first feeding end and a first end of the first coil, and the second conductive layer further includes a sixth line electrically connected between the third feeding end and a second end of the first coil, and the fifth line and the sixth line are oppositely arranged.

[0040] Since the current direction of the fifth line can be substantially opposite to the current direction of the sixth line, by arranging the fifth line and the sixth line close to each other, the magnetic field generated by the fifth line can be as much as possible to offset the magnetic field generated by the sixth line, which is conducive to reducing the influence of the feeding line of the coil on the magnetic field generated by the coil.

[0041] With reference to the first aspect, in some implementations of the first aspect, the first conductive layer further includes a seventh line electrically connected between the second feeding end and a first end of the second coil, and the second conductive layer further includes an eighth line electrically connected between the fourth feeding end and a second end of the second coil, and the seventh line and the eighth line are oppositely arranged.

[0042] Since the current direction of the seventh line can be substantially opposite to the current direction of the eighth line, by arranging the seventh line and the eighth line close to each other, the magnetic field generated by the seventh line can be as much as possible to offset the magnetic field generated by the eighth line, which is conducive to reducing the influence of the feeding line of the coil on the magnetic field generated by the coil.

[0043] With reference to the first aspect, in some implementations of the first aspect, the first coil and the second coil are cross-arranged.

[0044] The area surrounded by the first coil and the second coil can be an effective induction area of the communication tag. Within the effective induction area of the communication tag, the direction of the magnetic field generated by the communication tag can be relatively consistent, and the magnetic flux of the magnetic field generated by the communication tag can be relatively large. Therefore, the communication tag can meet the communication requirements of short-distance communication. For a specific short-distance communication frequency band, the length of the coil is generally relatively fixed. In the case of meeting the communication requirements, the induction area that can be achieved by a single coil is relatively small. The communication tag provided in the application can achieve a required coupling coefficient within a larger offset distance, and the effective induction area of the communication tag can be increased while the induction magnetic field amplitude of the communication tag is relatively high. Therefore, the scheme provided in the embodiments of the application can balance the induction area and the induction magnetic field amplitude of the communication tag.

[0045] For example, because the induction area of the communication tag can be relatively large and the magnetic flux amplitude is high, when the user places the other device close to any effective induction area of the communication tag, the other device can quickly complete pairing with the communication tag, or the other device can quickly complete pairing with the electronic device having the communication tag, thereby facilitating the convenience of the user using the communication tag.

[0046] With reference to the first aspect, in some implementations of the first aspect, the first coil is located on the first conductive layer, the second coil is located on the second conductive layer, and a part of the first coil that is projected on the second conductive layer is located within the area surrounded by the second coil.

[0047] The first coil and the second coil have a suitable degree of intersection, which is beneficial to improve the induction performance of the central area of the effective induction area formed by the first coil and the second coil, and is beneficial to enable the user to quickly complete pairing when the user is close to the central area of the communication tag.

[0048] With reference to the first aspect, in some implementations of the first aspect, the first coil is located on the first conductive layer, the second coil is located on the second conductive layer, and the first coil and the second coil do not intersect each other.

[0049] The circuit board further includes a third conductive layer, the third conductive layer includes a third coil, the third coil is arranged to intersect the first coil, and the third coil is arranged to intersect the second coil; and the communication tag further includes:

[0050] A capacitive device, a first port of the capacitive device is electrically connected to a first end of the third coil, and a second port of the capacitive device is electrically connected to a second end of the third coil.

[0051] The first coil and the second coil can form a magnetic field in a first direction. In the interval region of the first coil and the second coil, the first coil and the second coil can each form a magnetic field in a second direction opposite to the first direction. The magnetic field in the interval region of the first coil and the second coil can be utilized. By arranging a third coil intersecting the first coil and the second coil, the magnetic field in the second direction formed between the first coil and the second coil can cause the third coil to induce a magnetic field in the first direction. Therefore, the effective induction area of the communication tag can include the induction area of the first coil, the induction area of the second coil, and the induction area between the first coil and the second coil. Therefore, the effective induction area of the communication tag can be greater than the sum of the effective induction area of the first coil and the effective induction area of the second coil. The communication tag provided in the application can have a relatively large induction area, and the magnetic flux of the magnetic field radiated by the communication tag can be relatively good. Therefore, the scheme provided in the embodiments of the application can balance the induction area and the induction magnetic field amplitude of the communication tag, thereby facilitating improvement of the performance of the communication tag in inducing a short-distance communication signal.

[0052] With reference to the first aspect, in some implementations of the first aspect, a first portion of the third coil on the first conductive layer is projected in the region surrounded by the first coil, and a second portion of the third coil on the second conductive layer is projected in the region surrounded by the second coil.

[0053] The first coil and the third coil have a suitable degree of intersection, and the second coil and the third coil have a suitable degree of intersection, which is conducive to improving the induction performance of the effective induction area formed by the third coil and facilitating the user to quickly realize pairing when approaching the communication tag.

[0054] With reference to the first aspect, in some implementations of the first aspect, the chip and the capacitive device are arranged on the same side of the third conductive layer.

[0055] Reasonable arrangement of the positions of the chip and the capacitive device is conducive to improving the flexibility of wiring on the circuit board.

[0056] With reference to the first aspect, in some implementations of the first aspect, a projection of the chip on the circuit board is located outside the first coil and the second coil.

[0057] Arrangement of the chip at a position away from the first coil and the second coil is conducive to reducing the interference of the signal generated by the coil feeding circuit on the signal generated by the first coil and the second coil.

[0058] In a second aspect, an electronic device is provided, which includes the communication tag of any possible implementation of the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0059] Figure 1 is a schematic structural diagram of an electronic device provided by the present application.

[0060] Figure 2 is a schematic structural diagram of a communication tag provided by the present application.

[0061] Figure 3 is a schematic structural diagram of a balun provided by the present application.

[0062] Figure 4 is a schematic structural diagram of another balun provided by the present application.

[0063] Figure 5 is a magnetic field direction diagram of a communication tag provided by the present application.

[0064] Figure 6 is an inductive performance diagram of a communication tag provided by the present application.

[0065] Figure 7 is a schematic structural diagram of another communication tag provided by the present application.

[0066] Figure 8 is a magnetic field direction diagram of another communication tag provided by the present application.

[0067] Figure 9 is a schematic structural diagram of yet another communication tag provided by the present application.

[0068] Figure 10 is a self-resonant coil resonance standing wave ratio diagram of yet another communication tag provided by the present application. DETAILED DESCRIPTION

[0069] The technical solutions in the present application will be described below with reference to the accompanying drawings.

[0070] Figure 1 is a structural schematic diagram of an electronic device 100 provided by an embodiment of the present application. The electronic device 100 can be a mobile phone, a tablet computer, an e-reader, a television, a notebook computer, a digital camera, a sound box, a headset, a watch, a vehicle-mounted device, a wearable device, a server, a storage device, a data center, etc. containing a radio frequency function. The storage device can be a hard disk with a radio frequency function, etc. Figure 1 The embodiment shown takes the electronic device 100 as a storage device for example to illustrate. As shown in the figure, the electronic device 100 can have a short-distance communication tag 20. The short-distance communication tag 20 can also be referred to as a card reader. In one example, the short-distance communication tag 20 can be an NFC tag or an NFC card reader, for example. Figure 1

[0071] ​The principle of short-distance communication is described below by an example. Device A can include a tag A for short-distance communication. Device B can include a tag B for short-distance communication. When the distance between tag A and tag B is close enough, the magnetic flux of the magnetic field radiated by tag B that tag A senses can be relatively large, and an induced current is generated. Thus, device A can sense the short-distance communication signal from device B.

[0072] Two devices can interact information through short-distance communication. For example, terminal devices (such as mobile phones, computers, sound boxes, earphones, watches, and other electronic devices) and storage devices can each have a short-distance communication tag, so that the terminal devices and the storage devices can each have a short-distance communication function. When the short-distance communication tag of a terminal device is close to or touches the short-distance communication tag of a storage device, the terminal device and the storage device can interact information through a short-distance communication protocol. The terminal device can obtain relevant information of the storage device and complete pairing of the terminal device and the storage device.

[0073] Optionally, the storage device can open the function of reading and writing the storage device to the terminal device. Thus, the terminal device can read and / or write the memory in the storage device.

[0074] For example, the terminal device can display a control interface for the storage device. The user can control the storage device through the control interface. The control interface can display, for example, the files stored by the storage device. Through a series of operations on the control interface, the storage device can send the data stored by the storage device to the terminal device.

[0075] For another example, the terminal device can display a data backup interface of the terminal device. The user can back up the data stored by the terminal device to the storage device through the data backup interface. The data backup interface can display, for example, the files stored by the terminal device. Through a series of operations on the data backup interface, the terminal device can send the data to be backed up to the storage device.

[0076] In some possible scenarios, multiple devices can interact using multiple communication modes including short-distance communication. For example, the terminal device can also establish a communication connection with a gateway device through a communication protocol such as a wireless local area network (WLAN) or Bluetooth. Similarly, the storage device can establish a communication connection with the gateway device.

[0077] For example, when the terminal device backs up data to the storage device, the terminal device can send the data to be backed up to the storage device through the gateway device. For another example, when the terminal device reads data from the storage device, the storage device can send the data stored by the storage device to the terminal device through the gateway device.

[0078] The short-distance communication tag can include a coil. When a magnetic field from the outside penetrates the coil, the coil can generate an induced current. The inductive performance of the coil is closely related to the inductive performance of the short-distance communication tag. Generally, the larger the inductive area of the coil, the easier it is for the short-distance communication tag to approach other short-distance communication tags of devices. The more turns of the coil, the more stable and larger the induced current generated by the coil, and the relatively larger magnetic flux radiated by the coil, which is more conducive to enabling the short-distance communication tag to achieve relatively stable short-distance communication.

[0079] However, for a short-distance communication tag of a specific working frequency band, the length of the coil can be relatively fixed. If the inductive area of the coil is increased, the number of turns of the coil will be correspondingly reduced. How to improve the performance of the communication tag and the electronic device in inducting short-distance communication signals and break through the bottleneck of short-distance communication performance is a problem to be solved.

[0080] Figure 2 FIG. 1 is a schematic structural diagram of a communication tag 20 provided by an embodiment of the present application. Figure 2 The communication tag 20 shown in the figure can be a communication tag 20 for short-distance communication.

[0081] In Figure 2 In the example shown, the communication tag 20 can include a circuit board 21. The circuit on the circuit board 21 can be used to form a coil. In other examples, the circuit board 21 can also be replaced by other components that can form a coil, such as a coil formed by winding a copper wire.

[0082] The communication tag 20 can also include a chip 22 disposed on the circuit board 21. The chip 22 can include a first port 2201 and a second port 2202 with opposite polarities. That is, when the polarity (or potential) of the first port 2201 is positive, the polarity of the second port 2202 is negative; when the polarity of the first port 2201 is negative, the polarity of the second port 2202 is positive. The first port 2201 and the second port 2202 can be electrically connected to two ends of the coil, respectively, so that the first port 2201 of the chip 22, the coil, and the second port 2202 of the chip 22 can form a current loop.

[0083] The circuit board 21 can be a double-sided board. The circuit board 21 can include a first conductive layer 210 and a second conductive layer 220. The circuit of the first conductive layer 210 can be observed from a direction perpendicular to the first conductive layer 210. In Figure 2 , the circuit of the first conductive layer 210 is represented by a solid line profile and a black-and-white filling pattern. According to Figure 2 the observation direction shown, the first conductive layer 210 blocks the circuit of the second conductive layer 220, so in Figure 2In FIG. 2 , the circuits of the second conductive layer 220 are represented by dashed outlines and a fill pattern of black dots on a white background.

[0084] along Figure 2 Observing the communication tag 20 in the AA section, we can get Figure 2 With respect to the thickness direction of the circuit board 21 , the first conductive layer 210 and the second conductive layer 220 may be located on both sides of the circuit board 21 , respectively.

[0085] A first coil 23 is formed on the first conductive layer 210. A second coil 24 is formed on the second conductive layer 220. The first coil 23 and the second coil 24 can be arranged in a cross-over arrangement (i.e., partially overlapping or partially overlapping). In other words, the first portion of the first coil 23 and the first portion of the second coil 24 can be aligned, and the second portion of the first coil 23 and the second portion of the second coil 24 can be staggered. In some embodiments, the projection of the chip 22 on the circuit board 21 can be located outside the first coil 23 and the second coil 24.

[0086] In some embodiments, a portion of the line of the first coil 23 may be aligned with a portion of the line of the second coil 24 .

[0087] In other embodiments, the projection of the first portion of the first coil 23 on the second conductive layer 220 may be located within the area enclosed by the second coil 24, the projection of the second portion of the first coil 23 on the second conductive layer 220 may not intersect with the second coil 24, and the projection of the third portion of the first coil 23 on the second conductive layer 220 may be aligned with a portion of the second coil 24. The area enclosed by the second coil 24 may refer to the area enclosed by the inner circle of the second coil 24.

[0088] In yet other embodiments, the projection of the first portion of the second coil 24 on the first conductive layer 210 may be located within the area enclosed by the first coil 23, the projection of the second portion of the second coil 24 on the first conductive layer 210 may not intersect with the first coil 23, and the projection of the third portion of the second coil 24 on the first conductive layer 210 may be aligned with a portion of the first coil 23. The area enclosed by the first coil 23 may refer to the area enclosed by the inner circle of the first coil 23.

[0089] In one example, the percentage of the inductive area of ​​the intersection of the first coil 23 and the second coil 24 to the inductive area of ​​the first coil 23 may be, for example, a%. That is, the projected area of ​​the first portion of the first coil 23 aligned with the second coil 24 on the first conductive layer 210 is b1, the total projected area of ​​the first coil 23 on the first conductive layer 210 is b2, and the percentage of b1 / b2 may be a%. a% may be 5 to 95%, optionally 15 to 70%. In one example, a% may be 20 to 50%. Further, a% may be 25 to 40%. Further, a% may be 30 to 35%.

[0090] The first coil 23 and the second coil 24 can generate currents in the same direction (e.g., both clockwise or both counterclockwise), thereby forming magnetic fields in the same direction. Therefore, the magnetic field generated in the first portion of the first coil 23 can overlap with the magnetic field generated in the first portion of the second coil 24. The intersection of the first coil 23 and the second coil 24 can correspond to the central sensing area of ​​the communication tag 20, thereby increasing the magnetic flux of the magnetic field generated in the central sensing area of ​​the communication tag 20.

[0091] In addition, the magnetic flux of the magnetic field generated at the periphery of the coil is generally smaller than the magnetic flux of the magnetic field generated at the center of the coil. Therefore, the superimposed magnetic flux of the magnetic field generated at the periphery of the first coil 23 and the magnetic field generated at the periphery of the second coil 24 can be relatively small compared to the magnetic flux of the magnetic field generated at the center of the first coil 23 or the second coil 24, which is beneficial for improving the uniformity of the magnetic flux generated by the communication tag 23. Therefore, the solution provided by the embodiment of the present application is beneficial for improving the sensing performance of the communication tag 20.

[0092] The electrical connection relationship between the first coil 23 and the chip 22 , and the electrical connection relationship between the second coil 24 and the chip 22 are described below.

[0093] like Figure 2 As shown, chip 22 can be disposed on a side of circuit board 21 near first conductive layer 210. First port 2201 and second port 2202 of chip 22 can be located on either side of chip 22. Chip 22, first conductive layer 210, and second conductive layer 220 can form coil feed circuit 29. In some embodiments, coil feed circuit 29 can be located outside the area enclosed by first coil 23 and outside the area enclosed by second coil 24.

[0094] The coil feeding circuit 29 may include a feeding network in the circuit board 21 for feeding the first coil 23 and the second coil 24. The coil feeding circuit 29 may include a feeding terminal 291, a feeding terminal 292, a feeding terminal 293, and a feeding terminal 294.

[0095] The feeding end 291 and the feeding end 292 can be located on the first conductive layer 210. The feeding end 291 can be electrically connected to the first port 2201 of the chip 22. The feeding end 292 can be electrically connected to the second port 2202 of the chip 22. The feeding end 293 and the feeding end 294 can be located on the second conductive layer 220. The feeding end 293 can be electrically connected to the second port 2202 of the chip 22 through the via hole electrically connecting between the first conductive layer 210 and the second conductive layer 220. The feeding end 294 can be electrically connected to the first port 2201 of the chip 22 through the via hole electrically connecting between the first conductive layer 210 and the second conductive layer 220.

[0096] The feeding end 291 and the feeding end 293 can be oppositely arranged, and the polarities of the feeding end 291 and the feeding end 293 can be opposite. The first coil 23 is electrically connected between the feeding end 291 and the feeding end 293, so that the coil feeding circuit 29 can feed the first coil 23.

[0097] The feeding end 292 and the feeding end 294 can be oppositely arranged, and the polarities of the feeding end 292 and the feeding end 294 can be opposite. The second coil 24 is electrically connected between the feeding end 292 and the feeding end 294, so that the coil feeding circuit 29 can feed the second coil 24.

[0098] The polarities of the feeding end 291 and the feeding end 292 can be opposite, and the polarities of the feeding end 293 and the feeding end 294 can be opposite. Therefore, the coil feeding circuit 29 can form two 180° opposite differential ports on both sides of the chip 22, so as to feed the first coil 23 and the second coil 24, which is conducive to making the first coil 23 and the second coil 24 emit the same magnetic field.

[0099] The coil feeding circuit 29 can include a first line 211 and a second line 212. The first line 211 and the second line 212 can be lines on the first conductive layer 210. The first port 2201 of the chip 22 can be electrically connected to the first line 211. An end of the first line 211 away from the first port 2201 can be the feeding end 291 of the coil feeding circuit 29. The second port 2202 of the chip 22 can be electrically connected to the second line 212. An end of the second line 212 away from the second port 2202 can be the feeding end 292 of the coil feeding circuit 29.

[0100] The first coil 23 can include a first end 231 and a second end 232. The first end 231 of the first coil 23 can be located at the outer circle of the first coil 23, and the second end 232 of the first coil 23 can be located at the inner circle of the first coil 23.

[0101] The first end 231 of the first coil 23 can be electrically connected with the first port 2201 of the chip 22 through the first line 211 of the first conductive layer 210.

[0102] As shown in FIG. 1, the coil feeding circuit 29 can further include a third line 221. The third line 221 can be a line on the second conductive layer 220. As shown in FIG. 1, the third line 221 can be electrically connected with the second end 232 of the first coil 23. Figure 2 Figure 2 As shown in FIG. 1, the circuit board 21 can further include a through hole 251 electrically connected between the first coil 23 of the first conductive layer 210 and the third line 221 of the second conductive layer 220. The second end 232 of the first coil 23 can be electrically connected with the third line 221 of the second conductive layer 220 through the through hole 251.

[0103] In combination with Figure 2 and Figure 2 , or in combination with Figure 3 and Figure 2 , the circuit board 21 can further include a through hole 252 electrically connected between the second line 212 of the first conductive layer 210 and the third line 221 of the second conductive layer 220. That is, one end of the third line 221 away from the feeding end 293 can be connected with the through hole 252. The third line 221 of the second conductive layer 220 can be electrically connected with the second port 2202 of the chip 22 through the through hole 252, the second line 212 of the first conductive layer 210.

[0104] The second coil 24 can include a second end 242 and a first end 241. The second end 242 of the second coil 24 can be located at an outer circle of the second coil 24, and the first end 241 of the second coil 24 can be located at an inner circle of the second coil 24.

[0105] The third line 221 can be oppositely arranged with the first line 211 on the first conductive layer 210. For example, the distance between part of the third line 221 and part of the first line 211 is less than a preset distance. In the present application, the preset distance can be, for example, 10 mm, 5 mm, 2 mm, 1 mm, and can be smaller, for example, 0.5 mm, 0.2 mm or 0.1 mm. The preset distance can be determined according to the overall size of the communication tag. For another example, the projection of the third line 221 on the first conductive layer 210 intersects or overlaps with the first line 211. For another example, the projection of the first line 211 on the second conductive layer 220 intersects or overlaps with the third line 221. For another example, the first line 211 and the third line 221 can be arranged at least partially in alignment.

[0106] As shown in FIG. 1, the coil feeding circuit 29 can further include a third line 221. The third line 221 can be a line on the second conductive layer 220. As shown in FIG. 1, the third line 221 can be electrically connected with the second end 232 of the first coil 23. Figure 4 ​As shown, the coil feed circuit 29 can further include a fourth line 222. The fourth line 222 can be a line on the second conductive layer 220. The second end 242 of the second coil 24 can be electrically connected with the fourth line 222 of the second conductive layer 220. As shown in FIG. 2B, the fourth line 222 of the second conductive layer 220 can be electrically connected with the first end 231 of the first coil 23. Figure 2 As shown in the A-A cross-sectional view in FIG. 2C, the circuit board 21 can further include a via 253 electrically connecting between the first line 211 of the first conductive layer 210 and the fourth line 222 of the second conductive layer 220. The fourth line 222 of the second conductive layer 220 can be electrically connected with the first port 2201 of the chip 22 through the via 253 and the first line 211 of the first conductive layer 210.

[0107] In combination with Figure 2 and Figure 2 , or in combination with Figure 3 and Figure 2 , the circuit board 21 can further include a via 254 electrically connecting between the second coil 24 of the second conductive layer 220 and the second line 212 of the first conductive layer 210. That is, the end of the fourth line 222 away from the feed end 294 can be connected with the via 254. The first end 241 of the second coil 24 can be electrically connected with the second port 2202 of the chip 22 through the via 254 and the second line 212 of the first conductive layer 210.

[0108] The fourth line 222 can be oppositely arranged with the second line 212 on the first conductive layer 210. For example, the distance between the fourth line 222 and the second line 212 is less than a preset distance. For another example, the projection of the fourth line 222 on the first conductive layer 210 intersects or overlaps with the second line 212. For another example, the projection of the second line 212 on the second conductive layer 220 intersects or overlaps with the fourth line 222. For another example, the fourth line 222 and the second line 212 can be at least partially aligned.

[0109] Figure 4 The solid arrow in FIG. 2D further shows a possible current direction diagram of the first coil 23. Figures 2 to 4 The dashed arrow in FIG. 2E further shows a possible current direction diagram of the second coil 24.

[0110] Suppose the electrical signal from the chip 22 flows out from the first port 2201 of the chip 22, through the first line 211 of the first conductive layer 210, and into the first coil 23 from the first end 231 of the first coil 23. The first coil 23 can be wound in a clockwise direction from outside to inside, so that the first coil 23 can form a clockwise current and generate a magnetic field perpendicular to the first coil 23. The current conducted on the first coil 23 can flow out from the second end 232 of the first coil 23, through the via 251, the third line 221 of the second conductive layer 220, and into the second port 2202 of the chip 22.

[0111] Assume that the electric current from the chip 22 flows out from the first port 2201 of the chip 22, through the fourth line 222 of the second conductive layer 220, and into the second coil 24 from the second end 242 of the second coil 24. The second coil 24 can be wound from outside to inside in a clockwise direction. Thus, the second coil 24 can form a clockwise electric current and generate a magnetic field perpendicular to the second coil 24. The electric current flowing through the second coil 24 can flow out from the first end 241 of the second coil 24, through the via hole 254 and the second line 212 of the first conductive layer 210, and into the second port 2202 of the chip 22.

[0112] To make the first coil 23 and the second coil 24 form electric currents in the same direction, the first coil 23 and the second coil 24 can also have other possible structures.

[0113] For example, the first end 231 of the first coil 23 can be located at the inner coil of the first coil 23, and the first coil 23 is wound from outside to inside in a counterclockwise direction; the second end 242 of the second coil 24 can be located at the outer coil of the second coil 24, and the second coil 24 is wound from outside to inside in a clockwise direction. Assuming that the electric current flows out from the first port 2201 of the chip 22 and flows into the second port 2202 of the chip 22, the first coil 23 and the second coil 24 can both form a clockwise electric current.

[0114] For another example, the first end 231 of the first coil 23 can be located at the outer coil of the first coil 23, and the first coil 23 is wound from outside to inside in a clockwise direction; the second end 242 of the second coil 24 can be located at the inner coil of the second coil 24, and the second coil 24 is wound from outside to inside in a counterclockwise direction. Assuming that the electric current flows out from the first port 2201 of the chip 22 and flows into the second port 2202 of the chip 22, the first coil 23 and the second coil 24 can both form a clockwise electric current.

[0115] For another example, the first end 231 of the first coil 23 can be located at the inner coil of the first coil 23, and the first coil 23 is wound from outside to inside in a counterclockwise direction; the second end 242 of the second coil 24 can be located at the inner coil of the second coil 24, and the second coil 24 is wound from outside to inside in a counterclockwise direction. Assuming that the electric current flows out from the first port 2201 of the chip 22 and flows into the second port 2202 of the chip 22, the first coil 23 and the second coil 24 can both form a clockwise electric current.

[0116] For another example, the first end 231 of the first coil 23 can be located on the outer turn of the first coil 23, and the first coil 23 can be wound counterclockwise from the outside to the inside. The second end 242 of the second coil 24 can be located on the outer turn of the second coil 24, and the second coil 24 can be wound counterclockwise from the outside to the inside. Assuming that current flows out of the first port 2201 of the chip 22 and flows into the second port 2202 of the chip 22, both the first coil 23 and the second coil 24 can form a counterclockwise current.

[0117] For another example, the first end 231 of the first coil 23 can be located on the outer turn of the first coil 23, and the first coil 23 can be wound counterclockwise from the outside to the inside. The second end 242 of the second coil 24 can be located on the inner turn of the second coil 24, and the second coil 24 can be wound clockwise from the outside to the inside. Assuming that current flows out of the first port 2201 of the chip 22 and flows into the second port 2202 of the chip 22, both the first coil 23 and the second coil 24 can form a counterclockwise current.

[0118] For another example, the first end 231 of the first coil 23 can be located on the inner turn of the first coil 23, and the first coil 23 can be wound clockwise from the outside to the inside. The second end 242 of the second coil 24 can be located on the outer turn of the second coil 24, and the second coil 24 can be wound counterclockwise from the outside to the inside. Assuming that current flows out of the first port 2201 of the chip 22 and flows into the second port 2202 of the chip 22, both the first coil 23 and the second coil 24 can form a counterclockwise current.

[0119] For another example, the first end 231 of the first coil 23 can be located within the inner turn of the first coil 23, and the first coil 23 can be wound clockwise from the outside to the inside. The second end 242 of the second coil 24 can be located within the inner turn of the second coil 24, and the second coil 24 can be wound clockwise from the outside to the inside. Assuming that current flows out of the first port 2201 of the chip 22 and into the second port 2202 of the chip 22, both the first coil 23 and the second coil 24 can generate counterclockwise current.

[0120] Figures 2 to 4 1 shows a schematic structural diagram of a coil feeding circuit 29 provided in an embodiment of the present application. Figure 3 The local area where the middle chip 22 is located, combined with Figure 2 , describing an electrical connection relationship between the first coil 23 and the chip 22, and between the second coil 24 and the chip 22. Figure 3 The structure shown may be a balun structure.

[0121] The first end 231 of the first coil 23 can be located on the side of the chip 22 close to the first port 2201. The first line 211 of the first conductive layer 210 can extend from the first end 231 of the first coil 23 to the first port 2201 of the chip 22. The second end 232 of the first coil 23 can be located on the side of the chip 22 close to the first port 2201. Since the first port 2201 and the second port 2202 of the chip 22 can be located on both sides of the chip 22, the third line 221 of the second conductive layer 220 can extend from the side of the chip 22 close to the first port 2201 to the side close to the second port 2202. Since the second port 2202 of the chip 22 is electrically connected to the third line 221 of the second conductive layer 220 through the via hole 252, the via hole 252 may, for example, be located on the side of the chip 22 close to the second port 2202. In Figure 3 In the example shown, a portion of the second line 212 can extend from the second port 2202 of the chip 22 to the via hole 252, and another portion can extend from the second port 2202 of the chip 22 to the first end 241 of the second coil 24.

[0122] The second end 242 of the second coil 24 can be located on the side of the chip 22 close to the second port 2202. Since the first port 2201 and the second port 2202 of the chip 22 can be located on both sides of the chip 22, the fourth line 222 of the second conductive layer 220 can extend from the side of the chip 22 close to the first port 2201 to the side close to the second port 2202. Since the first port 2201 of the chip 22 is electrically connected to the fourth line 222 of the second conductive layer 220 through the via hole 254, the via hole 254 may, for example, be located on the side of the chip 22 close to the first port 2201. In Figure 3 In the example shown, a portion of the second line 212 can extend from the second port 2202 of the chip 22 to the via hole 252, and another portion can extend from the second port 2202 of the chip 22 to the first end 241 of the second coil 24.

[0123] The first line 211 of the first conductive layer 210 can extend from the feed end 291 to the first port 2201 of the chip 22. The second line 212 of the first conductive layer 210 can extend from the second port 2202 of the chip 22 to the feed end 292. The first line 211 and the second line 212 can be located on both sides of the chip 22, the via hole 252 can be located on the side of the chip 22 close to the second line 212, and the via hole 254 can be located on the side of the chip close to the first line 211.

[0124] like Figure 3 As shown, the via 252 can be located near the second port 2202 of the chip 22. For example, the via 252 can be located on a side of the chip 22 near the second port 2202. Alternatively, the via 252 can be located on the same side of the chip 22 as the second end 232 of the first coil 23. The via 254 can be located near the first port 2201 of the chip 22. For example, the via 254 can be located on a side of the chip 22 near the first port 2201. Alternatively, the via 254 can be located on the same side of the chip 22 as the second end 242 of the second coil 24.

[0125] The third trace 221 of the second conductive layer 220 can be electrically connected to the second port 2202 of the chip 22 via the second trace 212 and the via 252. A first portion 2211 of the third trace 221 can extend from the feeding terminal 293 to the vicinity of the via 254. A second portion 2212 of the third trace 221 can extend from the via 252 to the vicinity of the via 254. A third portion 2213 of the third trace 221 can be connected between the first portion 2211 and the second portion 2212 of the third trace 221, bypassing or avoiding the via 254.

[0126] The first portion 2211 of the third line 221 may be disposed close to the first line 211. For example, the first portion 2211 of the third line 221 may be aligned with the first line 211. In other words, the projection of the first portion 2211 of the third line 221 on the first conductive layer 210 may be spaced from the first line 211 by a distance less than a predetermined spacing, or the projection of the first portion 2211 of the third line 221 on the first conductive layer 210 may intersect with the first line 211, or the projection of the first portion 2211 of the third line 221 on the first conductive layer 210 may overlap with the first line 211.

[0127] Since the current direction of the first circuit 211 can be roughly opposite to the current direction of the first part 2211 of the third circuit 221, the magnetic field generated by the first part 2211 of the third circuit 221 can offset part of the magnetic field generated by the first circuit 211, which is beneficial to reducing the influence of the coil's feeding circuit on the magnetic field generated by the coil.

[0128] The second part 2212 of the third line 221 can be disposed close to the second line 212 or the first line 211, for example, the second part 2212 of the third line 221 can be disposed in alignment with the second line 212 or the first line 211. That is, the projection of the second part 2212 of the third line 221 on the first conductive layer 210 can be spaced apart from the second line 212 or the first line 211 by a distance less than a preset interval, or the projection of the second part 2212 of the third line 221 on the first conductive layer 210 can intersect the second line 212 or the first line 211, or the projection of the second part 2212 of the third line 221 on the first conductive layer 210 can overlap the second line 212 or the first line 211.

[0129] Since the current direction of the second line 212 or the first line 211 can be substantially opposite to the current direction of the second part 2212 of the third line 221, the magnetic field generated by the second part 2212 of the third line 221 can offset part of the magnetic field generated by the second line 212, which is conducive to reducing the influence of the feeding line of the coil on the magnetic field generated by the coil.

[0130] The fourth line 222 of the second conductive layer 220 and the first port 2201 of the chip 22 can be electrically connected through the via hole 254, the first line 211 of the first conductive layer 210. The first part 2221 of the fourth line 222 can extend from the feeding end 294 to the vicinity of the via hole 252, the second part 2222 of the fourth line 222 can extend from the via hole 254 to the vicinity of the via hole 252, and the third part 2223 of the fourth line 222 can be connected between the first part 2221 and the second part 2222 of the third line 221 and bypass or avoid the via hole 252.

[0131] The first part 2221 of the fourth line 222 can be disposed close to the second line 212, for example, the first part 2221 of the fourth line 222 can be disposed in alignment with the second line 212. That is, the projection of the first part 2221 of the fourth line 222 on the first conductive layer 210 can be spaced apart from the second line 212 by a distance less than a preset interval, or the projection of the first part 2221 of the fourth line 222 on the first conductive layer 210 can intersect the second line 212, or the projection of the first part 2221 of the fourth line 222 on the first conductive layer 210 can overlap the second line 212.

[0132] Since the current direction of the second line 212 can be substantially opposite to the current direction of the first part 2221 of the fourth line 222, the magnetic field generated by the first part 2221 of the fourth line 222 can offset part of the magnetic field generated by the second line 212, which is conducive to reducing the influence of the feeding line of the coil on the magnetic field generated by the coil.

[0133] The second portion 2222 of the fourth line 222 may be disposed close to the first line 211 or the second line 212. For example, the second portion 2222 of the fourth line 222 may be aligned with the first line 211 or the second line 212. In other words, the projection of the second portion 2222 of the fourth line 222 on the first conductive layer 210 may be spaced from the first line 211 or the second line 212 by a distance less than a predetermined spacing, or the projection of the second portion 2222 of the fourth line 222 on the first conductive layer 210 may intersect with the first line 211 or the second line 212, or the projection of the second portion 2222 of the fourth line 222 on the first conductive layer 210 may overlap with the first line 211 or the second line 212.

[0134] Since the current direction of the first circuit 211 can be roughly opposite to the current direction of the second part 2222 of the fourth circuit 222, the magnetic field generated by the second part 2222 of the fourth circuit 222 can offset part of the magnetic field generated by the first circuit 211, which is beneficial to reducing the influence of the coil's feeding circuit on the magnetic field generated by the coil.

[0135] Figure 3 1 shows a schematic structural diagram of a coil feeding circuit 29 provided in an embodiment of the present application. Figure 4 The local area where the middle chip 22 is located, combined with Figure 2 , describing an electrical connection relationship between the first coil 23 and the chip 22, and between the second coil 24 and the chip 22. Figure 4 The structure shown can be another balun structure.

[0136] exist Figure 4 In the example shown, the first end 231 and the second end 232 of the first coil 23 can be located on the same side of the chip 22. The second end 242 and the first end 241 of the second coil 24 can be located on the same side of the chip 22. The first end 231 of the first coil 23 and the second end 242 of the second coil 24 can be located on opposite sides of the chip 22. These two sides can be different from the side of the chip 22 close to the first port 2201 and the side close to the second port 2202.

[0137] by Figure 4For example, the chip 22 can have four sides, which are a first side, a second side, a third side, and a fourth side. The first side, the second side, the third side, and the fourth side can be, for example, the upper side, the right side, the lower side, and the left side of the chip 22. The first side can be the side of the chip 22 close to the first port 2201. The first end 231 and the second end 232 of the first coil 23 can be located on the second side of the chip 22. The third side can be the side of the chip 22 close to the second port 2202. The second end 242 and the first end 241 of the second coil 24 can be located on the fourth side of the chip 22. In other possible examples, the first end 231 and the second end 232 of the first coil 23 can also be located on the side of the chip 22 close to the first port 2201 or on the side of the chip 22 close to the second port 2202. Similarly, the second end 242 and the first end 241 of the second coil 24 can also be located on the side of the chip 22 close to the first port 2201 or on the side of the chip 22 close to the second port 2202.

[0138] The third line 221 of the second conductive layer 220 can extend from the feeding end 293 to the via hole 252. The fourth line 221 of the second conductive layer 220 can extend from the via hole 254 to the feeding end 294. The third line 221 and the fourth line 221 can be located on two sides of the chip 22, the via hole 252 can be located on the side of the chip 22 close to the third line 221, and the via hole 254 can be located on the side of the chip close to the fourth line 221.

[0139] The third line 221 of the second conductive layer 220 can be electrically connected to the second port 2202 of the chip 22 through the second line 212 and the via hole 252. The first part 2121 of the second line 212 can extend from the feeding end 292 to the vicinity of the via hole 254, the second part 2122 of the second line 212 can extend from the via hole 252 to the vicinity of the via hole 254, and the third part 2123 of the second line 212 can be connected between the first part 2121 and the second part 2122 of the second line 212 and bypass or avoid the via hole 254.

[0140] The first part 2111 of the first line 211 can be arranged close to the third line 221, for example, the first part 2111 of the first line 211 can be arranged in alignment with the third line 221. The description of the first part 2111 of the first line 211 can refer to the description of the first part 2211 of the third line 221 above. Since the current direction of the third line 221 can be substantially opposite to the current direction of the first part 2111 of the first line 211, the magnetic field generated by the first part 2111 of the first line 211 can offset part of the magnetic field generated by the third line 221, which is beneficial to reduce the influence of the feeding line of the coil on the magnetic field generated by the coil.

[0141] The first portion 2121 of the second line 212 can be arranged close to the fourth line 222. For example, the first portion 2121 of the second line 212 can be arranged in alignment with the fourth line 222. The description of the first portion 2121 of the second line 212 can refer to the description of the first portion 2221 of the fourth line 222. Since the current direction of the fourth line 222 can be substantially opposite to the current direction of the first portion 2121 of the second line 212, the magnetic field generated by the first portion 2121 of the second line 212 can offset part of the magnetic field generated by the fourth line 222, which is beneficial to reduce the influence of the feeding line of the coil on the magnetic field generated by the coil.

[0142] The second portion 2122 of the second line 212 can be arranged close to the second portion 2112 of the first line 211. That is, the distance between the second portion 2122 of the second line 212 and the second portion 2112 of the first line 211 can be less than the preset distance. Since the current direction of the second portion 2112 of the first line 211 can be substantially opposite to the current direction of the second portion 2122 of the second line 212, the magnetic field generated by the second portion 2122 of the second line 212 can offset part of the magnetic field generated by the second portion 2112 of the first line 211, which is beneficial to reduce the influence of the feeding line of the coil on the magnetic field generated by the coil.

[0143] In the embodiment shown in FIG. 2, the first conductive layer 210 can further include a line 213, and the line 213 can be electrically connected to the feeding end 291 of the coil feeding circuit 29 and the first end 231 of the first coil 23. The second conductive layer 20 can further include a line 223, and the line 223 can be electrically connected to the feeding end 293 of the coil feeding circuit 29 and the second end 232 of the first coil 23. The line 213 and the line 223 are oppositely arranged. For example, the distance between the line 213 and the line 223 can be less than the preset distance. Figure 4 In the embodiment shown in FIG. 2, the first conductive layer 210 can further include a line 213, and the line 213 can be electrically connected to the feeding end 291 of the coil feeding circuit 29 and the first end 231 of the first coil 23. The second conductive layer 20 can further include a line 223, and the line 223 can be electrically connected to the feeding end 293 of the coil feeding circuit 29 and the second end 232 of the first coil 23. The line 213 and the line 223 are oppositely arranged. For example, the distance between the line 213 and the line 223 can be less than the preset distance.

[0144] Figures 2 to 4 In the embodiment shown in FIG. 2, the first conductive layer 210 can further include a line 214, and the line 214 can be electrically connected to the feeding end 292 of the coil feeding circuit 29 and the first end 241 of the second coil 24. The second conductive layer 20 can further include a line 224, and the line 224 can be electrically connected to the feeding end 294 of the coil feeding circuit 29 and the second end 242 of the second coil 24. The line 214 and the line 224 are oppositely arranged. For example, the distance between the line 214 and the line 224 can be less than the preset distance.

[0145] Figures 2 to 4 The magnetic field distribution of the communication tag 20 provided by the present application is shown. The magnetic field distribution of the communication tag 20 provided by the present application is shown. Figure 5 ​It can be seen that the area surrounded by the first coil 23 and the second coil 24 can be the effective induction area of the communication tag 20. Within the effective induction area of the communication tag 20, the direction of the magnetic field generated by the communication tag 20 can be relatively consistent, and the magnetic flux of the magnetic field generated by the communication tag 20 can be relatively large. Therefore, the communication tag 20 can meet the communication requirements of short-distance communication.

[0146] Figure 5 A schematic diagram of the communication performance of the communication tag 20 provided in the present application is shown. Figure 6 The horizontal coordinate represents the offset distance to the center of the effective induction area of the communication tag 20. Figure 6 The vertical coordinate in the diagram can represent the coupling coefficient of the communication tag 20. Figure 6 The solid line in the diagram represents the communication performance of the scheme provided in the present application. Figure 6 The dashed line in the diagram represents the communication performance of the communication tag 20 with a single coil.

[0147] For a specific short-distance communication frequency part, the length of the coil is generally relatively fixed. In the case of meeting the communication requirements, the inductive area that can be achieved by a single coil is relatively small. The communication tag 20 provided in the present application can achieve a required coupling coefficient within a larger offset distance, and at the same time, the inductive magnetic field amplitude of the communication tag 20 can be relatively high while increasing the area of the effective induction area of the communication tag 20. Therefore, the scheme provided in the embodiments of the present application can take into account the inductive area and the inductive magnetic field amplitude of the communication tag 20.

[0148] Figure 6 is another structural schematic diagram of a communication tag 20 provided in an embodiment of the present application. Similar to the communication tag 20 shown in Figure 7 , the communication tag 20 shown in Figure 2 includes a circuit board 21, a chip 22, and the lines of the circuit board 21 form a first coil 23 and a second coil 24 of the communication tag 20. The structure of the first coil 23 and the structure of the second coil 24 can refer to the examples shown in Figure 7 . The electrical connection relationship, structural relationship and positional relationship between the first coil 23 and the chip 22, and the electrical connection relationship, structural relationship and positional relationship between the second coil 24 and the chip 22 can refer to the examples shown in Figure 2 .

[0149] The communication tag 20 shown in Figures 2 to 4 is slightly different from the communication tag 20 shown in Figure 2The first coil 23 and the second coil 24 shown in the figure do not cross each other. That is, the first coil 23 does not cross the second coil 24 in the projection area of the second conductive layer, and the second coil 24 does not cross the first coil 23 in the projection area of the first conductive layer. Alternatively, the first coil 23 and the second coil 24 can be arranged close to each other. For example, the distance between the first coil 23 and the second coil 24 in the projection area of the second conductive layer can be less than a preset distance. The distance between the second coil 24 and the first coil 23 in the projection area of the first conductive layer can be less than a preset distance.

[0150] According to the foregoing examples, Figure 7 The communication tag 20 can have two independent sensing areas, which can correspond to the sensing area of the first coil 23 and the sensing area of the second coil 24, respectively. In the area surrounded by the first coil 23, the first coil 23 can form a magnetic field in the first direction; similarly, in the area surrounded by the second coil 24, the second coil 24 can form a magnetic field in the first direction. Therefore, in the interval area of the first coil 23 and the second coil 24, the first coil 23 and the second coil 24 can form a magnetic field in the second direction opposite to the first direction, as shown in Figure 7 The magnetic field in the interval area of the first coil 23 and the second coil 24 can be utilized. For example, it can be used for communication, or for energy transmission.

[0151] Figure 8 is another structural schematic diagram of a communication tag 20 provided by the embodiment of the application. Along Figure 9 The communication tag 20 in the B-B section can obtain the view of the B-B section shown in Figure 9

[0152] Similar to the communication tag 20 shown in Figure 9 The communication tag 20 shown in Figure 7 includes a circuit board 21, a chip 22, and the circuit of the circuit board 21 forms a first coil 23 and a second coil 24 of the communication tag 20. The first coil 23 and the second coil 24 do not cross each other. The structure of the first coil 23 and the structure of the second coil 24 can refer to the examples shown in Figure 9 The electrical connection relationship, structural relationship and positional relationship between the first coil 23 and the chip 22, and the electrical connection relationship, structural relationship and positional relationship between the second coil 24 and the chip 22 can refer to the examples shown in Figure 2

[0153] The communication tag 20 shown in Figures 2 to 4 is slightly different from the communication tag 20 shown in Figure 7 ​​The communication tag 20 shown may further include a capacitive device 26, a third coil 27, and a fifth line 28. A first end of the third coil 27 is electrically connected to a first port of the capacitive device 26. A second end of the third coil 27 is electrically connected to a second port of the capacitive device 26 via a fifth line 28.

[0154] The capacitive device 26 can be a capacitive chip or a capacitor. The capacitive chip can be, for example, an inactive (or deactivated) chip. In some embodiments, the capacitive device 26 can be disposed on the same side of the third conductive layer 230 as the chip 22. In other embodiments, the capacitive device 26 can be disposed on opposite sides of the circuit board 21 as the chip 22.

[0155] One side of the third coil 27 may be arranged to cross the first coil 23. The other side of the third coil 27 may be arranged to cross the second coil 24. In some embodiments, the projection of the third coil 27 on the first conductive layer 210 may be located within the area enclosed by the first coil 23. The projection of the third coil 27 on the second conductive layer 220 may be located within the area enclosed by the second coil 24. The third coil 27 may be arranged on the third conductive layer 230 of the circuit board 21. Figure 9 In the illustrated embodiment, the third conductive layer 230 may be located on a side of the first conductive layer 210 away from the second conductive layer 220 .

[0156] The fifth line 28 can be provided on a conductive layer other than the third conductive layer 230 of the circuit board 21. For example, the fifth line 28 can be provided on the first conductive layer 210 or the second conductive layer 220. The fifth line 28 and the third coil 27 can be electrically connected through a conductive hole. The fifth line 28 and the capacitive device 26 can be electrically connected through a conductive hole. Figure 9 In the illustrated embodiment, the fifth line 28 may be located between the first coil 23 and the second coil 24 .

[0157] exist Figure 9 In the embodiment shown, the first coil 23 and the second coil 24 can form a magnetic field in a first direction. A magnetic field in a second direction can be formed between the first coil 23 and the second coil 24. The third coil 27 can be induced by the first coil 23 and the second coil 24 and form a magnetic field in the first direction. As a result, the directions of the magnetic fields formed by the first coil 23, the second coil 24, and the third coil 27 can be the same. The capacitive device 26 can be used to adjust the working frequency portion of the third coil 27 so that the working frequency portion of the third coil 27 can be the same as the working frequency portion of the first coil 23 and the second coil 24. The working frequency portion of the third coil 27 can correspond to Figure 9 The resonant frequency f0 is shown.

[0158] exist Figure 10In the embodiment shown, the magnetic field of the second direction formed between the first coil 23 and the second coil 24 can induce the magnetic field of the first direction in the third coil 27. Figure 9 Figure 9 In the illustrated embodiment, both the first coil 23 and the second coil 24 can generate a counterclockwise current, causing the third coil 27 to generate a counterclockwise current, thereby generating a magnetic field in the first direction. Therefore, the effective sensing area of ​​the communication tag 20 includes the sensing area of ​​the first coil 23, the sensing area of ​​the second coil 24, and the sensing area between the first coil 23 and the second coil 24. Therefore, the effective sensing area of ​​the communication tag 20 can be greater than the sum of the effective sensing areas of the first coil 23 and the second coil 24.

[0159] The communication tag provided in the present application can have a relatively large sensing area, and the magnetic flux of the magnetic field radiated by the communication tag can be relatively good. Therefore, the solution provided in the embodiment of the present application can take into account the sensing area and the amplitude of the induced magnetic field of the communication tag, thereby helping to improve the performance of the communication tag in sensing short-range communication signals. For example, since the sensing area of ​​the communication tag can be relatively large and the magnetic flux amplitude is high, when the user brings the other device close to any effective sensing area of ​​the communication tag, the other device can quickly complete pairing with the communication tag, or the other device can quickly complete pairing with an electronic device with the communication tag, which is conducive to improving the convenience of users using the communication tag.

[0160] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A communication tag (20), characterized in that: include: A circuit board (21), the circuit board (21) comprising a first coil (23) and a second coil (24), the first coil (23) and the second coil (24) being located on different conductive layers on the circuit board (21), and the current in the first coil (23) and the current in the second coil (24) having the same direction; A chip (22), the chip (22) being arranged on the circuit board (21), the chip (22) comprising a first port (2201) and a second port (2202), the first port (2201) and the second port (2202) having opposite polarities; The circuit board (21) includes a first conductive layer (210) and a second conductive layer (220); the chip (22), the first conductive layer (210), and the second conductive layer (220) form a coil feeding circuit (29); the coil feeding circuit (29) includes a first feeding terminal (291), a second feeding terminal (292), a third feeding terminal (293), and a fourth feeding terminal (294); The first feeding end (291) is located on the first conductive layer (210) and is electrically connected to the first port (2201); The second feeding end (292) is located on the first conductive layer (210) and is electrically connected to the second port (2202); The third feeding end (293) is located on the second conductive layer (220) and is arranged opposite to the first feeding end (291), and the third feeding end (293) is electrically connected to the second port (2202); The fourth feeding end (294) is located on the second conductive layer (220) and is arranged opposite to the second feeding end (292), and the fourth feeding end (294) is electrically connected to the first port (2201); The first coil (23) is electrically connected between the first feeding terminal (291) and the third feeding terminal (293), and the second coil (24) is electrically connected between the second feeding terminal (292) and the fourth feeding terminal (294).

2. The communication tag (20) according to claim 1, characterized in that The coil feeding circuit (29) further includes a first conductive hole (252) and a second conductive hole (254), The first conductive hole (252) is electrically connected between the second feeding terminal (292) on the first conductive layer (210) and the third feeding terminal (293) on the second conductive layer (220), The second via (254) is electrically connected between the first feeding terminal (291) on the first conductive layer (210) and the fourth feeding terminal (294) on the second conductive layer (220).

3. The communication tag (20) according to claim 1 or 2, characterized in that: The coil feeding circuit (29) comprises a first circuit (211), the first circuit (211) is located in the first conductive layer (210), and the first circuit (211) is electrically connected between the first port (2201) and the first feeding end (291); The coil feeding circuit (29) further includes a second circuit (212), the second circuit (212) being located in the first conductive layer (210), and the second circuit (212) being electrically connected between the second port (2202) and the second feeding end (292); The coil feeding circuit (29) further includes a third circuit (221), the third circuit (221) being located on the second conductive layer (220), the third circuit (221) being arranged opposite to the first circuit (211), the third circuit (221) being electrically connected between the first conductive hole (252) and the third feeding terminal (293), and the third circuit (221) being electrically connected to the second port (2202) via the first conductive hole (252) and the second circuit (212); The coil feeding circuit (29) further includes a fourth line (222), the fourth line (222) being located in the second conductive layer (220), the fourth line (222) being arranged opposite to the second line (212), the fourth line (222) being electrically connected between the second conductive hole (254) and the fourth feeding terminal (294), and the fourth line (222) being electrically connected to the first port (2201) and the first line (211) via the second conductive hole (254).

4. The communication tag (20) according to claim 3, characterized in that The third circuit (221) and the fourth circuit (222) are located on both sides of the chip (22), the first conductive hole (252) is located on a side of the chip (22) close to the third circuit (221), and the second conductive hole (254) is located on a side of the chip (22) close to the fourth circuit (222); The first line (211) includes a first portion (2111), the first portion (2111) of the first line (211) and the third line (221) are arranged relative to each other; the second line (212) includes a first portion (2121), the first portion (2121) of the second line (212) and the fourth line (222) are arranged relative to each other; The first circuit (211) further comprises a second portion (2112) and a third portion (2113), one end of the second portion (2112) of the first circuit (211) is connected to the second conductive hole (254), and the third portion (2113) of the first circuit (211) surrounds the first conductive hole (252) and is connected between the first portion (2111) and the second portion (2112) of the first circuit (211); The second circuit (212) further comprises a second portion (2122) and a third portion (2123); one end of the second portion (2122) of the second circuit (212) is connected to the first conductive hole (252); the third portion (2123) of the second circuit (212) surrounds the second conductive hole (254) and is connected between the first portion (2121) and the second portion (2122) of the second circuit (212); The distance between the second portion (2112) of the first line (211) and the second portion (2122) of the second line (212) is smaller than a preset distance.

5. The communication tag (20) according to claim 4, characterized in that The first port (2201) of the chip (22) is located between the second portion (2112) and the third portion (2113) of the first line (211), and the second port (2202) of the chip (22) is located between the second portion (2122) and the third portion (2123) of the second line (212).

6. The communication tag (20) according to claim 3, characterized in that The first circuit (211) and the second circuit (212) are located on both sides of the chip (22), the first conductive hole (252) is located on a side of the chip (22) close to the second circuit (212), and the second conductive hole (254) is located on a side of the chip (22) close to the first circuit (211); The third line (221) includes a first portion, the first portion (2211) of the third line (221) and the first line (211) are arranged relative to each other; the fourth line (222) includes a first portion (2221), the first portion (2221) of the fourth line (222) and the second line (212) are arranged relative to each other; The third circuit (221) further comprises a second portion (2212) and a third portion (2213); one end of the second portion (2212) of the third circuit (221) is connected to the first conductive hole (252); the second portion (2212) of the third circuit (221) and the first circuit (211) or the second circuit (212) are arranged opposite to each other; the third portion (2213) of the third circuit (221) surrounds the second conductive hole (254) and is connected between the first portion (2211) and the second portion (2212) of the third circuit (221); The fourth circuit (222) further comprises a second portion (2222) and a third portion (2223); one end of the second portion (2222) of the fourth circuit (222) is connected to the second conductive hole (254); the second portion (2222) of the fourth circuit (222) and the first circuit (211) or the second circuit (212) are arranged opposite to each other; the third portion (2223) of the fourth circuit (222) surrounds the first conductive hole (252) and is connected between the first portion (2221) and the second portion (2222) of the fourth circuit (222).

7. The communication tag (20) according to claim 6, characterized in that The first port (2201) of the chip (22) is connected to one end of the first line (211), and the second port (2202) of the chip (22) is connected to one end of the second line (212).

8. The communication tag (20) according to any one of claims 1 to 7, characterized in that: The first conductive layer (210) further includes a fifth line (213) electrically connected between the first feeding end (291) and the first end (231) of the first coil (23); the second conductive layer (220) further includes a sixth line (223) electrically connected between the third feeding end (293) and the second end (232) of the first coil (23); the fifth line (213) and the sixth line (223) are arranged relative to each other.

9. The communication tag (20) according to any one of claims 1 to 8, characterized in that: The first conductive layer (210) further includes a seventh line (214) electrically connected between the second feed end (292) and the first end (242) of the second coil (24); the second conductive layer (210) further includes an eighth line (224) electrically connected between the fourth feed end (294) and the second end (241) of the second coil (24); the seventh line (224) and the eighth line (214) are arranged relative to each other.

10. The communication tag (20) according to any one of claims 1 to 9, characterized in that: The first coil (23) and the second coil (24) are arranged crosswise.

11. The communication tag (20) according to claim 10, characterized in that The first coil (23) is located on the first conductive layer (210), the second coil (24) is located on the second conductive layer (220), and a partial projection of the first coil (23) on the second conductive layer (220) is located within an area enclosed by the second coil (24).

12. The communication tag (20) according to any one of claims 1 to 9, characterized in that: The first coil (23) is located on the first conductive layer (210), the second coil (24) is located on the second conductive layer (220), and the first coil (23) and the second coil (24) do not cross each other; The circuit board (21) further comprises a third conductive layer (230), the third conductive layer (230) comprises a third coil (27), the third coil (27) and the first coil (23) are arranged in a cross-arrangement, and the third coil (27) and the second coil (24) are arranged in a cross-arrangement; the communication tag (20) further comprises: A capacitive device (26), wherein a first port of the capacitive device (26) is electrically connected to a first end of the third coil (27), and a second port of the capacitive device is electrically connected to a second end of the third coil (27).

13. The communication tag (20) according to claim 12, characterized in that A first portion of the third coil (27) projected on the first conductive layer (210) is located within an area enclosed by the first coil (23), and a second portion of the third coil (27) projected on the second conductive layer (220) is located within an area enclosed by the second coil (24).

14. The communication tag (20) according to claim 12 or 13, characterized in that: The chip (22) and the capacitive device (26) are arranged on the same side of the third conductive layer (230).

15. The communication tag (20) according to any one of claims 1 to 14, characterized in that The projection of the chip (22) on the circuit board (21) is located outside the first coil (23) and the second coil (24).

16. An electronic device (100), characterized in that It comprises a communication tag (20) as claimed in any one of claims 1 to 15.

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