Semiconductor super junction power device

Abstract

The embodiment of the present application provides a semiconductor super-junction power device, which comprises an n-type drain region, an n-type drift region above the n-type drain region, a plurality of p-type columns with the same width, and the same interval between two adjacent p-type columns; a first p-type body region is arranged on the top of the p-type column, a first n-type source region is arranged in the first p-type body region; two gate trenches are arranged between two adjacent first p-type body regions, the interval between the two gate trenches has at least two different interval values; the width of the gate trench is the same, and a gate dielectric layer and a gate electrode are arranged in the gate trench. The present application can adjust the change curve of the gate-drain capacitance of the semiconductor super-junction power device, and reduce the on-resistance.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor power device technology, and in particular relates to a semiconductor superjunction power device. Background Technology

[0002] Superjunction power devices (SCDs) are based on charge-balancing technology, which reduces on-resistance and parasitic capacitance, resulting in extremely fast switching characteristics, reduced switching losses, and higher power conversion efficiency. During the turn-on and turn-off processes of SCDs, the Miller capacitance (Crss) and its corresponding gate-drain capacitance (Cgd) play crucial roles. It is well-known that the gate-drain capacitance (Cgd) of SCDs undergoes abrupt changes during turn-on and turn-off, causing a significant shift in the device's electrical performance. Summary of the Invention

[0003] In view of this, the purpose of the present invention is to provide a semiconductor superjunction power device with an adjustable gate-drain capacitance variation curve to solve the problem of sudden changes in gate-drain capacitance in existing semiconductor superjunction power devices.

[0004] An embodiment of the present invention provides a semiconductor superjunction power device, comprising:

[0005] n-type leak area;

[0006] An n-type drift region located above the n-type leak region;

[0007] Several p-shaped columns of the same width, with the same spacing between two adjacent p-shaped columns;

[0008] The top of the p-shaped column is provided with a first p-shaped body region, and a first n-shaped source region is provided within the first p-shaped body region;

[0009] The two gate trenches located between two adjacent first p-type body regions have at least two different spacing values ​​between them.

[0010] The gate trenches are all the same width, and a gate dielectric layer and a gate electrode are disposed in the gate trenches.

[0011] Optionally, it also includes a second p-type body region located between the two gate trenches, wherein a second n-type source region is provided in the second p-type body region, and the width of the second p-type body region has at least two different width values.

[0012] Optionally, the thickness of the gate dielectric layer at the bottom of the gate trench is greater than the thickness of the gate dielectric layer at the sidewall of the gate trench.

[0013] The semiconductor superjunction power device of this invention adopts a double trench gate structure between adjacent first p-type body regions. The gate-drain capacitance variation curve can be adjusted by adjusting the spacing between the gate trenches. At the same time, the on-resistance of the semiconductor superjunction power device can be reduced by increasing the number of current channels. Attached Figure Description

[0014] To more clearly illustrate the technical solutions of exemplary embodiments of the present invention, the accompanying drawings used in describing the embodiments are briefly introduced below.

[0015] Figure 1 This is a cross-sectional structural schematic diagram of the first embodiment of the semiconductor superjunction power device provided by the present invention;

[0016] Figure 2 This is a cross-sectional structural schematic diagram of the second embodiment of the semiconductor superjunction power device provided by the present invention. Detailed Implementation

[0017] The technical solutions of the present invention will be fully described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Furthermore, to clearly illustrate the specific implementation of the present invention, the sizes of the figures listed in the accompanying drawings do not represent actual dimensions; the accompanying drawings are schematic and should not limit the scope of the present invention.

[0018] Figure 1 This is a cross-sectional structural schematic diagram of the first embodiment of the semiconductor superjunction power device provided by the present invention, as shown below. Figure 1 As shown in the figure, an embodiment of the present invention provides a semiconductor superjunction power device, including an n-type drain region 20, which can be connected to an external drain voltage through a metal layer. An n-type drift region 21 is located above the n-type drain region 20.

[0019] Several p-type pillars 23, each with the same width and the same spacing between adjacent p-type pillars 23, form a charge-balanced pn junction structure with the adjacent n-type drift region 21. (For ease of demonstration and explanation...) Figure 1 Only three p-shaped columns 23 are shown as examples.

[0020] Each p-shaped column 23 has a first p-shaped body region 24 at its top, and a first n-shaped source region 25 is provided in the first p-shaped body region 24.

[0021] The two gate trenches 22 located between two adjacent first p-type body regions 24 have at least two different spacing values. In this embodiment of the invention, two different spacing values, b1 and b2 (b1≠b2), are exemplarily shown. When the source-drain voltage completely depletes the region between the gate trenches 22, the gate-drain capacitance drops suddenly at this voltage point. By setting at least two different spacing values ​​for the spacing between the gate trenches 22, the region with a smaller spacing between the gate trenches 22 is depleted first, and the gate-drain capacitance drops suddenly at this source-drain voltage point. Then, as the source-drain voltage further increases, the region with a slightly wider spacing between the gate trenches 22 is depleted sequentially, and the gate-drain capacitance drops suddenly at these source-drain voltage points sequentially. Thus, the abrupt change points of the gate-drain capacitance of the product are distributed across several different source-drain voltage points, which reduces the rate of change of the gate-drain capacitance and reduces the gate voltage oscillation caused by the abrupt change in gate-drain capacitance.

[0022] It should be noted that the spacing between the grid grooves 22 can be understood as the spacing between the grid grooves 22 between two adjacent p-shaped posts 23, rather than the spacing between two grid grooves 22 on both sides of the same p-shaped post 23.

[0023] The gate trenches 22 have the same width. A gate dielectric layer 26 and a gate 27 are provided in the gate trenches 22. The gate 27 is usually controlled by an external gate voltage to turn on and off the first current channel of the first p-type body region 24.

[0024] The semiconductor superjunction power device of the present invention adopts a double trench gate structure between the first p-type body regions 24. By adjusting the spacing between the gate trenches, the change curve of the gate drain capacitance is adjusted, so that the sudden change of the gate drain capacitance is slowed down when the semiconductor superjunction power device is turned on and off.

[0025] Figure 2 This is a cross-sectional structural schematic diagram of the second embodiment of the semiconductor superjunction power device provided by the present invention, and... Figure 1 Compared with the embodiments shown, Figure 2 The semiconductor superjunction power device of the present invention shown further includes a second p-type body region 44, which is disposed between the two gate trenches 22 and above the n-type drift region 21. In this case, the width of the second p-type body region 44 has at least two different width values, corresponding to... Figure 1 Correspondingly, Figure 2The second p-type body region 44 has two different width values, b1 and b2 (b1≠b2). A second n-type source region 45 is located within the second p-type body region 44. The gate 27 can also simultaneously control the opening and closing of the second current channel within the second p-type body region 44 via the gate voltage. This increases the number of current channels in the semiconductor superjunction power device, which can reduce the on-resistance of the semiconductor superjunction power device.

[0026] The semiconductor superjunction power device of the present invention can also make the thickness of the gate dielectric layer 26 at the bottom of the gate trench 22 greater than the thickness of the gate dielectric layer 26 at the sidewall of the gate trench 22, which can reduce the value of the gate drain capacitance and further reduce the degree of gate drain capacitance change.

[0027] The above specific implementation methods and embodiments are specific support for the technical concept of the present invention, and should not be used to limit the scope of protection of the present invention. Any equivalent changes or modifications made on the basis of the technical solution based on the technical concept proposed by the present invention shall still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A semiconductor superjunction power device, characterized in that, include: n-type leak area; An n-type drift region located above the n-type leak region; Several p-shaped columns of the same width, with the same spacing between two adjacent p-shaped columns; The top of the p-shaped column is provided with a first p-shaped body region, and a first n-shaped source region is provided within the first p-shaped body region; Two gate trenches are located between two adjacent first p-type body regions; wherein, the area between two adjacent first p-type body regions is an adjacent region, and the spacing between two gate trenches located in one adjacent region is different from the spacing between two gate trenches located in another adjacent region; The gate trenches are all the same width, and a gate dielectric layer and a gate are provided in the gate trenches; A second p-type body region is located between the two gate trenches, and a second n-type source region is provided within the second p-type body region. The width of the second p-type body region has at least two different width values. The second p-type body region and the first p-type body region are located on opposite sides of the same gate trench.

2. The semiconductor superjunction power device as described in claim 1, characterized in that, The thickness of the gate dielectric layer at the bottom of the gate trench is greater than the thickness of the gate dielectric layer at the sidewall of the gate trench.

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