A static parameter inl test method based on bipolar dac

Abstract

This invention relates to a static parameter INL testing method based on a bipolar DAC, belonging to the field of electronic component testing technology. It solves the problems of complex hardware structure or difficult software programming in existing bipolar DAC static parameter INL testing methods. The method includes: connecting the bipolar DAC under test to an ATE (Automatic Test Equipment); connecting the DAC's most significant digital input pin to the ATE without an inverter; performing positive and negative polarity INL tests on the DAC, including: the ATE sending a digital input ladder waveform to the non-most significant digital input pin of the bipolar DAC, and controlling the most significant digital input pin to maintain a low input level during the positive polarity test and a high input level during the negative polarity test; simultaneously, synchronously acquiring the voltage output of the DAC's analog output pin during the current polarity INL test; obtaining the measured INL value based on the synchronous acquisition results of the positive and negative polarity INL tests; if the measured INL value is within the INL criterion range, the test passes; otherwise, the test fails.

Description

Technical Field

[0001] This invention relates to the field of electronic component testing technology, and in particular to a static parameter INL testing method based on a bipolar DAC. Background Technology

[0002] A DAC is an interface circuit that converts digital signals into analog signals. INL (Integral Nonlinearity) characterizes the difference between the actual output and the ideal conversion curve of the DAC, reflecting the DAC's conversion performance and serving as a crucial static parameter. DNL (Differential Nonlinearity) primarily represents the difference between the actual code step size and the theoretical code step size, while INL (Integral Nonlinearity) focuses on the cumulative effect of all code nonlinearity errors. Most DACs are unipolar DACs, meaning their analog output voltage range is generally from GND to positive voltage. Bipolar DACs, on the other hand, have an analog output voltage range covering both negative and positive voltages. Bipolar DACs offer excellent compatibility, matching most bipolar driver and control circuits without signal conversion. However, due to their positive and negative voltage output range, the input digital code conversion curve of a bipolar DAC is no longer monotonous, exhibiting abrupt changes. Using ATE-based static testing methods for unipolar DACs will result in significant errors in the test results, making it difficult to accurately measure INL. Previously, there were two methods for testing the static parameters of bipolar DACs:

[0003] First, it requires the use of an inverter's peripheral circuit design. This method can perfectly solve the problem of non-monotonous and discontinuous conversion curves. Automatic testing equipment can directly input the parameter formulas to calculate continuous conversion curves. However, this method requires modification of the DAC's peripheral test loop, which increases hardware design costs and is quite cumbersome. It also has low compatibility with general-purpose DAC test adapters of the same series or type and is rarely used.

[0004] Secondly, without changing the typical DAC test loop design, the voltage value of each DAC output is sampled into the register of the automatic test machine. The sampled value of each step is shifted by software algorithm (negative voltage is shifted to positive voltage, positive voltage is shifted to negative voltage, and the shifted value is half of the ideal analog output voltage range). This method can also obtain a complete conversion curve, but it increases the difficulty of software programming, increases the software running time, is more cumbersome, and requires customized programs for the same series of DACs, resulting in high development costs. Summary of the Invention

[0005] Based on the above analysis, the present invention aims to provide a static parameter INL testing method based on a bipolar DAC, in order to solve the problems of complex hardware structure or difficult software programming in existing bipolar DAC static parameter INL testing methods.

[0006] This invention discloses a method for testing the static parameter INL based on a bipolar DAC, comprising:

[0007] Connect the bipolar DAC under test to the ATE; wherein the most significant bit of the bipolar DAC under test is not connected to the ATE via an inverter.

[0008] Perform positive and negative INL tests on the bipolar DAC, including: ATE sends a digital input ladder wave to the non-most significant digital input pin of the bipolar DAC, and controls the most significant digital input pin to maintain a low input level during the positive polarity test and a high input level during the negative polarity test. At the same time, during the INL test of the current polarity, the voltage output of the analog output pin of the bipolar DAC is synchronously acquired.

[0009] The measured INL value is obtained based on the synchronous acquisition results of the positive and negative polarity INL tests;

[0010] If the measured value of INL is within the range of the INL criterion, the static parameter INL test of the bipolar DAC under test is passed; otherwise, the test is failed.

[0011] Based on the above solution, the present invention also makes the following improvements:

[0012] Furthermore, each step in the digital input stepped wave uniquely corresponds to a digital code value, which monotonically increases from 0 to 2. n-1 , where n is the number of bits in the bipolar DAC.

[0013] Furthermore, when the ATE sends a digital input ladder wave to the non-most significant digital input pin of the bipolar DAC, bit 0 is the least significant bit of the digital input pin receiving the ladder wave, and bit n-2 is the most significant bit of the digital input pin receiving the ladder wave.

[0014] Furthermore, each step in the stepped wave is repeated N times.

[0015] Furthermore, the synchronous acquisition frequency in the positive and negative polarity INL test is controlled by the logic input pins of ATE to be no less than the conversion frequency of each step in the digital input stepped wave.

[0016] Furthermore, the voltages output from the analog output pins of the bipolar DAC during the INL test are synchronously acquired via the AWGD pin of the ATE for both positive and negative polarities.

[0017] Furthermore, the number of sampling points for synchronous acquisition of both positive and negative polarity INL tests is no less than the product of the number of digital code values ​​and the number of repetitions of each digital code value.

[0018] Furthermore, obtaining the measured INL value based on the synchronous acquisition results of the positive and negative polarity INL tests includes:

[0019] Calculate the average voltage of N analog output sampling points corresponding to each digital code value in the synchronous acquisition results of the INL test for positive and negative polarities respectively, sort the average voltage values ​​according to the sampling order, and obtain the sampling arrays corresponding to positive and negative polarities respectively.

[0020] The sampling arrays corresponding to the positive and negative polarities are respectively input into the INL algorithm of the DAC to obtain the static parameters INL corresponding to the positive and negative polarities;

[0021] The larger value in the static parameter INL corresponding to positive and negative polarities is taken as the measured value of INL.

[0022] Furthermore, when the sampling array corresponding to positive or negative polarity is input into the DAC's INL algorithm, the following is executed:

[0023] Obtain the deviation between the difference between the next element and the previous element in the sampling array corresponding to positive or negative polarity and lsbv, and use the sum of this deviation and the INL value corresponding to the previous element as the INL value corresponding to the next element; where the INL value corresponding to the first element in the sampling array is 0.

[0024] The INL value with the largest absolute value is taken as the static parameter INL corresponding to the current polarity;

[0025] Wherein, lsbv represents the ideal change value of the analog quantity corresponding to a unit change in digital code value.

[0026] Furthermore, after connecting the bipolar DAC under test to the ATE, the ATE first performs an output voltage range test on the analog output pins of the bipolar DAC under test.

[0027] If the output voltage range test passes, then perform positive and negative INL tests on the bipolar DAC separately; if the output voltage range test fails, then the static parameter INL test fails.

[0028] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0029] This invention proposes a rapid testing method for the static parameter INL in a bipolar DAC, improving upon previous testing methods. During the positive and negative INL testing of the bipolar DAC, the ATE (Automatic Test Equipment) sends a stepped wave only to the non-most significant bit digital input pin, while controlling the most significant bit digital input pin to maintain a low input level during the positive polarity test and a high input level during the negative polarity test. Then, the measured INL value is obtained by processing the synchronously acquired voltage, and the test pass / fail status is determined based on the measured INL value. This process requires no complex hardware structure and has relatively simple software programming, effectively reducing the computational load during the test and quickly obtaining test results. Using the scheme in this invention, the static parameter INL of a bipolar DAC can be tested quickly and accurately.

[0030] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained from what is particularly pointed out in the description and drawings. Attached Figure Description

[0031] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.

[0032] Figure 1 This is a schematic diagram of a typical unipolar DAC conversion curve;

[0033] Figure 2 This is a schematic diagram of the conversion characteristic curve of a bipolar DAC.

[0034] Figure 3 Flowchart of a rapid testing method for the static parameter INL of a bipolar DAC based on ATE;

[0035] Figure 4 A schematic diagram is provided to define the pin connections between the DAC under test and the ATE. Detailed Implementation

[0036] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.

[0037] This invention is a rapid testing method for the static parameter INL in a bipolar DAC. This method is based on ATE (Automatic Test Equipment). The following section describes the various parts of this concept.

[0038] DAC static parameters describe the intrinsic characteristics of the device and the errors in its internal circuitry. Among these, integral nonlinearity (INL) and error are among the most important test parameters for a DAC. The largest difference between two adjacent scale points on a DAC is called differential nonlinearity (DNL). Integral nonlinearity (INL) represents the error value at the point where the analog value of the DAC deviates most from the true value across all numerical points; in other words, it's the largest deviation of the output value from linearity. Differential nonlinearity describes the difference between the code conversion and the ideal state. A bipolar DAC is a DAC whose analog output voltage range covers both positive and negative voltage ranges, and its analog output voltage swings between ±VFS. A unipolar DAC's analog output voltage swings between VFS and GND.

[0039] For INL testing of unipolar DACs, the common electrical testing method is to send a stepped-wave digital signal (monotonically increasing from 0 to 2) using an automated testing machine. n1 (n1 is the number of bits in the unipolar DAC) is given to the digital input pin of the DAC under test. After configuring the DAC's sampling and holding, conversion rate, power supply conditions and other operating conditions, the input stepped wave is sampled and converted at a certain frequency and output. Thus, the test system can draw a digital code conversion curve based on the output voltage or current value. The horizontal axis is the digital code value voltage and the vertical axis is the sampling voltage. Figure 1 This is a typical schematic diagram of the conversion curve for a unipolar DAC. After the conversion curve is plotted, the data on the curve is calculated using formulas. According to the definition of INL, the INL parameter values ​​are calculated, and then it is determined whether these two parameters meet the requirements of the technical manual. However, because the output range of a bipolar DAC spans "0V", its conversion curve is non-monotonic. Directly applying the INL test method for a unipolar DAC to the test system will result in distorted results at non-monotonic conversion points in the INL formula, thus affecting the actual conversion error test.

[0040] This embodiment uses the AD7840, a typical bipolar DAC, as an example for illustration. The AD7840 is a 14-bit, parallel-output, voltage-type bipolar DAC with a bipolar output voltage range of ±3V. For a 14-bit DAC, its LSB = FSR / 16384, that is, 1 LSB = 6V / 16384 = 366μV. FSR represents the full-scale voltage. Taking the AD7840 as an example, its ideal input-output conversion relationship is shown in Table 1.

[0041] Table 1 Ideal Input-Output Conversion Relationship of AD7840

[0042]

[0043] As shown in Table 1, within the analog output range of -3V to 0V, there is a linear correspondence between digital input and analog output. Specifically, a -3V analog output corresponds to the digital code 10 0000 0000 0000, and GND (0V) corresponds to a linear change between 11 1111 1111 1111. Within the analog output range of 0V to 3V, there is also a linear correspondence between analog output voltage and digital input. An analog input of 0V corresponds to the digital code 00 0000 0000 0000, and an analog output voltage of 3V corresponds to the digital code 01 1111 11111111. However, around 0V, there is a sudden change in the output digital code. The digital code corresponding to the change from negative 0V to positive 0V changes directly from the maximum digital code 11 1111 1111 1111 to the minimum digital code 00 0000 0000 0001. A schematic diagram of the digital code conversion from -3V to 3V is shown below. Figure 2 As shown in Figure 2, the horizontal axis represents the digital code input, and the vertical axis represents the analog output voltage, having already converted the binary values ​​to decimal values. The corresponding unipolar DAC conversion characteristics are as follows: Figure 1 As shown, it is clear that the ideal conversion characteristics of a bipolar DAC differ from those of a unipolar DAC. The main reason for this is that the most significant bit of the digital input pin of a bipolar DAC is a flag bit. According to the rules of two's complement, this flag bit is 1 when the value is negative and 0 when the value is positive, resulting in a discontinuous conversion curve. Therefore, to test the static parameters of a bipolar DAC, it is necessary to connect an inverter to the most significant bit of the digital input pin in hardware or shift the sampled voltage value in the software program. This ensures that the analog output voltage corresponding to the digital input binary code from 00 0000 0000 0000 to 100000 0000 0000 is continuous. Then, the curve can be substituted into the INL formula for calculation.

[0044] The problem with these two methods is that testing peripheral circuits requires additional hardware, which increases the design difficulty of the test adapter and the testing cost; or the software algorithm requires numerical calculations, which increases the complexity of the program, especially for serial input bipolar DACs, where array calculations need to be completed in a loop, greatly increasing the overall testing time.

[0045] To address the aforementioned issues, this embodiment provides a static parameter INL testing method based on a bipolar DAC, the flowchart of which is shown below. Figure 3 As shown, it includes the following steps:

[0046] Step S1: Connect the bipolar DAC under test to the ATE; wherein, the most significant bit of the bipolar DAC under test is not connected to the ATE via an inverter;

[0047] In this step, the bipolar DAC under test is connected to the ATE by performing the following procedure:

[0048] Design a test adapter for a universal test circuit of a bipolar DAC (without inverter hardware). The test adapter is used to adapt and connect the bipolar DAC under test (DUT) to the ATE (Automatic Test Equipment). Wiring from the DUT is connected to the test adapter, and the adapter connects to the corresponding hardware resources of the ATE. The test adapter design follows the technical manual requirements of the DUT. Generally, the digital input pins and logic input pins of the DUT need to be connected to the digital communication module (DCM) of the test equipment. Analog output pins, power supply, and ground pins should be routed according to requirements (PCB traces). These wirings need to be connected to the test adapter, and the adapter connects to the corresponding hardware resources of the ATE. The test adapter facilitates engineering applications and modular development. The logic input pins serve as timing and logic control pins for the positive and negative polarity test patterns, and are connected to the ATE's DCM via the corresponding pins on the test adapter. The digital input pins connect to the digital channel resources of the test equipment. If the bipolar DAC is a voltage output type, connect its analog output pins to the AWGD resource in the ATE via the corresponding pins of the test adapter. If the bipolar DAC is a current output type, when designing the test adapter, it is also necessary to connect a sampling resistor in series with its analog output pins or design the peripheral circuit according to the test circuit requirements. Power and ground need to be connected to the power ground loop of the automatic test equipment. In addition, for some hardware settings requirements, such as shorting pins to ground or VCC, design them according to the manual. For the decoupling, voltage regulation, and differential circuit requirements needed for testing, design the corresponding capacitors, inductors, and other peripheral circuits (the function of the peripheral circuits is to stabilize the test waveform, stabilize the power supply, and make the test waveform more stable for easier measurement). It is particularly important to note that regarding the connection of digital input pins, the typical hardware testing method for bipolar DACs involves connecting the most significant digital input pin to an inverter before connecting it to the test equipment. However, in this embodiment, since the ATE only sends digital input ladder waveforms to the non-most significant digital input pins of the bipolar DAC, and the most significant digital input pin is only used to maintain the high / low level state corresponding to this polarity test, the synchronous acquisition result matches the digital input ladder waveform. Therefore, the subsequent step of obtaining the measured INL value based on the synchronous acquisition result does not need to consider the situation of the most significant digital input pin. Thus, the most significant digital input pin can be directly connected to the test equipment, equivalent to the unipolar DAC testing connection method.

[0049] After installing the aforementioned test adapter into the automated test bench, determine the hardware resource connection configuration in the automated test bench according to the test adapter and device datasheet, and perform corresponding pin definition programming in the test software; complete the detailed definition of each pin of the DAC under test in the test bench, ensuring a one-to-one correspondence between resource channels and the pins of the device under test, thus achieving a complete connection between the automated test bench and the hardware of the device under test, such as... Figure 4 As shown. Among them, AWGD, DCM, and PVI are analog waveform detection, digital, and power supply resources for automatic testing equipment.

[0050] Step S2: Perform positive and negative INL tests on the bipolar DAC, including: ATE sends a digital input ladder wave to the non-most significant digital input pin of the bipolar DAC, and controls the most significant digital input pin to maintain a low input level during the positive polarity test and a high input level during the negative polarity test. At the same time, during the INL test of the current polarity, the voltage output by the analog output pin of the bipolar DAC is synchronously acquired.

[0051] It should be noted that before executing step S2, an output voltage range test step for the analog output pin can be added to ensure that the analog output pin is in a normal working state. If the output voltage range test passes, then the bipolar DAC is tested for positive and negative INL values ​​respectively; if the output voltage range test fails, the static parameter INL test fails. The output voltage range test of the analog output pin is implemented using existing methods. This embodiment adds an output voltage range test of the analog output pin before the actual INL test to verify whether the analog output pin is in a normal working state. Only when the analog output pin is in a normal working state is the subsequent INL test process meaningful; otherwise, since the analog output pin itself is in an abnormal working state, there is no need to perform the subsequent INL test process, and the INL test failure can be foreseen.

[0052] Preferably, each step in the digital input stepped wave uniquely corresponds to a digital code value, and the digital code value monotonically increases from 0 to 2. n-1Simultaneously, when the ATE sends a digital input ladder waveform to the non-most significant digital input pin of the bipolar DAC, bit 0 is the least significant bit of the digital input pin receiving the ladder waveform, and bits n-2 are the most significant bits of the digital input pin receiving the ladder waveform, where n is the number of bits in the bipolar DAC. That is, during the positive and negative polarity INL tests of the bipolar DAC, the most significant digital input pin is controlled to maintain a low input level during the positive polarity test and a high input level during the negative polarity test. The remaining digital input pins are still configured according to the normal digital code value taking logic. Typically, the digital input pin vector state should be 0 / 1, i.e., low / high level. The logic control timing is based on the technical manual. It should be noted that in this embodiment, the most significant digital input pin still needs to be connected to hardware resources because if it is not connected, the analog output result may be incorrect. Furthermore, the state of the most significant digital input pin still needs to be assessed during other parameter tests.

[0053] In a stepped wave, a step can be repeated once or N times, with the number of repetitions equal to the step width. Generally, the more repetitions, the more accurate the analog output value corresponding to that step. However, the vector storage depth must also be considered; theoretically, a step should not be repeated more than 20 times.

[0054] In addition, this embodiment requires other general configurations, such as power-on sequence, input high and low levels, clock rate, and conversion mode. This step is a general test step, which can be programmed according to the datasheet of the device under test. The programming language is the language used by the software accompanying the automatic test machine, generally C++ or OTPL. In the positive and negative polarity INL test process in this embodiment, the synchronous acquisition frequency in the positive and negative polarity INL test is controlled by the logic input pin of ATE to be no less than the conversion frequency of each step in the digital input stepped wave. This ensures that the conversion result of each digital code value corresponding to the input stepped wave can be acquired accordingly. The number of sampling points of the positive and negative polarity analog output sampling results is equal to the product of the number of digital code values ​​and the number of repetitions of each digital code value.

[0055] It should be noted that this embodiment does not restrict the order of the positive and negative INL tests for the bipolar DAC.

[0056] Step S3: Obtain the measured INL value based on the synchronous acquisition results of the positive and negative polarity INL tests; specifically,

[0057] Step S31: Calculate the average voltage of N analog output sampling points corresponding to each digital code value in the synchronous acquisition results of the INL test for positive and negative polarities respectively, sort the average voltage values ​​according to the sampling order, and obtain the sampling array data_num corresponding to positive and negative polarities respectively;

[0058] Step S32: Input the sampling arrays data_num corresponding to the positive and negative polarities into the INL algorithm of the DAC respectively to obtain the static parameters INL corresponding to the positive and negative polarities;

[0059] When the sampling array corresponding to positive or negative polarity is input into the INL algorithm of the DAC, the following is executed:

[0060] Obtain the deviation between the difference between the next element and the previous element in the sampling array corresponding to positive or negative polarity and lsbv, and use the sum of this deviation and the INL value corresponding to the previous element as the INL value corresponding to the next element; where the INL value corresponding to the first element in the sampling array is 0.

[0061] The INL value with the largest absolute value is taken as the static parameter INL corresponding to the current polarity;

[0062] Wherein, lsbv represents the ideal change value of the analog quantity corresponding to a unit change in digital code value.

[0063] Specifically, the execution process of the INL algorithm can be described in the following form:

[0064] Step S321: INL_DATA[1] = 0, max_err = 0; Let i = 2;

[0065] Step S322: INL_DATA[i]=(data_num[i]-data_num[i-1])-lsbv+INL_DATA[i-1],

[0066] If fabs(INL_DATA[i])>fabs(max_err),

[0067] Then max_err=INL_DATA[i], i=i+1; otherwise, i=i+1;

[0068] Step S323: If i≤2 n-1 If the condition is met, proceed to step S322; otherwise, INL = max_err.

[0069] Step S33: Take the larger value of the static parameter INL corresponding to the positive and negative polarities as the measured value of INL.

[0070] Step S4: If the measured value of INL is within the INL criterion range, the static parameter INL test of the bipolar DAC under test passes; otherwise, the test fails. The INL criterion range is determined based on the technical manual of the bipolar DAC under test.

[0071] In summary, this embodiment proposes a rapid testing method for the static parameter INL in a bipolar DAC, improving upon previous testing methods. During the positive and negative INL testing of the bipolar DAC, the ATE (Automatic Test Equipment) only sends a stepped wave to the non-most significant bit digital input pin, while controlling the most significant bit digital input pin to maintain a low input level during the positive polarity test and a high input level during the negative polarity test. Then, the measured INL value is obtained by processing the synchronously acquired voltage, and the test pass / fail status is determined based on the measured INL value. This process requires no complex hardware structure and has relatively simple software programming, effectively reducing the computational load during the test and quickly obtaining test results. Using the scheme in this invention, the static parameter INL of a bipolar DAC can be tested quickly and accurately.

[0072] Those skilled in the art will understand that all or part of the processes of the methods described in the above embodiments can be implemented by a computer program instructing related hardware, and the program can be stored in a computer-readable storage medium. The computer-readable storage medium may be a disk, optical disk, read-only memory, or random access memory, etc.

[0073] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A static parameter integral non-linearity (INL) test method based on bipolar DAC, characterized in that, include: Connect the bipolar DAC under test to the automated test equipment (ATE); wherein the highest bit digital input pin of the bipolar DAC under test is connected to the ATE without an inverter. The bipolar DAC is subjected to integral nonlinearity (INL) tests for positive and negative polarities, including: the automatic test equipment (ATE) sends a digital input ladder wave to the non-most significant digital input pin of the bipolar DAC, and controls the most significant digital input pin to maintain a low input level during the positive polarity test and a high input level during the negative polarity test. At the same time, the voltage output by the analog output pin of the bipolar DAC is synchronously acquired during the integral nonlinearity (INL) test of the current polarity. The measured values ​​of integral nonlinearity (INL) are obtained based on the synchronous acquisition results of the positive and negative polarity integral nonlinearity (INL) test. If the measured value of the integral nonlinearity INL is within the range of the integral nonlinearity INL criterion, then the static parameter integral nonlinearity INL test of the bipolar DAC under test is passed; otherwise, the test is failed.

2. The static parameter integral non-linearity (INL) test method based on bipolar DAC according to claim 1, wherein, Each step in the digital input staircase uniquely corresponds to a digital code value, which monotonically increases from 0 to 2 n-1 , n is the number of bits of the bipolar DAC.

3. The static parameter integral non-linearity (INL) test method based on bipolar DAC of claim 2, wherein, When the automatic test equipment (ATE) sends a digital input ladder wave to the non-most significant digital input pin of the bipolar DAC, bit 0 is the least significant bit of the digital input pin receiving the ladder wave, and bit n-2 is the most significant bit of the digital input pin receiving the ladder wave.

4. The static parameter integral nonlinearity (INL) test method based on a bipolar DAC according to claim 3, characterized in that, Each step in the stepped wave is repeated N times.

5. The static parameter integral nonlinearity (INL) test method based on a bipolar DAC according to claim 4, characterized in that, The synchronous acquisition frequency in the integral nonlinearity (INL) test of the positive and negative polarities is controlled by the logic input pins of the automatic test equipment (ATE) to ensure that it is not lower than the conversion frequency of each step in the digital input stepped wave.

6. The static parameter integral nonlinearity (INL) test method based on a bipolar DAC according to any one of claims 3-5, characterized in that, The voltages output from the analog output pins of the bipolar DAC during the integral nonlinearity (INL) test of positive and negative polarities are synchronously acquired using the AWGD pins of the ATE (Automatic Test Equipment).

7. The static parameter integral nonlinearity (INL) test method based on a bipolar DAC according to any one of claims 3-5, characterized in that, For the synchronous acquisition of integral nonlinearity (INL) tests with positive and negative polarities, the number of sampling points is no less than the product of the number of digital code values ​​and the number of repetitions of each digital code value.

8. The static parameter integral nonlinearity (INL) test method based on a bipolar DAC according to claim 7, characterized in that, The process of obtaining the measured value of integral nonlinearity (INL) based on the synchronous acquisition results of the positive and negative polarity INL test includes: The average voltage of N analog output sampling points corresponding to each digital code value in the synchronous acquisition results of the integral nonlinearity (INL) test with positive and negative polarities is calculated in turn. The average voltage values ​​are sorted according to the sampling order to obtain the sampling arrays corresponding to the positive and negative polarities respectively. The sampling arrays corresponding to positive and negative polarities are respectively input into the integral nonlinearity INL algorithm of the DAC to obtain the static parameter integral nonlinearity INL corresponding to positive and negative polarities; The larger value in the static parameter integral nonlinearity INL corresponding to positive and negative polarities is taken as the measured value of the integral nonlinearity INL.

9. The static parameter integral nonlinearity (INL) test method based on a bipolar DAC according to claim 8, characterized in that, When the sampling array corresponding to positive or negative polarity is input into the integral nonlinear INL algorithm of the DAC, the following is executed: Obtain the deviation between the difference between the next element and the previous element in the sampling array corresponding to positive or negative polarity and lsbv, and use the sum of this deviation and the integral nonlinearity INL value corresponding to the previous element as the integral nonlinearity INL value corresponding to the next element; wherein, the integral nonlinearity INL value corresponding to the first element in the sampling array is 0. The integral nonlinearity INL with the largest absolute value is taken as the static parameter integral nonlinearity INL corresponding to the current polarity; Wherein, lsbv represents the ideal change value of the analog quantity corresponding to a unit change in digital code value.

10. The static parameter integral nonlinearity (INL) test method based on a bipolar DAC according to claim 1, characterized in that, After connecting the bipolar DAC under test to the automated test equipment (ATE), the ATE first performs an output voltage range test on the analog output pins of the bipolar DAC under test. If the output voltage range test passes, then perform integral nonlinearity (INL) tests on the bipolar DAC for both positive and negative polarities; if the output voltage range test fails, then the static parameter integral nonlinearity (INL) test fails.

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