Design method of multi-level precision adjustable floating point approximate divider based on piecewise approximation
By designing a multi-level precision adjustable floating-point approximation divider through piecewise approximation, and utilizing Taylor expansion and piecewise approximation algorithms combined with error compensation, the high resource consumption and poor flexibility of existing dividers are solved, realizing a low-power, high-performance divider design suitable for resource-constrained systems and image processing tasks.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ZHEJIANG UNIV
- Filing Date
- 2023-11-30
- Publication Date
- 2026-06-09
AI Technical Summary
Existing approximate divider designs suffer from high resource consumption, large latency, poor flexibility, and unadjustable precision, making it difficult to achieve high-performance and energy-efficient division operations in resource-constrained systems.
A multi-level precision adjustable floating-point approximate divider based on piecewise approximation is designed. Approximate division is achieved through Taylor expansion and piecewise approximation algorithm. Combined with error compensation and multi-level structure, the calculation process is simplified by reciprocal multiplication, and the approximation level is dynamically adjusted at runtime through compressed tree structure.
A low-power, high-performance divider design was achieved, which can flexibly adjust the accuracy in resource-constrained systems, optimize area, delay and power consumption, and perform excellently in image processing tasks.
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Figure CN117744544B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of divider circuit design, and more particularly to a multi-stage precision adjustable floating-point approximation divider design based on piecewise approximation. The invention considers the use of approximate calculation methods for the design and optimization of low-power, high-performance divider circuits. Background Technology
[0002] The divider is one of the four fundamental arithmetic operations, exhibiting the highest latency and energy consumption compared to the others. Due to the ubiquity of division, it cannot be completely avoided in many resource-constrained systems and applications. This necessitates that dividers achieve both high performance and high energy efficiency, a challenging task that has consistently garnered attention from academia and industry. Recently, with the increasing prevalence of human perception-related tasks (such as audio / image processing, machine learning, etc.), it has become apparent that perfectly accurate divider results are not always necessary. Therefore, researchers have begun exploring approximate designs for dividers to achieve sufficient, rather than overly precise, computational accuracy.
[0003] However, existing approximate divider designs still have shortcomings:
[0004] 1) Current work often uses approximate subtractors to replace the subtractor array in the exact divider, or converts the division operation into a multiplication operation based on the reciprocal principle. However, both the subtractor array and the multiplier still have large resource consumption, resulting in high latency and power consumption.
[0005] 2) Some tasks use logarithmic operations to approximate division operations in order to achieve lower resource requirements, but this comes at the cost of sacrificing the accuracy of division calculations, which can lead to larger errors in the calculation results;
[0006] 3) Most existing approximate divider designs either use fixed-point arithmetic or cannot adjust accuracy due to the use of circuits such as LUTs, resulting in poor flexibility and difficulty in meeting the functional requirements of adjustable accuracy during operation.
[0007] To address the aforementioned issues and ensure the design efficiency and superior performance of the approximate divider circuit, a multi-stage precision adjustable floating-point approximate divider design based on piecewise approximation is proposed. Summary of the Invention
[0008] The purpose of this invention is to address the shortcomings of existing technologies by proposing a design method for a multi-level precision adjustable floating-point approximation divider based on piecewise approximation. By approximating the 1 / y function piecewise through shift and addition operations, a division approximation without a multiplier can be achieved based on the reciprocal principle, resulting in a hardware approximation divider with better performance and lower power consumption.
[0009] The objective of this invention is achieved through the following technical solution:
[0010] A design method for a multi-level precision adjustable floating-point approximation divider based on piecewise approximation, the method comprising:
[0011] 1) Approximate division: Approximate division is achieved by using Taylor expansion for approximate substitution and employing a piecewise approximation algorithm.
[0012] 2) Error compensation: For approximation levels above L4, a constant term is introduced to approximate the division result, thereby improving the accuracy of the divider;
[0013] 3) Hardware implementation: A multi-level structure is used to implement approximate calculations, and a tree structure is used to support dynamic adjustment of the approximation level at runtime.
[0014] Furthermore, in approximate division, division is equivalent to reciprocal multiplication, and Taylor expansion and piecewise approximation are used to approximate division into simple shift and addition operations, thereby simplifying the hardware calculation process of division.
[0015] Furthermore, approximate division specifically includes:
[0016] According to the IEEE 754 standard, floating-point numbers can be represented as:
[0017]
[0018] where sign x , x, E x F represents floating-point number x The sign, mantissa, and exponent of the two floating-point numbers F, where x∈[1,2); x With F y Division between them includes:
[0019]
[0020] Considering that the mantissa division x / y consumes more resources and introduces greater delay compared to the sign and exponent calculations, this invention aims to achieve approximate calculation in the mantissa division part to reduce energy consumption.
[0021] To reduce the computational complexity of x / y, the following variation is proposed:
[0022] x / y = (1 / y) × (xy) + 1
[0023] In this case, 1 / y will be approximated based on the value of y. At this point, the above formula is essentially a linear planar interpolation fit of the x / y surface.
[0024] The process of approximating 1 / y includes:
[0025] For any y, we can construct an interval [y1, y2) such that y∈[y1, y2), where y1 and y2 are defined as follows:
[0026]
[0027]
[0028] In the formula, f1, f2∈[0,1), n represents the approximate level, and t is the parameter determined according to y;
[0029] Calculate the mean of 1 / y over the interval [y1, y2), denoted as .
[0030]
[0031] To further simplify the above equation, we perform a Taylor expansion of ln(1+f):
[0032]
[0033] Substitution The expression then has:
[0034]
[0035] Further simplification is considered to achieve hardware friendliness as much as possible while preserving first-order characteristics. This involves using subsequent terms of the first two terms in the above equation. Approximate substitution, the final approximate result is denoted as
[0036]
[0037] The approximate division result after substituting this approximation into the original transformed form is denoted as Then we have:
[0038]
[0039] Furthermore, when the approximation level exceeds L4, the native error of the divider tends to be constant. Therefore, the constant error value of the binary approximation is subtracted as a compensation constant term in the calculation to make the error of the approximate division result as small as possible.
[0040] Furthermore, error compensation specifically includes:
[0041] The accuracy of approximate division can be improved by... The difference is used to characterize and define The average error at each approximate level n is Then we have:
[0042]
[0043] An error compensation method is proposed, which involves adding a constant term k to the approximate result when n≥4. ec，4 Specifically, it is represented by the following formula:
[0044]
[0045] Furthermore, in the hardware implementation, each approximation level calculates a partial sum, and the final approximate division result is obtained by adding the partial sums of each level.
[0046] Furthermore, the basic architecture of the divider circuit is a multi-layer structure, where the first level is the primary division approximation, and the subsequent levels are iteration error correction levels. When a certain approximation level n is selected, the result is obtained by the circuits of levels |~n.
[0047] Furthermore, in the divider, for the mantissa division circuit, two initial subtractors first calculate xy and yx, and the difference is used to obtain the result, along with the mantissa and control bits, which is then input into a multi-level calculation structure; the first level is the primary approximation unit, denoted as... The subsequent levels serve as error correction levels, iteratively optimizing the approximation error, denoted as... The final approximate result can be expressed by the following formula:
[0048]
[0049] Based on the principle of approximate division, and The results are obtained by calculating using the following two formulas respectively:
[0050]
[0051] In the formula, floor(t / 2) is the floor function of t / 2.
[0052] A compression tree architecture based on a 3-2 compressor (e.g.) is proposed. Figure 4 It allows users to select the required level during runtime configuration, enabling dynamic adjustment of the approximation level and thus providing a better balance between latency and accuracy.
[0053] According to the calculation formula Approximation levels L1 to 4 produce 3, |, 2, and 3 parts and terms, respectively;
[0054] At the first level of the compressed tree, three 3-2 compressors are used to compress every three parts, resulting in six new parts and items;
[0055] At the second level of the compressed tree, two 3-2 compressors are used to compress every 3 parts and sums, resulting in 4 new parts and sums.
[0056] At the third level of the compressed tree, a 3-2 compressor is used to compress the first three parts and items, which together with the fourth part and item from the previous level result in three new parts and items.
[0057] At the fourth level of the compressed tree, a 3-2 compressor is used to compress the remaining 3 parts and sums, resulting in 2 new parts and sums.
[0058] Due to the nature of the tree structure, the sum of the first two new parts generated at each level of the compressed tree precisely represents the accumulated result of the corresponding approximate level. Based on this property, the sum of the first two new parts at each level is passed through a multiplexer (…). Figure 4 The multiplexer (Mux) connects to the final adder, enabling dynamically adjustable approximation levels at runtime. When selecting a smaller approximation level, the multiplexer directly retrieves the result from the previous compressed tree level, thereby reducing computational latency.
[0059] k in the error compensation section ec,4 As one of the three parts of the L4 level, it is added to the division approximation result in the same form as PS. The above-mentioned compressed tree design ensures that this error compensation term does not lead to a longer critical path.
[0060] The beneficial effects of this invention are as follows: It provides a design method for a multi-level precision adjustable floating-point approximate divider based on piecewise approximation. Through mathematical techniques, it achieves hardware-friendly approximate division operations, and utilizes a compressed tree structure to dynamically adjust the precision during runtime, better meeting the application needs of existing resource-constrained hardware. The divider hardware implemented using this design optimization method shows significant improvements in area, delay, and power consumption compared to traditional precision divider circuits. Compared to the most advanced existing approximate division techniques, the divider hardware implemented using this design optimization method achieves a more favorable balance between precision and resource efficiency. Attached Figure Description
[0061] Figure 1 This is a block diagram illustrating the implementation structure of the present invention;
[0062] Figure 2 This is a schematic diagram of the piecewise approximation and error compensation principle of the present invention. The horizontal and vertical axes in the diagram represent the independent variable and the function value, respectively.
[0063] Figure 3 This is a graph showing the relationship between the error and the approximation level of this invention;
[0064] Figure 4 This is a block diagram of the compressed tree structure proposed in this invention;
[0065] Figure 5 This is a comparison chart of the circuit specifications of the approximate divider of this invention with those of other technical circuits.
[0066] Figure 6 This is a comparison diagram of the image task metrics of this invention with other technical circuits. Detailed Implementation
[0067] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.
[0068] The specific implementation of this invention can be divided into the following parts:
[0069] 1) Approximate division:
[0070] According to the IEEE 754 standard, floating-point numbers can be represented as:
[0071]
[0072] where sign x , x, E x F represents floating-point number x The sign, mantissa, and exponent of the two floating-point numbers F, where x ∈ [1, 2). x With F y Division between them includes:
[0073]
[0074] Considering that the mantissa division x / y consumes more resources and introduces greater latency compared to the other two parts, the present invention mainly focuses on optimizing the energy consumption of this part in the subsequent parts.
[0075] To reduce the computational complexity of x / y, this invention proposes the following variation:
[0076] x / y = (1 / y) × (xy) + 1
[0077] Here, 1 / y will be approximated based on the value of y. In this case, the above formula is essentially a linear planar interpolation fit of the x / y surface.
[0078] The following describes the process of approximating 1 / y. For any y, an interval [y1, y2) can be constructed such that y∈[y1, y2), where y1 and y2 are defined as follows (f1, f2∈[0, 1), n represents the approximation level, and t is a parameter determined based on y):
[0079]
[0080]
[0081] Calculate the mean of 1 / y over the interval [y1, y2), denoted as .
[0082]
[0083] To further simplify the above equation, we perform a Taylor expansion of ln(1+f):
[0084]
[0085] Substitution The expression then has:
[0086]
[0087] Further simplification is needed to achieve hardware friendliness as much as possible while preserving first-order features, except for the first two terms in the above equation (1 and Subsequent items of ) Approximate substitution, the final approximate result is denoted as
[0088]
[0089] The approximate division result after substituting this approximation into the original transformed form is denoted as Then we have:
[0090]
[0091] Figure 2 (a)-(e) demonstrate 1 / y, The function graphs for approximation levels n = 1 to 5 show that the higher the approximation level, the more accurate the approximation. The aforementioned mathematical formulas lay the foundation for the energy-efficient and computationally simple approximate division method proposed in this invention.
[0092] 2) Error compensation:
[0093] The accuracy of approximate division can be improved by... The difference is used to characterize and define The average error at each approximate level n is Then we have:
[0094]
[0095] draw The curve is as follows Figure 3 As shown, when the approximation level n exceeds 4, the error no longer decreases with increasing approximation level. This necessitates error compensation. This invention employs a simple yet effective error compensation method: adding a constant term k to the approximation result when n≥4. ec，4 Specifically, it is represented by the following formula:
[0096]
[0097] from Figure 2 The comparison of (d) and (f) and Figure 3 The significant effectiveness of this error compensation method can be seen from the results.
[0098] 3) Hardware implementation:
[0099] The floating-point divider proposed in this invention has similar sign and exponentiation operations to the standard divider, which are relatively simple and will not be described in detail here. For the mantissa division circuit, two initial subtractors first calculate xy and yx. The difference, along with the mantissa and control bits, is input into a multi-level calculation structure. The first level is a primary approximation unit, denoted as... The subsequent levels serve as error correction levels, iteratively optimizing the approximation error, denoted as... The final approximate result can be expressed by the following formula:
[0100]
[0101] Based on the principle of approximate division, and The results are obtained by calculating using the following two formulas respectively:
[0102]
[0103] Each of the above-mentioned level calculations produces a partial summation (PS), which is then summed to obtain an approximate division result. To improve the efficiency of summation and reduce the latency of the critical path, this invention proposes a compressed tree architecture based on a 3-2 compressor (e.g., Figure 4 It allows users to select the required level during runtime configuration, enabling dynamic adjustment of the approximation level and thus providing a better balance between latency and accuracy.
[0104] Specifically, according to the above calculation formula, the L1 to 4 approximation levels generate 3, |, 2, and 3 parts and terms, respectively;
[0105] At the first level of the compressed tree, three 3-2 compressors are used to compress every three parts, resulting in six new parts and items;
[0106] At the second level of the compressed tree, two 3-2 compressors are used to compress every 3 parts and sums, resulting in 4 new parts and sums.
[0107] At the third level of the compressed tree, a 3-2 compressor is used to compress the first three parts and items, which together with the fourth part and item from the previous level result in three new parts and items.
[0108] At the fourth level of the compressed tree, a 3-2 compressor is used to compress the remaining 3 parts and sums, resulting in 2 new parts and sums.
[0109] Due to the nature of the tree structure, the sum of the first two new parts generated at each level of the compressed tree precisely represents the accumulated result of the corresponding approximate level. Based on this property, the sum of the first two new parts at each level is passed through a multiplexer (…). Figure 4 The multiplexer (Mux) connects to the final adder, enabling dynamically adjustable approximation levels at runtime. When selecting a smaller approximation level, the multiplexer directly retrieves the result from the previous compressed tree level, thereby reducing computational latency.
[0110] k in the error compensation section ec,4 As one of the three parts of the L4 level, it is added to the division approximation result in the same form as PS. The above-mentioned compressed tree design ensures that this error compensation term does not lead to a longer critical path.
[0111] The functions and effects of this invention are further illustrated and demonstrated through the following simulation experiments:
[0112] 1. Simulation conditions
[0113] Our experimental architecture comprises two parts: simulation and verification. We built a divider accuracy simulation tool using Python, then completed the RTL implementation of the optimized approximate divider, and used Design Compiler on UMC's 40nm library for functional verification and timing analysis. Finally, we applied the approximate divider to two image processing tasks: JPEG image compression and K-means color quantization, to examine its performance in practical applications.
[0114] To better illustrate the performance of the approximate divider proposed in this invention, we also tested some of the most advanced approximate dividers, including TruncApp, FaNZeD, LEAD, and QIAD. TruncApp is derived from non-patent literature (VAHDAT S, KAMAL M, AFZALI-KUSHA A, et al. TruncApp: A truncation-based approximate divider for energy efficient DSP applications [C / OL] / / Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.2017:1635-1638.DOI:10.23919 / DATE.2017.7927254.), and FaNZeD is derived from non-patent literature (SAADAT H, JAVAID H, PARAMESWARAN S. Approximate Integer and Floating-Point Dividers with Near-ZeroError Bias [C / OL] / / Proceedings of the 56th Annual Design Automation Conference 2019. Las Vegas NV). USA:ACM, 2019:1-6 [2023-06-29]. https: / / dl.acm.org / doi / 10.1145 / 3316781.3317773.DOI:10.1145 / 3316781.3317773.), LEAD is from non-patent literature (RATNAPARKHIO G, RAO M.LEAD: Logarithmic Exponent Approximate Divider For Image Quantization Application [C / OL] / / Proceedings of the Great Lakes Symposium on VLSI 2022. Irvine CA USA:ACM, 2022:437-442 [2023-06-29]. https: / / dl.acm.org / doi / 10.1145 / 3526241.3530323.DOI:10.1145 / 3526241.3530323.), QIAD is from non-patent literature (LIUH, WANG MJ, LIU M).QIAD:A quadratic interpolation approximate divider[J / OL].IEICE Electronics Express,2023,20(11):20230167-20230167.DOI:10.1587 / elex.20.20230167.).
[0115] 2. Simulation Results
[0116] 1) Accuracy Testing and Comparison of Approximate Dividers
[0117] We uniformly sampled 10,000 data points within the interval [1,2) as the divisor and dividend of the divider to verify the accuracy of the proposed approximate divider on different error measures. Three error measures were used in the experiment: Mean Absolute Error (MAE), Mean Relative Error Distance (RMSE), and Root Mean Square Error (RMSE). The experiment covered the four approximation levels L1 to L4 of the proposed approximate divider, and the results are listed in the table below along with those of other dividers used for comparison.
[0118] L1 L2 L3 L4 FaNZeD TruncApp LEAD QIAD MAE 0.028 0.015 0.011 0.005 0.03 0.085 0.021 0.006 MRED 0.026 0.014 0.011 0.005 0.028 0.083 0.02 0.005 RMSE 0.045 0.022 0.014 0.007 0.039 0.095 0.028 0.006
[0119] Clearly, the accuracy of the proposed approximate divider improves with increasing approximation level. For most metrics, even with L1 approximation, the proposed approximate divider outperforms FaNZeD and TruncApp. It also outperforms LEAD starting from L2 level. QIAD achieves high accuracy at the cost of very large area / power consumption and high latency (see Experiment 2 for details). The proposed approximate divider achieves similar accuracy at L4 level, but with a much smaller area / power consumption and lower latency.
[0120] 2) Hardware implementation and comparison of approximate dividers
[0121] To evaluate the hardware resource utilization and performance of the proposed approximate divider, we implemented the divider design as a 32-bit floating-point divider using a UMC 40nm process and reported the results from the Design Compiler. The table below presents the area, delay, and power consumption results of the approximate divider using the proposed design method, along with the normalized area-delay-product (ADP). An industrial-grade, precise 32-bit floating-point divider implementation from the Synopsys DesignWare library is used as a normalized reference standard for comparison.
[0122] Area (μm2) / Ratio Delay (ns) / Ratio Power consumption (mW) / ratio Normalized ADP Precision divider 15143 / 1× 9.54 / 1× 20.15 / 1× 1× Precise multiplier 7574 / 0.50× 4.63 / 0.48× 6.62 / 0.32× 0.242× L1 1978 / 0.13× 2.11 / 0.22× 1.23 / 0.06× 0.028× L2 2756 / 0.18× 2.48 / 0.25× 1.89 / 0.09× 0.047× L3 3275 / 0.21× 2.93 / 0.30× 2.41 / 0.11× 0.066× L4 4590 / 0.30× 3.43 / 0.35× 3.58 / 0.17× 0.108× FaNZeD 1660 / 0.11× 1.47 / 0.15× 0.93 / 0.05× 0.017× TruncApp 5643 / 0.37× 5.48 / 0.57× 4.61 / 0.22× 0.214× LEAD 7814 / 0.51× 7.31 / 0.77× 3.82 / 0.19× 0.395× QIAD 13594 / 0.89× 9.89 / 1.04× 11.82 / 0.59× 0.930×
[0123] The results show that, even at the most resource-intensive approximation level L4, the proposed approximate divider still has a 70% smaller area and a 65% faster operating speed than the exact divider, at the cost of the small error observed in Experiment 1. In fact, the proposed divider even outperforms the exact multiplier of the same number of bits in terms of resource consumption and performance at the L4 level.
[0124] Compared to other approximate dividers, the proposed approximate divider also shows significant advantages in terms of area, delay, and power. For example, the L4-level implementation uses only one-third of the area and is three times faster than QIAD while providing similar accuracy. FaNZeD is the only approximate divider that occupies less area than the proposed divider, but its error is approximately 5-6 times that of the L4-level divider. LEAD offers the best balance in terms of area, delay, power, and accuracy. However, compared to the L4-level of the proposed approximate divider, LEAD is 70% larger, 120% slower, and produces nearly four times the error.
[0125] It is worth noting that the proposed divider also shows a significant advantage in ADP index, improving it by more than 89% compared to the accurate divider. Figure 5 A comparison of ADP and MAE further illustrates the superior performance of the proposed divider. Data closer to the origin in the figure indicates a better trade-off between accuracy and resource utilization. The proposed divider achieves considerable accuracy gains with minimal resource overhead. Compared to LEAD, the proposed divider's L4 implementation shows a 72.41% improvement over ADP. Furthermore, the proposed divider uses only 11.61% of the ADP resources compared to QIAD, achieving near-lossless accuracy.
[0126] 3) Image processing task testing and comparison
[0127] We applied the aforementioned approximate divider to two image processing tasks: JPEG image compression and K-means color quantization. We tested it on the Caltech 101 image dataset, which includes 9144 images across 102 categories. To measure the impact of the approximation on image quality, we defined PSNR... 退化 The difference between the PSNR of the image of the exact division result and the PSNR of the image of the approximate division result is:
[0128] PSNR 退化 =PSNR 精确除法 -PSNR 近似除法
[0129] PSNR refers to the Peak Signal-to-Noise Ratio (PSNR) of the processed image relative to the source image. A lower PSNR results in a lower signal-to-noise ratio. 退化 This indicates that the image has better quality.
[0130] Figure 6 This demonstrates the PSNR of images processed on the Caltech101 image dataset. 退化 Box plots show that image quality improves with increasing approximation level for the proposed approximation divider. At level L2, the proposed approximation divider already surpasses other approximation dividers except QIAD; at level L4, the proposed approximation divider achieves only a 0.09 dB (K-means color quantization) and 0.63 dB (JPEG) PSNR improvement over the exact divider, respectively. 退化 Notably, compared to QIAD, the proposed divider's L4 level achieves better quality in both image tasks while using fewer resources and lower latency. Consistent experimental results obtained in both divider applications highlight the broad applicability and effectiveness of this invention across various division scenarios.
[0131] The above embodiments are used to explain and illustrate the present invention, but not to limit the present invention. Any modifications and changes made to the present invention within the spirit and scope of the claims shall fall within the protection scope of the present invention.
Claims
1. A design method for a multi-level precision adjustable floating-point approximation divider based on piecewise approximation, characterized in that, The method includes: 1) Approximate division: This method uses Taylor expansion for approximate substitution and employs a piecewise approximation algorithm to perform approximate division operations. Specifically, approximate division includes: According to the IEEE 754 standard, floating-point numbers are represented as: ， where sign x , x, E x F represents floating-point number x The sign, mantissa, and exponent of the two floating-point numbers F, where x∈[1,2); x and F y Division between them includes: ， To reduce the computational complexity of x / y, the following variation is proposed: ， In this case, 1 / y will be approximated based on the value of y. At this point, the above formula is essentially a linear planar interpolation fit of the x / y surface. The process of approximating 1 / y includes: In the piecewise approximation algorithm, for any y∈[1,2), an interval [y1,y2) can be constructed such that y∈[y1,y2), where y1 and y2 are defined as follows: ， ， In the formula, f1, f2 ∈ [0, 1), n represents the approximate level, and t is the parameter determined according to y; Calculate the mean of 1 / y over the interval [y1, y2), denoted as . : ， To further simplify the above equation, we perform a Taylor expansion of ln(1+f): ， Substitution The expression then has: ， Further simplification is considered to achieve hardware friendliness as much as possible while preserving first-order characteristics. This involves using subsequent terms of the first two terms in the above equation. Approximate substitution, the final approximate result is denoted as : ， The approximate division result after substituting this approximation into the original transformed form is denoted as Then we have: ， 2) Error compensation: For approximation levels above L4, a constant term is introduced to approximate the division result, thereby improving the accuracy of the divider; 3) Hardware implementation: A multi-level structure is used to implement approximate calculations, and a tree structure is used to support dynamic adjustment of the approximation level at runtime. In the hardware implementation, when accumulating the partial sums of each level, a compressed tree architecture based on a 3-2 compressor is used to enable runtime configuration to select the required level, so that the approximation level can be dynamically adjusted, thereby allowing users to make a better balance between latency and accuracy. According to the calculation formula The L1 to L4 approximation levels generate 3, 1, 2, and 3 parts and terms, respectively. At the first level of the compressed tree, three 3-2 compressors are used to compress every three parts, resulting in six new parts and items; At the second level of the compressed tree, two 3-2 compressors are used to compress every 3 parts and sums, resulting in 4 new parts and sums. At the third level of the compressed tree, a 3-2 compressor is used to compress the first three parts and items, which together with the fourth part and item from the previous level result in three new parts and items. At the fourth level of the compressed tree, a 3-2 compressor is used to compress the remaining 3 parts and items, resulting in 2 new parts and items; The sum of the first two new parts generated at each level of the compressed tree precisely represents the cumulative result of the corresponding approximation level. Based on this characteristic, the sum of the first two new parts at each level is connected to the final adder through a multiplexer, thereby achieving the effect of dynamically adjusting the approximation level at runtime. When selecting a smaller approximation level, the multiplexer directly obtains the result from the previous level of the compressed tree, thereby reducing the latency required for computation.
2. The design method for a multi-level precision adjustable floating-point approximation divider based on piecewise approximation according to claim 1, characterized in that, In approximate division, division is equivalent to reciprocal multiplication, and Taylor expansion and piecewise approximation are used to approximate division into simple shift and addition operations, thereby simplifying the hardware calculation process of division.
3. The design method for a multi-level precision adjustable floating-point approximation divider based on piecewise approximation according to claim 1, characterized in that, In error compensation, when the approximation level exceeds L4, the original error of the divider tends to be constant. Therefore, the constant error value of the binary approximation is subtracted as a compensation constant term in the calculation to make the error of the approximate division result as small as possible.
4. The design method for a multi-level precision adjustable floating-point approximation divider based on piecewise approximation according to claim 1, characterized in that, Error compensation specifically includes: The accuracy of approximate division is achieved through The difference is used to characterize and define The average error at each approximate level n is Then we have: ， An error compensation method is proposed, which involves adding a constant term k to the approximate result when n≥4. ec,4 Specifically, it is represented by the following formula: ， k in the error compensation section ec,4 As one of the three partial sums of the L4 level, it is added to the division approximation result in the same form as the partial sum.
5. The design method for a multi-level precision adjustable floating-point approximation divider based on piecewise approximation according to claim 1, characterized in that, In the hardware implementation, the basic architecture of the divider circuit is a multi-layer structure, where the first level is the primary division approximation, and the subsequent levels are iterative error correction levels. Each approximation level calculates a partial sum. When a certain approximation level n is selected, the final approximate division result is obtained by adding the results of the circuits from level 1 to level n.
6. The design method for a multi-level precision adjustable floating-point approximation divider based on piecewise approximation according to claim 1, characterized in that, In the divider, for the mantissa division circuit, two initial subtractors first calculate xy and yx, and the difference is used to obtain the result, along with the mantissa and control bits, which is then input into a multi-level calculation structure; the first level is the primary approximation unit, denoted as . The subsequent levels serve as error correction levels, iteratively optimizing the approximation error, denoted as... The final approximate result is expressed by the following formula: ， Based on the principle of approximate division, and The results are obtained by calculating using the following two formulas respectively: ， In the formula, floor(t / 2) is the floor function of t / 2.