A UART controller and data transmission validity detection method

Abstract

The present invention discloses a UART controller and a method for detecting the validity of data transmission. The UART controller includes a receiver for receiving external data; a transmitter for sending data to the outside; and a UART data transceiver control unit for controlling the receiver and the transmitter to transmit and receive data and to perform interrupt control in a timely manner. The present invention provides a UART controller and a method for detecting the validity of data transmission to solve the problem that, during the data transmission process of a UART serial port, there is no parity check bit or there is an even number of bit data transmission errors during the transmission of a frame of data, resulting in an inability to detect data transmission errors. The present invention solves the problem that, when the transmitted data is too large or the chip communication distance is too long, data errors accumulate, resulting in an inability to detect and interrupt data transmission in a timely manner. The present invention solves the problem that, during the data transmission process of a UART serial port, data transmission errors due to poor anti-interference ability lead to an inability to interrupt data transmission in a timely manner.

Description

Technical Field

[0001] The invention relates to a UART controller and a method for detecting the validity of data transmission. Background Art

[0002] Currently, in UART serial communication, some chips primarily use parity bits to verify the correctness of output transmissions during inter-chip data communication. UART serial communication data can only be sent and received one bit at a time, and within each frame of data transmission, the stop bit is primarily used to indicate the completion of a frame. For example, when using even parity to verify data transmission, the parity bit counts the number of "1" bits in a frame. If the number of "1" bits is even, the parity bit is output as a success, and data transmission can continue. Odd parity, similar to even parity, counts the number of "0" bits in a frame of data.

[0003] However, in UART serial communication, ensuring data transmission validity through parity bits cannot detect all data transmission errors. For example, if two, four, or even numbers of bits in a frame are incorrect, the parity check result will be incorrect. This is because the parity bit only counts the number of "1"s or "0"s in a frame. Therefore, if an even number of bits are incorrect, the parity bit cannot detect whether the data has been transmitted incorrectly. Furthermore, the parity bit can only be used for detection, not for correcting the data frame. Furthermore, many chip-to-chip communication systems do not incorporate parity checks to verify data transmission accuracy. Furthermore, UART serial communication, due to its full-duplex, asynchronous transmission mode, has relatively poor interference immunity, which can easily lead to data transmission errors. Furthermore, when chips communicate via serial ports, if the data size is too large or the distance between the two chips is too long, errors can accumulate, significantly affecting the accuracy of data transmission. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to overcome the deficiencies of the prior art and provide a UART controller and a method for detecting the validity of data transmission, so as to solve the problem that, during the data transmission process of the UART serial port, there is no parity bit or there is an even number of bit data transmission errors during the transmission of a frame of data, resulting in the inability to detect data transmission errors. The problem that, when the transmitted data is too large or the chip communication distance is too long, there are accumulated errors in the data, resulting in the inability to detect and interrupt data transmission in a timely manner is solved. The problem that, during the data transmission process of the UART serial port, data transmission errors are caused by poor anti-interference ability and cannot be interrupted in a timely manner is solved.

[0005] In order to solve the above technical problems, the technical solution of the present invention is:

[0006] One aspect of the present invention provides a UART controller, comprising:

[0007] A receiver, configured to receive external data;

[0008] A transmitter, configured to send data to the outside;

[0009] A UART data transceiver control unit, which is used to control the receiver and transmitter to send and receive data and perform interrupt control in a timely manner;

[0010] A baud rate generator, which is used to control the rate at which data is sent and received;

[0011] The data comparison unit is used to collect the data currently received and sent by the receiver and the transmitter according to the data collection instruction issued by the UART data transceiver control unit, and compare each frame of data between the receiver and the transmitter.

[0012] Furthermore, the UART data transceiver control unit includes a data receiving control unit, a data sending control unit and an interrupt control unit;

[0013] The data receiving control unit is used to send a data receiving instruction to the receiver;

[0014] The data sending control unit is used to send a data sending instruction to the transmitter;

[0015] The interrupt control unit is used to send interrupt control instructions to the receiver and the transmitter.

[0016] Further, the baud rate generator includes a data receiving baud rate control unit and a data sending baud rate control unit;

[0017] The data receiving baud rate control unit is used to control the rate at which the receiver receives data;

[0018] The data transmission baud rate control unit is used to control the rate at which the transmitter sends data.

[0019] Furthermore, the data comparison unit includes a data FIFO receiving buffer register, a data FIFO sending buffer register and two cascaded four-bit value comparators.

[0020] Another aspect of the present invention provides a method for detecting the validity of data transmission of a UART controller, comprising:

[0021] Step S1: The UART data transceiver control unit sends a data receiving instruction, and the receiver receives the data transmitted from the external chip;

[0022] Step S2: The UART data transceiver control unit issues a data comparison instruction, collects the frame data received by the receiver, and puts the data into the data FIFO receive buffer register in the data comparison unit;

[0023] Step S3: The UART data transceiver control unit issues a data transmission instruction, and the transmitter sends the transmitted data outward;

[0024] Step S4: The UART data transceiver control unit issues a data comparison instruction, collects the frame data sent by the transmitter, and puts the data into the data FIFO transmit buffer register in the data comparison unit;

[0025] Step S5: Use the four-bit numerical comparator of the data comparison unit to compare the received and transmitted data, and promptly feed back the comparison result to the UART data transceiver control unit. The UART data transceiver control unit makes a data transmission or interruption operation, and controls the data comparison unit to reset and clear the data FIFO receive buffer register and the data FIFO transmit buffer register.

[0026] Furthermore, the step S1 specifically includes the following steps:

[0027] After receiving the external data receiving instruction, the UART data transceiver control unit sends the data receiving instruction to the receiver, receives the communication data using the Rx receiving data line, and after receiving a frame of data, the receiver sends a frame data reception completion instruction to the UART data transceiver control unit.

[0028] Furthermore, the judgment condition for completing the reception of a frame of data is that the stop bit of the frame data received by the receiver is started.

[0029] Furthermore, step S3 specifically includes the following steps:

[0030] The UART data transceiver control unit sends a data sending instruction to the transmitter. When the transmitter receives the instruction from the UART data transceiver control unit to send frame data, the transmitter sends each frame of data through the Tx data line. After sending a frame of data, the transmitter sends a frame data sending completion instruction to the UART data transceiver control unit.

[0031] Furthermore, the judgment condition for completing the sending of a frame of data is that the stop bit of the frame data sent by the transmitter is started.

[0032] Furthermore, in step S5, the received and transmitted data are compared using a four-bit numerical comparator of the data comparison unit, and the comparison result is promptly fed back to the UART data transceiver control unit, which specifically includes the following steps:

[0033] Comparing a frame of data received by the receiver with a frame of data sent by the transmitter using a four-bit numerical comparator of the data comparison unit;

[0034] If a frame of data received by the receiver is completely consistent with a frame of data sent by the transmitter, the data comparison unit outputs a high level, and data transmission and reception continue;

[0035] If a frame of data received by the receiver is inconsistent with a frame of data sent by the transmitter, the data comparison unit outputs a low level, and data transmission and reception are interrupted.

[0036] The above technical solution is adopted. The present invention adds a data comparison unit inside the UART controller to sample and compare the data of the transmitter and receiver, and provides timely feedback on the data transmission and reception status to the UART data transceiver control unit, thereby solving the problem that the data transmission between some chips has no parity bit or the parity bit cannot identify the data transmission error, and greatly avoids the impact of data transmission errors on communication between chips. By adding a data comparison unit inside the UART serial port controller to compare a frame of data when sending and the same frame of data after receiving, the problem that the parity bit of the UART serial port cannot detect data transmission errors during data transmission can be well avoided. The data comparison unit can sample and collect the frame data transmitted by the receiver and the transmitter according to demand and then compare them, avoiding the problem that the data collection time is lengthy during data transmission, resulting in too slow a transmission speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A functional block diagram of a UART controller of the present invention;

[0038] Figure 2 The present invention is a flow chart of a method for detecting the validity of data transmission of a UART controller. DETAILED DESCRIPTION

[0039] In order to make the contents of the present invention more clearly understood, the present invention is further described in detail below based on specific embodiments in conjunction with the accompanying drawings.

[0040] Example 1

[0041] like Figure 1As shown, this embodiment provides a UART controller, which includes: a receiver, a transmitter, a UART data transceiver control unit, a baud rate generator, and a data comparison unit. The UART controller has two external transceiver data lines, one Rx for receiving data and one Tx for sending data.

[0042] The receiver is used to receive external data, and the transmitter is used to send data to the outside.

[0043] The UART data transceiver control unit is used to control the data transmission and reception between the receiver and transmitter, and to execute interrupt control when appropriate. The UART data transceiver control unit includes a data reception control unit, a data transmission control unit, and an interrupt control unit. The data reception control unit is used to send data reception instructions to the receiver; the data transmission control unit is used to send data transmission instructions to the transmitter; and the interrupt control unit is used to send interrupt control instructions to the receiver and transmitter.

[0044] The baud rate generator controls the rate at which data is received and sent. It must be connected to a clock source. It includes a receive baud rate control unit, which controls the rate at which the receiver receives data, and a transmit baud rate control unit, which controls the rate at which the transmitter sends data.

[0045] The data comparison unit collects the data currently being sent and received by the receiver and transmitter based on data collection instructions issued by the UART data transceiver control unit, and compares each frame of data between the receiver and transmitter. The data comparison unit comprises a data FIFO receive buffer register, a data FIFO transmit buffer register, and two cascaded four-bit numerical comparators. Typically, each frame of data contains 5 to 8 bits. Depending on the number of bits transmitted per frame, existing numerical comparators typically have four-bit numerical comparators. Two four-bit numerical comparators can be cascaded to compare 5 to 8 bits of data.

[0046] Example 2

[0047] like Figure 2 As shown, this embodiment provides a method for detecting data transmission validity of a UART controller, which includes:

[0048] Step S1: The UART data transceiver control unit sends a data receiving instruction, and the receiver receives the data transmitted by the external chip (the receiving mode is frame by frame);

[0049] Step S2: The UART data transceiver control unit issues a data comparison instruction, collects the frame data received by the receiver, and puts the data into the data FIFO receive buffer register in the data comparison unit;

[0050] Step S3: The UART data transceiver control unit issues a data transmission instruction, and the transmitter sends the transmitted data outward (the transmission mode is frame by frame);

[0051] Step S4: The UART data transceiver control unit issues a data comparison instruction, collects the frame data sent by the transmitter, and puts the data into the data FIFO transmit buffer register in the data comparison unit;

[0052] Step S5: Use the four-bit numerical comparator of the data comparison unit to compare the received and transmitted data, and promptly feed back the comparison result to the UART data transceiver control unit. The UART data transceiver control unit makes a data transmission or interruption operation, and controls the data comparison unit to reset and clear the data FIFO receive buffer register and the data FIFO transmit buffer register.

[0053] Specifically, step S1 includes the following steps:

[0054] After receiving an external data receive command, the UART data transceiver control unit sends a data receive command to the receiver, which then receives the communication data via the Rx data line. After receiving a frame of data, the receiver sends a frame data reception completion command to the UART data transceiver control unit. The completion of a frame of data is determined by the presence of a stop bit in the frame data received by the receiver. Each frame of data on the UART serial port is typically 8 bits, with the last bit being the stop bit.

[0055] Specifically, step S3 includes the following steps:

[0056] The UART data transceiver control unit sends a data transmission instruction to the transmitter. When the transmitter receives the instruction from the UART data transceiver control unit to transmit frame data, it transmits each frame of data via the Tx transmit data line. After completing transmission of a frame of data, the transmitter sends a frame data transmission completion instruction to the UART data transceiver control unit. The condition for determining the completion of transmission of a frame of data is the start of the stop bit of the frame data sent by the transmitter.

[0057] Specifically, in step S5, the received and transmitted data are compared using the four-bit numerical comparator of the data comparison unit, and the comparison result is promptly fed back to the UART data transceiver control unit, which specifically includes the following steps:

[0058] Comparing a frame of data received by the receiver with a frame of data sent by the transmitter using a four-bit numerical comparator of the data comparison unit;

[0059] If a frame of data received by the receiver is completely consistent with a frame of data sent by the transmitter, the data comparison unit outputs a high level, and data transmission and reception continue;

[0060] If a frame of data received by the receiver is inconsistent with a frame of data sent by the transmitter, the data comparison unit outputs a low level, and data transmission and reception are interrupted.

[0061] Suppose the receiver receives 11010101 and the transmitter sends 11010101, the comparison results are consistent and the output is high; if the result sent by the transmitter is 11011101, which is inconsistent with the result of the receiver, the comparison result is output as low level, that is, 0, and the interrupt unit interrupts data transmission and reception.

[0062] The working principle of the present invention is as follows:

[0063] like Figure 2 As shown, after the UART data transceiver control unit inside the UART controller receives the external data receive instruction, it sends the data receive instruction to the receiver inside the UART controller, and uses the Rx receive data line of the UART controller to receive the communication data. After receiving a frame of data, the receiver sends a frame data reception completion instruction to the UART data transceiver control unit, and then the UART data transceiver control unit sends a data sending instruction to the transmitter. When the transmitter receives the instruction from the UART data transceiver control unit to send frame data, the transmitter sends each frame of data through the Tx send data line.

[0064] During each frame of data transmission, when the stop bit of the frame data in the receiver and transmitter is started, the UART data transceiver control unit starts to send a data acquisition instruction to the data comparison unit. After receiving the acquisition instruction, the data comparison unit starts to acquire the data transmitted by the data bits of each frame of the receiver and transmitter. After comparison by two cascaded four-bit value comparators, the data comparison result is sent to the UART data transceiver control unit, and the UART data transceiver control unit controls whether the data transmission and reception is interrupted according to the comparison result.

[0065] If the data comparison result is correct, data transmission and reception will continue; if it is incorrect, data transmission and reception will be interrupted.

[0066] At the same time, the UART data transceiver control unit feeds back a data comparison reset signal to the data comparison unit, which resets and clears the previous comparison data content so that frame data sampling can continue next time. The baud rate generator controls the data transmission rate according to the data transmission requirements between chips.

[0067] In order not to affect the speed of data transmission, the UART data transceiver control unit independently controls the data comparison unit to better sample and collect the data of the transmitter and receiver, and the data collection time of the receiver and transmitter should be carried out at the stop bit after the receiver completes receiving each frame of data and the stop bit after the transmitter completes sending data.

[0068] The specific embodiments described above further illustrate the technical problems, technical solutions and beneficial effects solved by the present invention. It should be understood that the above are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A UART controller, characterized in that: It includes: A receiver, configured to receive external data; A transmitter, configured to send data to the outside; A UART data transceiver control unit, which is used to control the receiver and transmitter to send and receive data and perform interrupt control in a timely manner; A baud rate generator, which is used to control the rate at which data is sent and received; A data comparison unit, configured to collect data currently being sent and received by the receiver and transmitter according to a data collection instruction issued by the UART data transceiver control unit, and compare each frame of data between the receiver and transmitter; The UART data transceiver control unit includes a data receiving control unit, a data sending control unit and an interrupt control unit; The data receiving control unit is used to send a data receiving instruction to the receiver; The data sending control unit is used to send a data sending instruction to the transmitter; The interrupt control unit is used to send interrupt control instructions to the receiver and the transmitter; The data transmission validity detection method of the UART controller comprises: Step S1: The UART data transceiver control unit sends a data receiving instruction, and the receiver receives the data transmitted from the external chip; Step S2: The UART data transceiver control unit issues a data comparison instruction, collects the frame data received by the receiver, and puts the data into the data FIFO receive buffer register in the data comparison unit; Step S3: The UART data transceiver control unit issues a data transmission instruction, and the transmitter sends the transmitted data outward; Step S4: The UART data transceiver control unit issues a data comparison instruction, collects the frame data sent by the transmitter, and puts the data into the data FIFO transmit buffer register in the data comparison unit; Step S5: using the four-bit comparator of the data comparison unit to compare the received and transmitted data, and promptly feeding back the comparison result to the UART data transceiver control unit, the UART data transceiver control unit makes a data transmission or interruption operation, and controls the data comparison unit to reset and clear the data FIFO receive buffer register and the data FIFO transmit buffer register; The step S3 specifically includes the following steps: The UART data transceiver control unit sends a data sending instruction to the transmitter. When the transmitter receives the instruction from the UART data transceiver control unit to send frame data, the transmitter sends each frame of data through the Tx data line. After sending a frame of data, the transmitter sends a frame data sending completion instruction to the UART data transceiver control unit. In step S5, the received and transmitted data are compared using a four-bit numerical comparator of the data comparison unit, and the comparison result is promptly fed back to the UART data transceiver control unit, which specifically includes the following steps: Comparing a frame of data received by the receiver with a frame of data sent by the transmitter using a four-bit numerical comparator of the data comparison unit; If a frame of data received by the receiver is completely consistent with a frame of data sent by the transmitter, the data comparison unit outputs a high level, and data transmission and reception continue; If a frame of data received by the receiver is inconsistent with a frame of data sent by the transmitter, the data comparison unit outputs a low level, and data transmission and reception are interrupted.

2. The UART controller according to claim 1, wherein: The baud rate generator includes a data receiving baud rate control unit and a data sending baud rate control unit; The data receiving baud rate control unit is used to control the rate at which the receiver receives data; The data transmission baud rate control unit is used to control the rate at which the transmitter sends data.

3. The UART controller according to claim 1, wherein: The data comparison unit includes a data FIFO receiving buffer register, a data FIFO sending buffer register and two cascaded four-bit value comparators.

4. The UART controller according to claim 1, wherein The step S1 specifically includes the following steps: After receiving the external data receiving instruction, the UART data transceiver control unit sends the data receiving instruction to the receiver, receives the communication data using the Rx receiving data line, and after receiving a frame of data, the receiver sends a frame data reception completion instruction to the UART data transceiver control unit.

5. The UART controller according to claim 4, wherein: The judgment condition for completing the reception of a frame of data is that the stop bit of the frame data received by the receiver is started.

6. The UART controller according to claim 4, wherein: The judgment condition for completing the sending of a frame of data is that the stop bit of the frame data sent by the transmitter is started.

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