LED drive pulse modulation method and circuit

Abstract

Disclosed is an LED drive pulse modulation method, comprising: dividing N-bit grayscale data into P-bit integer grayscale and R-bit fractional grayscale, wherein the clock period of the P-bit integer grayscale is a first clock period T1, and the clock period of the N-bit grayscale data is a second clock period T2, where N=P+R; dividing the display period of the N-bit grayscale data into 2 L sub-periods, each sub-period includes 2 M‑R A first clock cycle, each sub-cycle includes a high gray display area and at least one low gray display area, N = M + L; according to the optimization level K, the first grayscale value that can be allocated to the low gray display area in each sub-cycle is set, and the maximum low grayscale value corresponding to the low gray display area is obtained; when the size of the grayscale data is less than or equal to the maximum low grayscale value, the grayscale data is allocated to 2 L The present application also provides an LED drive pulse modulation circuit, which realizes the display of high-bit grayscale data at the refresh frequency of low-bit grayscale data.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and in particular to an LED drive pulse modulation method and circuit. Background Art

[0002] Light-emitting diode (LED) displays use the accumulated illumination time of each subframe to display different grayscales. The area within each subframe that can be used to illuminate the LED is called the display area. Given a fixed display frequency, the display time of the display area varies depending on the number of line scans. Figure 1 The schematic diagram of the principle of LED display screen in the prior art is shown. Figure 1 As shown, each row scan is turned on sequentially when displaying data. To prevent the current of the R / G / B display channels from coupling with the row tubes when they are turned off or on, the row tubes are locked at the off voltage when not on, causing the LEDs to be in a reverse biased, non-illuminated state. When the voltage at the enabled row scan terminal changes, the channel control terminal's output voltage is pulled down to reach the forward biased conduction voltage of the LEDs, thereby illuminating the LEDs.

[0003] Currently, the driver chips of LED displays generally use pulse width modulation ("PWM") technology. In short, PWM generates a series of voltage pulses to output the column voltage OUT that drives the LED. However, PWM technology has certain defects. It will produce "color unevenness" and "human eye flicker" phenomena at high grayscale levels. Based on the PWM algorithm, the SPWM algorithm, which is a broken PWM algorithm, was developed. Figure 2 A schematic diagram of the SPWM algorithm used in the prior art is shown. This algorithm breaks the entire display cycle into several sub-cycles (G0, G1, ...), each containing several clock cycles (GCLK). The original PWM pulses are evenly distributed across these sub-cycles, maintaining the original PWM duty cycle and, therefore, the brightness. By increasing the number of channel openings, the display refresh rate can be significantly increased, enhancing visual smoothness. For example, if grayscale data is 13 bits and the entire display cycle is broken into 64 sub-cycles, with 128 GCLKs per sub-cycle, the columns associated with each row within each sub-cycle can display grayscale values ​​ranging from 0 to 128.

[0004] Row scanning is performed in each sub-cycle. When the row tube is not turned on, the output voltage OUT of the channel control end needs to be pulled up to the shutdown voltage to put the LED lamp in a reverse biased and non-lit state; when the row tube is turned on, the output voltage OUT of the channel control end needs to be pulled down to the pre-turn-on voltage DN, and then continue to drop to the turn-on voltage to light up the LED lamp. The interval in which the LED lamp is lit in each sub-cycle is the display area PWM_DIS. After displaying the corresponding grayscale value, the output voltage OUT of the channel control end needs to be pulled up to a certain voltage to put the LED lamp in a reverse biased and non-lit state.

[0005] Ideally, the channel opens like Figure 3a As shown, the area of ​​region a determines the grayscale value of channel Channel_0. However, the grayscale values ​​of other channels that share the same row tube as channel Channel_0 may be any range from 0 to 128, and the grayscale values ​​of other channels have different effects on the coupling of channel Channel_0. When channels Channel_0 and Channel_1 have the same grayscale value, the speed of turning on and off the LED light will become faster, but the effects of the two are different, resulting in the grayscale of channel Channel_0 being inconsistent with the original. For example, the grayscale value of channel Channel_0 is determined by the area of ​​region b. Figure 3b If the grayscale value of channel Channel_1 is high, the pre-turn-on voltage of channel Channel_0 will be coupled lower than the preset value, thereby reducing the turn-on time and causing the grayscale value of channel Channel_0 to become larger.

[0006] During the same row display period, when one channel displays a low grayscale value, other channels may display grayscale values ​​of 0, low grayscale values, or high grayscale values. The grayscale values ​​displayed by other channels will have different coupling effects on the channel, resulting in different brightness levels for the same grayscale. In addition, different color LED lights have different turn-off voltages, pre-turn-on voltages, and turn-on voltages, resulting in different coupling effects between channels. Summary of the Invention

[0007] In view of the above problems, an object of the present invention is to provide an LED driving pulse modulation method and circuit to solve the problem of displaying high-bit grayscale data at a low-bit grayscale data refresh rate.

[0008] According to a first aspect of the present invention, a method for LED driving pulse modulation is provided, comprising: dividing N-bit grayscale data into P-bit integer grayscale and R-bit fractional grayscale, wherein the clock period of the P-bit integer grayscale is a first clock period T1, and the clock period of the N-bit grayscale data is a second clock period T2, where T1=2 R *T2, N, P, R are positive integers, N=P+R; the display period of N-bit grayscale data is evenly divided into 2 L sub-periods, each sub-period includes 2 M-R First clock cycles, each sub-cycle includes a high gray display area and at least one low gray display area, M, L are positive integers, N = M + L; according to the optimization level K, the first grayscale value that can be assigned to the low gray display area in each sub-cycle is set, and the maximum low grayscale value corresponding to the low gray display area in the entire display cycle is obtained, and the first grayscale value is less than or equal to 2 K , K is a positive integer less than M; when the size of the grayscale data is less than or equal to the maximum low grayscale value, the grayscale data is allocated to 2 LIn the low gray display area of ​​the sub-cycle.

[0009] Preferably, the first grayscale value assignable to the low gray display area in each sub-period is a fixed value.

[0010] Preferably, the grayscale data is distributed in 2 L The low gray display area of ​​the sub-cycle includes: generating a gray scale display time t according to the first clock signal and the delayed clock signal, wherein the period of the first clock signal is the first clock period, the period of the delayed clock signal is the second clock signal, and the delay between the first clock signal and the clock signal is F*T2, wherein F is 0, 1, 2, ..., (2 R -1), where t=DT1±F*T2, D is a non-negative integer; the grayscale display time is distributed in 2 L In the low gray display area of ​​the sub-cycle.

[0011] Preferably, setting the first grayscale value assignable to the low gray display area in each sub-period according to the optimization level K includes: setting the grayscale data of the same color (2 K -1) sub-periods, the first grayscale values ​​that can be assigned to the low gray display area are 1, 2, ..., (2 K -1); and set the first grayscale value that can be assigned to the low gray display area of ​​the remaining sub-periods of the same color grayscale data to 2 K .

[0012] Preferably, setting the first grayscale value assignable to the low gray display area in each sub-period according to the optimization level K includes: setting the first grayscale values ​​assignable to the low gray display area of ​​K sub-periods of the same color grayscale data to be 2 0 , 2 1 ,……,2 K-1 ; and set the first grayscale value that can be assigned to the low gray display area of ​​the remaining sub-periods of the same color grayscale data to 2 K .

[0013] Preferably, setting the first grayscale value assignable to the low gray display area in each sub-period according to the optimization level K includes: setting the grayscale data of the same color (2 K -1) The first grayscale value that can be assigned to the low gray display area of ​​the sub-period is 1; and the first grayscale value that can be assigned to the low gray display area of ​​the remaining sub-periods of the same color grayscale data is 2 K .

[0014] Preferably, the color of the grayscale data includes at least one of red, green and blue.

[0015] Preferably, each sub-period includes a low-gray display area, and each sub-period displays grayscale data of one color, and each sub-period displays corresponding colors in sequence.

[0016] Preferably, each sub-period includes a plurality of low-gray display areas, and each sub-period displays grayscale data of a corresponding number of colors, and the plurality of low-gray display areas of each sub-period display corresponding colors in sequence.

[0017] Preferably, the LED driving pulse modulation method further comprises: when the size of the grayscale data is greater than the maximum low grayscale value, allocating the grayscale data to 2 L wherein the high gray display area in each sub-period can be assigned a second grayscale value, the second grayscale value is not fixed, and the second grayscale value is 0 or (2 K ~2 M )

[0018] Preferably, the LED driving pulse modulation method further comprises: when the size of the grayscale data is greater than the maximum low grayscale value, allocating the grayscale data to 2 L The high gray display area and the low gray display area of ​​each sub-period can be assigned a second grayscale value, and the second grayscale value is not fixed. The second grayscale value is 2 K multiples of .

[0019] Preferably, the optimization level K is the number of reference clock cycles set at low grayscale. K , requiring that each group of PWM pulses in each sub-cycle is not less than the set reference clock cycle number 2 K The optimization level K can be 0, 1, 2, 3, ..., K, and the corresponding reference clock cycles are 2 0 , 2 1 , 2 2 , 2 3 ,……,2 K , K is a non-negative integer less than N.

[0020] According to another aspect of the present invention, there is provided an LED driving pulse modulation circuit, comprising: a bit division unit for dividing N-bit grayscale data into P-bit integer grayscale and R-bit fractional grayscale, wherein the clock period of the P-bit integer grayscale is a first clock period T1, and the clock period of the N-bit grayscale data is a second clock period T2, T1=2 R *T2, N, P, R are positive integers, N = P + R; period division unit, used to divide the display period of N-bit grayscale data into 2 L sub-periods, each sub-period includes 2 M-Ra first clock cycle, each sub-cycle includes a high gray display area and at least one low gray display area, M and L are positive integers, N=M+L; an optimization unit is used to set the first grayscale value that can be assigned to the low gray display area in each sub-cycle according to the optimization level K, and obtain the maximum low grayscale value corresponding to the low gray display area in the entire display cycle, and the first grayscale value is less than or equal to 2 K , K is a positive integer less than M; the grayscale allocation unit is used to allocate the grayscale data to 2 when the size of the grayscale data is less than or equal to the maximum low grayscale value. L In the low gray display area of ​​the sub-cycle.

[0021] Preferably, the first grayscale value assignable to the low gray display area in each sub-period is a fixed value.

[0022] Preferably, the grayscale distribution unit is further configured to generate a grayscale display time t according to a first clock signal and a delayed clock signal, wherein the period of the first clock signal is a first clock period, the period of the delayed clock signal is a second clock signal, and the delay between the first clock signal and the clock signal is F*T2, wherein F is 0, 1, 2, ..., (2 R -1), where t=DT1±F*T2, D is a non-negative integer; and the grayscale display time is distributed in 2 L In the low gray display area of ​​the sub-cycle.

[0023] Preferably, the optimization unit is used to set the grayscale data of the same color (2 K -1) sub-periods, the first grayscale values ​​that can be assigned to the low gray display area are 1, 2, ..., (2 K -1); and set the first grayscale value that can be assigned to the low gray display area of ​​the remaining sub-periods of the same color grayscale data to 2 K .

[0024] Preferably, the optimization unit is used to set the first grayscale values ​​assignable to the low gray display areas of K sub-periods of grayscale data of the same color to be 2 0 , 2 1 ,……,2 K-1 ; and set the first grayscale value that can be assigned to the low gray display area of ​​the remaining sub-periods of the same color grayscale data to 2 K .

[0025] Preferably, the optimization unit is used to set the grayscale data of the same color (2 K -1) The first grayscale value that can be assigned to the low gray display area of ​​the sub-period is 1; and the first grayscale value that can be assigned to the low gray display area of ​​the remaining sub-periods of the same color grayscale data is 2 K .

[0026] Preferably, the color of the grayscale data includes at least one of red, green and blue.

[0027] Preferably, each sub-period includes a low-gray display area, and the grayscale allocation unit displays grayscale data of one color in each sub-period, and each sub-period displays corresponding colors in sequence.

[0028] Preferably, each sub-period includes a plurality of low-gray display areas, the grayscale allocating unit displays grayscale data of a corresponding number of colors in each sub-period, and the plurality of low-gray display areas in each sub-period display corresponding colors in sequence.

[0029] Preferably, the grayscale allocation unit is further configured to allocate the grayscale data to the 2 grayscale data when the grayscale data size is greater than the maximum low grayscale value. L wherein the high gray display area in each sub-period can be assigned a second grayscale value, the second grayscale value is not fixed, and the second grayscale value is 0 or (2 K ~2 M )

[0030] Preferably, the grayscale allocation unit is further configured to allocate the grayscale data to the 2 grayscale data when the grayscale data size is greater than the maximum low grayscale value. L The high gray display area and the low gray display area of ​​each sub-period can be assigned a second grayscale value, and the second grayscale value is not fixed. The second grayscale value is 2 K multiples of .

[0031] Preferably, the optimization level K is the number of reference clock cycles set at low grayscale. K , requiring that each group of PWM pulses in each sub-cycle is not less than the set reference clock cycle number 2 K The optimization level K can be 0, 1, 2, 3, ..., K, and the corresponding reference clock cycles are 2 0 , 2 1 , 2 2 , 2 3 ,……,2 K , K is a non-negative integer less than N.

[0032] The LED drive pulse modulation method and circuit provided by the present invention use the clock period of the integer grayscale in N-bit grayscale data as the refresh period, and use fractional PWM to display the grayscale value of the N-bit grayscale data. It can realize the display of high-bit grayscale data at the refresh frequency of low-bit grayscale data, thereby reducing power consumption.

[0033] Furthermore, each broken-up sub-period includes a high-gray display area and at least one low-gray display area, so that the high-gray and low-gray are staggered in time, eliminating the coupling between the high and low gray levels.

[0034] Furthermore, setting the first grayscale value assignable to the low-gray display area of ​​each sub-period as a fixed value can reduce coupling caused by different grayscales of multiple channels during low-gray display. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0036] Figure 1 The schematic diagram of the principle of LED display screen in the prior art is shown;

[0037] Figure 2 Shown is a schematic diagram of an SPWM algorithm in the prior art;

[0038] Figure 3a and Figure 3b A schematic diagram of an output voltage waveform of a column control terminal in the prior art is shown;

[0039] Figure 4 A flow chart of an LED drive pulse modulation method provided by an embodiment of the present invention is shown;

[0040] Figure 5 A schematic diagram showing a clock signal waveform of an LED driving pulse modulation method provided by an embodiment of the present invention is shown;

[0041] Figure 6 A schematic diagram showing the working waveforms of the LED driving pulse modulation method provided by the first embodiment of the present invention is shown;

[0042] Figure 7 A diagram showing the relationship between the sub-periods when the row tube is turned on and the grayscale data of different colors provided by the first embodiment of the present invention;

[0043] Figure 8a-8c The grayscale distribution diagrams of the sub-periods when the grayscale data provided by the embodiment of the present invention is a low grayscale value are respectively shown;

[0044] Figure 9 A schematic diagram showing the working waveforms of the LED driving pulse modulation method provided by the second embodiment of the present invention is shown;

[0045] Figure 10 A diagram showing the relationship between the sub-periods when the row tube is turned on and the grayscale data of different colors provided by the second embodiment of the present invention;

[0046] Figure 11 and Figure 12 The grayscale distribution diagrams of the sub-periods when the grayscale data provided by the embodiment of the present invention is a high grayscale value are respectively shown;

[0047] Figure 13A schematic diagram of an LED driving pulse modulation circuit provided according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0048] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, identical elements are represented by identical or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0049] The specific implementation of the present invention is further described in detail below with reference to the accompanying drawings and examples.

[0050] Figure 4 FIG. 1 is a flow chart of a method for modulating LED drive pulses according to an embodiment of the present invention. Figure 4 As shown, the LED driving pulse modulation method includes the following steps.

[0051] In step S110, the N-bit grayscale data is divided into P-bit integer grayscale and R-bit fractional grayscale, wherein the clock period of the P-bit integer grayscale is the first clock period T1, and the clock period of the N-bit grayscale data is the second clock period T2, T1=2 R *T2, N, P, R are positive integers, N=P+R.

[0052] In this embodiment, N-bit binary grayscale data is input from the outside to the LED driving pulse modulation circuit and provided to the LED display screen via the channel control terminal. The grayscale value range corresponding to the grayscale data is 0~2 N -1, where N is a positive integer. The clock cycle when the LED display screen displays a P-bit integer grayscale is the first clock cycle T1; the clock cycle when the LED display screen displays a P-bit integer grayscale is the first clock cycle T2, where T1=2 R *T2 (see Figure 5 As can be seen, as the number of grayscale data bits increases, the required refresh rate of the display increases exponentially. For example, 13-bit grayscale data reaches a refresh rate of 50Hz, while 14-bit grayscale data increases to a refresh rate of 100Hz, which increases the power consumption of the display. This application can not only display more grayscale data bits while maintaining the same refresh rate, but also reduce power consumption.

[0053] In step S120, the display period of the N-bit grayscale data is evenly divided into 2 L sub-periods, each sub-period includes 2 M-R First clock cycles, each sub-cycle includes a high gray display area and at least one low gray display area, N, M, L are positive integers, N=M+L.

[0054] In this embodiment, for the entire display period, the first clock period T1 of the P-bit integer data is used for refreshing, so the number of the scattered sub-periods is 2 L , the total number of clock cycles in each sub-cycle is 2 M-R See also Figure 6 and Figure 9 Each sub-period includes a high gray display area PWM_DIS_H and at least one low gray display area PWM_DIS_L, wherein the order of the high gray display area and the low gray display area can be interchanged, and the low gray display area can be before or after the high gray display area.

[0055] Take N=14bit, L=6, M=8, P=13, R=1 as an example for illustration, but it is not limited to this. The entire display cycle is broken up into 64 sub-cycles (G0, G1, ..., G63), that is, each sub-cycle includes 128 first clock cycles T1, T1=2T2. Therefore, refreshing one first clock cycle T1 is equivalent to refreshing two second clock cycles T2, that is, when displaying one clock cycle T1 in one sub-cycle, the displayed grayscale value for 13-bit grayscale data is 1, and the displayed grayscale value for 14-bit grayscale data is 2. You can subtract one second clock cycle T2 from one first clock cycle T1 to get T1 / 2, that is, the grayscale value 1 corresponding to the 14-bit grayscale data is displayed. Similarly, one first clock cycle T1 plus one second clock cycle T2 can be obtained to get 3T1 / 2, that is, the grayscale value 3 corresponding to the 14-bit grayscale data is displayed.

[0056] In step S130, the first grayscale value that can be assigned to the low gray display area in each sub-period is set according to the optimization level K, and the maximum low grayscale value corresponding to the low gray display area in the entire display period is obtained. The first grayscale value is less than or equal to 2 K , K is a positive integer less than M.

[0057] In this embodiment, the optimization level K is the number of reference clock cycles set at low grayscale. K , requiring that each group of PWM pulses in each sub-cycle is not less than the set reference clock cycle number 2 K The optimization level K can be 0, 1, 2, 3, ..., K, and the corresponding reference clock cycles are 2 0 , 2 1 , 2 2 , 2 3 ,……,2 K , K is a non-negative integer less than N.

[0058] In this embodiment, step S130 specifically includes setting the grayscale data of the same color (2 K-1) sub-periods, the first grayscale values ​​that can be assigned to the low gray display area are 1, 2, ..., (2 K -1); and set the first grayscale value that can be assigned to the low gray display area of ​​the remaining sub-periods of the same color grayscale data to 2 K .

[0059] The color of the grayscale data includes at least one of red (R), green (G), and blue (B).

[0060] In step S140, when the size of the grayscale data is less than or equal to the maximum low grayscale value, the grayscale data is allocated to 2 L The low gray display area of ​​each sub-period is allocated a first gray scale value that can be allocated to the low gray display area in each sub-period.

[0061] In this embodiment, the first grayscale value is from 0 to 2 K For example, the optimization level K = 3 is used to illustrate that the first grayscale value can be 1, 2, 3, 4, 5, 6, or 7, and 7 of these sub-periods are selected to display the corresponding grayscale values ​​1, 2, 3, 4, 5, 6, and 7, respectively. The first grayscale value can also be 1, 2, or 4, and 3 of these sub-periods are selected to display the grayscale values ​​1, 2, and 4, respectively. Each sub-period can display or not display its assignable first grayscale value.

[0062] In this embodiment, the grayscale data is distributed in 2 L The low gray display area of ​​the sub-cycle includes: generating a gray scale display time t according to the first clock signal and the delayed clock signal, wherein the period of the first clock signal is the first clock period, the period of the delayed clock signal is the second clock signal, and the delay between the first clock signal and the clock signal is F*T2, wherein F is 0, 1, 2, ..., (2 R -1), where t=DT1±F*T2, D is a non-negative integer; the grayscale display time is distributed in 2 L In the low gray display area of ​​the sub-cycle.

[0063] This example uses N = 14 bits, L = 6, M = 8, P = 13, and R = 1, but is not limited to this. In this case, T1 = 2T2. When t = DT1 + F * T2, D can be 0, and the values ​​of t can be T2 = T1 / 2, T1, T1 + T2 = 3T1 / 2, and so on, resulting in grayscale values ​​of 1, 2, 3, and so on.

[0064] In step S150, when the size of the grayscale data is greater than the maximum low grayscale value, the grayscale data is allocated to 2 LThe high gray display area and the low gray display area of ​​each sub-period can be assigned a second grayscale value, and the second grayscale value is not fixed. The second grayscale value is 2 K multiples of .

[0065] In this embodiment, the second grayscale value can be 2 K ~2 M Any one of them can also be 2 K The second grayscale value is not greater than 2 M Taking the optimization level K=3 as an example, the first grayscale value can be 1, 2, 3, 4, 5, 6, or 7, and 7 sub-periods are selected to display the corresponding first grayscale value. Each sub-period can display or not display its assignable first grayscale value.

[0066] The LED driving pulse modulation method provided by the embodiment of the present invention uses the clock period of the integer grayscale bits in the N-bit grayscale data as the refresh period, and uses fractional PWM to display the grayscale value of the N-bit grayscale data.

[0067] Furthermore, each broken-up sub-period includes a high-gray display area and at least one low-gray display area, so that the high-gray and low-gray are staggered in time, eliminating the coupling between the high and low gray levels.

[0068] Furthermore, setting the first grayscale value assignable to the low-gray display area of ​​each sub-period as a fixed value can reduce coupling caused by different grayscales of multiple channels during low-gray display.

[0069] Figure 6 FIG1 shows a schematic diagram of the working waveform of the LED driving pulse modulation method provided by the first embodiment of the present invention. Figure 6 When each sub-period includes a low gray display area PWM_DIS_L, each sub-period displays grayscale data of one color, and each sub-period displays the corresponding colors in sequence, for example, in the order of RGB, but not limited thereto. This embodiment is described in the order of RGB. Figure 7 The 0th sub-cycle G0 displays red grayscale data, the 1st sub-cycle G1 displays green grayscale data, the 2nd sub-cycle G3 displays blue grayscale data, and subsequent sub-cycles display grayscale data of corresponding colors in sequence. The 63rd sub-cycle does not display any data. Therefore, when red grayscale data is less than the maximum low grayscale value, this grayscale data is displayed in the low grayscale display area PWM_DIS_L in the 0th sub-cycle G0, the 3rd sub-cycle G3, the 6th sub-cycle G6, ..., and the 60th sub-cycle G60.

[0070] In this embodiment, the optimization level is set to 3, that is, the minimum PWM pulse width of each sub-cycle is 8 clock cycles.

[0071] Figure 8a-8c The grayscale distribution diagram of the sub-period when the grayscale data is a low grayscale value is shown, and the setting of the first grayscale value is not limited thereto.

[0072] See also Figure 8a , the first grayscale values ​​that can be assigned to the seven sub-cycles (G0, G3, G6, G9, ..., G18) of the grayscale data of the same color are set to 1, 2, 3, 4, 5, 6, and 7, respectively. That is, the 0th sub-cycle is used to display grayscale value 1, the 3rd sub-cycle is used to display grayscale value 2, the 6th sub-cycle is used to display grayscale value 3, ... and the 18th sub-cycle is used to display grayscale value 7. The first grayscale value that can be assigned to the remaining sub-cycles of the grayscale data of the same color is set to 8. From this, the maximum low grayscale value can be calculated as 7 + 8 * 14 = 119. In other words, when the size of the grayscale data is less than or equal to 119, the grayscale data can be assigned to the low grayscale display area PWM_DIS_L of each sub-cycle.

[0073] See also Figure 8b , the first grayscale values ​​that can be assigned to the seven sub-cycles (G0, G3, G6, G9, ..., G18) of the same color grayscale data are all set to 1, and the first grayscale values ​​that can be assigned to the remaining sub-cycles of the same color grayscale data are set to 8. From this, the maximum low grayscale value can be calculated as 7 + 8 * 14 = 119. In other words, when the grayscale data size is less than or equal to 119, the grayscale data can be assigned to the low grayscale display area PWM_DIS_L of each sub-cycle.

[0074] See also Figure 8c , the first grayscale values ​​that can be assigned to the three sub-cycles (G0, G3, and G6) of the same color grayscale data are set to 1, 2, and 4, respectively. The first grayscale values ​​that can be assigned to the remaining sub-cycles of the same color grayscale data are set to 8. From this, the maximum low grayscale value can be calculated as 1+2+4+8*14=119. In other words, when the grayscale data size is less than or equal to 119, the grayscale data can be assigned to the low grayscale display area PWM_DIS_L of each sub-cycle.

[0075] Figure 9 A schematic diagram of the operating waveforms of the LED drive pulse modulation method provided by the second embodiment of the present invention is shown. Compared to the first embodiment, each sub-cycle includes multiple low-grayscale display areas PWM_DIS_L. Each sub-cycle displays grayscale data for a corresponding number of colors, and the multiple low-grayscale display areas PWM_DIS_L in each sub-cycle display corresponding colors in sequence.

[0076] This embodiment is described by taking as an example that each sub-period includes three low-gray display areas PWM_DIS_L, and the three low-gray display areas are displayed in sequence according to the order of RGB, but is not limited thereto. Figure 10In each sub-period, the first low-gray display area PWM_DIS_L1 displays red grayscale data, the second low-gray display area PWM_DIS_L2 displays green grayscale data, and the third low-gray display area PWM_DIS_L3 displays blue grayscale data.

[0077] If the first grayscale values ​​that can be assigned to the seven sub-cycles of grayscale data (G0, G1, G2, G3, ..., G6) are set to 1, 2, 3, 4, 5, 6, and 7, respectively, that is, the 0th sub-cycle is used to display grayscale value 1, the 1st sub-cycle is used to display grayscale value 2, the 2nd sub-cycle is used to display grayscale value 3, ... and the 6th sub-cycle is used to display grayscale value 7, and the first grayscale values ​​that can be assigned to the remaining sub-cycles of grayscale data are set to 8, then the maximum low grayscale value can be calculated as 7 + 57 * 8 = 463.

[0078] Figure 11 and Figure 12 Grayscale distribution diagrams of sub-periods when the grayscale data provided by the embodiments of the present invention is a high grayscale value are respectively shown.

[0079] When the size of the grayscale data is greater than the maximum low grayscale value, the grayscale data is distributed between 2 L In the high gray display area of ​​each sub-period, the high gray display area in each sub-period can be assigned a second grayscale value, the second grayscale value is not fixed, and the second grayscale value is 0 or (2 K ~2 M )

[0080] See also Figure 11 , the low gray display area PWM_DIS_L of each sub-period is no longer displayed, and the second grayscale value that can be allocated to each sub-period can be 0 or any value between 8 and 128.

[0081] See also Figure 12 The low gray display area PWM_DIS_L of each sub-cycle continues to display the grayscale part between 112 and 119, and the higher part is displayed in the high gray display area PWM_DIS_H of each sub-cycle. The second grayscale value that can be allocated to each sub-cycle can be a multiple of 8.

[0082] Figure 13 FIG. 1 is a schematic diagram of an LED driving pulse modulation circuit according to an embodiment of the present invention. Figure 13 As shown, the LED driving pulse modulation circuit 100 includes a bit division unit 110 , a cycle division unit 120 , an optimization unit 130 and a grayscale allocation unit 140 .

[0083] The bit division unit 110 is used to divide the N-bit grayscale data into P-bit integer grayscale and R-bit fractional grayscale, wherein the clock period of the P-bit integer grayscale is the first clock period T1, and the clock period of the N-bit grayscale data is the second clock period T2, T1=2 R *T2, N, P, R are positive integers, N=P+R.

[0084] In this embodiment, N-bit binary grayscale data is input from the outside to the LED driving pulse modulation circuit and provided to the LED display screen via the channel control terminal. The grayscale value range corresponding to the grayscale data is 0~2 N -1, where N is a positive integer. The clock cycle when the LED display screen displays a P-bit integer grayscale is the first clock cycle T1; the clock cycle when the LED display screen displays a P-bit integer grayscale is the first clock cycle T2, where T1=2 R *T2 (see Figure 5 As can be seen, as the number of grayscale data bits increases, the required refresh rate of the display increases exponentially. For example, 13-bit grayscale data reaches a refresh rate of 50Hz, while 14-bit grayscale data increases to a refresh rate of 100Hz, which increases the power consumption of the display. This application can not only display more grayscale data bits while maintaining the same refresh rate, but also reduce power consumption.

[0085] The period division unit is used to divide the display period of N-bit grayscale data into 2 L sub-periods, each sub-period includes 2 M-R First clock cycles, each sub-cycle includes a high gray display area and at least one low gray display area, M and L are positive integers, N=M+L.

[0086] In this embodiment, for the entire display period, the first clock period T1 of the P-bit integer data is used for refreshing, so the number of the scattered sub-periods is 2 L , the total number of clock cycles in each sub-cycle is 2 M-R See also Figure 6 and Figure 9 Each sub-period includes a high gray display area PWM_DIS_H and at least one low gray display area PWM_DIS_L, wherein the order of the high gray display area and the low gray display area can be interchanged, and the low gray display area can be before or after the high gray display area.

[0087] Take N=14bit, L=6, M=8, P=13, R=1 as an example for illustration, but it is not limited to this. The entire display cycle is broken up into 64 sub-cycles (G0, G1, ..., G63), that is, each sub-cycle includes 128 first clock cycles T1, T1=2T2. Therefore, refreshing one first clock cycle T1 is equivalent to refreshing two second clock cycles T2, that is, when displaying one clock cycle T1 in one sub-cycle, the displayed grayscale value for 13-bit grayscale data is 1, and the displayed grayscale value for 14-bit grayscale data is 2. You can subtract one second clock cycle T2 from one first clock cycle T1 to get T1 / 2, that is, the grayscale value 1 corresponding to the 14-bit grayscale data is displayed. Similarly, one first clock cycle T1 plus one second clock cycle T2 can be obtained to get 3T1 / 2, that is, the grayscale value 3 corresponding to the 14-bit grayscale data is displayed.

[0088] The optimization unit 130 is used to set the first grayscale value that can be allocated to the low gray display area in each sub-period according to the optimization level K, and obtain the maximum low grayscale value corresponding to the low gray display area in the entire display period. The first grayscale value is less than or equal to 2 K , K is a positive integer less than M.

[0089] In this embodiment, the optimization level K is the number of reference clock cycles set at low grayscale. K , requiring that each group of PWM pulses in each sub-cycle is not less than the set reference clock cycle number 2 K The optimization level K can be 0, 1, 2, 3, ..., K, and the corresponding reference clock cycles are 2 0 , 2 1 , 2 2 , 2 3 ,……,2 K , K is a non-negative integer less than N.

[0090] The grayscale allocation unit 140 is used to allocate the grayscale data to the 2 grayscale data when the grayscale data size is less than or equal to the maximum low grayscale value. L In the low gray display area of ​​the sub-cycle.

[0091] In this embodiment, the first grayscale value is from 0 to 2 K For example, the optimization level K = 3 is used to illustrate that the first grayscale value can be 1, 2, 3, 4, 5, 6, or 7, and 7 of these sub-periods are selected to display the corresponding grayscale values ​​1, 2, 3, 4, 5, 6, and 7, respectively. The first grayscale value can also be 1, 2, or 4, and 3 of these sub-periods are selected to display the grayscale values ​​1, 2, and 4, respectively. Each sub-period can display or not display its assignable first grayscale value.

[0092] In this embodiment, the grayscale data is distributed in 2L The low gray display area of ​​the sub-cycle includes: generating a gray scale display time t according to the first clock signal and the delayed clock signal, wherein the period of the first clock signal is the first clock period, the period of the delayed clock signal is the second clock signal, and the delay between the first clock signal and the clock signal is F*T2, wherein F is 0, 1, 2, ..., (2 R -1), where t=DT1±F*T2, D is a non-negative integer; the grayscale display time is distributed in 2 L In the low gray display area of ​​the sub-cycle.

[0093] This example uses N = 14 bits, L = 6, M = 8, P = 13, and R = 1, but is not limited to this. In this case, T1 = 2T2. When t = DT1 + F * T2, D can be 0, and the values ​​of t can be T2 = T1 / 2, T1, T1 + T2 = 3T1 / 2, and so on, resulting in grayscale values ​​of 1, 2, 3, and so on.

[0094] In a preferred embodiment, the grayscale allocation unit 140 is further configured to allocate the grayscale data to the 2 grayscale data blocks when the grayscale data is larger than the maximum low grayscale value. L The high gray display area and the low gray display area of ​​each sub-period can be assigned a second grayscale value, and the second grayscale value is not fixed. The second grayscale value is 2 K multiples of .

[0095] In this embodiment, the second grayscale value can be 2 K ~2 M Any one of them can also be 2 K The second grayscale value is not greater than 2 M Taking the optimization level K=3 as an example, the first grayscale value can be 1, 2, 3, 4, 5, 6, or 7, and 7 sub-periods are selected to display the corresponding first grayscale value. Each sub-period can display or not display its assignable first grayscale value.

[0096] The LED driving pulse modulation circuit provided by the embodiment of the present invention uses the clock period of the integer grayscale bits in the N-bit grayscale data as the refresh period, and uses fractional PWM to display the grayscale value of the N-bit grayscale data.

[0097] Furthermore, each broken-up sub-period includes a high-gray display area and at least one low-gray display area, so that the high-gray and low-gray are staggered in time, eliminating the coupling between the high and low gray levels.

[0098] Furthermore, setting the first grayscale value assignable to the low-gray display area of ​​each sub-period as a fixed value can reduce coupling caused by different grayscales of multiple channels during low-gray display.

[0099] While embodiments of the present invention have been described above, these embodiments do not exhaustively describe all details and do not limit the invention to the specific embodiments described. Obviously, many modifications and variations are possible based on the above description. These embodiments are selected and described in detail in this specification in order to better explain the principles and practical applications of the present invention, thereby enabling those skilled in the art to better utilize the present invention and its modifications. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for LED drive pulse modulation, characterized in that: include: The N-bit grayscale data is divided into P-bit integer grayscale and R-bit fractional grayscale, wherein the clock period of the P-bit integer grayscale is the first clock period T1, and the clock period of the N-bit grayscale data is the second clock period T2, T1=2 R *T2, N, P, R are positive integers, N=P+R; The display period of N-bit grayscale data is evenly divided into 2 L sub-periods, each sub-period includes 2 M-R a first clock cycle, each sub-cycle includes a high-gray display area and at least one low-gray display area, M and L are positive integers, and N=M+L; Setting the first grayscale value assigned to the low-gray display area in each sub-period according to the optimization level K, and obtaining the maximum low-grayscale value corresponding to the low-gray display area in the entire display period, where K is a positive integer less than M; When the size of the grayscale data is less than or equal to the maximum low grayscale value, the grayscale data is allocated to 2 L In the low gray display area of ​​the sub-cycle, The grayscale data of the same color is allocated to Q sub-periods, 0<Q≤2 L , A of the Q sub-periods have a value less than 2 K The first grayscale value of the A sub-periods is different from each other or all the same, and the remaining sub-periods have a grayscale value equal to 2 K The first grayscale value, The maximum low grayscale value , A=K or A=2 K -1.

2. The LED driving pulse modulation method according to claim 1, characterized in that: The first grayscale value allocated to the low gray display area in each sub-period is a fixed value.

3. The LED driving pulse modulation method according to claim 1 or 2, characterized in that: Distribute the grayscale data to 2 L The low gray display area of ​​the sub-cycle includes: generating a gray scale display time t according to the first clock signal and the delayed clock signal, wherein the period of the first clock signal is the first clock period, the period of the delayed clock signal is the second clock period, and the delay between the first clock signal and the delayed clock signal is F*T2, wherein F is 0, 1, 2, ..., (2 R -1), where t=DT1±F*T2, and D is a non-negative integer; The grayscale display time is distributed over 2 L In the low gray display area of ​​the sub-cycle.

4. The LED driving pulse modulation method according to claim 1, characterized in that: Setting the first grayscale value allocated to the low gray display area in each sub-period according to the optimization level K includes: Set the grayscale data of the same color (2 K The first grayscale values ​​assigned to the low gray display area of ​​the sub-periods are 1, 2, ..., (2 K -1); and Set the first grayscale value assigned to the low gray display area of ​​the remaining sub-periods of the grayscale data of the same color to 2 K .

5. The LED driving pulse modulation method according to claim 1, wherein: Setting the first grayscale value allocated to the low gray display area in each sub-period according to the optimization level K includes: The first grayscale values ​​assigned to the low gray display areas of K sub-periods of grayscale data of the same color are 2 0 , 2 1 ,……,2 K-1 ;as well as Set the first grayscale value assigned to the low gray display area of ​​the remaining sub-periods of the grayscale data of the same color to 2 K .

6. The LED driving pulse modulation method according to claim 1, characterized in that: Setting the first grayscale value allocated to the low gray display area in each sub-period according to the optimization level K includes: Set the grayscale data of the same color (2 K -1) sub-periods in which the first grayscale value assigned to the low gray display area is 1; and Set the first grayscale value assigned to the low gray display area of ​​the remaining sub-periods of the grayscale data of the same color to 2 K .

7. The LED driving pulse modulation method according to any one of claims 4 to 6, characterized in that: The color of the grayscale data includes at least one of red, green, and blue.

8. The LED driving pulse modulation method according to any one of claims 4 to 6, characterized in that: Each sub-period includes a low-gray display area, and each sub-period displays grayscale data of one color, and each sub-period displays corresponding colors in sequence.

9. The LED driving pulse modulation method according to any one of claims 4 to 6, characterized in that: Each sub-period includes a plurality of low-gray display areas, and each sub-period displays grayscale data of a corresponding number of colors. The plurality of low-gray display areas of each sub-period displays corresponding colors in sequence.

10. The LED driving pulse modulation method according to claim 1, characterized in that: Also includes: When the size of the grayscale data is greater than the maximum low grayscale value, the grayscale data is allocated to 2 L In the high gray display area of ​​the sub-cycle; In each sub-period, the high gray display area is assigned a second grayscale value, and the second grayscale value is not fixed. The second grayscale value is 0 or (2 K ~2 M ) 11. The LED driving pulse modulation method according to claim 1, characterized in that: Also includes: When the size of the grayscale data is greater than the maximum low grayscale value, the grayscale data is allocated to 2 L In the high gray display area and low gray display area of ​​the sub-cycle; In each sub-period, the high gray display area is assigned a second grayscale value, and the second grayscale value is not fixed. The second grayscale value is 2 K multiples of .

12. The LED driving pulse modulation method according to claim 1, wherein: The optimization level K is the number of reference clock cycles set at low grayscale. K , requiring that each group of PWM pulses in each sub-cycle is not less than the set reference clock cycle number 2 K , the optimization level K is 0, 1, 2, 3..., K, and the corresponding reference clock cycle number is 2 0 , 2 1 , 2 2 , 2 3 ,……,2 K , K is a non-negative integer less than N.

13. An LED driving pulse modulation circuit, characterized in that: include: The bit division unit is used to divide the N-bit grayscale data into P-bit integer grayscale and R-bit fractional grayscale, wherein the clock period of the P-bit integer grayscale is the first clock period T1, and the clock period of the N-bit grayscale data is the second clock period T2, T1=2 R *T2, N, P, R are positive integers, N=P+R; The period division unit is used to divide the display period of N-bit grayscale data into 2 L sub-periods, each sub-period includes 2 M-R a first clock cycle, each sub-cycle includes a high-gray display area and at least one low-gray display area, M and L are positive integers, and N=M+L; an optimization unit, configured to set a first grayscale value assigned to the low-gray display area in each sub-period according to an optimization level K, and obtain a maximum low-grayscale value corresponding to the low-gray display area in the entire display period, where K is a positive integer less than M; The grayscale allocation unit is used to allocate the grayscale data to the 2 L In the low gray display area of ​​the sub-cycle, The grayscale data of the same color is allocated to Q sub-periods, 0<Q≤2 L , A of the Q sub-periods have a value less than 2 K The first grayscale value of the A sub-periods is different from each other or all the same, and the remaining sub-periods have a grayscale value equal to 2 K The first grayscale value, The maximum low grayscale value , A=K or A=2 K -1.

14. The LED driving pulse modulation circuit according to claim 13, characterized in that: The first grayscale value allocated to the low gray display area in each sub-period is a fixed value.

15. The LED driving pulse modulation circuit according to claim 13 or 14, characterized in that: The grayscale distribution unit is further configured to generate a grayscale display time t according to a first clock signal and a delayed clock signal, wherein the period of the first clock signal is a first clock period, the period of the delayed clock signal is a second clock period, and the delay between the first clock signal and the delayed clock signal is F*T2, wherein F is 0, 1, 2, ..., (2 R -1), where t=DT1±F*T2, D is a non-negative integer; and the grayscale display time is distributed in 2 L In the low gray display area of ​​the sub-cycle.

16. The LED driving pulse modulation circuit according to claim 13, characterized in that: The optimization unit is used to set the grayscale data of the same color (2 K The first grayscale values ​​assigned to the low gray display area of ​​the sub-periods are 1, 2, ..., (2 K -1); and setting the first grayscale value assigned to the low gray display area of ​​the remaining sub-periods of the same color grayscale data to 2 K .

17. The LED driving pulse modulation circuit according to claim 13, characterized in that: The optimization unit is used to set the first grayscale values ​​allocated to the low gray display areas of K sub-periods of grayscale data of the same color to be 2 0 , 2 1 ,……,2 K-1 ; And set the first grayscale value assigned to the low gray display area of ​​the remaining sub-periods of the grayscale data of the same color to 2 K .

18. The LED driving pulse modulation circuit according to claim 13, characterized in that: The optimization unit is used to set the grayscale data of the same color (2 K -1) The first grayscale value assigned to the low gray display area of ​​the sub-period is 1; And set the first grayscale value assigned to the low gray display area of ​​the remaining sub-periods of the grayscale data of the same color to 2 K .

19. The LED driving pulse modulation circuit according to any one of claims 16 to 18, characterized in that: The color of the grayscale data includes at least one of red, green, and blue.

20. The LED driving pulse modulation circuit according to any one of claims 16 to 18, characterized in that: Each sub-period includes a low-gray display area, and each sub-period displays grayscale data of one color, and each sub-period displays corresponding colors in sequence.

21. The LED driving pulse modulation circuit according to any one of claims 16 to 18, characterized in that: Each sub-period includes a plurality of low-gray display areas, and each sub-period displays grayscale data of a corresponding number of colors. The plurality of low-gray display areas of each sub-period displays corresponding colors in sequence.

22. The LED driving pulse modulation circuit according to claim 13, characterized in that: The grayscale allocation unit is further configured to allocate the grayscale data to the 2 grayscale layers when the grayscale data is larger than the maximum low grayscale value. L In the high gray display area of ​​the sub-cycle; In each sub-period, the high gray display area is assigned a second grayscale value, and the second grayscale value is not fixed. The second grayscale value is 0 or (2 K ~2 M ) 23. The LED driving pulse modulation circuit according to claim 13, characterized in that: The grayscale allocation unit is further configured to allocate the grayscale data to the 2 grayscale layers when the grayscale data is larger than the maximum low grayscale value. L The high gray display area and the low gray display area of ​​each sub-period are assigned a second grayscale value, and the second grayscale value is not fixed. The second grayscale value is 2 K multiples of .

24. The LED driving pulse modulation circuit according to claim 13, characterized in that: The optimization level K is the number of reference clock cycles set at low grayscale. K , requiring that each group of PWM pulses in each sub-cycle is not less than the set reference clock cycle number 2 K , the optimization level K is 0, 1, 2, 3..., K, and the corresponding reference clock cycle number is 2 0 , 2 1 , 2 2 , 2 3 ,……,2 K , K is a non-negative integer less than N.

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