Defect detection method, device, apparatus, storage medium, and program product

Abstract

The application relates to a defect detection method, device, equipment, storage medium and program product. The method comprises the following steps: obtaining life change information of a target chip under a preset working condition; determining a target cavity area ratio corresponding to the target chip according to a pre-established mapping relationship and the life change information, and taking the target cavity area ratio as a defect detection result; wherein the mapping relationship comprises life time change conditions corresponding to different cavity area ratios under multiple working conditions, and the cavity area ratio is used for representing a ratio of a cavity area to a via area. By using the method, the via filling effect of the whole batch of chips can be determined, so that the whole batch of chips can be judged to be accepted or rejected.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a defect detection method, apparatus, device, storage medium, and program product. Background Technology

[0002] With the development of VLSI process technology, the size of vias in chips is getting smaller and smaller and the aspect ratio of vias is high. Therefore, the metal in vias is not easy to fill evenly and is prone to forming voids, which can easily lead to electromigration problems.

[0003] In traditional techniques, the reliability of metal filling in through-holes is often checked using the fine cutting and grinding function of focused ion beam (FIB). By creating a cross-section of the through-hole, the uniformity of metal filling in the through-hole can be observed from the physical morphology.

[0004] However, the above method can only obtain the via filling effect of the prepared sample, and cannot determine the via filling effect of the entire batch of chips. Summary of the Invention

[0005] Therefore, it is necessary to provide a defect detection method, apparatus, equipment, storage medium, and program product that can determine the via filling effect of an entire batch of chips, in order to address the aforementioned technical problems.

[0006] Firstly, this application provides a defect detection method, the method comprising:

[0007] Obtain information on the lifespan variation of the target chip under preset operating conditions;

[0008] Based on the pre-established mapping relationship and lifetime change information, the target void area ratio corresponding to the target chip is determined, and the target void area ratio is used as the defect detection result;

[0009] The mapping relationship includes the changes in lifetime time corresponding to different void area ratios under multiple working conditions. The void area ratio is used to characterize the ratio of void area to through-hole area.

[0010] In one embodiment, the above-described defect detection method further includes:

[0011] Under each operating condition, obtain multiple test void area ratios;

[0012] The test lifetime time corresponding to the area ratio of each test cavity is determined according to the preset formula;

[0013] A mapping relationship is established based on multiple operating conditions, multiple test void area ratios, and the test lifetime time corresponding to each test void area ratio.

[0014] In one embodiment, determining the test lifetime time corresponding to each test void area ratio according to a preset formula includes:

[0015] Activation energy and current density factor were obtained based on accelerated life testing;

[0016] Obtain the current density corresponding to the area ratio of each test void;

[0017] For each test void area ratio, the activation energy, current density factor, and current density corresponding to the test void area ratio are substituted into the preset relationship to obtain the test lifetime time corresponding to the test void area ratio.

[0018] In one embodiment, the process of obtaining the activation energy includes:

[0019] Under a preset current density, the first lifetime of the test chip at different test temperatures was obtained;

[0020] The activation energy is obtained by curve fitting based on the test temperature and the first lifetime time.

[0021] In one embodiment, the process of obtaining the current density factor includes:

[0022] At a preset temperature, the second lifetime of the test chip under different current densities was obtained;

[0023] The current density factor is obtained by curve fitting based on the current density and the second lifetime time.

[0024] In one embodiment, the aforementioned preset relation includes:

[0025]

[0026] Where τ is the lifetime time, A is the proportionality constant, J is the current density, n is the current density factor, and E is the current density factor. a The activation energy is given by k, the Boltzmann constant is given by T, and the absolute temperature is given by T.

[0027] Secondly, this application also provides a defect detection device, which includes:

[0028] The lifespan acquisition module is used to acquire lifespan change information of the target chip under preset operating conditions;

[0029] The void area determination module is used to determine the target void area ratio of the target chip based on the pre-established mapping relationship and lifetime change information, and use the target void area ratio as the defect detection result;

[0030] The mapping relationship includes the changes in lifetime time corresponding to different void area ratios under multiple working conditions. The void area ratio is used to characterize the ratio of void area to through-hole area.

[0031] In one embodiment, the device further includes:

[0032] The void area acquisition module is used to acquire multiple test void area ratios under each working condition;

[0033] The lifetime determination module is used to determine the test lifetime corresponding to each test void area ratio according to a preset formula.

[0034] The relationship establishment module is used to establish mapping relationships based on multiple operating conditions, multiple test void area ratios, and the test lifetime time corresponding to each test void area ratio.

[0035] In one embodiment, the lifetime determination module includes:

[0036] The first acquisition submodule is used to acquire activation energy and current density factor based on accelerated life test;

[0037] The second acquisition submodule is used to acquire the current density corresponding to each test void area ratio;

[0038] The time determination submodule is used to substitute the activation energy, current density factor and current density corresponding to the test void area ratio into a preset formula for each test void area ratio to obtain the test lifetime time corresponding to the test void area ratio.

[0039] In one embodiment, the first acquisition submodule is specifically used to acquire the first lifetime of the test chip at different test temperatures under a preset current density; and to obtain the activation energy by curve fitting based on the test temperature and the first lifetime.

[0040] In one embodiment, the first acquisition submodule is specifically used to acquire the second lifetime of the test chip at different current densities at a preset temperature; and to obtain the current density factor by curve fitting based on the current density and the second lifetime.

[0041] In one embodiment, the preset relation includes:

[0042]

[0043] Where τ is the lifetime time, A is the proportionality constant, J is the current density, n is the current density factor, and E is the current density factor. a The activation energy is given by k, the Boltzmann constant is given by T, and the absolute temperature is given by T.

[0044] Thirdly, this application also provides a computer device. The computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to perform the steps described in the first aspect.

[0045] Fourthly, this application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program thereon, which, when executed by a processor, performs the steps described in the first aspect.

[0046] Fifthly, this application also provides a computer program product. The computer program product includes a computer program that, when executed by a processor, performs the steps described in the first aspect.

[0047] The aforementioned defect detection method, apparatus, equipment, storage medium, and program product acquire lifetime change information of the target chip under preset operating conditions; determine the target void area ratio corresponding to the target chip based on the pre-established mapping relationship and lifetime change information, and use the target void area ratio as the defect detection result. In this application embodiment, the via filling effect of the entire batch of chips can be determined based on the defect detection result, thereby making a decision to accept or reject the entire batch of chips. Attached Figure Description

[0048] Figure 1 This is a diagram illustrating the application environment of a defect detection method in one embodiment;

[0049] Figure 2 This is a flowchart illustrating a defect detection method in one embodiment;

[0050] Figure 3 This is a graph showing the relationship between different void area ratios and lifetime variation in one embodiment.

[0051] Figure 4 This is a flowchart illustrating the steps for establishing mapping relationships in one embodiment;

[0052] Figure 5 This is a flowchart illustrating the steps for determining the test lifetime in one embodiment;

[0053] Figure 6 This is a flowchart illustrating the step of obtaining activation energy in one embodiment;

[0054] Figure 7 This is a flowchart illustrating the steps for obtaining the current density factor in one embodiment;

[0055] Figure 8 This is a flowchart illustrating a defect detection method in another embodiment;

[0056] Figure 9This is one of the structural block diagrams of a defect detection device in one embodiment;

[0057] Figure 10 This is a second structural block diagram of a defect detection device in one embodiment;

[0058] Figure 11 This is the third structural block diagram of the defect detection device in one embodiment;

[0059] Figure 12 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0060] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0061] The defect detection method provided in this application embodiment can be applied to, for example, Figure 1 In the application environment shown, terminal 01 communicates with server 02 via a network. A data storage system can store the data that server 02 needs to process. The data storage system can be integrated onto server 02, or it can be located in the cloud or on other network servers. Server 02 can be implemented as a standalone server or a server cluster consisting of multiple servers.

[0062] In one embodiment, such as Figure 2 As shown, this method is applied to Figure 1 Taking the terminal shown as an example, the following steps may be included:

[0063] S101, Obtain the lifetime change information of the target chip under preset operating conditions.

[0064] The preset operating conditions include at least one of preset temperature and preset current density. Lifetime variation information includes changes in lifetime time as current density changes, and also changes in lifetime time as temperature changes.

[0065] Obtain information on the lifetime changes of the target chip under preset temperature and preset current density.

[0066] S102, based on the pre-established mapping relationship and lifetime change information, determine the target void area ratio corresponding to the target chip, and use the target void area ratio as the defect detection result.

[0067] The mapping relationship includes the changes in lifetime time corresponding to different void area ratios under multiple working conditions. The void area ratio is used to characterize the ratio of void area to through-hole area.

[0068] The aforementioned multiple operating conditions refer to operating conditions under different temperatures and different current densities. Different void area ratios include void area ratios of 10%, 20%, 30%, and 40%. The mapping relationship of the embodiments of this application is shown in Table 1.

[0069] Table 1 Mapping Relationships

[0070]

[0071] As shown in Table 1, under different working conditions, the same void area ratio has roughly the same impact on service life, and the impact on service life increases with the increase of void area ratio.

[0072] Based on the lifetime change information of the target chip under preset temperature and current density, different void area ratios corresponding to the target chip are obtained in the pre-established mapping relationship. A relationship diagram is drawn between different void area ratios and lifetime change information. The target void area ratio is obtained based on the relationship diagram and is used as the defect detection result.

[0073] For example, based on the target chip at a preset temperature of 125℃ and a preset current density of 2×10⁻⁶. 5 A / cm 2 The lifetime variation information is used to find different void area ratios corresponding to the target chip in a pre-established mapping relationship. A relationship diagram is then drawn between the different void area ratios and the lifetime variation information, such as... Figure 3 As shown.

[0074] Depend on Figure 3 It can be seen that a 20% void area ratio has a greater impact on lifetime than a 30% void area ratio. If a 20% decrease in lifetime is used as the defect detection criterion, the corresponding void area ratio is approximately 12%. Therefore, according to... Figure 3 The target void area ratio was obtained as 12%, and the target void area ratio of 12% was taken as the defect detection result.

[0075] For example, the standard for accepting a batch of chips is that the target void area in the via is less than 20%. Since the target void area ratio is 12%, the chip corresponding to this target void area has a good filling effect, so the chip corresponding to this target void area is accepted. As another example, the standard for accepting a batch of chips is that the target void area in the via is less than 10%. Since the target void area ratio is 12%, the chip corresponding to this target void area has a poor filling effect, so the chip corresponding to this target void area is rejected.

[0076] In the above embodiments, the lifetime change information of the target chip under preset working conditions is obtained. Based on the pre-established mapping relationship and lifetime change information, the target void area ratio corresponding to the target chip is determined, and the target void area ratio is used as the defect detection result. In this way, the standard for accepting a batch of chips can be established, the via filling effect of the batch of chips can be determined, and the batch of chips can be judged to accept or reject. This has the advantages of saving time, saving money, being convenient to use, and being highly efficient.

[0077] In one embodiment, such as Figure 4 As shown, this method is applied to Figure 1 Taking the terminal shown as an example, the following steps may also be included:

[0078] S201, under each working condition, obtain multiple test void area ratios.

[0079] Multiple test void area ratios were obtained at each temperature and current density. For example, at a temperature of 125°C and a current density of 5 × 10⁻⁶... 5 A / cm 2 Under the operating conditions, the test void area ratio was obtained from 0% to 60%. The temperature was 105℃, and the current density was 1×10⁻⁶. 5 A / cm 2 Under the operating conditions, the test void area ratios were obtained from 0% to 60%. This process was repeated to obtain multiple test void area ratios.

[0080] S202, determine the test life time corresponding to the area ratio of each test void according to the preset formula.

[0081] When voids exist in a via, different void area ratios have varying effects on current density. A pre-defined formula includes a functional relationship between current density and lifetime. Therefore, the test lifetime corresponding to each test void area can be determined based on this pre-defined formula.

[0082] For example, at a temperature of 125℃ and a current density of 5×10 5 A / cm 2 Under the operating conditions, the test life time corresponding to the test void area ratio from 0% to 60% is determined according to the preset relationship, as shown in Table 2.

[0083] Table 2 125℃, 5×10 5 A / cm 2 Relationship between lifetime and void area ratio

[0084]

[0085]

[0086] S203 establishes a mapping relationship based on multiple working conditions, multiple test void area ratios, and the test lifetime time corresponding to each test void area ratio.

[0087] Several operating conditions include temperature variations from 125°C to 85°C and current density variations from 5 × 10⁻⁶. 5 A / cm 2 Up to 1×10 5 A / cm 2 The activation energy changes from 0.578 eV to 0.778 eV.

[0088] A mapping relationship is established based on multiple temperature, current density and activation energy conditions, multiple test void area ratios and the test lifetime time corresponding to each test void area ratio, as shown in Table 1.

[0089] In the above embodiments, under each working condition, multiple test void area ratios are obtained, and the test lifetime corresponding to each test void area ratio is determined according to a preset relationship. A mapping relationship is established based on multiple working conditions, multiple test void area ratios, and the test lifetime corresponding to each test void area ratio, laying the foundation for determining the target void area ratio based on the mapping relationship.

[0090] In one embodiment, such as Figure 5 As shown, the steps described above for determining the test lifetime time corresponding to each test void area ratio based on a preset formula may include:

[0091] S301, based on accelerated life testing, obtains activation energy and current density factor.

[0092] Accelerated life testing refers to a test that uses increased stress to induce electromigration in through-holes within a short period of time. In this application, the tests were conducted under five different stress conditions, as shown in Table 3. Under each stress condition, 30 valid reliability characterization structures were used for testing. At least 50% of the samples should fail before the end of the test, with the failure criterion being a 20% increase in initial resistance. The reliability characterization structure is a metal strip with a specific width and length, electrically connected using a four-terminal structure in a Kelvin configuration.

[0093] Table 3 Stress settings for accelerated life testing

[0094]

[0095]

[0096] The accelerated life test was conducted under high temperature and high current conditions, with a maximum current density of 5 × 10⁻⁶. 5 A / cm 2The experimental temperature range was 200℃-350℃ to ensure that electromigration occurred in the through-hole within a short time, thus obtaining effective experimental data. Electromigration refers to the mass transport phenomenon caused by the directional movement of ions within a metal conductor placed in an electric field, resulting in the accumulation or voids of metal atoms in a localized area of ​​the metal conductor.

[0097] Activation energy E obtained from accelerated life testing a and current density factor n.

[0098] S302, obtain the current density corresponding to each test void area ratio.

[0099] Different void area ratios have different effects on current density J. The current density J corresponding to each test area ratio is obtained.

[0100] S303, for each test void area ratio, substitute the activation energy, current density factor and the current density corresponding to the test void area ratio into the preset relationship to obtain the test lifetime time corresponding to the test void area ratio.

[0101] For each test void area ratio, the activation energy E will be... a Substituting the current density factor n and the current density J corresponding to the test void area ratio into the preset relationship, the test lifetime time τ corresponding to the test void area ratio is obtained.

[0102] In the above embodiments, activation energy and current density factor are obtained based on accelerated life testing, and the current density corresponding to each test void area ratio is obtained. For each test void area ratio, the activation energy, current density factor and current density corresponding to the test void area ratio are substituted into a preset relationship to obtain the test lifetime time corresponding to the test void area ratio. In this embodiment, only one test structure needs to be fabricated. The activation energy and current density factor are extracted through accelerated life testing, so the test lifetime time can be obtained quickly and accurately according to the preset relationship.

[0103] In one embodiment, such as Figure 6 As shown, the process of obtaining the activation energy described above may include:

[0104] S401, under a preset current density, obtains the first lifetime of the test chip at different test temperatures.

[0105] The different test temperatures are T1, T2, and T3.

[0106] Under a preset current density, the first lifetime times τ1, τ2, and τ3 of the test chip at 1 / T1, 1 / T2, and 1 / T3 are obtained.

[0107] S402, the activation energy is obtained by curve fitting based on the test temperature and the first lifetime time.

[0108] A curve is fitted with the test temperature on the x-axis and the logarithm of the first lifetime time on the y-axis. The slope of the curve is the activation energy. The typical value of the activation energy is generally between 0.5 eV and 0.9 eV. The curve fitting method can be either the least squares method or the maximum likelihood method. This application does not limit the curve fitting method and can be set according to the actual situation.

[0109] In the above embodiments, the first lifetime of the test chip is obtained at different test temperatures under a preset current density. The activation energy is obtained by curve fitting based on the test temperature and the first lifetime. This application embodiment uses three temperatures to determine the activation energy, which is accurate and efficient.

[0110] In one embodiment, such as Figure 7 As shown, the process of obtaining the current density factor mentioned above may include:

[0111] S501, at a preset temperature, obtains the second lifetime of the test chip under different current densities.

[0112] The different current densities are J1, J2, and J3.

[0113] Under a preset current density, the first lifetime times τ1, τ2, and τ3 of the test chip at test temperatures of 1 / T1, 1 / T2, and 1 / T3 are obtained.

[0114] At a preset temperature, the second lifetime times τ4, τ5, and τ6 of the test chip were obtained at current densities J1, J2, and J3.

[0115] S502, based on curve fitting of current density and second lifetime time, obtains current density factor.

[0116] A curve is fitted with current density on the x-axis and the logarithm of the second lifetime time on the y-axis. The slope of the curve is the current density factor. A typical value for the current density factor is 2. The curve fitting method can be either the least squares method or the maximum likelihood method. This application does not limit the curve fitting method and can be set according to the actual situation.

[0117] In the above embodiments, the second lifetime of the test chip under different current densities is obtained at a preset temperature. A curve is then fitted based on the current density and the second lifetime to obtain the current density factor. This application embodiment uses three current densities to determine the current density factor, which is accurate and efficient.

[0118] In one embodiment, the aforementioned preset relation may include:

[0119]

[0120] Where τ is the lifetime time, A is the proportionality constant, J is the current density, n is the current density factor, and E is the current density factor. a The activation energy is given by k, the Boltzmann constant is given by T, and the absolute temperature is given by T.

[0121] Lifetime is typically measured in seconds (s), while current density is typically measured in megahertz (mA / cm²). 2 The unit of activation energy is generally eV, the Boltzmann constant is 8.6174E-5eV / K, and the unit of absolute temperature is generally K.

[0122] In the above embodiments, the lifetime can be calculated according to a preset formula, thereby enabling the establishment of a mapping relationship based on the lifetime.

[0123] In one embodiment, such as Figure 8 The diagram illustrates the defect detection process, using a terminal as an example, and includes the following steps:

[0124] S601, based on accelerated life testing, obtains activation energy and current density factor.

[0125] Under each operating condition, multiple test void area ratios are obtained; under a preset current density, the first lifetime of the test chip at different test temperatures is obtained; and the activation energy is obtained by curve fitting based on the test temperature and the first lifetime.

[0126] At a preset temperature, the second lifetime of the test chip under different current densities is obtained; the current density factor is obtained by curve fitting based on the current density and the second lifetime.

[0127] S602, obtain the current density corresponding to each test void area ratio.

[0128] S603, for each test void area ratio, substitute the activation energy, current density factor and the current density corresponding to the test void area ratio into the preset relationship to obtain the test lifetime time corresponding to the test void area ratio.

[0129] S604 establishes a mapping relationship based on multiple operating conditions, multiple test void area ratios, and the test lifetime time corresponding to each test void area ratio.

[0130] S605: Obtain information on the lifespan variation of the target chip under preset operating conditions.

[0131] S606 determines the target void area ratio corresponding to the target chip based on the pre-established mapping relationship and lifetime change information, and uses the target void area ratio as the defect detection result.

[0132] The mapping relationship includes the changes in lifetime time corresponding to different void area ratios under multiple working conditions. The void area ratio is used to characterize the ratio of void area to through-hole area.

[0133] In the above embodiments, activation energy and current density factor are obtained based on accelerated life testing; the current density corresponding to each test void area ratio is obtained; for each test void area ratio, the activation energy, current density factor, and current density corresponding to the test void area ratio are substituted into a preset formula to obtain the test life time corresponding to the test void area ratio; a mapping relationship is established based on multiple operating conditions, multiple test void area ratios, and the test life time corresponding to each test void area ratio; the lifespan change information of the target chip under preset operating conditions is obtained; based on the pre-established mapping relationship and lifespan change information, the target void area ratio corresponding to the target chip is determined, and the target void area ratio is used as the defect detection result. This embodiment only requires fabricating a test structure once. By extracting the activation energy and current density factor through accelerated life testing, a defect detection criterion can be formulated. With the defect detection criterion, defect detection can be performed on any via at any location on the circuit chip without fabricating a test structure again, which has the advantages of saving time and money, being convenient to use, and being highly efficient.

[0134] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0135] Based on the same inventive concept, this application also provides a defect detection device for implementing the defect detection method described above. The solution provided by this device is similar to the solution described in the above method; therefore, the specific limitations in one or more defect detection device embodiments provided below can be found in the limitations of the defect detection method described above, and will not be repeated here.

[0136] In one embodiment, such as Figure 9 As shown, a defect detection device is provided, comprising:

[0137] The lifespan acquisition module 701 is used to acquire lifespan change information of the target chip under preset operating conditions;

[0138] The void area determination module 702 is used to determine the target void area ratio corresponding to the target chip based on the pre-established mapping relationship and lifetime change information, and use the target void area ratio as the defect detection result;

[0139] The mapping relationship includes the changes in lifetime time corresponding to different void area ratios under multiple working conditions. The void area ratio is used to characterize the ratio of void area to through-hole area.

[0140] In one embodiment, such as Figure 10 As shown, the device also includes:

[0141] The void area acquisition module 703 is used to acquire multiple test void area ratios under each working condition;

[0142] The lifetime determination module 704 is used to determine the test lifetime corresponding to each test void area ratio according to a preset formula.

[0143] The relationship establishment module 705 is used to establish a mapping relationship based on multiple working conditions, multiple test void area ratios, and the test lifetime time corresponding to each test void area ratio.

[0144] In one embodiment, the lifetime determination module 704, such as Figure 11 As shown, it includes:

[0145] The first acquisition submodule 7041 is used to acquire activation energy and current density factor based on accelerated life test;

[0146] The second acquisition submodule 7042 is used to acquire the current density corresponding to each test void area ratio;

[0147] The time determination submodule 7043 is used to substitute the activation energy, current density factor and current density corresponding to the test void area ratio into a preset formula for each test void area ratio to obtain the test lifetime time corresponding to the test void area ratio.

[0148] In one embodiment, the first acquisition submodule 7041 is specifically used to acquire the first lifetime of the test chip at different test temperatures under a preset current density; and to obtain the activation energy by curve fitting based on the test temperature and the first lifetime.

[0149] In one embodiment, the first acquisition submodule 7041 is specifically used to acquire the second lifetime time of the test chip at different current densities at a preset temperature; and to obtain the current density factor by curve fitting based on the current density and the second lifetime time.

[0150] In one embodiment, the preset relation includes:

[0151]

[0152] Where τ is the lifetime time, A is the proportionality constant, J is the current density, n is the current density factor, and E is the current density factor. a The activation energy is given by k, the Boltzmann constant is given by T, and the absolute temperature is given by T.

[0153] Each module in the aforementioned defect detection device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the corresponding operations of each module.

[0154] In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 12 As shown, the computer device includes a processor, memory, communication interface, display screen, and input device connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, NFC (Near Field Communication), or other technologies. When executed by the processor, the computer program implements a defect detection method.

[0155] Those skilled in the art will understand that Figure 12 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0156] In one embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to perform the following steps:

[0157] Obtain information on the lifespan variation of the target chip under preset operating conditions;

[0158] Based on the pre-established mapping relationship and lifetime change information, the target void area ratio corresponding to the target chip is determined, and the target void area ratio is used as the defect detection result;

[0159] The mapping relationship includes the changes in lifetime time corresponding to different void area ratios under multiple working conditions. The void area ratio is used to characterize the ratio of void area to through-hole area.

[0160] In one embodiment, the processor further performs the following steps when executing the computer program:

[0161] Under each operating condition, obtain multiple test void area ratios;

[0162] The test lifetime time corresponding to the area ratio of each test cavity is determined according to the preset formula;

[0163] A mapping relationship is established based on multiple operating conditions, multiple test void area ratios, and the test lifetime time corresponding to each test void area ratio.

[0164] In one embodiment, the processor further performs the following steps when executing the computer program:

[0165] Activation energy and current density factor were obtained based on accelerated life testing;

[0166] Obtain the current density corresponding to the area ratio of each test void;

[0167] For each test void area ratio, the activation energy, current density factor, and current density corresponding to the test void area ratio are substituted into the preset relationship to obtain the test lifetime time corresponding to the test void area ratio.

[0168] In one embodiment, the processor further performs the following steps when executing the computer program:

[0169] Under a preset current density, the first lifetime of the test chip at different test temperatures was obtained;

[0170] The activation energy is obtained by curve fitting based on the test temperature and the first lifetime time.

[0171] In one embodiment, the processor further performs the following steps when executing the computer program:

[0172] At a preset temperature, the second lifetime of the test chip under different current densities was obtained;

[0173] The current density factor is obtained by curve fitting based on the current density and the second lifetime time.

[0174] In one embodiment, the processor further performs the following steps when executing the computer program:

[0175]

[0176] Where τ is the lifetime time, A is the proportionality constant, J is the current density, n is the current density factor, and E is the current density factor. a The activation energy is given by k, the Boltzmann constant is given by T, and the absolute temperature is given by T.

[0177] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, the computer program performing the following steps when executed by a processor:

[0178] Obtain information on the lifespan variation of the target chip under preset operating conditions;

[0179] Based on the pre-established mapping relationship and lifetime change information, the target void area ratio corresponding to the target chip is determined, and the target void area ratio is used as the defect detection result;

[0180] The mapping relationship includes the changes in lifetime time corresponding to different void area ratios under multiple working conditions. The void area ratio is used to characterize the ratio of void area to through-hole area.

[0181] In one embodiment, when the computer program is executed by the processor, it further performs the following steps:

[0182] Under each operating condition, obtain multiple test void area ratios;

[0183] The test lifetime time corresponding to the area ratio of each test cavity is determined according to the preset formula;

[0184] A mapping relationship is established based on multiple operating conditions, multiple test void area ratios, and the test lifetime time corresponding to each test void area ratio.

[0185] In one embodiment, when the computer program is executed by the processor, it further performs the following steps:

[0186] Activation energy and current density factor were obtained based on accelerated life testing;

[0187] Obtain the current density corresponding to the area ratio of each test void;

[0188] For each test void area ratio, the activation energy, current density factor, and current density corresponding to the test void area ratio are substituted into the preset relationship to obtain the test lifetime time corresponding to the test void area ratio.

[0189] In one embodiment, when the computer program is executed by the processor, it further performs the following steps:

[0190] Under a preset current density, the first lifetime of the test chip at different test temperatures was obtained;

[0191] The activation energy is obtained by curve fitting based on the test temperature and the first lifetime time.

[0192] In one embodiment, when the computer program is executed by the processor, it further performs the following steps:

[0193] At a preset temperature, the second lifetime of the test chip under different current densities was obtained;

[0194] The current density factor is obtained by curve fitting based on the current density and the second lifetime time.

[0195] In one embodiment, when the computer program is executed by the processor, it further performs the following steps:

[0196]

[0197] Where τ is the lifetime time, A is the proportionality constant, J is the current density, n is the current density factor, and E is the current density factor. a The activation energy is given by k, the Boltzmann constant is given by T, and the absolute temperature is given by T.

[0198] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, performs the following steps:

[0199] Obtain information on the lifespan variation of the target chip under preset operating conditions;

[0200] Based on the pre-established mapping relationship and lifetime change information, the target void area ratio corresponding to the target chip is determined, and the target void area ratio is used as the defect detection result;

[0201] The mapping relationship includes the changes in lifetime time corresponding to different void area ratios under multiple working conditions. The void area ratio is used to characterize the ratio of void area to through-hole area.

[0202] In one embodiment, when the computer program is executed by the processor, it further performs the following steps:

[0203] Under each operating condition, obtain multiple test void area ratios;

[0204] The test lifetime time corresponding to the area ratio of each test cavity is determined according to the preset formula;

[0205] A mapping relationship is established based on multiple operating conditions, multiple test void area ratios, and the test lifetime time corresponding to each test void area ratio.

[0206] In one embodiment, when the computer program is executed by the processor, it further performs the following steps:

[0207] Activation energy and current density factor were obtained based on accelerated life testing;

[0208] Obtain the current density corresponding to the area ratio of each test void;

[0209] For each test void area ratio, the activation energy, current density factor, and current density corresponding to the test void area ratio are substituted into the preset relationship to obtain the test lifetime time corresponding to the test void area ratio.

[0210] In one embodiment, when the computer program is executed by the processor, it further performs the following steps:

[0211] Under a preset current density, the first lifetime of the test chip at different test temperatures was obtained;

[0212] The activation energy is obtained by curve fitting based on the test temperature and the first lifetime time.

[0213] In one embodiment, when the computer program is executed by the processor, it further performs the following steps:

[0214] At a preset temperature, the second lifetime of the test chip under different current densities was obtained;

[0215] The current density factor is obtained by curve fitting based on the current density and the second lifetime time.

[0216] In one embodiment, when the computer program is executed by the processor, it further performs the following steps:

[0217]

[0218] Where τ is the lifetime time, A is the proportionality constant, J is the current density, n is the current density factor, and E is the current density factor. a The activation energy is given by k, the Boltzmann constant is given by T, and the absolute temperature is given by T.

[0219] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0220] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0221] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A defect detection method, characterized in that, The method includes: Obtain information on the lifespan variation of the target chip under preset operating conditions; Based on the pre-established mapping relationship and the lifetime change information, the target void area ratio corresponding to the target chip is determined, and the target void area ratio is used as the defect detection result; The mapping relationship includes the lifespan changes corresponding to different void area ratios under multiple working conditions, and the void area ratio is used to characterize the ratio of void area to through-hole area.

2. The method according to claim 1, characterized in that, The method further includes: Under each of the aforementioned operating conditions, multiple test void area ratios were obtained; The test lifetime time corresponding to each test void area ratio is determined according to a preset formula. The mapping relationship is established based on the multiple operating conditions, the multiple test void area ratios, and the test lifetime time corresponding to each test void area ratio.

3. The method according to claim 2, characterized in that, The step of determining the test lifetime time corresponding to each test void area ratio according to a preset formula includes: Activation energy and current density factor were obtained based on accelerated life testing; Obtain the current density corresponding to each of the test void area ratios; For each of the aforementioned test void area ratios, the activation energy, the current density factor, and the current density corresponding to the test void area ratio are substituted into the preset relationship to obtain the test lifetime time corresponding to the test void area ratio.

4. The method according to claim 3, characterized in that, The process of acquiring the activation energy includes: Under a preset current density, the first lifetime of the test chip at different test temperatures was obtained; The activation energy is obtained by curve fitting based on the test temperature and the first lifetime.

5. The method according to claim 3, characterized in that, The process of obtaining the current density factor includes: At a preset temperature, the second lifetime of the test chip under different current densities was obtained; The current density factor is obtained by curve fitting based on the current density and the second lifetime time.

6. The method according to any one of claims 2-5, characterized in that, The preset relational expressions include: Where τ is the lifetime time, A is the proportionality constant, J is the current density, n is the current density factor, and E is the current density factor. a The activation energy is given by k, the Boltzmann constant is given by T, and the absolute temperature is given by T.

7. A defect detection device, characterized in that, The device includes: The first acquisition module is used to acquire information on the lifespan changes of the target chip under preset operating conditions; The void area determination module is used to determine the target void area ratio corresponding to the target chip based on the pre-established mapping relationship and the lifetime change information, and to use the target void area ratio as the defect detection result; wherein, the mapping relationship includes the lifetime time change corresponding to different void area ratios under multiple operating conditions, and the void area ratio is used to characterize the ratio of void area to via area.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

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