Integrated circuit on-die burn-in circuit and integrated circuit die

Abstract

This invention relates to integrated circuit technology, specifically an on-chip aging detection circuit and an integrated circuit chip. The invention comprises a signal sampling and processing module, a voltage-controlled oscillator (VCO), and a Schmitt trigger module connected in series. The signal sampling and processing module outputs a temperature-dependent voltage signal to the VCO. The Schmitt trigger shapes the output waveform of the VCO. The VCO is composed of an odd number of identical inverters arranged sequentially. In adjacent inverters, the output of the preceding inverter is connected to the input of the following inverter; the output of the final inverter is connected to the input of the first inverter. This invention can detect the aging degree of a chip at different temperatures, with temperature having minimal impact on the detection results.

Description

Technical Field

[0001] This invention relates to integrated circuit technology. Background Technology

[0002] Circuit aging refers to the degradation of certain characteristic parameters of hardware in integrated circuits over time during operation. It can be simply summarized as transistor aging leading to increased threshold voltage, transistor failure, and metal wire aging leading to increased resistance and eventual breakage. The transistor aging effects in digital integrated circuits are mainly hot carrier injection, negative bias temperature instability, and time-induced dielectric breakdown. Both hot carrier injection and negative bias temperature instability effects cause threshold voltage degradation in digital integrated circuit transistors. The aging effect of metal wires is mainly electromigration.

[0003] Currently, chip aging testing abroad is generally undertaken by chip manufacturers and specialized aging testing companies. In China, the main organizations capable of conducting chip aging testing include aerospace research institutes, military enterprises, and Huawei HiSilicon. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide an on-chip aging detection technology for integrated circuits that can suppress the effects of temperature.

[0005] The technical solution adopted by the present invention to solve the aforementioned technical problem is an on-chip aging detection circuit for integrated circuits, characterized in that it includes a signal sampling and processing module, a voltage-controlled oscillator, and a Schmitt trigger module connected in series.

[0006] The signal sampling and processing module outputs a voltage signal that is positively correlated with temperature to the voltage-controlled oscillator.

[0007] The Schmitt trigger shapes the output waveform of the voltage-controlled oscillator;

[0008] The voltage-controlled oscillator is composed of an odd number of inverters with identical structures arranged in sequence;

[0009] Each inverter includes a first PMOS transistor, a first NMOS transistor, and a second NMOS transistor; the source of the first PMOS transistor is connected to the high-level terminal VDD, the drain is used as the output terminal, and the gate is used as the input terminal; the drain of the first NMOS transistor is connected to the drain of the first PMOS transistor, the source is connected to the drain of the second NMOS transistor, and the gate is connected to the control signal input terminal; the source of the second NMOS transistor is grounded, and the gate is connected to the gate of the first PMOS transistor.

[0010] In two adjacent inverters, the output of the preceding inverter is connected to the input of the following inverter;

[0011] The output of the final stage inverter is connected to the input of the first stage inverter.

[0012] The signal sampling and processing module includes:

[0013] The fourteenth PMOS transistor Q14 has its source connected to a high level VDD, its drain connected to the drain of the fifteenth NMOS transistor Q15, and its gate connected to the gate and drain of the thirteenth PMOS transistor Q13.

[0014] The drain and gate of the fifteenth NMOS transistor Q15 are connected to the gate of the sixteenth NMOS transistor Q16, and the source is connected to the collector of the eleventh transistor Q11.

[0015] The eleventh PNP transistor Q11 has its emitter and base grounded;

[0016] The thirteenth PMOS transistor Q13 has its source connected to a high level VDD and its drain connected to the drain of the sixteenth NMOS transistor Q16.

[0017] The source of the sixteenth NMOS transistor Q16 is connected to the collector of the twelfth PNP transistor Q12 through the eleventh resistor R11.

[0018] The twelfth PNP transistor Q12 has its emitter and base grounded;

[0019] The seventeenth NMOS transistor Q17 has its drain connected to a high level VDD through the twelfth resistor R12, its source grounded, and its gate connected to the drain of the thirteenth PMOS transistor Q13.

[0020] Furthermore, the eleventh PNP transistor Q11 and the twelfth PNP transistor Q12 have different areas;

[0021] The width-to-length ratio of the thirteenth PMOS transistor Q13 and the fourteenth PMOS transistor Q14 is the same;

[0022] The width-to-length ratio of the fifteenth NMOS transistor Q15 and the sixteenth NMOS transistor Q16 is the same.

[0023] Furthermore, the Schmitt trigger module includes:

[0024] The source of the 24th PMOS transistor Q24 is connected to the high level VDD, the drain is connected to the drain of the 21st NMOS transistor Q21, the gate is connected to the gate of the 21st NMOS transistor Q21 as the input terminal, the source of the 21st NMOS transistor Q21 is grounded, and the drain of the 21st NMOS transistor Q21 is connected to the first reference point through the 21st resistor R21.

[0025] The source of the 25th PMOS transistor Q25 is connected to a high level VDD, the drain is connected to the drain of the 22nd NMOS transistor Q22, the gate is connected to the first reference point, the first reference point is connected to the gate of the 22nd NMOS transistor Q22, and the source of the 22nd NMOS transistor Q22 is grounded.

[0026] The 26th PMOS transistor Q26 has its source connected to a high level VDD, its drain connected to the drain of the 23rd NMOS transistor Q23, and its gate connected to the second reference point. The second reference point is connected to the gate of the 23rd NMOS transistor Q23 and the drain of the 22nd NMOS transistor Q22. The source of the 23rd NMOS transistor Q23 is grounded, and its drain is connected to the first reference point through the 22nd resistor R22.

[0027] The present invention also provides an integrated circuit chip, the integrated circuit chip including a packaging structure and an internal circuit, the internal circuit including the aforementioned integrated circuit on-chip aging detection circuit.

[0028] The beneficial effects of this invention are: firstly, as an IP for chip aging detection, it can detect how long a chip has been used and whether it is severely aged. Secondly, unlike other aging detection circuits based on oscillators, this invention can detect the degree of chip aging at different temperatures, with temperature having minimal impact on the detection results. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the module structure of the present invention.

[0030] Figure 2 This is the circuit diagram of the signal sampling and processing module.

[0031] Figure 3 This is the circuit diagram of a voltage-controlled oscillator.

[0032] Figure 4 This is the circuit diagram of a Schmitt trigger. Detailed Implementation

[0033] Voltage-controlled oscillators (VCOs) exhibit varying output waveform periods at different aging stages. However, this data is significantly affected by temperature. A temperature change of approximately 25 degrees Celsius is equivalent to 10 years of oscillator aging, thus temperature variations can introduce substantial errors into chip aging measurements. This invention proposes a chip aging test circuit for VCOs with temperature negative feedback, overcoming this deficiency.

[0034] See Figures 1-4 The on-chip detection circuit of this invention includes: a signal sampling and processing module, a voltage-controlled oscillator (VCO) circuit, and a Schmitt trigger. The signal sampling and processing module consists of a voltage reference and a common-source amplifier. The voltage reference provides a voltage signal proportional to temperature, and the common-source amplifier amplifies the voltage signal to a factor sufficient for subsequent circuitry. The input of the VCO module is connected to the output voltage of the temperature feedback module. The Schmitt trigger shapes the output waveform of the VCO.

[0035] The signal sampling and processing module generates a temperature-related signal, which is then amplified to an appropriate output and amplification factor before being passed to the next stage. The voltage at the voltage control terminal of the voltage-controlled oscillator (VCO) varies at different temperatures, thus suppressing the effects of temperature. A Schmitt trigger shapes the VCO output waveform, ultimately producing a waveform related to the degree of aging.

[0036] Example

[0037] like Figure 2 As shown, the eleventh PNP transistor Q11 and the twelfth PNP transistor Q12 are two PNP transistors with different areas. These two transistors provide a variable voltage signal as the temperature changes.

[0038] The thirteenth PMOS transistor Q13 and the fourteenth PMOS transistor Q14 are two identical PMOS transistors.

[0039] The fifteenth NMOS transistor Q15 and the sixteenth NMOS transistor Q16 are two identical NMOS transistors.

[0040] The area ratio of the two PNP transistors Q11:Q12 is 1:25; the width-to-length ratio of the two NMOS transistors Q15 and Q16 is 2µm / 180µm; the width-to-length ratio of the two PMOS transistors Q13 and Q14 is 2µm / 180µm; the eleventh resistor R11 has a resistance of 500 ohms; the twelfth resistor R12 has a resistance of 4.75 kΩ; the seventeenth NMOS transistor Q17 has a width-to-length ratio of 2µm / 1µm; VDD is 1.8V. All MOS transistors operate in the saturation region.

[0041] Given the Sachtang equation

[0042]

[0043] The seventeenth NMOS transistor Q17 and the twelfth resistor R12 form a basic common-source amplifier circuit. Its input signal is the voltage signal at the drain of the sixteenth NMOS transistor Q16. Since the input voltage is related to the NMOS transistor, some of the nonlinearity of the threshold voltage change of the seventeenth NMOS transistor Q17 can be reduced. During the design, adjusting the width-to-length ratio of the seventeenth NMOS transistor Q17 and the value of the resistor can ensure that the output voltage is within a suitable amplification range and suitable for the operation of the voltage-controlled oscillator.

[0044] Figure 3 This is a voltage-controlled oscillator (VCO) circuit. The ring oscillator is composed of an odd number of inverters connected end to end. Let's analyze one stage, MP1, MN1, and MN2. MP1 and MN2 form an inverter. The input signal of each inverter stage is connected to the input signal of the previous stage. The input signal of the first stage is determined by the output signal of the last stage.

[0045] The oscillation frequency of the ring oscillator is determined by the length of the inverter chain and the delay of each inverter. The circuit consists of five inverter stages (three are shown in the diagram). The oscillation frequency is determined by the RC delay of each inverter. The parasitic capacitance C is also fixed.

[0046] The gate voltage of MN1 is determined by Figure 3 An NMOS transistor with output voltage control. This transistor operates in the linear region when turned on, and its on-resistance is determined by the difference between the input voltage and the threshold voltage.

[0047]

[0048] The larger the input voltage, the more V GS The larger the value of V, the smaller the on-resistance and the shorter the delay. GS At a large value, the on-resistance varies with V. GS The changes will be relatively smooth.

[0049] V GS The change in V is used to suppress the effects of temperature changes on the oscillator. When the temperature changes, V GS The change is such that it exactly offsets the effect of temperature on the oscillator's oscillation frequency. Therefore, the oscillator is no longer sensitive to temperature, but mainly sensitive to aging of the threshold voltage caused by effects such as HCI and NBTI.

[0050] at last, Figure 3 The circuit continuously outputs high and low levels. By observing the duration or frequency of these high and low levels, the threshold voltage can be determined. This process is no longer sensitive to temperature. When the threshold voltage differs significantly from the initial threshold voltage of the chip (i.e., when the oscillator output frequency changes excessively), the chip can be considered aged.

[0051] Figure 3 In the diagram, the aspect ratio of MP1 is 1u / 180n; the aspect ratio of MN1 is 220n / 1u; the aspect ratio of MN2 is 1u / 180n; the aspect ratio of MP2 is 1u / 180n; the aspect ratio of MN3 is 220n / 1u; the aspect ratio of MN4 is 1u / 180n; the aspect ratio of MP3 is 1u / 180n; the aspect ratio of MN5 is 220n / 1u; and the aspect ratio of MN6 is 1u / 180n.

[0052] Figure 4 It is a Schmitt trigger that shapes the output waveform of the oscillator, making the waveform a qualified pulse wave.

[0053] The 21st resistor R21 has a resistance of 10K ohms, and the 22nd resistor R22 has a resistance of 20K ohms; the three PMOS transistors (Q24, Q25, Q26) have a width-to-length ratio of 2u / 1u; the three NMOS transistors (Q21, Q22, Q23) have a width-to-length ratio of 1u / 1u.

Claims

1. An on-chip aging detection circuit for integrated circuits, characterized in that, It includes a signal sampling and processing module, a voltage-controlled oscillator, and a Schmitt trigger module connected in series; The signal sampling and processing module outputs a voltage signal that is positively correlated with temperature to the voltage-controlled oscillator. The Schmitt trigger shapes the output waveform of the voltage-controlled oscillator; The voltage-controlled oscillator is composed of an odd number of inverters with identical structures arranged in sequence; Each inverter includes a first PMOS transistor, a first NMOS transistor, and a second NMOS transistor; the source of the first PMOS transistor is connected to the high-level terminal VDD, the drain is used as the output terminal, and the gate is used as the input terminal; the drain of the first NMOS transistor is connected to the drain of the first PMOS transistor, the source is connected to the drain of the second NMOS transistor, and the gate is connected to the control signal input terminal; the source of the second NMOS transistor is grounded, and the gate is connected to the gate of the first PMOS transistor. In two adjacent inverters, the output of the preceding inverter is connected to the input of the following inverter; The output of the final stage inverter is connected to the input of the first stage inverter. The signal sampling and processing module includes: The source of the fourteenth PMOS transistor (Q14) is connected to the high level VDD, the drain is connected to the drain of the fifteenth NMOS transistor (Q15), and the gate is connected to the gate and drain of the thirteenth PMOS transistor (Q13). The drain and gate of the fifteenth NMOS transistor (Q15) are connected to the gate of the sixteenth NMOS transistor (Q16), and the source is connected to the collector of the eleventh transistor (Q11). The eleventh PNP transistor (Q11) has its emitter and base grounded; The thirteenth PMOS transistor (Q13) has its source connected to a high level VDD and its drain connected to the drain of the sixteenth NMOS transistor (Q16). The source of the sixteenth NMOS transistor (Q16) is connected to the collector of the twelfth PNP transistor (Q12) through the eleventh resistor (R11); The twelfth PNP transistor (Q12) has its emitter and base grounded; The seventeenth NMOS transistor (Q17) has its drain connected to the high level VDD through the twelfth resistor (R12), its source grounded, and its gate connected to the drain of the thirteenth PMOS transistor (Q13). The eleventh PNP transistor (Q11) and the twelfth PNP transistor (Q12) have different areas; The width-to-length ratio of the thirteenth PMOS transistor (Q13) and the fourteenth PMOS transistor (Q14) is the same; The width-to-length ratio of the fifteenth NMOS transistor (Q15) and the sixteenth NMOS transistor (Q16) is the same.

2. The integrated circuit on-chip aging detection circuit as described in claim 1, characterized in that, The Schmitt trigger module includes: The source of the 24th PMOS transistor (Q24) is connected to a high level VDD, the drain is connected to the drain of the 21st NMOS transistor (Q21), the gate is connected to the gate of the 21st NMOS transistor (Q21) as the input terminal, the source of the 21st NMOS transistor (Q21) is grounded, and the drain of the 21st NMOS transistor (Q21) is connected to the first reference point through the 21st resistor (R21). The source of the 25th PMOS transistor (Q25) is connected to a high level VDD, the drain is connected to the drain of the 22nd NMOS transistor (Q22), the gate is connected to the first reference point, the first reference point is connected to the gate of the 22nd NMOS transistor (Q22), and the source of the 22nd NMOS transistor (Q22) is grounded. The source of the 26th PMOS transistor (Q26) is connected to a high level VDD, the drain is connected to the drain of the 23rd NMOS transistor (Q23), and the gate is connected to the second reference point. The second reference point is connected to the gate of the 23rd NMOS transistor (Q23) and the drain of the 22nd NMOS transistor (Q22). The source of the 23rd NMOS transistor (Q23) is grounded, and the drain is connected to the first reference point through the 22nd resistor (R22).

3. An integrated circuit chip, comprising a packaging structure and internal circuitry, characterized in that, The internal circuit includes an on-chip aging detection circuit for integrated circuits, which includes a signal sampling and processing module, a voltage-controlled oscillator, and a Schmitt trigger module connected in series. The signal sampling and processing module outputs a voltage signal that is positively correlated with temperature to the voltage-controlled oscillator. The Schmitt trigger shapes the output waveform of the voltage-controlled oscillator; The voltage-controlled oscillator is composed of an odd number of inverters with identical structures arranged in sequence; Each inverter includes a first PMOS transistor, a first NMOS transistor, and a second NMOS transistor; the source of the first PMOS transistor is connected to the high-level terminal VDD, the drain is used as the output terminal, and the gate is used as the input terminal; the drain of the first NMOS transistor is connected to the drain of the first PMOS transistor, the source is connected to the drain of the second NMOS transistor, and the gate is connected to the control signal input terminal; the source of the second NMOS transistor is grounded, and the gate is connected to the gate of the first PMOS transistor. In two adjacent inverters, the output of the preceding inverter is connected to the input of the following inverter; The output of the final stage inverter is connected to the input of the first stage inverter. The signal sampling and processing module includes: The source of the fourteenth PMOS transistor (Q14) is connected to the high level VDD, the drain is connected to the drain of the fifteenth NMOS transistor (Q15), and the gate is connected to the gate and drain of the thirteenth PMOS transistor (Q13). The drain and gate of the fifteenth NMOS transistor (Q15) are connected to the gate of the sixteenth NMOS transistor (Q16), and the source is connected to the collector of the eleventh transistor (Q11). The eleventh PNP transistor (Q11) has its emitter and base grounded; The thirteenth PMOS transistor (Q13) has its source connected to a high level VDD and its drain connected to the drain of the sixteenth NMOS transistor (Q16). The source of the sixteenth NMOS transistor (Q16) is connected to the collector of the twelfth PNP transistor (Q12) through the eleventh resistor (R11); The twelfth PNP transistor (Q12) has its emitter and base grounded; The seventeenth NMOS transistor (Q17) has its drain connected to the high level VDD through the twelfth resistor (R12), its source grounded, and its gate connected to the drain of the thirteenth PMOS transistor (Q13).

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