Asynchronous mouse trap handshake unit and system with matching delays

Abstract

The application belongs to the field of asynchronous circuits, and discloses an asynchronous MouseTrap handshake unit with a matching delay and a system, the handshake unit comprising: a delay latch, a self-clock generator and an output inverter; an enabling output end of the self-clock generator is connected with an enabling input end of the delay latch, and output ends of the delay latch are respectively connected with an input end of the self-clock generator and an input end of the output inverter; the delay latch comprises: a Schmitt trigger unit, and a delay module is arranged on an input side of the Schmitt trigger unit, and the delay module is used for making the Schmitt trigger unit produce a delay. The circuit structure of the application is simple, the Schmitt trigger unit can increase the driving capacity of the delay latch, and dynamic power consumption is reduced.

Description

Technical Field

[0001] This invention belongs to the field of asynchronous circuits, specifically relating to an asynchronous MouseTrap handshake unit and system with built-in matching delay. Background Technology

[0002] Asynchronous circuits are a type of sequential circuit that does not require synchronous clock signal control. Asynchronous self-clocking circuits are a type of sequential circuit in which a circuit module generates its own local clock signal to drive the data path as needed. These include self-clocking state machines and asynchronous self-clocking handshake circuits.

[0003] The MouseTrap asynchronous self-clocking circuit is a self-clocking asynchronous circuit structure first proposed in 2007. It is a binary asynchronous handshake circuit based on latches and XNOR gates, and is often used for self-clocking control of high-speed binary protocol pipelines or controllers based on C2MOS dynamic logic or latches.

[0004] Delay units are commonly used in VLSI digital circuit design as standard cells to introduce delays in the signal path. They have functions such as adjusting clock distribution, timing synchronization, and signal alignment. Asynchronous circuits need to insert delay units to match the transmission delay of the data path they control.

[0005] There are currently three types of delay cells in terms of design structure: buffer-based delay cells, RC oscillator-based delay cells, and LC circuit-based oscillator cells. Among these, buffer-based delay cells are commonly used in VLSI design. Their circuit structure consists of multiple stages of interconnected inverters. While they have advantages such as small area and simple structure, they have shorter delay times and poorer driving capability. RC oscillator delay cells can achieve larger delay times, but their circuit structure is complex, dynamic power consumption is high, and their area is large, making them unsuitable for low-power asynchronous circuit designs. LC circuits cannot be used in standard cell designs because they require inductors. Summary of the Invention

[0006] The purpose of this invention is to provide an asynchronous MouseTrap handshake unit and system with built-in matching delay, in order to solve the problem that the existing technology cannot simultaneously combine the advantages of small size, simple structure, long delay time and low efficiency.

[0007] To achieve the above objectives, the present invention adopts the following technical solution:

[0008] In a first aspect, the present invention provides an asynchronous MouseTrap handshake unit with built-in matching delay. The handshake unit includes: a delay latch, a self-clock generator, and an output inverter; the enable output terminal of the self-clock generator is connected to the enable input terminal of the delay latch, and the output terminal of the delay latch is connected to the input terminal of the self-clock generator and the input terminal of the output inverter, respectively.

[0009] The delay latch includes a Schmitt trigger unit, on the input side of which a delay module is deployed, the delay module being used to cause the Schmitt trigger unit to generate a delay.

[0010] Preferably, the delay latch further includes an output conversion unit, the input of which is connected to the output of the Schmitt trigger unit, and the output of the output conversion unit is used as the output of the delay latch, which is connected to the input of the self-clock generator and the input of the output inverter, respectively.

[0011] Preferably, the Schmitt trigger unit includes: a first MOS transistor, a third MOS transistor, an eighth MOS transistor, a tenth MOS transistor, a twelfth MOS transistor, a seventeenth MOS transistor, and a nineteenth MOS transistor; wherein the first MOS transistor, the third MOS transistor, the eighth MOS transistor, and the tenth MOS transistor are all N-type MOS transistors, and the twelfth MOS transistor, the seventeenth MOS transistor, and the nineteenth MOS transistor are all P-type MOS transistors;

[0012] The gate of the first MOS transistor is the enable input terminal of the delay latch, and the gate of the first MOS transistor is connected to the enable output terminal of the self-clock generator.

[0013] The drain of the first MOS transistor is connected to the gate of the eighth MOS transistor and the drain of the twelfth MOS transistor, respectively; the source of the first MOS transistor is connected to the drain of the third MOS transistor and the gate of the seventeenth MOS transistor, respectively.

[0014] The source of the twelfth MOS transistor is connected to the drain of the nineteenth MOS transistor and the drain of the seventeenth MOS transistor, respectively.

[0015] The source of the third MOS transistor is connected to the drain of the tenth MOS transistor and the drain of the eighth MOS transistor, respectively.

[0016] The source of the tenth MOS transistor and the source of the seventeenth MOS transistor are both grounded, and the source of the nineteenth MOS transistor and the source of the eighth MOS transistor are both connected to the power supply.

[0017] The gates of the tenth MOSFET, the third MOSFET, the twelfth MOSFET, and the nineteenth MOSFET are used as the request input terminals of the delay latch;

[0018] The gates of the eighth MOS transistor and the seventeenth MOS transistor are both used as the output terminals of the Schmitt trigger unit.

[0019] Preferably, the nineteenth MOSFET and the tenth MOSFET are used as delay modules.

[0020] Preferably, the output conversion unit includes: an eleventh MOSFET, a second MOSFET, a thirteenth MOSFET, and a fourth MOSFET; wherein the eleventh MOSFET and the thirteenth MOSFET are both P-type MOSFETs, and the second MOSFET and the fourth MOSFET are both N-type MOSFETs;

[0021] The gate of the eleventh MOS transistor is connected to the gate of the second MOS transistor, the drain of the thirteenth MOS transistor, and the drain of the fourth MOS transistor, respectively.

[0022] The source of the thirteenth MOSFET and the source of the eleventh MOSFET are both connected to the power supply, and the source of the second MOSFET and the source of the fourth MOSFET are both grounded.

[0023] The gates of the thirteenth MOS transistor and the fourth MOS transistor are both used as input terminals of the output conversion unit. The gate of the thirteenth MOS transistor is connected to the gate of the eighth MOS transistor, and the gate of the fourth MOS transistor is connected to the gate of the seventeenth MOS transistor.

[0024] The common terminal of the drain of the eleventh MOSFET and the drain of the second MOSFET is used as the output terminal of the output conversion unit.

[0025] Preferably, the self-clock generator includes: a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, a fourteenth MOS transistor, a fifteenth MOS transistor, and a sixteenth MOS transistor; wherein the fifth MOS transistor, the sixth MOS transistor, and the seventh MOS transistor are all N-type MOS transistors, and the fourteenth MOS transistor, the fifteenth MOS transistor, and the sixteenth MOS transistor are all P-type MOS transistors;

[0026] The source of the fifteenth MOS transistor is connected to the drain of the sixteenth MOS transistor, and the drain of the fifteenth MOS transistor is connected to the drain of the sixth MOS transistor, the drain of the seventh MOS transistor, the gate of the fourteenth MOS transistor, and the gate of the fifth MOS transistor.

[0027] The gate of the sixteenth MOS transistor is connected to the gate of the seventh MOS transistor and the source of the sixth MOS transistor, respectively, and the common terminal of the gate of the sixteenth MOS transistor, the gate of the seventh MOS transistor and the source of the sixth MOS transistor is used as the response input terminal of the self-clock generator.

[0028] The gate of the fifteenth MOS transistor is connected to the gate of the sixth MOS transistor and the source of the seventh MOS transistor, respectively. The common terminal of the gate of the fifteenth MOS transistor, the gate of the sixth MOS transistor and the source of the seventh MOS transistor is used as the input terminal of the self-clock generator and connected to the output terminal of the delay latch.

[0029] The drain of the fourteenth MOS transistor is connected to the drain of the fifth MOS transistor, and the common terminal of the drain of the fourteenth MOS transistor and the drain of the fifth MOS transistor is used as the enable output terminal of the self-clock generator and connected to the enable input terminal of the delay latch.

[0030] The source of the fourteenth MOS transistor and the source of the sixteenth MOS transistor are both connected to the power supply, and the source of the fifth MOS transistor is grounded.

[0031] Preferably, the output inverter includes an eighteenth MOS transistor and a ninth MOS transistor, wherein the eighteenth MOS transistor is a P-type MOS transistor and the ninth MOS transistor is an N-type MOS transistor;

[0032] The drain of the eighteenth MOS transistor is connected to the drain of the ninth MOS transistor, and the common terminal of the drain of the eighteenth MOS transistor and the drain of the ninth MOS transistor is used as the output terminal of the output inverter.

[0033] The gate of the eighteenth MOS transistor is connected to the gate of the ninth MOS transistor, and the common terminal of the gate of the eighteenth MOS transistor and the gate of the ninth MOS transistor is used as the input terminal of the output inverter.

[0034] The source of the eighteenth MOS transistor is connected to the power supply, and the source of the ninth MOS transistor is grounded.

[0035] Secondly, the present invention provides a handshake system, the system comprising: a plurality of asynchronous MouseTrap handshake units with built-in matching delays, the plurality of asynchronous MouseTrap handshake units with built-in matching delays being connected in series, and the output terminal of the output inverter of the k-th asynchronous MouseTrap handshake unit with built-in matching delays being connected to the request input terminal of the delay latch of the (k+1)-th asynchronous MouseTrap handshake unit with built-in matching delays, and the output terminal of the output inverter of the (k+1)-th asynchronous MouseTrap handshake unit with built-in matching delays being connected to the response input terminal of the self-clock generator of the k-th asynchronous MouseTrap handshake unit with built-in matching delays; wherein, k is a positive integer.

[0036] Beneficial effects:

[0037] 1. The delay latch of the present invention utilizes the hysteresis characteristic of the Schmitt trigger unit to generate a hysteresis effect during the voltage rise in the charging process, thereby ensuring the slope of the output signal of the handshake unit.

[0038] 2. The handshake unit of the present invention can reuse the same circuit, and the delay module can meet the requirements of different delay times without changing the topology of the circuit layout;

[0039] 3. The circuit structure of the present invention is simple, and the Schmitt trigger unit can increase the driving capability of the delay latch and reduce dynamic power consumption. Attached Figure Description

[0040] The accompanying drawings are provided to further illustrate embodiments of the present invention and form part of the specification. They are used together with the following detailed description to explain the embodiments of the present invention, but do not constitute a limitation thereof. In the drawings:

[0041] Figure 1 This is a block diagram of an asynchronous MouseTrap handshake unit with built-in matching delay provided in one embodiment of the present invention;

[0042] Figure 2 This is a schematic diagram of an asynchronous MouseTrap handshake unit with built-in matching delay provided in one embodiment of the present invention;

[0043] Figure 3 This is a block diagram of a handshake system provided in one embodiment of the present invention.

[0044] Explanation of reference numerals in the attached figures:

[0045] mn0, first MOSFET; mn1, second MOSFET; mn2, third MOSFET; mn3, fourth MOSFET; mn4, fifth MOSFET; mn5, sixth MOSFET; mn6, seventh MOSFET; mn7, eighth MOSFET; mn8, ninth MOSFET; mn9, tenth MOSFET; mp1, eleventh MOSFET; mp2, twelfth MOSFET; mp3, thirteenth MOSFET; mp4, fourteenth MOSFET; mp5, fifteenth MOSFET; mp6, sixteenth MOSFET; mp7, seventeenth MOSFET; mp8, eighteenth MOSFET; mp9, nineteenth MOSFET. Detailed Implementation

[0046] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the present invention will be briefly introduced below in conjunction with the accompanying drawings and descriptions of the embodiments or the prior art. Obviously, the following description of the structure of the accompanying drawings is only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. It should be noted that the description of these embodiments is for the purpose of helping to understand the present invention, but does not constitute a limitation of the present invention.

[0047] Example 1

[0048] Figure 1 This is a block diagram of an asynchronous MouseTrap handshake unit with built-in matching delay provided in one embodiment of the present invention. Figure 1 As shown, this embodiment provides a handshake unit including: a delay latch, a self-clock generator, and an output inverter; the enable output terminal of the self-clock generator is connected to the enable input terminal of the delay latch, and the output terminal of the delay latch is connected to the input terminal of the self-clock generator and the input terminal of the output inverter, respectively.

[0049] The delay latch includes a Schmitt trigger unit, on the input side of which a delay module is deployed, the delay module being used to cause the Schmitt trigger unit to generate a delay.

[0050] In this embodiment, the self-clock generator has an acknowledgment input terminal. By adjusting the high or low level of the acknowledgment signal at the acknowledgment input terminal, the enable signal output by the enable output terminal of the self-clock generator can be adjusted. The enable signal can adjust the state of the delay latch. The state of the delay latch includes a pass-through state and a latched state. For example, when the enable signal is high, the delay latch is in the pass-through state; when the enable signal is low, the delay latch is in the latched state.

[0051] Taking the request input signal of the delay latch as an example, when the delay latch is in the pass-through state, it is used to transmit the request input signal of the delay latch; when the delay latch is in the latched state, it is used to latch the request input signal of the delay latch.

[0052] In this embodiment, the delay module is mainly used to generate a delay that can be self-adjusted; therefore, the handshake unit can reuse the same circuit, and the delay module can meet the requirements of different delay times without changing the topology of the layout.

[0053] In this embodiment, the present invention generates an enable signal by a self-clock generator based on transmission gate logic, eliminating the need for an enable signal generator based on CMOS logic. This reduces the number of transistors used and simplifies the circuit structure. The reduced number of circuit components also lowers static power consumption. Furthermore, the Schmitt trigger unit can increase the driving capability of the delay latch and reduce dynamic power consumption.

[0054] In this embodiment, the delay latch utilizes the hysteresis characteristic of the Schmitt trigger unit to generate a hysteresis effect during the voltage rise of the charging process, thereby ensuring the slope of the output signal of the handshake unit.

[0055] As a further optimization of this embodiment, the delay latch further includes: an output conversion unit, the input terminal of which is connected to the output terminal of the Schmitt trigger unit, and the output terminal of the output conversion unit is used as the output terminal of the delay latch, which is connected to the input terminal of the self-clock generator and the input terminal of the output inverter, respectively.

[0056] As a further optimization of this embodiment, such as Figure 2 As shown, the Schmitt trigger unit includes: a first MOSFET mn0, a third MOSFET mn2, an eighth MOSFET mn7, a tenth MOSFET mn9, a twelfth MOSFET mp2, a seventeenth MOSFET mp7, and a nineteenth MOSFET mp9; wherein the first MOSFET mn0, the third MOSFET mn2, the eighth MOSFET mn7, and the tenth MOSFET mn9 are all N-type MOSFETs, and the twelfth MOSFET mp2, the seventeenth MOSFET mp7, and the nineteenth MOSFET mp9 are all P-type MOSFETs; wherein the nineteenth MOSFET mp9 and the tenth MOSFET mn9 are used as delay modules, and both the nineteenth MOSFET mp9 and the tenth MOSFET mn9 are inverted proportional transistors. An inverted proportional transistor is a MOSFET with a channel length greater than its channel width, which can be used to increase the gate capacitance and reduce the source-drain conduction current. Different delay times can be achieved by finely adjusting the channel length of the inverted proportional transistor without changing the topology of the circuit layout.

[0057] In this embodiment, the gate of the first MOSFET mn0 is the enable input of the delay latch. When the gate of the first MOSFET mn0 is high, the third MOSFET mn2, the eighth MOSFET mn7, the tenth MOSFET mn9, the twelfth MOSFET mp2, the seventeenth MOSFET mp7, and the nineteenth MOSFET mp9 automatically form a Schmitt trigger structure. When the gate of the first MOSFET mn0 is low, the third MOSFET mn2, the eighth MOSFET mn7, the tenth MOSFET mn9, the twelfth MOSFET mp2, the seventeenth MOSFET mp7, and the nineteenth MOSFET mp9 cannot be turned on, the Schmitt trigger structure is released, and the delay latch is in a latched state. Therefore, the inverting proportional transistor and the Schmitt trigger unit increase the driving capability of the delay latch and reduce dynamic power consumption.

[0058] The gate of the first MOS transistor mn0 is the enable input terminal of the delay latch, and the gate of the first MOS transistor mn0 is connected to the enable output terminal of the self-clock generator.

[0059] The drain of the first MOS transistor mn0 is connected to the gate of the eighth MOS transistor mn7 and the drain of the twelfth MOS transistor mp2, respectively; the source of the first MOS transistor mn0 is connected to the drain of the third MOS transistor mn2 and the gate of the seventeenth MOS transistor mp7, respectively.

[0060] The source of the twelfth MOS transistor mp2 is connected to the drain of the nineteenth MOS transistor mp9 and the drain of the seventeenth MOS transistor mp7, respectively.

[0061] The source of the third MOS transistor mn2 is connected to the drain of the tenth MOS transistor mn9 and the drain of the eighth MOS transistor mn7, respectively.

[0062] The sources of the tenth MOSFET mn9 and the seventeenth MOSFET mp7 are both grounded, while the sources of the nineteenth MOSFET mp9 and the eighth MOSFET mn7 are both connected to a power supply. The power supply is the attached... Figure 2 vcc in;

[0063] The gates of the tenth MOSFET mn9, the third MOSFET mn2, the twelfth MOSFET mp2, and the nineteenth MOSFET mp9 are used as the request input terminals of the delay latch.

[0064] The gates of the eighth MOS transistor mn7 and the seventeenth MOS transistor mp7 are both used as the output terminals of the Schmitt trigger unit.

[0065] As a further optimization of this embodiment, the output conversion unit includes: an eleventh MOS transistor mp1, a second MOS transistor mn1, a thirteenth MOS transistor mp3, and a fourth MOS transistor mn3; wherein, the eleventh MOS transistor mp1 and the thirteenth MOS transistor mp3 are both P-type MOS transistors, and the second MOS transistor mn1 and the fourth MOS transistor mn3 are both N-type MOS transistors;

[0066] The gate of the eleventh MOS transistor mp1 is connected to the gate of the second MOS transistor mn1, the drain of the thirteenth MOS transistor mp3, and the drain of the fourth MOS transistor mn3, respectively.

[0067] The sources of the thirteenth MOSFET mp3 and the eleventh MOSFET mp1 are both connected to a power supply, while the sources of the second MOSFET mn1 and the fourth MOSFET mn3 are both grounded. Grounding is an auxiliary... Figure 2 gnd in;

[0068] The gates of the thirteenth MOS transistor mp3 and the fourth MOS transistor mn3 are both used as input terminals of the output conversion unit. The gate of the thirteenth MOS transistor mp3 is connected to the gate of the eighth MOS transistor mn7, and the gate of the fourth MOS transistor mn3 is connected to the gate of the seventeenth MOS transistor mp7.

[0069] The common terminal of the drain of the eleventh MOS transistor mp1 and the drain of the second MOS transistor mn1 is used as the output terminal of the output conversion unit.

[0070] As a further optimization of this embodiment, such as Figure 2 As shown, the self-clock generator includes: a fifth MOSFET mn4, a sixth MOSFET mn5, a seventh MOSFET mn6, a fourteenth MOSFET mp4, a fifteenth MOSFET mp5, and a sixteenth MOSFET mp6; wherein, the fifth MOSFET mn4, the sixth MOSFET mn5, and the seventh MOSFET mn6 are all N-type MOSFETs, and the fourteenth MOSFET mp4, the fifteenth MOSFET mp5, and the sixteenth MOSFET mp6 are all P-type MOSFETs;

[0071] The source of the fifteenth MOS transistor mp5 is connected to the drain of the sixteenth MOS transistor mp6, and the drain of the fifteenth MOS transistor mp5 is connected to the drain of the sixth MOS transistor mn5, the drain of the seventh MOS transistor mn6, the gate of the fourteenth MOS transistor mp4, and the gate of the fifth MOS transistor mn4.

[0072] The gate of the sixteenth MOS transistor mp6 is connected to the gate of the seventh MOS transistor mn6 and the source of the sixth MOS transistor mn5, and the common terminal of the gate of the sixteenth MOS transistor mp6, the gate of the seventh MOS transistor mn6 and the source of the sixth MOS transistor mn5 is used as the response input terminal of the self-clock generator.

[0073] The gate of the fifteenth MOS transistor mp5 is connected to the gate of the sixth MOS transistor mn5 and the source of the seventh MOS transistor mn6, respectively. The common terminal of the gate of the fifteenth MOS transistor mp5, the gate of the sixth MOS transistor mn5 and the source of the seventh MOS transistor mn6 is used as the input terminal of the self-clock generator and connected to the output terminal of the delay latch.

[0074] The drain of the fourteenth MOS transistor mp4 is connected to the drain of the fifth MOS transistor mn4, and the common terminal of the drain of the fourteenth MOS transistor mp4 and the drain of the fifth MOS transistor mn4 is used as the enable output terminal of the self-clock generator and connected to the enable input terminal of the delay latch.

[0075] The source of the fourteenth MOS transistor mp4 and the source of the sixteenth MOS transistor mp6 are both connected to the power supply, and the source of the fifth MOS transistor mn4 is grounded.

[0076] In this embodiment, the self-clock generator setting can reduce the number of transistors used in the delay latch and reduce static power consumption.

[0077] As a further optimization of this embodiment, such as Figure 2As shown, the output inverter includes: an eighteenth MOS transistor mp8 and a ninth MOS transistor mn8, wherein the eighteenth MOS transistor mp8 is a P-type MOS transistor and the ninth MOS transistor mn8 is an N-type MOS transistor;

[0078] The drain of the eighteenth MOS transistor mp8 is connected to the drain of the ninth MOS transistor mn8, and the common terminal of the drain of the eighteenth MOS transistor mp8 and the drain of the ninth MOS transistor mn8 is used as the output terminal of the output inverter.

[0079] The gate of the eighteenth MOS transistor mp8 is connected to the gate of the ninth MOS transistor mn8, and the common terminal of the gate of the eighteenth MOS transistor mp8 and the gate of the ninth MOS transistor mn8 is used as the input terminal of the output inverter.

[0080] The source of the eighteenth MOS transistor mp8 is connected to the power supply, and the source of the ninth MOS transistor mn8 is grounded.

[0081] In this embodiment, with Figure 2 For example, the common terminal connection of the nineteenth MOSFET mp9, the seventeenth MOSFET mp7, and the twelfth MOSFET mp2 is marked as n1; the common terminal connection of the twelfth MOSFET mp2, the thirteenth MOSFET mp3, the first MOSFET mn0, and the eighth MOSFET mn7 is marked as n2; the common terminal connection of the first MOSFET mn0, the fourth MOSFET mn3, the third MOSFET mn2, and the seventeenth MOSFET mp7 is marked as n3; the common terminal connection of the tenth MOSFET mn9, the third MOSFET mn2, and the eighth MOSFET mn7 is marked as n4; the common terminal connection of the first MOSFET mn0, the fourteenth MOSFET mp4, and the fifth MOSFET mn4 is marked as e; and the common terminal connection of the thirteenth MOSFET mp3... The common terminal connection of the eleventh MOSFET mp1, the second MOSFET mn1, and the fourth MOSFET mn3 is marked as n6. The common terminal connection of the fourteenth MOSFET mp4, the fifteenth MOSFET mp5, the sixth MOSFET mn5, and the fifth MOSFET mn4 is marked as n5. The connection between the fifteenth MOSFET mp5 and the sixteenth MOSFET mp6 is marked as n6. The common terminal connection of the eleventh MOSFET mp1, the second MOSFET mn1, the sixth MOSFET mn5, the seventh MOSFET mn6, the fifteenth MOSFET mp5, the eighteenth MOSFET mp8, and MOSFET mm8 is marked as n7. The acknowledge input is marked as ack, the request input is marked as req, and the output of the output inverter is marked as done.

[0082] Therefore, when the output done is initially low, the acknowledgment input ack remains low, and the request input req changes from low to high, the handshake unit of this invention performs a request set transmission process. The working principle of the handshake unit is as follows:

[0083] 1. When the output done, the acknowledge input ack, and the request input req are initially low, then n5 is low, the enable signal e is high, the first MOSFET mn0 is turned on, and the delay latch is in punch-through state.

[0084] 2. When req becomes high, the gate capacitance of the nineteenth MOSFET mp9 and the tenth MOSFET mn9 begins to charge. When the voltage exceeds the Schmitt trigger voltage vtlh, the tenth MOSFET mn9 and the third MOSFET mn2 turn on, and the nineteenth MOSFET mp9 and the twelfth MOSFET mp2 turn off, so that n2 and n3 become low.

[0085] 3. When n2 goes low, it turns on the thirteenth MOSFET mp3. When n3 goes low, it turns off the fourth MOSFET mn3 and turns n6 high.

[0086] 4. When n6 goes high, the eleventh MOSFET mp1 is turned off, the second MOSFET mn1 is turned on, and n7 goes low.

[0087] 5. When n7 goes low, it causes n5 to go high, and the enable signal e goes low. The first MOSFET mn0 is turned off, the delay latch is in latched state, and the output done goes high.

[0088] When the output "done" is initially high, the acknowledge input "ack" remains high, and the request input "req" changes from high to low, the handshake unit performs a reset request transmission process. The working principle of the handshake unit is as follows:

[0089] 1. When the output done, the acknowledge input ack and the request input req are initially high, n5 is made low, the enable signal e is high, the first MOSFET mn0 is turned on, and the delay latch is in punch-through state;

[0090] 2. When req goes low, it begins to discharge the gate capacitance of the nineteenth MOSFET mp9 and the tenth MOSFET mn9. When the voltage is lower than the Schmitt trigger voltage vthl, the tenth MOSFET mn9 and the third MOSFET mn2 turn off, the nineteenth MOSFET mp9 and the twelfth MOSFET mp2 turn on, and n2 and n3 go high.

[0091] 3. When n2 goes high, the thirteenth MOSFET mp3 is turned off. When n3 goes high, the fourth MOSFET mn3 is turned on, and n6 goes low.

[0092] 4. When n6 goes low, the eleventh MOSFET mp1 is turned on, the second MOSFET mn1 is turned off, and n7 goes high.

[0093] 5. When n7 goes high, it causes n5 to go high and the enable signal e to go low. The first MOSFET mn0 is turned off, the delay latch is in latched state, and the output done goes low.

[0094] When the output "done" is initially low, the acknowledge input "ack" changes from high to low, and the request input "req" remains low, the handshake unit performs an acknowledge-reset transmission process. The working principle of the handshake unit is as follows:

[0095] 1. When the output done and the request input req are initially low, and the acknowledgment input ack is high, n5 is high, the enable signal e is low, the first MOSFET mn0 is turned off, and the delay latch is in latching state.

[0096] 2. When ack goes low, n5 goes low, the enable signal e goes high, the first MOSFET mn0 turns on, and the delay latch is in punch-through state.

[0097] Therefore, the delay latch of the present invention utilizes the hysteresis characteristic of the Schmitt trigger unit to generate a hysteresis effect during the voltage rise in the charging process, thereby ensuring the slope of the output signal of the handshake unit; the handshake unit can reuse the same circuit, and the delay module can meet the requirements of different delay times without changing the topology of the circuit layout; furthermore, the circuit structure of the present invention is simple, and the Schmitt trigger unit can increase the driving capability of the delay latch and reduce dynamic power consumption.

[0098] Example 2

[0099] Figure 3 This is a block diagram of a handshake system provided in one embodiment of the present invention. Figure 3 As shown, this embodiment provides a handshake system, which includes: multiple asynchronous MouseTrap handshake units with built-in matching delays, which are connected in series. The output terminal of the output inverter of the k-th asynchronous MouseTrap handshake unit with built-in matching delay is connected to the request input terminal of the delay latch of the (k+1)-th asynchronous MouseTrap handshake unit with built-in matching delay, and the output terminal of the output inverter of the (k+1)-th asynchronous MouseTrap handshake unit with built-in matching delay is connected to the response input terminal of the self-clock generator of the k-th asynchronous MouseTrap handshake unit with built-in matching delay; where k is a positive integer.

[0100] exist Figure 3The diagram illustrates the digital paths of two asynchronous MouseTrap handshake units with built-in matching delays. These digital paths are used to transmit data, which is then processed according to... Figure 3 The arrows in the diagram transmit data from left to right. The transmission delay generated by the delay latch is greater than the transmission delay of the kth computation unit plus the preset delay.

[0101] exist Figure 3 In this context, done[k] is the output of the inverter of the k-th asynchronous MouseTrap handshake unit with its own matching delay, done[k+1] is the output of the inverter of the (k+1)-th asynchronous MouseTrap handshake unit with its own matching delay, req[k] is the request input of the delay latch of the (k+1)-th asynchronous MouseTrap handshake unit with its own matching delay, req[k+1] is the request input of the delay latch of the (k+2)-th asynchronous MouseTrap handshake unit with its own matching delay, and req[k+1] is the request input of the delay latch of the (k+1)-th asynchronous MouseTrap handshake unit with its own matching delay. The request input of the delay latch of the useTrap handshake unit; ack[k] is the response input of the self-clock generator of the k asynchronous MouseTrap handshake units with matching delays, ack[k+1] is the response input of the self-clock generator of the k+1 asynchronous MouseTrap handshake units with matching delays; e[k] is the enable signal output of the self-clock generator of the k+1 asynchronous MouseTrap handshake unit with matching delays, e[k-1] is the enable signal output of the self-clock generator of the k asynchronous MouseTrap handshake unit with matching delays;

[0102] In this embodiment, when the two asynchronous MouseTrap handshake units with built-in matching delays are connected in series, done[k+1] is used as req[k+1] and done[k+1] is used as ack[k].

[0103] The delay latch of the present invention utilizes the hysteresis characteristic of the Schmitt trigger unit to generate a hysteresis effect during the voltage rise in the charging process, thereby ensuring the slope of the output signal of the handshake unit. The handshake unit can reuse the same circuit, and the delay module can meet the requirements of different delay times without changing the topology of the circuit layout. Furthermore, the circuit structure of the present invention is simple, and the Schmitt trigger unit can increase the driving capability of the delay latch and reduce dynamic power consumption.

[0104] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. An asynchronous MouseTrap handshake unit with built-in matching delay, characterized in that, The handshake unit includes: a delay latch, a self-clock generator, and an output inverter; the enable output terminal of the self-clock generator is connected to the enable input terminal of the delay latch, and the output terminal of the delay latch is connected to the input terminal of the self-clock generator and the input terminal of the output inverter, respectively. The delay latch includes: a Schmitt trigger unit, wherein a delay module is deployed on the input side of the Schmitt trigger unit, and the delay module is used to cause the Schmitt trigger unit to generate a delay; The delay latch further includes an output conversion unit, the input of which is connected to the output of the Schmitt trigger unit, and the output of the output conversion unit is used as the output of the delay latch, which is connected to the input of the self-clock generator and the input of the output inverter, respectively.

2. The asynchronous MouseTrap handshake unit with built-in matching delay according to claim 1, characterized in that, The Schmitt trigger unit includes: a first MOS transistor (mn0), a third MOS transistor (mn2), an eighth MOS transistor (mn7), a tenth MOS transistor (mn9), a twelfth MOS transistor (mp2), a seventeenth MOS transistor (mp7), and a nineteenth MOS transistor (mp9); wherein the first MOS transistor (mn0), the third MOS transistor (mn2), the eighth MOS transistor (mn7), and the tenth MOS transistor (mn9) are all N-type MOS transistors, and the twelfth MOS transistor (mp2), the seventeenth MOS transistor (mp7), and the nineteenth MOS transistor (mp9) are all P-type MOS transistors; The gate of the first MOS transistor (mn0) is the enable input terminal of the delay latch, and the gate of the first MOS transistor (mn0) is connected to the enable output terminal of the self-clock generator; The drain of the first MOS transistor (mn0) is connected to the gate of the eighth MOS transistor (mn7) and the drain of the twelfth MOS transistor (mp2), respectively; the source of the first MOS transistor (mn0) is connected to the drain of the third MOS transistor (mn2) and the gate of the seventeenth MOS transistor (mp7), respectively. The source of the twelfth MOS transistor (mp2) is connected to the drain of the nineteenth MOS transistor (mp9) and the drain of the seventeenth MOS transistor (mp7), respectively. The source of the third MOS transistor (mn2) is connected to the drain of the tenth MOS transistor (mn9) and the drain of the eighth MOS transistor (mn7), respectively. The source of the tenth MOS transistor (mn9) and the source of the seventeenth MOS transistor (mp7) are both grounded, and the source of the nineteenth MOS transistor (mp9) and the source of the eighth MOS transistor (mn7) are both connected to the power supply. The gates of the tenth MOSFET (mn9), the third MOSFET (mn2), the twelfth MOSFET (mp2), and the nineteenth MOSFET (mp9) are used as the request input terminals of the delay latch; The gates of the eighth MOS transistor (mn7) and the seventeenth MOS transistor (mp7) are both used as the output terminals of the Schmitt trigger unit.

3. The asynchronous MouseTrap handshake unit with built-in matching delay according to claim 2, characterized in that, The nineteenth MOSFET (mp9) and the tenth MOSFET (mn9) are used as delay modules.

4. The asynchronous MouseTrap handshake unit with built-in matching delay according to claim 2, characterized in that, The output conversion unit includes: an eleventh MOSFET (mp1), a second MOSFET (mn1), a thirteenth MOSFET (mp3), and a fourth MOSFET (mn3); wherein the eleventh MOSFET (mp1) and the thirteenth MOSFET (mp3) are both P-type MOSFETs, and the second MOSFET (mn1) and the fourth MOSFET (mn3) are both N-type MOSFETs; The gate of the eleventh MOS transistor (mp1) is connected to the gate of the second MOS transistor (mn1), the drain of the thirteenth MOS transistor (mp3), and the drain of the fourth MOS transistor (mn3), respectively. The source of the thirteenth MOS transistor (mp3) and the source of the eleventh MOS transistor (mp1) are both connected to the power supply, and the source of the second MOS transistor (mn1) and the source of the fourth MOS transistor (mn3) are both grounded. The gates of the thirteenth MOS transistor (mp3) and the fourth MOS transistor (mn3) are both used as input terminals of the output conversion unit. The gate of the thirteenth MOS transistor (mp3) is connected to the gate of the eighth MOS transistor (mn7), and the gate of the fourth MOS transistor (mn3) is connected to the gate of the seventeenth MOS transistor (mp7). The common terminal of the drain of the eleventh MOS transistor (mp1) and the drain of the second MOS transistor (mn1) is used as the output terminal of the output conversion unit.

5. The asynchronous MouseTrap handshake unit with built-in matching delay according to claim 1, characterized in that, The self-clock generator includes: a fifth MOS transistor (mn4), a sixth MOS transistor (mn5), a seventh MOS transistor (mn6), a fourteenth MOS transistor (mp4), a fifteenth MOS transistor (mp5), and a sixteenth MOS transistor (mp6); wherein the fifth MOS transistor (mn4), the sixth MOS transistor (mn5), and the seventh MOS transistor (mn6) are all N-type MOS transistors, and the fourteenth MOS transistor (mp4), the fifteenth MOS transistor (mp5), and the sixteenth MOS transistor (mp6) are all P-type MOS transistors; The source of the fifteenth MOS transistor (mp5) is connected to the drain of the sixteenth MOS transistor (mp6), and the drain of the fifteenth MOS transistor (mp5) is connected to the drain of the sixth MOS transistor (mn5), the drain of the seventh MOS transistor (mn6), the gate of the fourteenth MOS transistor (mp4), and the gate of the fifth MOS transistor (mn4). The gate of the sixteenth MOS transistor (mp6) is connected to the gate of the seventh MOS transistor (mn6) and the source of the sixth MOS transistor (mn5), and the common terminal of the gate of the sixteenth MOS transistor (mp6), the gate of the seventh MOS transistor (mn6) and the source of the sixth MOS transistor (mn5) is used as the response input terminal of the self-clock generator. The gate of the fifteenth MOS transistor (mp5) is connected to the gate of the sixth MOS transistor (mn5) and the source of the seventh MOS transistor (mn6), respectively. The common terminal of the gate of the fifteenth MOS transistor (mp5), the gate of the sixth MOS transistor (mn5) and the source of the seventh MOS transistor (mn6) is used as the input terminal of the self-clock generator and connected to the output terminal of the delay latch. The drain of the fourteenth MOS transistor (mp4) is connected to the drain of the fifth MOS transistor (mn4), and the common terminal of the drain of the fourteenth MOS transistor (mp4) and the drain of the fifth MOS transistor (mn4) is used as the enable output terminal of the self-clock generator and connected to the enable input terminal of the delay latch. The source of the fourteenth MOS transistor (mp4) and the source of the sixteenth MOS transistor (mp6) are both connected to the power supply, and the source of the fifth MOS transistor (mn4) is grounded.

6. The asynchronous MouseTrap handshake unit with built-in matching delay according to claim 1, characterized in that, The output inverter includes an eighteenth MOSFET (mp8) and a ninth MOSFET (mn8), wherein the eighteenth MOSFET (mp8) is a P-type MOSFET and the ninth MOSFET (mn8) is an N-type MOSFET. The drain of the eighteenth MOS transistor (mp8) is connected to the drain of the ninth MOS transistor (mn8), and the common terminal of the drain of the eighteenth MOS transistor (mp8) and the drain of the ninth MOS transistor (mn8) is used as the output terminal of the output inverter. The gate of the eighteenth MOS transistor (mp8) is connected to the gate of the ninth MOS transistor (mn8), and the common terminal of the gate of the eighteenth MOS transistor (mp8) and the gate of the ninth MOS transistor (mn8) is used as the input terminal of the output inverter. The source of the eighteenth MOS transistor (mp8) is connected to the power supply, and the source of the ninth MOS transistor (mn8) is grounded.

7. A handshake system, characterized in that, The system includes: a plurality of asynchronous MouseTrap handshake units with built-in matching delays as described in any one of claims 1-6, wherein the plurality of asynchronous MouseTrap handshake units with built-in matching delays are connected in series, and the output terminal of the output inverter of the k-th asynchronous MouseTrap handshake unit with built-in matching delays is connected to the request input terminal of the delay latch of the (k+1)-th asynchronous MouseTrap handshake unit with built-in matching delays, and the output terminal of the output inverter of the (k+1)-th asynchronous MouseTrap handshake unit with built-in matching delays is connected to the response input terminal of the self-clock generator of the k-th asynchronous MouseTrap handshake unit with built-in matching delays; wherein k is a positive integer.

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