A method and apparatus for breaking an asynchronous encryption circuit
By analyzing the encrypted netlist structure of asynchronous encryption circuits and using the Boolean satisfiability SAT solver to classify potential forgery paths, the problem of asynchronous encryption circuits being difficult to crack is solved, and fast key recovery is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ZHEJIANG UNIV
- Filing Date
- 2023-12-18
- Publication Date
- 2026-06-02
AI Technical Summary
Existing asynchronous encryption circuits employ data stream obfuscation techniques, making them difficult to crack using various SAT attack methods, thus lacking effective cracking methods.
By analyzing the encrypted netlist structure of the asynchronous encryption circuit, the control path and data path are separated, and the Boolean satisfiability SAT solver is used to classify potential forgery paths and recover the key.
It achieves effective cracking of asynchronous encryption circuits, simplifies circuit structure, speeds up SAT solving, and improves key recovery speed.
Smart Images
Figure CN117892366B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit and cryptography technology, and specifically relates to a method and apparatus for cracking asynchronous encryption circuits. Background Technology
[0002] In recent years, many methods for encryption circuits have emerged to protect the intellectual property rights of integrated circuits. For example... Figure 1 As shown, these methods control the behavior of the circuit by using the key as an additional input, and the circuit functions normally only when the key is correct; furthermore, they ensure the security of key storage by introducing tamper-proof memory as the physical medium for storing the key.
[0003] For encrypted circuits, attacks typically require combining the encrypted netlist with the activated chip. A common attack method is the SAT (Boolean satisfiability) attack, which is divided into combinational SAT attacks and sequential SAT attacks. Combinatorial SAT attacks directly transform the attack on the encrypted circuit into a Boolean satisfiability problem, and obtain the key through a solver. This type of attack is suitable for circuits composed of combinational logic gates. Sequential SAT attacks expand the sequential circuit according to the clock cycle, modeling it as a combinational circuit, and further transform it into a Boolean satisfiability problem for a solver. This type of attack is suitable for circuits containing sequential units. Other attack methods generally start from the characteristics of the encryption method itself, studying its coverage, structure, and netlist traces to break it.
[0004] Data flow obfuscation is a newly proposed method for circuit encryption using asynchronous circuits. It splits flip-flops into latches, replaces the synchronous clock with an asynchronous controller, and thus converts a synchronous circuit into an asynchronous one. Subsequently, a false path is inserted, and the signal transition diagram is updated, adding logic gates (including C* cells and logic gates) controlled by a key. For example... Figure 2 As shown, the top right corner shows the latch in the forged path, the bottom right corner shows the asynchronous controller in the forged path, and C* and the logic gates are gates controlled by the key. Figure 3 As shown, the lighter-colored areas represent the new content added after the signal conversion diagram was updated. For example... Figure 4 As shown, the C* unit consists of a C unit and a 2-to-1 multiplexer.
[0005] Because data flow obfuscation replaces the synchronous clock with an asynchronous controller, introducing a functional combinational logic loop, many SAT attack methods cannot model the encrypted circuit and therefore cannot launch effective attacks. Furthermore, the real path is encrypted using the same method as the forged path, making it impossible for other attack methods to identify the key location and thus failing. Therefore, there is currently no effective method to crack it. Summary of the Invention
[0006] To overcome the shortcomings of existing technologies and achieve the goal of cracking asynchronous encryption circuits, this invention adopts the following technical solution:
[0007] A method for cracking an asynchronous encryption circuit includes the following steps:
[0008] Step 1: Analyze the encryption netlist structure of the asynchronous encryption circuit and extract the control path and data path;
[0009] Step 2: Perform structural analysis on the asynchronous controllers in the control path, dividing them into the first real path group and the potential fake path group;
[0010] Step 3: Based on the first real path group and the potential forged path group respectively, the data path is resynchronized to obtain a simplified circuit;
[0011] Step 4: Use the Boolean satisfiability SAT solver to classify potential fake paths in the simplified circuit, and obtain the second real path group and the fake path group.
[0012] Step 5: Recover the key based on the classification results of the first real path group, the second real path group, and the forged path group.
[0013] Furthermore, in step one, the separation of the control path and the data path is achieved by using the enable port of each latch in the encrypted netlist as the dividing point, dividing the netlist into two modules: one module generates the enable signals of all latches and outputs them to the module port, which is the control path; the other module receives the enable signals of all latches as the input port, which is the data path.
[0014] Furthermore, in step two, for each group of asynchronous controllers, a variable key is created for the connection relationship of its different signals, and constraints are constructed based on different variable keys so that the existence of erroneous paths does not affect the activities of the upper and lower level asynchronous controllers. The value of the second-level latch in the forged path is kept at the reset value. Asynchronous controllers that meet the constraints are assigned to the potential forged path group, and asynchronous controllers that do not meet the constraints are assigned to the first real path group.
[0015] Furthermore, the variable key in step two includes key0 to key4, where key0 represents the connection relationship with the response signal (ACK) of the upper-level asynchronous controller; key1 represents the connection relationship with the request signal (REQ) of the upper-level asynchronous controller; key2 represents the connection relationship of the handshake signal between two latches; key3 represents the connection relationship with the request signal (REQ) of the lower-level asynchronous controller; and key4 represents the connection relationship with the response signal (ACK) of the lower-level asynchronous controller.
[0016] Furthermore, the constraints in step two include:
[0017] Constraint 1: The existence of an error path should not affect the activity of the parent asynchronous controller, i.e.:
[0018] ﹁key1∨(key0∧key2)=1
[0019] Wherein, ﹁ is the symbol for negation in digital logic, V is the symbol for OR in digital logic, and ∧ is the symbol for AND in digital logic;
[0020] Constraint 2: The existence of an error path should not affect the activity of the next-level asynchronous controller, i.e.:
[0021] ﹁key4∨(key2∧key3)=1
[0022] Constraint 3: The value of the second-level latch in the forged path should remain at the reset value, i.e.:
[0023] key2∨key3≠1
[0024] For missing keys, assign them the value 1. All asynchronous controllers that satisfy the above three constraints are assigned to the potential forgery path group; otherwise, they are assigned to the first real path group.
[0025] Furthermore, in step three, for the potential forged path group, the storage unit in its data path is replaced with a two-to-one multiplexer and a trigger group controlled by key*; for the first real path group, the storage unit in its data path is replaced with a trigger group without key*. In each trigger group, the first-level trigger is connected to the synchronous clock, and the second-level trigger is connected to the inverted synchronous clock.
[0026] Furthermore, in step four, each call to the SAT solver only calculates one feasible solution and records the corresponding key*. For each potential forgery path, if key* selects the trigger end of the multiplexer, i.e., key*0 = 1, it is assigned to the second real path group; otherwise, it is assigned to the forgery path group.
[0027] Furthermore, in step five, for each variable key in the encryption circuit, if it belongs to the first real path group or the second real path group, it is assigned the value 1; if it belongs to the forged path group, it is assigned the value 0, thereby recovering the key.
[0028] A device for cracking asynchronous encryption circuits includes an encryption netlist structure analysis module, an asynchronous controller structure analysis module, a circuit simplification module, a potential forgery path classification module, and a key recovery module;
[0029] The encrypted netlist structure analysis module analyzes the encrypted netlist structure of the asynchronous encryption circuit and extracts the control path and data path.
[0030] The asynchronous controller structure analysis module performs structural analysis on the asynchronous controllers in the control path, dividing them into a first real path group and a potential fake path group.
[0031] The circuit simplification module resynchronizes the data paths based on the first real path group and the potential forged path group to obtain a simplified circuit.
[0032] The potential forgery path classification module uses a Boolean satisfiability SAT solver to classify potential forgery paths in the simplified circuit, obtaining a second real path group and a forgery path group.
[0033] The key recovery module recovers the key based on the classification results of the first real path group, the second real path group, and the forged path group.
[0034] Furthermore, in the circuit simplification module, for potential forged path groups, the storage units in their data paths are replaced with a two-to-one multiplexer and a set of flip-flops controlled by key*; for the first real path group, the storage units in their data paths are replaced with a set of flip-flops without key*. In each set of flip-flops, the first-stage flip-flop is connected to the synchronous clock, and the second-stage flip-flop is connected to the inverted synchronous clock.
[0035] The advantages and beneficial effects of this invention are as follows:
[0036] Unlike other attack methods, the present invention provides a method and apparatus for cracking asynchronous encryption circuits. Instead of directly transforming the encryption circuit into a Boolean satisfiability problem, it first combines the characteristics of the asynchronous circuit and the encryption method to transform the problem into a classification problem of forged paths and real paths. The present invention performs structural analysis on the encryption circuit, extracts the correlation and distribution characteristics between keys, merges related keys, removes certain keys, simplifies the circuit, and accelerates the SAT solution speed. The structural analysis, SAT solution, and key recovery time of the present invention are based on the number of triggers, circuit size (the depth of the largest register in the circuit), and number of keys in the encryption circuit. The design incorporates correlations so that the condition regarding key recovery speed is transformed from the complexity of the encryption circuit to the CPU used for key recovery operations. Attached Figure Description
[0037] Figure 1 This is a schematic diagram of a traditional encryption circuit that uses a key for encryption.
[0038] Figure 2 This is a schematic diagram of an existing encryption circuit that uses asynchronous circuits for encryption.
[0039] Figure 3 This is the updated signal transformation diagram in asynchronous circuit encryption.
[0040] Figure 4 This is a schematic diagram of the C* unit structure in asynchronous circuit encryption.
[0041] Figure 5 This is a flowchart of the method in an embodiment of the present invention.
[0042] Figure 6 This is a schematic diagram of the encrypted asynchronous controller structure in an embodiment of the present invention.
[0043] Figure 7 This is a simplified circuit diagram in an embodiment of the present invention.
[0044] Figure 8 This is a schematic diagram of the device in an embodiment of the present invention. Detailed Implementation
[0045] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.
[0046] like Figure 5 As shown, a method for cracking an asynchronous encryption circuit includes the following steps:
[0047] Step 1: Analyze the encryption netlist structure of the asynchronous encryption circuit and extract the control path and data path;
[0048] To separate the control path and the data path, the enable port of each latch in the encrypted netlist is used as the dividing point to divide the netlist into two modules: one module generates the enable signal of all latches and outputs it to the module port, which is the control path; the other module receives the enable signal of all latches as the input port, which is the data path.
[0049] Step 2: Perform structural analysis on the asynchronous controllers in the control path, dividing them into the first real path group and the potential fake path group;
[0050] Structural analysis methods such as Figure 6 As shown, for each group of asynchronous controllers, five variables (key0-key4) are created to represent its structural characteristics: key0 represents the connection relationship with the response signal (ACK) of the upper-level asynchronous controller; key1 represents the connection relationship with the request signal (REQ) of the upper-level asynchronous controller; key2 represents the connection relationship of the handshake signal between two latches; key3 represents the connection relationship with the request signal (REQ) of the lower-level asynchronous controller; and key4 represents the connection relationship with the response signal (ACK) of the lower-level asynchronous controller. Then, the following constraints are added:
[0051] Constraint 1: The existence of an error path should not affect the activity of the parent asynchronous controller, i.e.:
[0052] ﹁key1∨(key0∧key2)=1
[0053] Wherein, ﹁ is the symbol for negation in digital logic, V is the symbol for OR in digital logic, and ∧ is the symbol for AND in digital logic;
[0054] Constraint 2: The existence of an error path should not affect the activity of the next-level asynchronous controller, i.e.:
[0055] ﹁key4∨(key2∧key3)=1
[0056] Constraint 3: The value of the second-level latch in the forged path should remain at the reset value;
[0057] key2∨key3≠1
[0058] For missing keys, assign them the value 1. All asynchronous controllers that satisfy the above three constraints are assigned to the potential forgery path group; otherwise, they are assigned to the first real path group.
[0059] The time required for structural analysis is directly proportional to the number of triggers in the encryption circuit. When running structural analysis with 64 CPUs, the analysis can be completed within 1 second for circuits with no more than 500 triggers, and within 10 seconds for circuits with no more than 5000 triggers.
[0060] Step 3: Based on the first real path group and the potential forged path group respectively, the data path is resynchronized to obtain a simplified circuit;
[0061] For potential forged path groups, replace the storage units in their data paths with 2-to-1 multiplexers and trigger groups controlled by key*; for the first genuine path group, replace the storage units in their data paths with trigger groups without key*. In each trigger group, the first-stage trigger is connected to the synchronous clock, and the second-stage trigger is connected to the inverted synchronous clock, as shown below. Figure 7 As shown.
[0062] Step 4: Use the Boolean satisfiability SAT solver to classify potential fake paths in the simplified circuit, and obtain the second real path group and the fake path group.
[0063] Each call to the SAT solver finds only one feasible solution and records the corresponding key*. For each potential forgery path, if key* selects the trigger end of the multiplexer, i.e., key*0 = 1, then it is assigned to the second real path group; otherwise, it is assigned to the forgery path group.
[0064] The time required to solve the SAT is related to the circuit size, primarily depending on the maximum register depth in the circuit. When running the SAT with 64 CPUs, the solution can be completed within 1 minute for circuits with a register depth of less than 10, and within 1 day for circuits with a register depth of less than 40.
[0065] Step 5: Recover the key based on the classification results of the first real path group, the second real path group, and the forged path group;
[0066] For each key in the encryption circuit, if it belongs to the first or second real path group, it is assigned the value 1; if it belongs to the forged path group, it is assigned the value 0. Thus, the key is recovered.
[0067] The time required to recover the key is directly proportional to the number of keys in the encryption circuit. When 64 CPUs are running key recovery, for a circuit with no more than 1000 keys, recovery can be completed within 1 second.
[0068] like Figure 8 As shown, a device for cracking asynchronous encryption circuits includes an encryption netlist structure analysis module, an asynchronous controller structure analysis module, a circuit simplification module, a potential forgery path classification module, and a key recovery module.
[0069] The encrypted netlist structure analysis module analyzes the encrypted netlist structure of asynchronous encryption circuits and extracts control and data paths.
[0070] The asynchronous controller structure analysis module performs structural analysis on the asynchronous controllers in the control path, dividing them into the first real path group and the potential fake path group.
[0071] The circuit simplification module resynchronizes the data paths based on the first real path group and the potential spoofing path group to obtain a simplified circuit. For the potential spoofing path group, the storage units in its data path are replaced with a 2-to-1 multiplexer and a set of flip-flops controlled by key*. For the first real path group, the storage units in its data path are replaced with a set of flip-flops without key*. In each set of flip-flops, the first-stage flip-flop is connected to the synchronous clock, and the second-stage flip-flop is connected to the inverted synchronous clock.
[0072] The potential forgery path classification module uses the Boolean satisfiability SAT solver to classify potential forgery paths in the simplified circuit, obtaining a second real path group and a forgery path group.
[0073] The key recovery module recovers the key based on the classification results of the first real path group, the second real path group, and the forged path group.
[0074] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for cracking asynchronous encryption circuits, characterized in that... Includes the following steps: Step 1: Analyze the encryption netlist structure of the asynchronous encryption circuit and extract the control path and data path; Step 2: Perform structural analysis on the asynchronous controllers in the control path, dividing them into the first real path group and the potential fake path group. For the asynchronous controller, create variable keys for the connection relationship of its different signals, and construct constraints based on different variable keys to ensure that the existence of erroneous paths does not affect the activities of the upper and lower level asynchronous controllers. The values of the second-level latches in the fake path are kept at the reset value. Asynchronous controllers that meet the constraints are assigned to the potential fake path group, and asynchronous controllers that do not meet the constraints are assigned to the first real path group. Step 3: Based on the first real path group and the potential fake path group respectively, resynchronize the data path to obtain a simplified circuit; for the potential fake path group, replace the storage unit in its data path with a 2-to-1 multiplexer and a set of flip-flops controlled by key*; for the first real path group, replace the storage unit in its data path with a set of flip-flops without key*, in which the first stage flip-flop is connected to the synchronous clock and the second stage flip-flop is connected to the inverted synchronous clock. Step 4: Use the Boolean satisfiability SAT solver to classify potential fake paths in the simplified circuit, obtaining a second group of real paths and a group of fake paths. Each time the SAT solver is called, only one feasible solution is obtained, and the corresponding key* is recorded. For potential fake paths, if key* selects the flip-flop terminal of the multiplexer, it is assigned to the second group of real paths; otherwise, it is assigned to the group of fake paths. Step 5: Recover the key based on the classification results of the first real path group, the second real path group, and the forged path group.
2. The method for cracking an asynchronous encryption circuit according to claim 1, characterized in that: In step one, the separation of the control path and the data path is achieved by using the enable port of the latch in the encrypted netlist as the dividing point, dividing the netlist into two modules: one module generates the enable signal of all latches and outputs it to the module port, which is the control path; the other module receives the enable signal of all latches as the input port, which is the data path.
3. The method for cracking an asynchronous encryption circuit according to claim 1, characterized in that: The variable key in step two includes key0 to key4, where key0 represents the connection relationship with the response signal of the upper-level asynchronous controller; key1 represents the connection relationship with the request signal of the upper-level asynchronous controller; key2 represents the connection relationship with the handshake signal between two latches; key3 represents the connection relationship with the request signal of the lower-level asynchronous controller; and key4 represents the connection relationship with the response signal of the lower-level asynchronous controller.
4. The method for cracking an asynchronous encryption circuit according to claim 3, characterized in that: The constraints in step two include: Constraint 1: The existence of an error path should not affect the activity of the parent asynchronous controller, i.e.: Wherein, ﹁ is the symbol for negation in digital logic, V is the symbol for OR in digital logic, and ∧ is the symbol for AND in digital logic; Constraint 2: The existence of an error path should not affect the activity of the next-level asynchronous controller, i.e.: Constraint 3: The value of the second-level latch in the forged path should remain at the reset value, i.e.: For missing keys, assign them the value 1. All asynchronous controllers that satisfy the above three constraints are assigned to the potential forgery path group; otherwise, they are assigned to the first real path group.
5. The method for cracking an asynchronous encryption circuit according to claim 1, characterized in that: In step five, if the variable key in the encryption circuit belongs to the first real path group or the second real path group, then it is assigned the value 1. If it belongs to the forged path group, assign it a value of 0, thereby recovering the key.
6. A device for cracking asynchronous encryption circuits, comprising an encryption netlist structure analysis module, an asynchronous controller structure analysis module, a circuit simplification module, a potential forgery path classification module, and a key recovery module, characterized in that: The encrypted netlist structure analysis module analyzes the encrypted netlist structure of the asynchronous encryption circuit and extracts the control path and data path. The asynchronous controller structure analysis module performs structural analysis on the asynchronous controllers in the control path, dividing them into a first real path group and a potential fake path group. For the asynchronous controller, a variable key is created for the connection relationship of its different signals, and constraints are constructed based on different variable keys to ensure that the existence of erroneous paths does not affect the activities of the upper and lower level asynchronous controllers. The value of the second-level latch in the fake path is kept at the reset value. Asynchronous controllers that meet the constraints are assigned to the potential fake path group, and asynchronous controllers that do not meet the constraints are assigned to the first real path group. The circuit simplification module resynchronizes the data path based on the first real path group and the potential spoofing path group to obtain a simplified circuit. For the potential spoofing path group, the storage unit in its data path is replaced with a 2-to-1 multiplexer and a set of flip-flops controlled by key*. For the first real path group, the storage unit in its data path is replaced with a set of flip-flops without key*. In the set of flip-flops, the first-stage flip-flop is connected to the synchronous clock, and the second-stage flip-flop is connected to the inverted synchronous clock. The potential forgery path classification module uses the Boolean satisfiability SAT solver to classify potential forgery paths in the simplified circuit, obtaining a second real path group and a forgery path group. Each call to the SAT solver only calculates one feasible solution and records the corresponding key*. For a potential forgery path, if key* selects the flip-flop terminal of a multiplexer, it is classified into the second real path group; otherwise, it is classified into the forgery path group. The key recovery module recovers the key based on the classification results of the first real path group, the second real path group, and the forged path group.