A hot plug implementation architecture for an ARINC 659 bus

Abstract

The application belongs to the field of aviation technology and discloses a hot plug implementation architecture of an ARINC659 bus. The hot plug implementation architecture comprises a hot plug power supply control module, a 659 bus driver, a connector, a BIU module and a power supply conversion module. The input end of the hot plug power supply control module is connected with a serial backplane power supply, and the output end of the hot plug power supply control module is connected with the power supply conversion module. The hot plug power supply control module is used for limiting transient surge current. The 659 bus driver is used for connecting the BIU module and the connector and is used for bus data transmission. The power supply conversion module is used for level conversion from primary power supply to secondary power supply, so that the node device in the computer architecture can be pulled out or inserted in the bus working state without affecting or damaging other devices, and the problem that the 659 bus board card cannot be hot plugged is solved.

Description

Technical Field

[0001] This invention belongs to the field of aerospace technology, and in particular relates to a hot-swappable implementation architecture for the ARINC659 bus. Background Technology

[0002] Hot-swapping is defined as inserting or removing a circuit board from a powered backplane. This technology allows for the replacement of a faulty circuit board while maintaining the voltage of the system backplane, while other working circuit boards in the system continue to operate. This technology has been widely used in buses such as USB, PCI-X, IEEE 1394, and CompactPCI.

[0003] The ARINC 659 bus is a bus specification proposed by Honeywell for data transmission between various functional modules in an integrated modular avionics rack. The specification describes the electrical characteristics, bus protocol, timing, and speed required for the serial backplane bus. It can be used for communication within the rack and has extremely high fault detection coverage and fault redundancy reliability. However, the standard specification has never supported hot-swapping. When adding or removing nodes in an ARINC 659 bus system, power must be turned off.

[0004] The patent "A General Two-out-of-Two Computer Architecture and Its Implementation Method (CN202010912899.X)" describes a computer architecture based on the ARINC 659 bus. This architecture boasts advantages such as high security, high reliability, modular reconfigurability, and ease of operation, and has been widely used in railway signaling systems. However, because this system typically requires 24-hour continuous operation, replacing or maintaining components necessitates system shutdown. This shutdown significantly impacts the continuous operation of the system and disrupts normal railway operations. As more and more of this computer architectures are deployed, system maintenance costs are escalating, making the need for hot-swappable capabilities increasingly urgent. Summary of the Invention

[0005] The purpose of this invention is to provide a hot-swappable architecture for the ARINC659 bus, enabling node devices in a two-out-of-two computer architecture to be unplugged or plugged in while the bus is in operation, without affecting or even damaging other devices, thus solving the problem of the inability to hot-swap 659 bus boards.

[0006] The technical solution of the present invention: In order to achieve the above-mentioned objectives, the present invention adopts the following technical solution.

[0007] A hot-swappable implementation architecture for the ARINC659 bus includes: a hot-swappable power control module, a 659 bus driver, a connector, a BIU module, and a power conversion module;

[0008] The input terminal of the hot-swappable power control module is connected to the serial backplane power supply, and the output terminal of the hot-swappable power control module is connected to the power conversion module; used to limit transient surge current.

[0009] The 659 bus driver enables the connection between the BIU module and the connector for bus data transmission;

[0010] The power conversion module is used for level conversion from primary power supply to secondary power supply.

[0011] The features and further improvements of the technical solution of this invention are as follows:

[0012] (1) The connector is connected to the serial backplane and adopts a mechanical structure of long pins, medium pins and short pins, so that when the 659 bus node board is inserted into or removed from the chassis, each signal pin is connected or disconnected from the backplane in a certain order.

[0013] (2) The 659 bus driver uses the GTLP bus driver. Since the GTLP level is different from the bus voltage defined in the 659 bus protocol specification, the bus termination voltage in the serial backplane is adjusted to +1.5V. According to the driving capability of the GTLP bus driver and the signal integrity of the backplane, the termination resistor value is recalculated and pulled up to +1.5V.

[0014] (3) The hot-swappable power control module is implemented using a positive high voltage control chip, and a pre-charge source V is added to the peripheral circuit of the positive high voltage control chip. BIAS .

[0015] (4) The long pin in the connector is defined as V BIAS The middle pin is defined as the I / O signal of the 659 bus, and the short pin is defined as the input power supply +24V signal.

[0016] (5) The long pin in the connector and the pre-charge power supply V BIAS The middle pin is connected to the ground signal GND, the middle pin is connected to the 8 data lines and 4 clock lines of the 659 bus, and the short pin is connected to the input power supply +24V.

[0017] (6) The GTLP bus driver precharge pin is connected to the precharge power supply V. BIAS .

[0018] (7) The power conversion module is implemented by a DC-DC conversion module to complete the conversion of +24V to +3.3V power. The converted +3.3V power is used to power the BIU module and the 659 bus driver.

[0019] This invention provides a hot-swappable architecture for the ARINC659 bus. By hot-swapping the power control module and the 659 bus driver, the power and signal protection of the functional boards is provided, which effectively reduces the interference of the boards to the 659 bus during hot-swapping without affecting the normal bus data transmission of the system. The functions and performance meet the expectations and can be widely used in products with the 659 bus architecture. Attached Figure Description

[0020] Figure 1 A schematic diagram of a computer based on a 659 bus architecture is provided for an embodiment of the present invention;

[0021] Figure 2 A hot-plugging implementation architecture diagram of the ARINC659 bus provided in this embodiment of the invention;

[0022] Figure 3 A circuit diagram of the bus and driver components provided in an embodiment of the present invention;

[0023] Figure 4 This is a circuit diagram of a hot-swappable power supply protection section provided in an embodiment of the present invention. Detailed Implementation

[0024] The present invention will now be described in further detail with reference to the accompanying drawings.

[0025] This invention provides a hot-swappable architecture for the ARINC659 bus, which mainly addresses power and signal issues during hot-swapping. The architecture includes a hot-swappable power control module, a 659 bus driver, a connector, a BIU module, and a power conversion module.

[0026] (1) The hot-swap power control module is directly connected to the backplane power supply and is used to limit transient surge current. On the one hand, it prevents the transient surge current generated during the hot-swap process from damaging the capacitors, wires and connectors on the circuit board; on the other hand, it controls the backplane power supply voltage to remain within the normal operating range so as not to affect the normal operation of other nodes or cause a restart.

[0027] (2) The 659 bus driver is used to realize bus data and clock transmission. The clock rate is 30MHz. It adopts the GTLP specification open collector device. While having wired or OR capability, it can ensure that the bus signal output is in a high impedance state during power-on or power-off, so as not to affect the data transmission of other nodes.

[0028] (3) The connector is physically connected to the backplane and adopts a mechanical structure of long pins, medium pins and short pins, so that when the 659 bus node board is inserted into or removed from the chassis, each signal pin is connected or disconnected from the backplane in a certain order.

[0029] The serial backplane includes four isolated 659 buses (AX, BX, AY, and BY), each bus including two data lines (D0 and D1) and one clock line (CLK), with each end of the bus pulled up to the bus voltage via a bus terminator.

[0030] The hot-swappable power control module integrates overvoltage and undervoltage protection, active current limiting via a constant current source during overload, disconnection of faulty loads before power voltage drops, reverse current protection using an external FET to form an "ideal diode," and automatic restart after a load fault. It protects the +24V input power line before the power module generates V. CC ;

[0031] The 659 bus driver uses a GTLP bus driver and has V BIAS The pre-charge function first establishes V when the board is inserted into the chassis. BIAS The voltage and GND signal precharge the driver's I / O pin voltage when V CC After establishing, power is supplied to the driver, along with V CC Level rises, V BIAS The pre-charge circuit will be turned off, so that the I / O pin voltages will eventually operate within the normal range;

[0032] The long pin in the connector is defined as V BIAS The middle pin is defined as the I / O signal of the 659 bus, and the short pin is defined as the input power supply +24V signal.

[0033] Furthermore, since the GTLP level is different from the bus voltage defined in the 659 specification, the bus termination voltage in the backplane is adjusted to +1.5V. Based on the driving capability of the bus driver and the signal integrity of the backplane, the termination resistor value is recalculated and pulled up to +1.5V.

[0034] Combined with appendix Figure 1 This invention provides a computer system based on the 659 bus architecture, comprising: computer system I (1) and computer system II (2) with identical structures connected via the ARINC 659 bus;

[0035] Furthermore, the computer (1, 2) includes a processor board VCU (10, 20), a discrete quantity board DIO (11, 21) and a backplane BP (30). Boards with the same function can be interchanged and maintained or replaced independently.

[0036] Furthermore, each functional board contains the same hot-swappable circuit (40) to enable 659 bus data transmission while protecting the power and signals of the functional board.

[0037] Combined with appendix Figure 2 and attached Figure 3 This invention provides a hot-swappable implementation architecture for the ARINC659 bus, including: a GTLP level bus driver (101), a BIU module (102), a hot-swappable power control module (103), a power conversion module (104), and a connector (105).

[0038] Furthermore, the bus driver (101) converts the TTL level output by the BIU module (102) to the GTLP level of the 659 bus. It is implemented using TI's SN74GTLP chip (101-1, 101-2, 101-3, 101-4, 101-5, 101-6, 101-7, 101-8, 101-9, 101-10, 101-11, 101-12), which can meet the bus "wired OR" capability.

[0039] Furthermore, the 659 bus uses an independent GTLP driver (201) for each of its 8 data lines (AxD0, AXD1, BxD0, BxD1, AyD0, AyD1, ByD0, ByD1) and 4 clock lines (AxCk, BxCk, AyCk, ByCk), totaling 12. The precharge pin is connected to V... BIAS Power supply connected, V CC The pin is connected to the tertiary power supply +3.3V of this board, and the enable pin ENB is connected to the BIU module (102) and pulled up to +3.3V through a resistor;

[0040] The BIU module (102) is implemented using FPGA and works together with the ARINC659 bus to control the normal data transmission and reception, time synchronization and other bus behaviors of this node according to the time schedule.

[0041] The hot-swap power control module (103) is implemented using a positive high voltage control chip from TI. Through its programmable current limiting function, it can prevent transient surge current from being generated by the +24V power supply input to the backplane during hot-swapping.

[0042] The power conversion module (104) is implemented using a DC-DC conversion module to complete the conversion of +24V to +3.3V three times. The converted +3.3V power is used to provide power to the BIU module (102) and the bus driver (101).

[0043] The connector (105) has long and short pins, wherein the long pin (105-1) is connected to the pre-charged power supply V. BIAS Connect the middle pin (105-2) to the ground signal GND, and connect the middle pin (105-2) to the 8 data lines (AxD0, AXD1, BxD0, BxD1, AyD0, AyD1, ByD0, ByD1) and 4 clock lines (AxCk, BxCk, AyCk, ByCk) of the 659 bus. Connect the short pin (105-3) to the input power supply +24V.

[0044] Furthermore, the 659 backplane BP (30) pulls up both ends of the 8 data lines (AxD0, AXD1, BxD0, BxD1, AyD0, AyD1, ByD0, ByD1) and 4 clock lines (AxCk, BxCk, AyCk, ByCk) of the 659 bus, and pulls them up to the bus power supply (302) through the terminator (301);

[0045] Furthermore, the 659 backplane BP (30) has four independent bus power supplies +1.5V (302) and one pre-charge power supply V. BIAS (303), which is used by various functional boards through connectors;

[0046] Furthermore, the 659 backplane BP (30) provides a +24V power supply (304) and is connected to the power control module (103) via a connector.

[0047] Combined with appendix Figure 4 The present invention provides a circuit design procedure for a hot-swappable power supply protection section, including the following steps:

[0048] Step 1: Use the TPS2490 chip (103-1) to limit the transient inrush current of the +24V input power supply. Based on the normal power consumption of the board, consider the input transient current limit I. MAX It is 980mA, according to R s =0.05 / (1.2×I) MAX Determine the induced resistance R. S The resistance of (103-2) is 0.0425Ω;

[0049] Step 2: In the design, the IRFU3504Z is selected as the external MOSFET (103-3) for the 24V hot-swappable circuit. DS 40V, I D For 42A, R DSON(MAX) The resistance is 9mΩ, which meets the design requirements of a maximum input voltage of 24V and a maximum output current of 1A.

[0050] Step 3: MOSFETs consume a significant amount of power during hot-plugging and output short-circuiting, limiting P...LIM This protects the tube from damage due to overheating. The P value is set by adjusting the voltage at the PROG pin. LIM The size of P is determined by calculation. LIM For a power rating of 20.9W, the design selects R3 (10³-4) as 20KΩ and R4 (10³-5) as 2KΩ.

[0051] Step 4: Select a suitable capacitor (103-6). Besides setting the fault restart interval, the capacitor must also ensure sufficient power dissipation of the external MOSFET during the overload duration to prevent damage. In this design, C is selected. T 0.1uF

[0052] Step 5: Setting the start-up voltage. The controller's start-up voltage is 1.35V, and the stop-down voltage is 1.25V. Undervoltage protection can be implemented by setting the input voltage on the EN pin. In this design, R1 (10³-7) is selected as 200KΩ, and R2 (10³-8) as 15KΩ. Calculations show that undervoltage protection is activated when the voltage drops below 17.92V.

[0053] Step 6: The GATE drive resistor R5 (103-9) is used to suppress high-frequency oscillations. In the design, R5 is set to 10Ω.

[0054] Step 7: The pull-up resistor (103-10) is used to ensure that the current absorbed by the PG pin is less than 2mA. Therefore, the value of R6 in the design is 100KΩ.

[0055] This invention proposes a hot-swappable architecture for the ARINC659 bus. Through the design of hot-swappable control circuits and bus driver circuits, power and signal protection is provided for functional boards, effectively reducing interference to the 659 bus during hot-swapping without affecting normal bus data transmission. The functions and performance meet expectations and can be widely used in products based on the 659 bus architecture.

Claims

1. A hot-plugging implementation architecture for the ARINC659 bus, characterized in that, include: The system includes a hot-swappable power control module, a 659 bus driver, a connector, a BIU module, and a power conversion module. The input of the hot-swappable power control module is connected to the serial backplane power supply, and its output is connected to the power conversion module. This is used to limit transient inrush current. The 659 bus driver connects the BIU module and the connector for bus data transmission. The power conversion module performs level conversion from primary to secondary power. The connector, which connects to the serial backplane, uses a mechanical structure of long pins, medium pins, and short pins, so that when the 659 bus node board is inserted into or removed from the chassis, each signal pin is connected or disconnected from the backplane in a certain order. The 659 bus driver uses a GTLP bus driver. Since the GTLP level is different from the bus voltage defined in the 659 bus protocol specification, the bus termination voltage in the serial backplane is adjusted to +1.5V. According to the driving capability of the GTLP bus driver and the signal integrity of the backplane, the termination resistor value is recalculated and pulled up to +1.5V. The hot-swappable power control module is implemented using a positive high-voltage control chip, and a pre-charge source V is added to the peripheral circuit of the positive high-voltage control chip. BIAS ; The power conversion module is implemented using a DC-DC converter to convert +24V to +3.3V power. The converted +3.3V power is used to power the BIU module and the 659 bus driver. The long pin in the connector is defined as V BIAS The middle pin is defined as the I / O signal of the 659 bus, and the short pin is defined as the input power supply +24V signal. The long pin in the connector and the pre-charge power source V BIAS The middle pin is connected to the ground signal GND, the middle pin is connected to the 8 data lines and 4 clock lines of the 659 bus, and the short pin is connected to the input power supply +24V.

2. The hot-plugging implementation architecture of the ARINC659 bus according to claim 1, characterized in that, The GTLP bus driver precharge pin is connected to the precharge power source V. BIAS .

Images