Memory design method, device, electronic device and storage medium

Abstract

The present disclosure relates to a memory design method, design apparatus, electronic device, and computer-readable storage medium. The design method includes: obtaining a first target parameter of a target memory related to a first structural indicator and a second target parameter of a second operational performance indicator; using the first target parameter and the second target parameter, searching multiple data tables corresponding to multiple memory configurations, obtaining a target configuration from the multiple memory configurations, each memory configuration being a combination of multiple hardware parameters of the memory, and each of the multiple data tables including a first correspondence between multiple first candidate parameters for the first indicator and multiple second candidate parameters for the second indicator; and generating design information of the target memory based on the target configuration. This method can improve the efficiency of memory design.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a memory design method, device, electronic device, and computer-readable storage medium. Background Art

[0002] Memory design is a crucial component of large-scale integrated circuit (LSI) chip design. With a wide variety of memory types available, chip designers often select the appropriate memory for their chip by studying each memory's technical parameters, such as area, speed, power consumption, and shape. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a memory design method, comprising: obtaining a first target parameter of a target memory regarding a first indicator of construction and a second target parameter of a second indicator of operating performance; using the first target parameter and the second target parameter to search for multiple data tables corresponding to multiple memory configurations, and obtain a target configuration from the multiple memory configurations, wherein each memory configuration is a combination of multiple hardware parameters of the memory, and each of the multiple data tables includes a first correspondence between multiple first alternative parameters of the first indicator and multiple second alternative parameters of the second indicator; and generating design information of the target memory based on the target configuration.

[0004] For example, in a design method provided in an embodiment of the present disclosure, each of the multiple data tables further includes multiple third alternative parameters regarding a constructed third indicator, and includes a second correspondence between the multiple first alternative parameters of the first indicator and the multiple third alternative parameters of the third indicator; based on the target configuration, the design information of the target memory is generated, including: when the number of the target configurations is multiple, based on the second correspondence, determining the multiple third alternative parameters corresponding to the multiple target configurations; selecting a third selection parameter that meets the requirements regarding the third indicator from the multiple third alternative parameters corresponding to the multiple target configurations; and generating the design information of the target memory according to the target configuration corresponding to the third selection parameter.

[0005] For example, in the design method provided by an embodiment of the present disclosure, the third indicator requirement includes selecting a minimum value from a plurality of third candidate parameters corresponding to the plurality of target configurations.

[0006] For example, in a design method provided in an embodiment of the present disclosure, the first target parameter and the second target parameter are used to search for the multiple data tables corresponding to the multiple memory configurations, and the target configuration is obtained from the multiple memory configurations, including: for a currently selected configuration among the multiple memory configurations, finding at least one first intermediate parameter closest to the first target parameter from the data table corresponding to the currently selected configuration; based on the at least one first intermediate parameter and the first corresponding relationship, calculating a second reference parameter of the second indicator corresponding to the first target parameter under the currently selected configuration; in response to the second reference parameter satisfying the second target parameter, the currently selected configuration is used as the target configuration.

[0007] For example, in the design method provided in one embodiment of the present disclosure, based on the at least one first intermediate parameter and the first corresponding relationship, the second reference parameter of the second indicator corresponding to the first target parameter under the currently selected configuration is calculated, including: based on the first corresponding relationship, determining the second intermediate parameter corresponding to each of the at least one first intermediate parameter; performing interpolation calculation on the at least one first intermediate parameter and the at least one second intermediate parameter to obtain the second reference parameter of the second indicator corresponding to the first target parameter.

[0008] For example, in the design method provided in an embodiment of the present disclosure, the first indicator includes a first sub-indicator and a second sub-indicator, each first intermediate parameter includes a first sub-parameter and a second sub-parameter, and interpolation calculation is performed on the at least one first intermediate parameter and the at least one second intermediate parameter to obtain a second reference parameter of the second indicator corresponding to the first target parameter, including: performing bilinear interpolation calculation on the at least one first intermediate parameter and the at least one second intermediate parameter to obtain a second reference parameter of the second indicator corresponding to the first target parameter.

[0009] For example, the design method provided in an embodiment of the present disclosure further includes: in response to the second reference parameter of the second indicator obtained as the currently selected configuration of each of the multiple memory configurations not satisfying the second target parameter, splitting the first target parameter into multiple target sub-parameters; for each target sub-parameter, using the target sub-parameter and the second target parameter, searching for the multiple data tables corresponding to the multiple memory configurations, and obtaining the target configuration from the multiple memory configurations.

[0010] For example, in a design method provided in an embodiment of the present disclosure, generating design information of the target memory based on the target configuration includes: generating design information of the target memory based on the target configuration corresponding to each target sub-parameter.

[0011] For example, in the design method provided in an embodiment of the present disclosure, the first indicator includes memory depth and memory width, wherein the memory depth is the number of words of the memory, and the memory width is the bit width of the memory.

[0012] For example, in the design method provided by an embodiment of the present disclosure, the second indicator includes the memory operating speed.

[0013] For example, in the design method provided by an embodiment of the present disclosure, the third indicator includes memory area.

[0014] For example, in the design method provided in an embodiment of the present disclosure, the multiple hardware parameters include at least two of the following: the number of logic storage blocks, the location of the address encoding and decoding logic circuit, and the value of the bit line multiplexer.

[0015] For example, in a design method provided in an embodiment of the present disclosure, the design information includes at least two of the following: the number of logic storage blocks, the location of the address encoding and decoding logic circuit, and the value of the bit line multiplexer.

[0016] For example, the design method provided in an embodiment of the present disclosure further includes: generating the target memory according to the design information of the target memory by using a memory compiler.

[0017] At least one embodiment of the present disclosure provides a memory design method, comprising: setting target parameters of a target memory at an interface layer; generating an instantiated memory at an instantiation layer based on the target parameters; and compiling the instantiated memory into a memory at a compilation layer.

[0018] For example, in a design method provided in an embodiment of the present disclosure, an instantiated memory is generated at an instantiation layer based on the target parameters, including: at the instantiation layer, searching for multiple data tables corresponding to multiple memory configurations based on the target parameters to obtain a target configuration that meets the target parameters from the multiple memory configurations; and generating an instantiated memory based on the target configuration.

[0019] For example, in a design method provided in an embodiment of the present disclosure, generating an instantiated memory based on the target configuration includes: acquiring configuration information at the interface layer; and generating the instantiated memory based on the configuration information and the target configuration.

[0020] For example, in the design method provided in one embodiment of the present disclosure, the configuration information includes at least one of the following: the interface type of the target memory, the number of bits of the target memory updated each time, whether the target memory is a graphics design memory, and whether to perform bit mask operations.

[0021] At least one embodiment of the present disclosure provides a memory design device, comprising: a target parameter acquisition unit, configured to acquire a first target parameter of a first indicator of construction and a second target parameter of a second indicator of operating performance of a target memory; a search unit, configured to use the first target parameter and the second target parameter to search for multiple data tables corresponding to multiple memory configurations, and obtain a target configuration from the multiple memory configurations, wherein each memory configuration is a combination of multiple hardware parameters of a memory, and each of the multiple data tables includes a first correspondence between multiple first alternative parameters of the first indicator and multiple second alternative parameters of the second indicator; and a design information generation unit, configured to generate design information of the target memory based on the target configuration.

[0022] At least one embodiment of the present disclosure provides a memory design device, comprising: an interface layer configured to obtain target parameters of a target memory; an instantiation layer configured to generate an instantiated memory based on the target parameters; and a compilation layer configured to compile the instantiated memory into a memory.

[0023] At least one embodiment of the present disclosure provides an electronic device, comprising a processor; a memory comprising one or more computer program instructions; wherein the one or more computer program instructions are stored in the memory and, when executed by the processor, implement instructions of the design method provided by any embodiment of the present disclosure.

[0024] At least one embodiment of the present disclosure provides a computer-readable storage medium that non-temporarily stores computer-readable instructions, wherein when the computer-readable instructions are executed by a processor, the design method provided by any embodiment of the present disclosure is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0026] Figure 1 A flowchart of a memory design method provided by at least one embodiment of the present disclosure is shown;

[0027] Figure 2 At least one embodiment of the present disclosure provides a Figure 1 Flowchart of the method of step S30;

[0028] Figure 3A At least one embodiment of the present disclosure provides a Figure 1 Flowchart of the method of step S20;

[0029] Figure 3BA schematic diagram illustrating a two-dimensional coordinate system established according to a first indicator provided by at least one embodiment of the present disclosure is shown;

[0030] Figure 4 A flowchart showing another memory design method provided by at least one embodiment of the present disclosure is shown;

[0031] Figure 5 A schematic diagram showing a three-layer structure of a memory design provided by at least one embodiment of the present disclosure is shown;

[0032] Figure 6 A schematic block diagram of an information processing device provided by at least one embodiment of the present disclosure is shown;

[0033] Figure 7 A schematic block diagram of another information processing device provided by at least one embodiment of the present disclosure is shown;

[0034] Figure 8A A schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure is shown;

[0035] Figure 8B A schematic block diagram showing another electronic device provided by at least one embodiment of the present disclosure; and

[0036] Figure 9 A schematic diagram of a computer-readable storage medium provided by at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0037] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0038] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0039] To select the right memory, chip designers often spend a significant amount of time researching the detailed usage of memory compilers and the technical specifications of each memory type (e.g., area, speed, power consumption, and shape). This approach is not only time-consuming and inefficient, but also prone to errors. Furthermore, this memory design approach, performed by chip designers, is not easily transferable, requiring repeated memory design for different projects and processes.

[0040] At least one embodiment of the present disclosure provides a memory design method. The design method includes: obtaining a first target parameter of a first indicator of construction and a second target parameter of a second indicator of operating performance of the target memory; using the first target parameter and the second target parameter, searching for multiple data tables corresponding to multiple memory configurations, obtaining a target configuration from the multiple memory configurations, each memory configuration being a combination of multiple hardware parameters of the memory, and each of the multiple data tables including a first correspondence between multiple first candidate parameters of the first indicator and multiple second candidate parameters of the second indicator; and generating design information of the target memory based on the target configuration. The design method determines appropriate design information by searching the data table of each memory, thereby obtaining an appropriate memory based on the design information, which not only improves the efficiency of designing the memory but also makes it less prone to errors.

[0041] At least one embodiment of the present disclosure provides another memory design method. This design method includes: setting target parameters of a target memory at the interface layer; generating an instantiated memory at the instantiation layer based on the target parameters; and compiling the instantiated memory into a memory at the compilation layer. This memory design method is easy to port and improves production efficiency.

[0042] Figure 1A flowchart of a memory design method provided by at least one embodiment of the present disclosure is shown.

[0043] like Figure 1 As shown, the method may include steps S10 to S30.

[0044] Step S10: Acquire a first target parameter of a first index related to the configuration of the target memory and a second target parameter of a second index related to the operation performance.

[0045] Step S20: using the first target parameter and the second target parameter, searching for multiple data tables corresponding to multiple memory configurations, and obtaining a target configuration from the multiple memory configurations.

[0046] Step S30: Generate design information of the target memory based on the target configuration.

[0047] For step S10, the structure may refer to the physical structure or appearance of the target memory. For example, the first indicator may include memory depth (Depth) and memory width (Width). For example, the memory depth is the number of words in the memory, and the memory width is the bit width of the memory.

[0048] For example, a static random-access memory (SRAM) consists of multiple memory cells arranged into a memory matrix. Memory cells in the same row are connected to the same wordline (WL) to receive wordline control signals, and memory cells in the same column are connected to the same bitline (BL) to receive bitline control signals. For example, each memory cell in an SRAM stores 1 bit of data, and the data stored in a row of memory cells is called a word. The number of rows in the memory matrix, or the number of words the memory can store, is the memory depth. The bit width of the memory is the width of a word, and the number of memory cells in a row is the memory bit width, or the memory width. For example, the memory depth is 32, 64, etc., and the memory bit width is 128 bits, 256 bits, etc. For example, the capacity of an SRAM is equal to the product of the memory depth and the memory width.

[0049] The first indicator may also include only the memory depth, or only the memory width, or other physical structure indicators. The present disclosure does not specifically limit the first indicator and the first target parameter.

[0050] For example, the first target parameter is 32×256, where 32 represents the depth of the SRAM and 256 represents the width of the SRAM.

[0051] Operational performance may include, for example, memory operating speed or memory power consumption and other memory operating characteristics. For example, the second indicator is memory operating speed, and the second target parameter is 1 GHz, 2 GHz, etc. This disclosure does not specifically limit the second indicator and the second target parameter.

[0052] The first target parameter and the second target parameter may be directly input by a chip designer, for example. The first target parameter and the second target parameter may also be determined based on the size and performance of the chip input by the chip designer.

[0053] In step S20, each memory configuration is a combination of multiple hardware parameters of the memory, such as the number of logical memory banks, the location of address encoding and decoding logic circuits, and the value of the bit line multiplexer.

[0054] In memory, a long BL can lead to slow charge and discharge speeds and low frequencies. Therefore, the memory can be divided into multiple banks to reduce the BL length. The number of logical memory blocks can be any number, such as 1, 2, 3, or 4.

[0055] The location of the address coding and decoding logic circuit may include, for example, the address coding and decoding logic circuit being located in the middle of the chip (abbreviated as "CD") or the address coding and decoding logic circuit being located at the periphery of the chip (abbreviated as "SD").

[0056] The value of the column mux (CM) determines the shape of the memory. For example, a CM value of 2 indicates that two words share a single bit line. For a memory with a fixed storage capacity, a larger CM value means a smaller memory depth.

[0057] The value of the column mux (CM) can be any value such as 1, 2, or 4.

[0058] For example, a memory configuration is CM2bank2CD, which means CM = 2, the number of logical memory blocks is 2, and the address encoding and decoding logic circuit is located in the middle of the chip. Another example is CM4bank1SD, which means CM = 4, the number of logical memory blocks is 1, and the address encoding and decoding logic circuit is located on the periphery of the chip.

[0059] In some embodiments of the present disclosure, each memory configuration corresponds to a data table. For example, CM2bank2CD corresponds to one data table, and CM4bank1SD corresponds to another data table.

[0060] In some embodiments of the present disclosure, for example, there are four possible values ​​of CM, three possible numbers of banks, and two possible locations of the address encoding and decoding logic circuit (i.e., CD or SD). Then, there are a total of 4×3×2=24 memory configurations, and these 24 memory configurations correspond to 24 data tables.

[0061] Each of the plurality of data tables includes a first correspondence between a plurality of first candidate parameters of the first indicator and a plurality of second candidate parameters of the second indicator.

[0062] For example, each data table includes a correspondence between a combination of memory depth and memory width and a memory operating speed, or each data table includes a correspondence between memory depth, memory width, and memory operating speed. In this example, memory depth and memory width are first indicators, and memory operating speed is a second indicator.

[0063] Table 1 shows a schematic diagram of a data table corresponding to, for example, CM2bank2CD provided by at least one embodiment of the present disclosure.

[0064] Table 1

[0065]

[0066] The above d1, d2, w1, w2, tcc11, tcc12, tcc21, tcc22, a11, a12, a21 and a22 are all greater than 0. It should be noted that the above memory configuration and Table 1 are only for illustrating the embodiment of the present disclosure and do not limit the present disclosure.

[0067] In Table 1, the first indicator is (memory width, memory depth), the second indicator is the memory operating speed, multiple first candidate parameters include (128, 32), (256, 32), and multiple second candidate parameters include 2GHZ and 1GHZ.

[0068] In some embodiments of the present disclosure, for step S20, for example, based on the first target parameter and the second target parameter, a data table corresponding to each memory configuration is searched. If a first alternative parameter and a second alternative parameter that meet the first target parameter and the second target parameter exist in a certain data table, then the memory configuration corresponding to the data table can be used as the target configuration.

[0069] For example, if the first target parameter is (128, 32) and the second target parameter is 2 GHz, then the first candidate parameter and the second candidate parameter in the first row of Table 1 are the same as the first target parameter and the second target parameter. Therefore, the corresponding memory configuration CM2bank2CD in Table 1 can be used as the target configuration of the target memory. In this embodiment, the first target parameter is one of multiple first candidate parameters, and the second target parameter is one of multiple second candidate parameters.

[0070] In other embodiments of the present disclosure, the plurality of first candidate parameters may not include the first target parameter, and the plurality of second candidate parameters may not include the second target parameter. FIG3 below shows a flowchart of the method of step S20 when the plurality of first candidate parameters may not include the first target parameter, and the plurality of second candidate parameters may not include the second target parameter. Please refer to the example of FIG3 below.

[0071] In step S30 , for example, design information of the target memory is generated according to the memory depth and memory width in the target configuration.

[0072] In some embodiments of the present disclosure, the design information includes at least various hardware parameters included in the memory configuration. For example, the design information includes the number of logical memory blocks, the location of the address encoding and decoding logic circuitry, and the value of the bitline multiplexer. For details about the number of logical memory blocks, the location of the address encoding and decoding logic circuitry, and the value of the bitline multiplexer, please refer to the above description.

[0073] In other embodiments of the present disclosure, the design information may further include configuration information. The configuration information includes at least one of the following: the interface type of the target memory, the number of bits per target memory update, whether the target memory is a graphics design memory, whether a bit mask operation is performed, etc. The configuration information may be input by a chip designer.

[0074] For example, the interface type of the target memory includes single-port, pseudo-dual-port, dual-port, and the like.

[0075] The number of bits of the target memory updated each time may be, for example, 64 bits, 128 bits, etc.

[0076] In some embodiments of the present disclosure, after obtaining the design information of the target memory, a memory compiler may be used to generate the target memory according to the design information of the target memory.

[0077] This design method generates design information that meets the requirements of the first target parameter and the second target parameter by searching the data table of each memory configuration. Therefore, chip designers do not need to spend a lot of time studying the detailed usage of the memory compiler and the technical parameters of each memory, and can obtain a memory that meets both the structural requirements and the operational performance requirements, thereby improving the efficiency of memory design and being less prone to errors.

[0078] In some embodiments of the present disclosure, each of the plurality of data tables further includes a plurality of third candidate parameters for the constructed third indicator, and includes a second correspondence between the plurality of first candidate parameters of the first indicator and the plurality of third candidate parameters of the third indicator.

[0079] For example, the third indicator can be the memory area. As shown in Table 1, each data table also includes a plurality of third candidate parameters for the memory area (for example, 1 cm 2 , 2cm 2 The plurality of third candidate parameters correspond one-to-one to the plurality of first candidate parameters.

[0080] For example, as shown in Table 1, the third candidate parameter corresponding to the first candidate parameter (128,32) is 1cm 2 , which means that if the memory width is 128 and the memory depth is 32, the memory area of ​​the memory is 1cm 2 For example, the third candidate parameter corresponding to the first candidate parameter (256,32) is 2cm 2 , which means that if the memory width is 256 and the memory depth is 32, the memory area of ​​the memory is 2cm 2 .

[0081] Figure 2 At least one embodiment of the present disclosure provides a Figure 1 Flowchart of the method for step S30 in FIG.

[0082] like Figure 2 As shown, step S30 may include steps S31 to S33.

[0083] Step S31: when there are multiple target configurations, determining multiple third candidate parameters corresponding to the multiple target configurations based on the second corresponding relationship;

[0084] Step S32: selecting a third selected parameter that meets the third indicator requirement from a plurality of third candidate parameters corresponding to a plurality of target configurations.

[0085] Step S33: Generate design information of the target memory according to the target configuration corresponding to the third selection parameter.

[0086] For step S31 , the number of target configurations being multiple means that at least two memory configurations can simultaneously meet the first target parameter and the second target parameter.

[0087] In the case that there are multiple target configurations, a third candidate parameter is determined based on the second corresponding relationship when each target configuration satisfies the first target parameter.

[0088] For example, if the plurality of first candidate parameters in the target configuration include the first target parameter, the third candidate parameter corresponding to the first candidate parameter that meets the first target parameter may be determined directly by searching the data table.

[0089] For example, the target configuration includes CM2bank2CD, the first target parameter is (128, 32), and the second target parameter is 2GHZ. The data table (Table 1) corresponding to CM2bank2CD includes the first candidate parameter (128, 32) and the second candidate parameter 2GHZ that meet the first target parameter and the second target parameter. Then, directly look up Table 1 to determine that the third candidate parameter corresponding to the first candidate parameter that meets the first target parameter under this target configuration is 1cm. 2 For another example, the target configuration includes not only CM2bank2CD but also CM4bank1SD. Similarly, the first candidate parameter that meets the first target parameter (128, 32) and the second target parameter 2GHZ and the third candidate parameter corresponding to the second candidate parameter are determined according to the data table corresponding to CM4bank1SD. For example, by searching the data table corresponding to CM4bank1SD, the third candidate parameter that meets the first target parameter and the second target parameter is 2cm. 2 .

[0090] In some other embodiments of the present disclosure, if the multiple first candidate parameters in the target configuration do not include the first target parameter, the following Figure 3B The described method is used to calculate and obtain third candidate parameters corresponding to a plurality of target configurations.

[0091] Regarding step S32, in some embodiments of the present disclosure, the third indicator requirement includes selecting a minimum value from a plurality of third candidate parameters corresponding to a plurality of target configurations. For example, if the third indicator is area, the third indicator requirement is the minimum area value corresponding to the plurality of target configurations.

[0092] For example, in the above embodiment, the target configuration CM2bank2CD results in a memory area of ​​1cm 2 The target configuration CM4bank1SD obtains a memory area of ​​2cm 2 , then the third selection parameter is a plurality of third candidate parameters corresponding to the plurality of target configurations (ie, 1cm 2 and 2cm 2 ) in the target configuration CM2bank2CD. 2 as the third selection parameter.

[0093] The third indicator may also be other indicators, not limited to area. The third indicator requirement may also be other requirements, not limited to the minimum area.

[0094] For step S33, for example, based on the memory area of ​​1cm 2 The corresponding CM2bank2CD generates the design information of the target memory.

[0095] This embodiment can not only quickly and easily obtain a memory that meets the structural and operational performance requirements, but also minimize the memory area, eliminating the need to manually select the memory design with the smallest area, thereby saving chip production costs and improving design efficiency.

[0096] Figure 3A At least one embodiment of the present disclosure provides a Figure 1 Flowchart of the method for step S20 in FIG.

[0097] like Figure 3A As shown, step S20 includes steps S21 to S23.

[0098] Step S21 : for a currently selected configuration among a plurality of memory configurations, finding at least one first intermediate parameter closest to a first target parameter from a data table corresponding to the currently selected configuration.

[0099] Step S22: Based on the at least one first intermediate parameter and the first corresponding relationship, a second reference parameter of the second indicator corresponding to the first target parameter in the currently selected configuration is calculated.

[0100] Step S23: In response to the second reference parameter satisfying the second target parameter, the currently selected configuration is used as the target configuration.

[0101] In step S21, for example, each of the multiple memory configurations is sequentially selected as the current selected configuration. For example, if the current selected configuration is CM2bank2CD, then at least one first intermediate parameter closest to the first target parameter is found from the data table corresponding to CM2bank2CD, such as Table 1.

[0102] For example, multiple first candidate parameter mappings and the first target parameter are respectively mapped into the coordinate system, and at least one first candidate parameter closest to the first target parameter is found by calculating the distance between each first candidate parameter and the first target parameter, and the at least one candidate parameter closest to the first target parameter is at least one intermediate parameter.

[0103] For example, a first indicator includes a first sub-indicator and a second sub-indicator. For example, the first sub-indicator is memory depth, and the second sub-indicator includes memory width. Each first candidate parameter includes memory depth and memory width, and each first intermediate parameter includes a first sub-parameter and a second sub-parameter. The first sub-parameter represents memory depth, and the second sub-parameter represents memory width.

[0104] Figure 3B A schematic diagram of a two-dimensional coordinate system established according to a first indicator provided by at least one embodiment of the present disclosure is shown.

[0105] like Figure 3BAs shown, in this two-dimensional coordinate system, the memory depth is the Y-axis and the memory width is the X-axis.

[0106] For example, Figure 3B As shown in the data table, the memory depth increases in fixed steps of d2-d1, and the memory width increases in fixed steps of w2-w1. If the coordinate point of the first target parameter in the two-dimensional coordinate system is M_wd(w,d) (hereinafter referred to as "first target parameter M_wd"), then the four first candidate parameters M_11(w1,d1), M_12(w1,d2), M_21(w2,d1), and M_22(w2,d2) located around the first target parameter M_wd are the four first intermediate parameters.

[0107] For step S22, for example, based on the first corresponding relationship, determine the second intermediate parameter corresponding to each of the at least one first intermediate parameters; perform interpolation calculation on the at least one first intermediate parameter and the at least one second intermediate parameter to obtain a second reference parameter of the second indicator corresponding to the first target parameter.

[0108] For example, search the data table corresponding to CM2bank2CD to determine the second intermediate parameters corresponding to M_11(w1,d1), M_12(w1,d2), M_21(w2,d1), and M_22(w2,d2). Interpolate the four found second intermediate parameters to obtain the second reference parameter corresponding to the first target parameter. The second intermediate parameter is the second candidate parameter corresponding to each first intermediate parameter.

[0109] For example, first calculate linear interpolation along the width of the memory. For example, interpolate between M_11 and M_21 at M_i1(w, d1), and interpolate between M_21 and M_22 at M_i2(w, d2). Then, calculate linear interpolation along the depth of the memory. For example, interpolate between M_i1 and M_i2 at M_wd, with width w and depth d. For example, perform bilinear interpolation on at least one first intermediate parameter and at least one second intermediate parameter to obtain a second reference parameter for a second indicator corresponding to the first target parameter.

[0110] For example, the second intermediate parameter is the memory operating speed. The calculation method for estimating the operating speed of the first target parameter M_wd based on bilinear interpolation is as follows:

[0111] Working speed of M_i1 tcc_i1=(w2-w) / (w2-w1)×tcc11+(w-w1) / (w2-w1)×tcc21;

[0112] The working speed of M_i2 is tcc_i2 = (w2-w) / (w2-w1)×tcc12+(w-w1) / (w2-w1)×tcc22;

[0113] The working speed of M_wd is tcc_wd=(d2-d) / (d2-d1)×tcc_i1+(d-d1) / (d2-d1)×tcc_i2.

[0114] For example, the operating speed tcc11, the operating speed tcc12, the operating speed tcc21 and the operating speed tcc22 are all obtained by looking up Table 1.

[0115] In step S23, for example, a determination is made as to whether the operating speed tcc_wd of M_wd satisfies a second target parameter. If so, CM2bank2CD is selected as the target configuration. For example, if the second target parameter is 2 GHz, and the operating speed tcc_wd of M_wd is greater than 2 GHz, then the operating speed tcc_wd of M_wd satisfies the second target parameter.

[0116] For example, if CM2bank2CD is the target configuration and there are other memory configurations different from CM2bank2CD, then based on the second corresponding relationship, the third candidate parameters corresponding to CM2bank2CD and the other memory configurations are calculated (i.e., executing the above Figure 2 Step S31 described above).

[0117] For example, the third candidate parameter corresponding to CM2bank2CD refers to the third candidate parameter when the memory configuration is CM2bank2CD and the first indicator is M_wd. In the following description, the third candidate parameter corresponding to the target configuration calculated based on the second corresponding relationship is referred to as the "third reference parameter."

[0118] exist Figure 3B In the example, similarly, for example, a third intermediate parameter corresponding to each of at least one first intermediate parameter can be determined based on the second corresponding relationship; and an interpolation calculation is performed on at least one first intermediate parameter and at least one third intermediate parameter to obtain a third reference parameter of the third indicator.

[0119] For example, if the third reference parameter is the memory area, the memory area when the first target parameter is M_wd is calculated based on the first intermediate parameters corresponding to M_11 (w1, d1), M_12 (w1, d2), M_21 (w2, d1), and M_22 (w2, d2).

[0120] For example, the memory area of ​​the first target parameter M_wd is estimated using bilinear interpolation. For example, the memory area of ​​the first target parameter M_wd is calculated as follows:

[0121] The memory area of ​​M_i1 is a_i1 = (w2-w) / (w2-w1)×a11+(w-w1) / (w2-w1)×a21;

[0122] The memory area of ​​M_i2 is a_i2 = (w2-w) / (w2-w1)×a12+(w-w1) / (w2-w1)×a22;

[0123] The memory area of ​​M_wd is a_wd=(d2-d) / (d2-d1)×a_i1+(d-d1) / (d2-d1)×a_i2.

[0124] For example, storage area a11, storage area a12, storage area a21, and storage area a22 are all obtained by looking up table 1.

[0125] Those skilled in the art may also use other methods to estimate the second reference parameter and the third reference parameter. For example, if the first indicator includes only one indicator (e.g., memory depth or memory width), that is, the first intermediate parameter includes only one parameter, then the second reference parameter and the third reference parameter may be estimated using an average value.

[0126] In the above embodiment, the memory width and the memory depth are both increased in fixed steps, so the second reference parameter and the third reference parameter can be accurately estimated by using bilinear difference, and it is easy to implement.

[0127] like Figure 3A As shown, in some other embodiments of the present disclosure, step S20 includes steps S24 to S25.

[0128] Step S24 : In response to the second reference parameter of the second indicator obtained by each of the multiple memory configurations as the currently selected configuration not satisfying the second target parameter, splitting the first target parameter into multiple target sub-parameters.

[0129] Step S25: for each target sub-parameter, use the target sub-parameter and the second target parameter to search for multiple data tables corresponding to multiple memory configurations, and obtain the target configuration from the multiple memory configurations.

[0130] For step S24, for example, the second target parameter is 2 GHZ. If the second reference parameter of the second indicator obtained by each of the multiple memory configurations as the currently selected configuration is less than 2 GHZ, then the second reference parameter of the second indicator obtained by each of the multiple memory configurations as the currently selected configuration does not meet the second target parameter 2 GHZ, and the first target parameter is split into multiple target sub-parameters.

[0131] In some embodiments of the present disclosure, multiple target sub-parameters may be the same or different.

[0132] In some other embodiments of the present disclosure, the first target parameter may be split into multiple target sub-parameters according to the memory width in the first target parameter.

[0133] For example, if the first target parameter is (128, 32), the first target parameter can be split into two target sub-parameters according to the memory width in the first target parameter, and both target sub-parameters are (62, 32), or the first target parameter can be split into two target sub-parameters according to the memory width in the first target parameter, which are (32, 32) and (96, 32).

[0134] In some other embodiments of the present disclosure, the first target parameter may be split into multiple target sub-parameters according to the memory depth in the first target parameter.

[0135] For step S25, for example, each target sub-parameter is used as the first target parameter, and the Figure 1 The method described in step S20 searches for multiple data tables corresponding to multiple memory configurations and obtains a target configuration from the multiple memory configurations.

[0136] For example, for the target subparameter (32,32), using Figure 1 The method described in step S20 searches for multiple data tables corresponding to multiple memory configurations, and obtains a first target configuration from the multiple memory configurations; then, for the target sub-parameter (96, 32), using Figure 1 The method described in step S20 searches for multiple data tables corresponding to multiple memory configurations, and obtains a second target configuration from the multiple memory configurations.

[0137] In this embodiment, Figure 1 Step S30 includes generating design information of the target memory based on the target configuration corresponding to each target sub-parameter, for example, generating the design information of the target memory based on the first target configuration and the second target configuration.

[0138] For example, if there are multiple first target configurations, the first target configuration with the smallest memory area is found from the first target configurations; if there are multiple second target configurations, the second target configuration with the smallest memory area is found from the second target configurations, thereby generating design information of the target memory based on the first target configuration with the smallest memory area and the second target configuration with the smallest memory area.

[0139] In the embodiment of the present disclosure, the operating speed of the memory becomes monotonically slower with the increase of the memory width and memory depth, while the memory area increases monotonically. Therefore, a database of memory width and memory depth, operating speed and memory area is established, and then a bilinear interpolation method is used to find various suitable memory configurations (Memview) that meet the operating speed, and then the configuration with the smallest memory area is found as the target memory configuration to reduce chip costs.

[0140] Figure 4 A flowchart of another memory design method provided by at least one embodiment of the present disclosure is shown.

[0141] like Figure 4 As shown, the design method includes steps S401 to S403.

[0142] Step S401: setting target parameters of the target memory at the interface layer.

[0143] Step S402: Generate instantiated memory at the instantiation layer based on the target parameters.

[0144] Step S403: compile the instantiated memory into a memory at the compilation layer.

[0145] This design method provides a three-layer structure for memory design, which includes an interface layer, an instantiation layer, and a compilation layer. Therefore, chip designers only need to understand the functions of each interface in the interface layer, and do not need to spend a lot of time studying the detailed usage of the memory compiler and the technical details of each memory. In addition, this design method is easy to transplant projects or process conversion.

[0146] In step S401, the interface layer includes, for example, an interactive interface, in which the chip designer can input target parameters of the target memory. The target parameters may include, for example, memory depth, memory width, etc. The target parameters may include, for example, the first target parameter and the second target parameter mentioned above.

[0147] Step S402 , for example, includes searching multiple data tables corresponding to multiple memory configurations based on target parameters at the instantiation layer to obtain a target configuration that meets the target parameters from the multiple memory configurations; and generating an instantiated memory based on the target configuration.

[0148] Step S402 performs, for example, a process similar to Figure 1 Steps S10 to S30 are described. For example, the instantiation layer includes Figure 1 The execution script of the described method searches multiple data tables according to target parameters to obtain target configuration, thereby generating design information of instantiated memory according to the target configuration.

[0149] In some embodiments of the present disclosure, generating an instantiated memory based on a target configuration includes: acquiring configuration information at an interface layer; and generating the instantiated memory based on the configuration information and the target configuration.

[0150] In some embodiments of the present disclosure, the configuration information includes at least one of the following: the interface type of the target memory, the number of bits of the target memory updated each time, whether the target memory is a graphics design memory, and whether a bit mask operation is performed. For a description of the configuration information, please refer to the above.

[0151] For example, chip designers can input the interface type, the number of bits updated each time, whether it is a graphics design memory, whether to perform bit mask operations, memory depth and memory width, etc. in the interactive interface.

[0152] In some other embodiments of the present disclosure, the instantiation layer may also perform different Figure 1 Other methods of the described method can be used as long as they can generate instantiated memory according to target parameters. Those skilled in the art can design methods for generating instantiated memory at the instantiation layer based on target parameters.

[0153] In step S403, the compiling layer generates a target memory according to the design information. The compiling layer may include a memory compiler, for example.

[0154] The following combination Figure 5 Further illustrate at least one embodiment of the present disclosure.

[0155] Figure 5 A schematic diagram of a three-layer structure of a memory design provided by at least one embodiment of the present disclosure is shown.

[0156] like Figure 5 As shown, the three-layer structure includes the interface layer, the instantiation layer and the compilation layer.

[0157] For example, the interface layer converts the configuration information and target parameters received from the interactive interface into parameter configuration information that conforms to a preset format. The parameter configuration information is, for example, ccp_mem2p32×256b64ps, where ccp is the name of a module, _mem is a convention to indicate the first layer of the ccp module, 2p indicates the use of rfps type memory, which refers to pseudo dual-single-port memory, 32 indicates the memory depth, 256 indicates the memory width, b indicates bit mask operations, 64p indicates 64 bits are updated each time, and the "s" in 64ps ​​indicates a non-graphically designed memory. For another example, the parameter configuration information is ccp_mem2pa32×256b64ps, where 2pa indicates the use of rfsd type memory, which refers to dual-single-port memory, and the other symbols or parameters are the same as those in ccp_mem2p32×256b64ps. For another example, in the parameter configuration information ccp_mem2pa32×256b64pg, except for “g” representing the graphic design memory, the other symbols or parameters have the same meanings as those in the above ccp_mem2p32×256b64ps.

[0158] In the above embodiment, the first target parameters include the memory depth 32 and the memory width 256 .

[0159] Next, the instantiation layer generates an instantiation memory based on the parameter configuration information received by the interface layer. Figure 5 As shown above, Figure 1 The described design method results in two target configurations with a memory depth of 32 and a memory width of 128 based on the first target parameter.

[0160] like Figure 5 As shown, the instantiation layer obtains two instantiated memories, instantiated memory 1 and instantiated memory 2, based on the parameter configuration information ccp_mem2p32×256b64ps. These two instantiated memories are, for example, ccp_rfps2ps2rm32×128m2bps. Rfps indicates the use of rfps type memory, 2p indicates the use of pseudo dual port, the symbol "s" next to 2p indicates that the address encoding and decoding logic circuit of this memory is located on the periphery of the chip, and 2rm indicates that the memory speed regulator is set to gear 2. 32 indicates the memory depth, 128 indicates the memory width, m2 indicates the value of the bit multiplexer is 2, b indicates the performance of bit masking operations, p indicates pipeline output, and s indicates non-graphic design memory.

[0161] Next, each instantiated memory is compiled into a sub-memory at the compilation layer. Figure 5As shown, the instantiated memory 1 is compiled to obtain sub-memory 1rfps2ps2rm32×128m2bp, and the instantiated memory 2 is compiled to obtain sub-memory 2rfps2ps2rm32×128m2bp. Sub-memory 1 and sub-memory 2 are combined to obtain the target memory.

[0162] exist Figure 5 In the example, the instantiated memory does not include the number of banks information, which means, for example, that the number of banks is a default value, such as 1, or the number of banks is an arbitrary value, or the memory configuration does not include the number of banks information but only includes the value of CM and the location of the address encoding and decoding logic circuit.

[0163] In other embodiments of the present disclosure, the instantiated memory may include data information of a bank.

[0164] Figure 6 A schematic block diagram of a memory design device 600 provided by at least one embodiment of the present disclosure is shown.

[0165] For example, Figure 6 As shown, the design device 600 includes a target parameter acquisition unit 610 , a search unit 620 and a design information generation unit 630 .

[0166] The target parameter acquisition unit 610 is configured to acquire a first target parameter of a first index regarding configuration and a second target parameter of a second index regarding operation performance of a target memory.

[0167] The target parameter acquisition unit 610 may execute, for example, Figure 1 Step S10 is described.

[0168] The search unit 620 is configured to use the first target parameter and the second target parameter to search for multiple data tables corresponding to multiple memory configurations, and obtain a target configuration from the multiple memory configurations, wherein each memory configuration is a combination of multiple hardware parameters of the memory, and each of the multiple data tables includes a correspondence between multiple first alternative parameters of the first indicator and multiple second alternative parameters of the second indicator.

[0169] The search unit 620 may, for example, execute Figure 1 Step S20 is described.

[0170] The design information generating unit 630 is configured to generate design information of the target memory based on the target configuration.

[0171] The design information generating unit 630 may, for example, execute Figure 1 Step S30 is described.

[0172] Figure 7 FIG2 shows a schematic block diagram of another memory design device 700 provided by at least one embodiment of the present disclosure.

[0173] For example, Figure 7 As shown, the design apparatus 700 includes an interface layer 710 , an instantiation layer 720 , and a compilation layer 730 .

[0174] The interface layer 710 is configured to obtain target parameters of the target memory. The interface layer 710 may, for example, execute Figure 4 Step S410 described.

[0175] The instantiation layer 720 is configured to generate an instantiated memory based on the target parameters. The instantiation layer 720 may, for example, execute Figure 4 Step S420 described.

[0176] The compilation layer 730 is configured to compile the instantiated memory into a memory. The compilation layer 730 may, for example, execute Figure 4 Step S430 described.

[0177] For example, the target parameter acquisition unit 610, the search unit 620, the design information generation unit 630, the interface layer 710, the instantiation layer 720, and the compilation layer 730 can be hardware, software, firmware, or any feasible combination thereof. For example, the target parameter acquisition unit 610, the search unit 620, the design information generation unit 630, the interface layer 710, the instantiation layer 720, and the compilation layer 730 can be dedicated or general-purpose circuits, chips, or devices, or can be a combination of a processor and a memory. The embodiments of the present disclosure do not limit the specific implementation of each of the above units.

[0178] It should be noted that in the embodiments of the present disclosure, the various units of the design device 600 and the design device 700 correspond to the various steps of the aforementioned design method. For the specific functions of the design device 600 and the design device 700, please refer to the relevant description of the design method, which will not be repeated here. Figure 6 The design device 600 shown and Figure 7 The components and structures of the design device 700 shown are only exemplary and not restrictive. Figure 6 The design device 600 shown and Figure 7 The illustrated design device 700 may also include other components and structures.

[0179] At least one embodiment of the present disclosure further provides an electronic device comprising a processor and a memory, wherein the memory includes one or more computer program modules. The one or more computer program modules are stored in the memory and configured to be executed by the processor, and the one or more computer program modules include instructions for implementing the above-described design method. This electronic device can improve the efficiency of memory design.

[0180] Figure 8A This is a schematic block diagram of an electronic device provided in some embodiments of the present disclosure. Figure 8A As shown, the electronic device 800 includes a processor 810 and a memory 820. The memory 820 is used to store non-transitory computer-readable instructions (e.g., one or more computer program modules). The processor 810 is used to execute the non-transitory computer-readable instructions. When the non-transitory computer-readable instructions are executed by the processor 810, one or more steps in the design method described above can be performed. The memory 820 and the processor 810 can be interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0181] For example, the processor 810 may be a central processing unit (CPU), a graphics processing unit (GPU), or other processing units with data processing capabilities and / or program execution capabilities. For example, the central processing unit (CPU) may be an X86 or ARM architecture. The processor 810 may be a general-purpose processor or a dedicated processor, and may control other components in the electronic device 800 to perform desired functions.

[0182] For example, the memory 820 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), a hard disk, an erasable programmable read-only memory (EPROM), a portable compact disk read-only memory (CD-ROM), a USB memory, a flash memory, etc. One or more computer program modules may be stored on the computer-readable storage medium, and the processor 810 may execute one or more computer program modules to implement various functions of the electronic device 800. Various applications and various data, as well as various data used and / or generated by the applications, may also be stored in the computer-readable storage medium.

[0183] It should be noted that, in the embodiment of the present disclosure, the specific functions and technical effects of the electronic device 800 can be referred to the description of the design method above, and will not be repeated here.

[0184] Figure 8B This is a schematic block diagram of another electronic device provided in some embodiments of the present disclosure. The electronic device 900 is suitable for implementing the design method provided in the embodiments of the present disclosure. The electronic device 900 may be a terminal device, etc. It should be noted that Figure 8B The electronic device 900 shown is merely an example and does not limit the functions and scope of use of the embodiments of the present disclosure.

[0185] like Figure 8B As shown, the electronic device 900 may include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 910, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 920 or a program loaded from a storage device 980 into a random access memory (RAM) 930. Various programs and data required for the operation of the electronic device 900 are also stored in the RAM 930. The processing device 910, the ROM 920, and the RAM 930 are connected to each other via a bus 940. An input / output (I / O) interface 950 is also connected to the bus 940.

[0186] Typically, the following devices may be connected to the I / O interface 950: an input device 960 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 970 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 980 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 990. The communication device 990 may allow the electronic device 900 to communicate with other electronic devices wirelessly or by wire to exchange data. Although Figure 8B The electronic device 900 is shown with various devices, but it should be understood that it is not required to implement or possess all of the devices shown, and the electronic device 900 may instead implement or possess more or fewer devices.

[0187] For example, according to an embodiment of the present disclosure, the above-mentioned design method can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a non-transitory computer-readable medium, and the computer program includes a program code for executing the above-mentioned design method. In such an embodiment, the computer program can be downloaded and installed from the network through the communication device 990, or installed from the storage device 980, or installed from the ROM 920. When the computer program is executed by the processing device 910, the functions defined in the design method provided in the embodiment of the present disclosure can be implemented.

[0188] At least one embodiment of the present disclosure further provides a computer-readable storage medium for storing non-transitory computer-readable instructions. When the non-transitory computer-readable instructions are executed by a computer, the aforementioned design method can be implemented. Utilizing this computer-readable storage medium can improve memory design efficiency.

[0189] Figure 9 A schematic diagram of a storage medium provided in some embodiments of the present disclosure. Figure 9 As shown, the storage medium 1000 is used to store non-transitory computer-readable instructions 1010. For example, when the non-transitory computer-readable instructions 1010 are executed by a computer, one or more steps in the design method described above can be performed.

[0190] For example, the storage medium 1000 can be applied to the electronic device 800. Figure 8A The memory 820 in the electronic device 800 is shown. For example, the description of the storage medium 1000 can be referred to Figure 8A The corresponding description of the memory 820 in the electronic device 800 is not repeated here.

[0191] There are a few points to note:

[0192] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0193] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0194] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A memory design method, comprising: obtaining a first target parameter of a target memory related to a first indicator of configuration and a second target parameter of a second indicator of operational performance; Using the first target parameter and the second target parameter, searching for a plurality of data tables corresponding to a plurality of memory configurations, and obtaining a target configuration from the plurality of memory configurations, wherein each memory configuration is a combination of a plurality of hardware parameters of a memory, and each of the plurality of data tables includes a first correspondence between a plurality of first candidate parameters of the first indicator and a plurality of second candidate parameters of the second indicator; and Based on the target configuration, design information of the target memory is generated, wherein: The step of searching the plurality of data tables corresponding to the plurality of memory configurations using the first target parameter and the second target parameter to obtain the target configuration from the plurality of memory configurations includes: For a currently selected configuration among the multiple memory configurations, finding at least one first intermediate parameter closest to the first target parameter from a data table corresponding to the currently selected configuration; Calculating a second reference parameter of a second indicator corresponding to the first target parameter in the currently selected configuration based on the at least one first intermediate parameter and the first corresponding relationship; In response to the second reference parameter satisfying the second target parameter, the currently selected configuration is used as the target configuration.

2. The design method according to claim 1, wherein: Each of the plurality of data tables further includes a plurality of third candidate parameters for the constructed third indicator, and includes a second correspondence between the plurality of first candidate parameters of the first indicator and the plurality of third candidate parameters of the third indicator; Generating design information of the target memory based on the target configuration, including: In the case where there are multiple target configurations, determining multiple third candidate parameters corresponding to the multiple target configurations based on the second corresponding relationship; Selecting a third selected parameter that meets the third indicator requirement from a plurality of third candidate parameters corresponding to the plurality of target configurations; and Design information of the target memory is generated according to the target configuration corresponding to the third selection parameter.

3. The design method according to claim 2, wherein: The third indicator requirement includes selecting a minimum value from a plurality of third candidate parameters corresponding to the plurality of target configurations.

4. The method according to claim 1, wherein Calculating a second reference parameter of a second indicator corresponding to the first target parameter in the currently selected configuration based on the at least one first intermediate parameter and the first corresponding relationship includes: Based on the first corresponding relationship, determining a second intermediate parameter corresponding to each of the at least one first intermediate parameters; An interpolation calculation is performed on the at least one first intermediate parameter and the at least one second intermediate parameter to obtain a second reference parameter of the second indicator corresponding to the first target parameter.

5. The method according to claim 4, wherein The first indicator includes a first sub-indicator and a second sub-indicator, and each first intermediate parameter includes a first sub-parameter and a second sub-parameter. Performing interpolation calculation on the at least one first intermediate parameter and the at least one second intermediate parameter to obtain a second reference parameter of the second indicator corresponding to the first target parameter includes: Bilinear interpolation calculation is performed on the at least one first intermediate parameter and the at least one second intermediate parameter to obtain a second reference parameter of the second indicator corresponding to the first target parameter.

6. The method according to claim 1, further comprising: In response to the second reference parameter of the second indicator obtained by each of the multiple memory configurations as the currently selected configuration not satisfying the second target parameter, splitting the first target parameter into a plurality of target sub-parameters; For each target sub-parameter, the target sub-parameter and the second target parameter are used to search the multiple data tables corresponding to the multiple memory configurations, and the target configuration is obtained from the multiple memory configurations.

7. The method according to claim 6, wherein: Generating design information of the target memory based on the target configuration, including: Based on the target configuration corresponding to each target sub-parameter, design information of the target memory is generated.

8. The method according to claim 1, wherein The first indicator includes memory depth and memory width, The memory depth is the number of words in the memory, and the memory width is the bit width of the memory.

9. The method according to claim 1, wherein The second indicator includes memory operating speed.

10. The method according to claim 2, wherein: The third indicator includes memory area.

11. The method according to claim 1, wherein The multiple hardware parameters include at least two of the following: The number of logical storage blocks, the location of the address encoding and decoding logic circuits, and the values ​​of the bit line multiplexers.

12. The method according to claim 1, wherein The design information includes at least two of the following: The number of logical storage blocks, the location of the address encoding and decoding logic circuits, and the values ​​of the bit line multiplexers.

13. The method according to claim 1, further comprising: The target memory is generated according to the design information of the target memory by using a memory compiler.

14. A memory design method, comprising: Set the target parameters of the target memory at the interface layer; Based on the target parameters, generating an instantiated memory at the instantiation layer; The instantiated memory is compiled into a memory at a compilation layer, wherein: The generating of the instantiated memory at the instantiation layer based on the target parameters includes: At the instantiation layer, searching multiple data tables corresponding to multiple memory configurations based on the target parameters to obtain a target configuration that meets the target parameters from the multiple memory configurations; and Based on the target configuration, an instantiated memory is generated.

15. The method according to claim 14, wherein Based on the target configuration, generating an instantiated memory includes: Obtaining configuration information at the interface layer; and The instantiated memory is generated based on the configuration information and the target configuration.

16. The method according to claim 15, wherein The configuration information includes at least one of the following: The interface type of the target memory, the number of bits of the target memory updated each time, whether the target memory is a graphics design memory, and whether a bit mask operation is performed.

17. A memory design device, comprising: a target parameter acquisition unit configured to acquire a first target parameter of a first indicator of configuration and a second target parameter of a second indicator of operation performance of the target memory; a search unit configured to use a first target parameter and a second target parameter to search a plurality of data tables corresponding to a plurality of memory configurations, and obtain a target configuration from the plurality of memory configurations, wherein each memory configuration is a combination of a plurality of hardware parameters of the memory, and each of the plurality of data tables includes a first correspondence between a plurality of first candidate parameters of the first indicator and a plurality of second candidate parameters of the second indicator; A design information generating unit is configured to generate design information of the target memory based on the target configuration, wherein: The step of searching the plurality of data tables corresponding to the plurality of memory configurations using the first target parameter and the second target parameter to obtain the target configuration from the plurality of memory configurations includes: For a currently selected configuration among the multiple memory configurations, finding at least one first intermediate parameter closest to the first target parameter from a data table corresponding to the currently selected configuration; Calculating a second reference parameter of a second indicator corresponding to the first target parameter in the currently selected configuration based on the at least one first intermediate parameter and the first corresponding relationship; In response to the second reference parameter satisfying the second target parameter, the currently selected configuration is used as the target configuration.

18. A memory design device, comprising: An interface layer configured to obtain target parameters of a target memory; An instantiation layer configured to generate an instantiated memory based on the target parameters; as well as A compilation layer configured to compile the instantiated memory into a memory, wherein The generating of the instantiated memory at the instantiation layer based on the target parameters includes: At the instantiation layer, searching multiple data tables corresponding to multiple memory configurations based on the target parameters to obtain a target configuration that meets the target parameters from the multiple memory configurations; and Based on the target configuration, an instantiated memory is generated.

19. An electronic device comprising: processor; a memory comprising one or more computer program instructions; The one or more computer program instructions are stored in the memory and, when executed by the processor, implement the design method according to any one of claims 1 to 16.

20. A computer-readable storage medium non-transitorily storing computer-readable instructions, wherein: When the computer-readable instructions are executed by a processor, the design method according to any one of claims 1 to 16 is implemented.

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