Display panel and display device

Abstract

Embodiments of the present application provide a display panel and a display device, and relate to the technical field of display, and improve the light transmittance and the anode flatness. The display panel comprises: a pixel circuit comprising a driving transistor and a first reset transistor; a first signal line comprising an interval signal line and a direct signal line; a connection signal line at least partially electrically connected with the interval signal line, the connection signal line comprising a first connection signal line and a second connection signal line; an anode; a pixel circuit group comprising at least a pair of pixel circuits which are locally symmetrical and adjacent, the first reset transistors of the pair of pixel circuits being adjacent, the adjacent first reset transistors being connected through a first semiconductor connection line, the first semiconductor connection line being connected with a reset signal line; and a pixel column, two first signal lines and two second connection signal lines being respectively arranged on both sides of the driving transistor in the pixel column, at least part of the anode overlapping with the adjacent first signal line, and / or at least part of the anode overlapping with the adjacent two second connection signal lines.

Description

[Technical Field]

[0001] This invention relates to the field of display technology, and more particularly to a display panel and display device. [Background Technology]

[0002] In the current structural design of display panels, new connecting lines need to be introduced into the display area to achieve specific functions. For example, data lines on both sides of the display area can be led to the middle of the display area through connecting lines. In this way, when designing fan-out lines, it is only necessary to concentrate the fan-out lines in the area directly opposite the driver chip, thereby reducing the width of the corner bezel.

[0003] However, after the connection lines are introduced into the display area, they will not only affect the light transmittance of the display panel, but also affect the flatness of the anode in the light-emitting element, resulting in problems such as color deviation in the display panel. [Summary of the Invention]

[0004] In view of this, embodiments of the present invention provide a display panel and a display device that can optimize the layout design of the display panel, thereby improving the light transmittance and anode flatness of the display panel.

[0005] On one hand, embodiments of the present invention provide a display panel, including:

[0006] Display area;

[0007] A pixel circuit located in the display area, the pixel circuit including a driving transistor and a first reset transistor electrically connected to a reset signal line;

[0008] A first signal line located in the display area, the first signal line including an indirect signal line and a direct signal line;

[0009] The connection signal line located in the display area is at least partially electrically connected to the inter-connection signal line. The connection signal line includes a first connection signal line extending along the first direction and a second connection signal line extending along the second direction, the second direction intersecting the first direction.

[0010] A light-emitting element located in the display area, the light-emitting element including an anode;

[0011] A pixel circuit group, the pixel circuit group including at least a partially symmetrical and adjacent pair of pixel circuits, and the first reset transistors of the pair of pixel circuits in the pixel circuit group are adjacent to each other, the adjacent first reset transistors are connected by a first semiconductor connection line, and the first semiconductor connection line is connected to the reset signal line.

[0012] A plurality of pixel columns arranged along the first direction, the pixel columns including a plurality of pixel circuits arranged along the second direction, wherein the driving transistors in the pixel columns are respectively provided with two first signal lines and two second connection signal lines on both sides of the first direction, and in a direction perpendicular to the plane of the display panel, at least a portion of the anodes overlaps with two adjacent first signal lines, and / or, at least a portion of the anodes overlaps with two adjacent second connection signal lines.

[0013] On the other hand, embodiments of the present invention provide a display device including the above-described display panel.

[0014] One of the above technical solutions has the following beneficial effects:

[0015] In this design, all pixel circuits in the display area adopt a uniform orientation. Under this design, the first reset transistor in each pixel circuit is located on the same side of its respective pixel circuit. Therefore, the first reset transistors in adjacent pixel circuits are relatively far apart. The first reset transistors in each pixel circuit need to be led to the reset signal line via semiconductor interconnects and connected to the reset signal line via vias.

[0016] In this embodiment of the invention, by designing at least locally symmetrical designs for two adjacent pixel circuits, the first reset transistors in these two adjacent pixel circuits are positioned close to and adjacent to each other. These two adjacent first reset transistors can then be connected by a short first semiconductor interconnect line. This first semiconductor interconnect line is then connected to the reset signal line via a via, thus achieving the connection between the two first reset transistors and the reset signal line. This design allows for the sharing of vias between some of the first reset transistors, thereby significantly reducing the number of vias connecting the first reset transistors and the reset signal line.

[0017] Furthermore, in related designs, introducing connecting lines into the display area to reduce the bezel area significantly reduces the light-transmitting area of ​​the display area, affecting under-display optical sensors such as ambient light sensors and fingerprint sensors, making this technology unable to meet customer specifications. However, with the design in this application, even if connecting signal lines are introduced into the display area, the reduced light-transmitting area released by these vias can compensate for the area blocked by the connecting signal lines, allowing the display panel to maintain high light transmittance. When an under-display optical sensor is located on the backlight side of the display panel, the ambient light intensity detected by the photosensitive element can be increased, thereby helping to optimize the effects of auxiliary functions such as camera and fingerprint recognition.

[0018] Furthermore, in related designs, after introducing connection signal lines into the display panel, the first signal line and the second connection signal line in the connection signal line are generally arranged alternately. That is, there is one first connection signal line and one second connection signal line between the driving transistors of two adjacent pixel columns. In this way, when designing the anode in the light-emitting element, at least part of the anode will overlap with one first connection signal line and one second connection signal line simultaneously. Due to the different functions of the first signal line and the second connection signal line, there may be differences in film thickness, linewidth, or whether they need to be connected to vias. For example, if the anode overlaps with one direct connection signal line and one second connection signal line, since the direct connection signal line does not need to be connected to the connection signal line through a via, while the second connection signal line may need to be connected to the first connection signal line through a via, the anode will only overlap with one via. This via will locally raise the anode in a small area, resulting in an uneven anode surface.

[0019] To address this issue, this embodiment of the invention further adjusts the arrangement of the first signal lines and the second connection signal lines, ensuring that either two first connection signal lines or two second connection signal lines are provided between the driving transistors of two adjacent pixel columns. This way, when at least a portion of the anode is located between two adjacent pixel columns, the anode overlaps with either two first signal lines of the same type or two second connection signal lines of the same type. This improves the problem of uneven film caused by the anode overlapping with different types of signal lines. With improved anode film flatness, the difference in the amount of light emitted by the light-emitting element at different azimuth angles is reduced, effectively weakening color shift and improving visual effect. [Attached Image Description]

[0020] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of a display panel provided in an embodiment of the present invention;

[0022] Figure 2 This is a partial structural diagram of a display panel provided in an embodiment of the present invention;

[0023] Figure 3 This is a schematic diagram of a pixel circuit structure provided in an embodiment of the present invention;

[0024] Figure 4This is a schematic diagram of another partial structure of the display panel provided in an embodiment of the present invention;

[0025] Figure 5 This is a schematic diagram of a film layer structure of a display panel provided in an embodiment of the present invention;

[0026] Figure 6 This is a partial structural diagram of the display panel provided in an embodiment of the present invention;

[0027] Figure 7 This is a schematic diagram of another film layer structure of the display panel provided in an embodiment of the present invention;

[0028] Figure 8 This is a schematic diagram of another film layer structure of the display panel provided in an embodiment of the present invention;

[0029] Figure 9 This is a schematic diagram of a film structure for an auxiliary power signal line, a power signal line, a first signal line, and an anode provided in an embodiment of the present invention.

[0030] Figure 10 This is a schematic diagram showing the position of a film layer of an auxiliary power signal line, a power signal line, a first signal line, and an anode provided in an embodiment of the present invention.

[0031] Figure 11 This is a schematic diagram of another film structure for the auxiliary power signal line, power signal line, first signal line, and anode provided in an embodiment of the present invention;

[0032] Figure 12 This is a schematic diagram of another film layer structure of the display panel provided in an embodiment of the present invention;

[0033] Figure 13 This is a schematic diagram of another film layer structure of the display panel provided in an embodiment of the present invention;

[0034] Figure 14 This is a schematic diagram of another partial structure of the display panel provided in an embodiment of the present invention;

[0035] Figure 15 This is a schematic diagram of another film layer structure of the display panel provided in an embodiment of the present invention;

[0036] Figure 16 for Figure 15 A schematic diagram of a local membrane structure;

[0037] Figure 17 for Figure 16 A sectional view along the A1-A2 direction;

[0038] Figure 18 for Figure 15Another schematic diagram of a local membrane structure;

[0039] Figure 19 for Figure 18 A sectional view along the B1-B2 direction;

[0040] Figure 20 This is a schematic diagram of another partial structure of the display panel provided in an embodiment of the present invention;

[0041] Figure 21 This is a schematic diagram of an anode arrangement provided in an embodiment of the present invention;

[0042] Figure 22 This is a schematic diagram of another film layer structure of the display panel provided in an embodiment of the present invention;

[0043] Figure 23 This is a schematic diagram of another film layer structure of the display panel provided in an embodiment of the present invention;

[0044] Figure 24 This is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0045] Figure 25 This is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0046] Figure 26 This is a schematic diagram of another film layer structure of the display panel provided in an embodiment of the present invention;

[0047] Figure 27 A schematic diagram of a film structure for a threshold compensation transistor, a second light-emitting control transistor, and a second connecting signal line provided in an embodiment of the present invention;

[0048] Figure 28 A schematic diagram of another film structure for the threshold compensation transistor, the second light-emitting control transistor, and the second connection signal line provided in an embodiment of the present invention;

[0049] Figure 29 This is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0050] Figure 30 This is a schematic diagram of another film layer structure of the display panel provided in an embodiment of the present invention;

[0051] Figure 31 This is a schematic diagram of a film layer stacking method for a display panel provided in an embodiment of the present invention;

[0052] Figure 32 This is a schematic diagram of another film layer stacking method for a display panel provided in an embodiment of the present invention;

[0053] Figure 33 This is a schematic diagram of another film layer stacking of a display panel provided in an embodiment of the present invention;

[0054] Figure 34 This is a schematic diagram showing the overlap of the anode and the first structure provided in an embodiment of the present invention;

[0055] Figure 35 This is another schematic diagram showing the overlap between the anode and the first structure provided in an embodiment of the present invention;

[0056] Figure 36 This is another schematic diagram showing the overlap between the anode and the first structure provided in an embodiment of the present invention;

[0057] Figure 37 This is another schematic diagram showing the overlap between the anode and the first structure provided in an embodiment of the present invention;

[0058] Figure 38 This is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0059] Figure 39 This is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0060] Figure 40 This is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention;

[0061] Figure 41 This is a schematic diagram of a display device provided in an embodiment of the present invention.

Detailed Implementation Methods

[0062] To better understand the technical solution of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0063] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0064] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0065] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0066] This invention provides a display panel, such as... Figure 1 As shown, Figure 1 This is a schematic diagram of a display panel provided in an embodiment of the present invention. The display panel includes a display area 1, a pixel circuit 2, a first signal line 3, a connecting signal line 4, and a light-emitting element 9.

[0067] The pixel circuit 2 is located in the display area 1. The pixel circuit 2 includes a driving transistor M0 and a first reset transistor M1 electrically connected to the reset signal line Vref.

[0068] The first signal line 3 is located in the display area 1. The first signal line 3 can be electrically connected to the pixel circuit 2 to transmit the signal required for display to the pixel circuit 2. The first signal line 3 includes an indirect signal line 5 and a direct signal line 6.

[0069] The connecting signal line 4 is located in the display area 1, and at least a portion of the connecting signal line 4 is electrically connected to the indirect connecting signal line 5. In one configuration, the direct connecting signal line 6 is directly electrically connected to the fan-out line in the bezel area, while the indirect connecting signal line 5 is indirectly electrically connected to the fan-out line in the bezel area through the connecting signal line 4. The connecting signal line 4 includes a first connecting signal line 7 extending along a first direction x and a second connecting signal line 8 extending along a second direction y, the second direction y intersecting the first direction x. It should be noted that, in this embodiment of the invention, the indirect connecting signal line 5 may have a connection relationship with only one first connecting signal line 7 and one second connecting signal line 8, or it may have a connection relationship with at least two first connecting signal lines 7 and at least two second connecting signal lines 8.

[0070] The light-emitting element 9 is located in the display area 1. The light-emitting element 9 includes an anode 10, which is electrically connected to the pixel circuit 2 and is used to receive the driving current provided by the pixel circuit 2 to realize the normal light emission of the light-emitting element 9.

[0071] In addition, see again Figure 1 The display panel also includes a pixel circuit group 11, which includes at least a partially symmetrical and adjacent pair of pixel circuits 2. The first reset transistors M1 of the pair of pixel circuits 2 in the pixel circuit group 11 are adjacent to each other, and the adjacent first reset transistors M1 are connected by a first semiconductor connection line 12, which is connected to the reset signal line Vref.

[0072] The display panel also includes a plurality of pixel columns 13 arranged along a first direction x, and the pixel columns 13 include a plurality of pixel circuits 2 arranged along a second direction y. The driving transistors M0 in the pixel columns 13 are respectively provided with two first signal lines 3 and two second connection signal lines 8 on both sides of the first direction x. That is, if two adjacent first signal lines 3 are considered as a first trace group, and two adjacent second connection signal lines 8 are considered as a second trace group, the first trace group and the second trace group are arranged alternately. In a direction perpendicular to the plane of the display panel, at least a portion of the anode 10 overlaps with two adjacent first signal lines 3, and / or, at least a portion of the anode 10 overlaps with two adjacent second connection signal lines 8.

[0073] In the relevant design, the pixel circuits 2 in the display area 1 all adopt a uniform orientation design. Under this design, the first reset transistor M1 in each pixel circuit 2 is located on the same side of the pixel circuit 2. Therefore, the first reset transistors M1 in two adjacent pixel circuits 2 are far apart. The first reset transistors M1 in each pixel circuit 2 need to be led to the reset signal line Vref through semiconductor interconnects and connected to the reset signal line Vref through vias.

[0074] In this embodiment of the invention, by designing at least locally symmetrical designs for two adjacent pixel circuits 2, the first reset transistors M1 in these two adjacent pixel circuits 2 are positioned close to and adjacent to each other. These two adjacent first reset transistors M1 can then be connected by a short first semiconductor connection line 12. This first semiconductor connection line 12 is then connected to the reset signal line Vref via a via, thus achieving the connection between the two first reset transistors M1 and the reset signal line Vref. This design allows the first reset transistors M1 to share vias, thereby significantly reducing the number of vias connecting the first reset transistors M1 and the reset signal line Vref.

[0075] It should be noted that although reducing the number of connection holes increases connection resistance, leading to an increase in voltage drop, the reset voltage applied to the pixel circuit 2 is done row by row, for example, alternating between rows or between two rows. Whether the reset voltage is used to reset the gate of the driving transistor M0 to charge the storage capacitor C, or to reset the anode 10 of the light-emitting element 9 to charge its capacitor, the charging current is very small compared to the light-emitting current of the light-emitting element 9, resulting in a very small voltage drop. Furthermore, this voltage drop only affects the reset signal level and does not affect the light-emitting current; therefore, it ultimately does not affect the brightness of the light-emitting element 9 and has almost no impact on the display effect.

[0076] Furthermore, in related designs, introducing connecting lines into display area 1 to reduce the bezel area reduces the light-transmitting area of ​​display area 1 significantly, affecting under-display optical sensors such as the Ambient Light Sensor (ALS) and fingerprint on display (FOD), making these technologies unable to meet customer specifications. However, with the design in this application, even with the introduction of connecting signal lines 4 into display area 1, the reduced light-transmitting area released by these vias can compensate for the area blocked by the connecting signal lines 4, allowing the display panel to maintain high light transmittance. When an under-display optical sensor is located on the backlight side of the display panel, the ambient light intensity detected by the photosensitive element can be increased, thereby helping to optimize the effects of auxiliary functions such as camera and fingerprint recognition.

[0077] Furthermore, in related designs, after introducing the connection signal line 4 into the display panel, the first signal line 3 and the second connection signal line 8 in the connection signal line 4 are generally arranged alternately. That is, there is a first connection signal line 7 and a second connection signal line 8 between the driving transistors M0 of two adjacent pixel columns 13. In this way, when designing the anode 10 in the light-emitting element 9, at least part of the anode 10 will overlap with a first connection signal line 7 and a second connection signal line 8 simultaneously. Since the first signal line 3 and the second connection signal line 8 have different functions, there may be differences in film thickness, linewidth, or whether they need to be connected to vias. For example, if the anode 10 overlaps with a direct connection signal line 7 and a second connection signal line 8, since the direct connection signal line 6 does not need to be connected to the connection signal line 4 through a via, while the second connection signal line 8 may need to be connected to the first connection signal line 7 through a via, the anode 10 will only overlap with one via. This via will locally raise the anode 10 in a small area, resulting in an uneven surface of the anode 10.

[0078] To address this issue, this embodiment of the invention further adjusts the arrangement of the first signal line 3 and the second connection signal line 8, ensuring that either two first connection signal lines 7 or two second connection signal lines 8 are provided between the driving transistors M0 of two adjacent pixel columns 13. This way, when at least a portion of the anode 10 is located between two adjacent pixel columns 13, the anode overlaps with two first signal lines 3 of the same type, or with two second connection signal lines 8 of the same type. This improves the problem of uneven film caused by the overlap of the anode 10 with different types of signal lines. With improved film flatness of the anode 10, the difference in the amount of light emitted by the light-emitting element 9 at different azimuth angles is reduced, effectively weakening color shift and improving visual effect.

[0079] In one feasible implementation, such as Figure 2 As shown, Figure 2 This is a partial structural diagram of a display panel provided in an embodiment of the present invention. The pixel circuit group 11 includes a first pixel circuit group 14, and the first pixel circuit group 14 includes a pair of adjacent pixel circuits 2 in two adjacent pixel columns 13. In other words, the pixel circuits 2 in two adjacent pixel columns 13 are symmetrically arranged, and any two adjacent pixel circuits 2 in two adjacent pixel columns 13 can constitute a first pixel circuit group 14.

[0080] For clarity, in this embodiment of the invention, the k1-th pixel column along the first direction x is represented by reference numeral 13_k1. Figure 2 The diagram only shows four pixel columns 13: the (2i-1)th pixel column 13_2i-1, the 2ith pixel column 13_2i, the (2i+1)th pixel column 13_2i+1, and the (2i+2)th pixel column 13_2i+2.

[0081] The first reset transistor M1 includes a first sub-reset transistor M11 and a second sub-reset transistor M12. The reset signal line Vref includes a first reset signal line Vref1 electrically connected to the first sub-reset transistor M11 and a second reset signal line Vref2 electrically connected to the second sub-reset transistor M12.

[0082] In one configuration method, such as Figure 3 As shown, Figure 3 This is a schematic diagram of a pixel circuit 2 provided in an embodiment of the present invention. A first sub-reset transistor M11 is electrically connected to the gate of a driving transistor M0, and is used to reset the gate of the driving transistor M0 using a first reset voltage provided by a first reset signal line Vref1 when it is turned on. A second sub-reset transistor M12 is connected to the anode 10 of the light-emitting element 9, and is used to reset the anode 10 of the light-emitting element 9 using a second reset voltage provided by a second reset signal line Vref2 when it is turned on. The first reset voltage and the second reset voltage can be different. In one configuration, the second reset voltage can be lower than the first reset voltage to improve the problem of light leakage from the light-emitting element 9. Depending on the start-up voltage of the light-emitting element 9, the second reset voltage can also be higher than the first reset voltage to improve the problems of image retention and color trailing. Alternatively, a dynamic second reset voltage can be used to solve different technical problems at different times.

[0083] The first semiconductor interconnect 12 includes a first interconnect 15 and a second interconnect 16.

[0084] In this configuration, the second sub-reset transistors M12 in the (2n-1)th pixel column 13_2n-1 and the 2nth pixel column 13_2n are arranged adjacently, and two adjacent second sub-reset transistors M12 are connected through a second connecting line 16, which is electrically connected to the second reset signal line Vref2. The first sub-reset transistors M11 in the 2nth pixel column 13_2n and the 2n+1th pixel column 13_2n+1 are arranged adjacently, and two adjacent first sub-reset transistors M11 are connected through a first connecting line 15, which is electrically connected to the first reset signal line Vref1. The value of n is 1, 2, 3, 4, 5, ... in sequence.

[0085] That is, in the embodiments of the present invention, the second sub-reset transistors M12 in the first pixel column 13_1 and the second pixel column 13_2 are arranged adjacent to each other, the second sub-reset transistors M12 in the third pixel column 13_3 and the fourth pixel column 13_4 are arranged adjacent to each other, the second sub-reset transistors M12 in the fifth pixel column 13_5 and the sixth pixel column 13_6 are arranged adjacent to each other, and so on; the second sub-reset transistors M12 in the second pixel column 13_2 and the third pixel column 13_3 are arranged adjacent to each other, the second sub-reset transistors M12 in the fourth pixel column 13_4 and the fifth pixel column 13_5 are arranged adjacent to each other, the second sub-reset transistors M12 in the sixth pixel column 13_6 and the seventh pixel column 13_7 are arranged adjacent to each other, and so on.

[0086] The above configuration employs a column-symmetrical design for the pixel circuit 2. This design allows the second sub-reset transistors M12 in the (2n-1)th pixel column 13_2n-1 and the 2nth pixel column 13_2n to be very close together. Adjacent second sub-reset transistors M12 in these pixel columns 13 can be connected by only a short second connection line 16. Therefore, while achieving via sharing, it further reduces the extension length of the semiconductor connection lines between adjacent second sub-reset transistors M12, thereby reducing the shading of ambient light by these semiconductor connection lines. Simultaneously, the first sub-reset transistors M11 in the 2nth pixel column 13_2n and the (2n+1)th pixel column 13_2n+1 are also very close together. This also reduces the extension length of the first connection line 15 between adjacent first sub-reset transistors M11 in these pixel columns 13, further reducing the shading of ambient light by these semiconductor connection lines and improving the light transmittance of the display panel.

[0087] In one feasible implementation, such as Figure 4 and Figure 5 As shown, Figure 4 This is a schematic diagram of another partial structure of the display panel provided in an embodiment of the present invention. Figure 5This is a schematic diagram of a film layer structure of a display panel provided in an embodiment of the present invention. The first reset signal line Vref1 includes a first sub-reset line Vref11 and a second sub-reset line Vref12 that are electrically connected. The second reset signal line Vref2 includes a third sub-reset line Vref21 and a fourth sub-reset line Vref22 that are electrically connected. The first sub-reset line Vref11 and the third sub-reset line Vref21 extend along a first direction x, and the second reset line Vref12 and the fourth reset line Vref22 extend along a second direction y.

[0088] The second sub-reset line Vref12 and the fourth sub-reset line Vref22 are arranged alternately, with a pixel column 13 between adjacent second sub-reset lines Vref12 and fourth sub-reset lines Vref22. Furthermore, the fourth sub-reset line Vref22 is located between the (2n-1)th pixel column 13_2n-1 and the 2nth pixel column 13_2n. The first connecting line 15 is electrically connected to the second sub-reset line Vref12, and the second connecting line 16 is electrically connected to the fourth sub-reset line Vref22.

[0089] This configuration has several advantages. First, the first sub-reset line Vref11 and the second sub-reset line Vref12 intersect to form a grid structure, effectively reducing the overall trace load of the first reset signal line Vref1. Similarly, the third sub-reset line Vref21 and the fourth sub-reset line Vref22 intersect to form a grid structure, effectively reducing the overall trace load of the second reset signal line Vref2. Second, in designing the arrangement of the second sub-reset line Vref12 and the fourth sub-reset line Vref22, this embodiment of the invention also matches their symmetrical design with that of the pixel circuit 2. Taking the fourth sub-reset line Vref22 as an example, combined with the symmetrical arrangement of pixel circuit 2, it can be seen that the second sub-reset transistors M12 in the (2n-1)th pixel column 13_2n-1 and the 2nth pixel column 13_2n are relatively close to each other, and the second sub-reset transistors M12 are connected to the second reset signal line Vref2. Therefore, by setting the fourth sub-reset line Vref22 in the second reset signal line Vref2 between the (2n-1)th pixel column 13_2n-1 and the 2nth pixel column 13_2n, the second connecting line 16 connecting the two adjacent second sub-reset transistors M12 can be directly connected through a via at the position where it overlaps with the fourth sub-reset line Vref22. At this time, the extension length of the second connecting line 16 can be further shortened, thereby further reducing the occlusion of the second connecting line 16 on ambient light.

[0090] Furthermore, see again Figure 4The display panel also includes a plurality of pixel rows 17 arranged along the second direction y, and the pixel rows 17 include a plurality of pixel circuits 2 arranged along the first direction x. The first sub-reset line Vref11 and the third sub-reset line Vref21 are arranged alternately, and there is a driving transistor M0 in the pixel row 17 between two adjacent first sub-reset lines Vref11 and third sub-reset lines Vref21.

[0091] For clarity, in the accompanying drawings of this embodiment of the invention, the k2th pixel row along the second direction y is represented by the reference numeral 17_k2. Figure 4 The image only shows four pixel rows 17: the 2p-1 pixel row 17_2p-1, the 2p pixel row 17_2p, the 2p+1 pixel row 17_2p+1, and the 2p+2 pixel row 17_2p+2.

[0092] This design reduces the number of first sub-reset lines Vref11 and third sub-reset lines Vref21. Moreover, although only one first sub-reset line Vref11 or one third sub-reset line Vref21 is set for each pixel row 17, the first sub-reset transistor M11 in the pixel row 17 can still be connected to the first sub-reset line Vref11 through the second sub-reset line Vref12, and the second sub-reset transistor M12 in the pixel row 17 can be connected to the third sub-reset line Vref21 through the fourth sub-reset line Vref22.

[0093] In one feasible implementation, such as Figure 6 As shown, Figure 6 This is a partial structural diagram of a display panel provided in an embodiment of the present invention. The display panel further includes a plurality of pixel rows 17 arranged along the second direction y, and the pixel rows 17 include a plurality of pixel circuits 2 arranged along the first direction x.

[0094] The first reset signal line Vref1 extends along the first direction x, and one first reset signal line Vref1 is set for each pixel row 17. The second reset signal line Vref2 extends along the second direction y, and the second reset signal line Vref2 is located between the 2n-1 pixel column 13_2n-1 and the 2n pixel column 13_2n.

[0095] In the above configuration, each pixel row 17 corresponds to a horizontally extending first reset signal line Vref1. In this case, the first sub-reset transistor M11 in each pixel row 17 can be connected to the adjacent first reset signal line Vref1, resulting in a short connection distance between the first sub-reset transistor M11 and the first reset signal line Vref1. Based on the symmetrical arrangement of the pixel circuit, the second sub-reset transistors M12 in the (2n-1)th pixel column 13_2n-1 and the 2nth pixel column 13_2n are relatively close. By setting a vertically extending second reset signal line Vref2 between the (2n-1)th pixel column 13_2n-1 and the 2nth pixel column 13_2n, the connection distance between the second sub-reset transistor M12 and the second reset signal line Vref2 can also be shortened. Therefore, the above configuration can shorten the extension length of the first connecting line 15 and the second connecting line 16, thereby further improving the light transmittance of the display panel.

[0096] Furthermore, in the above configuration, there is no need to set a second reset signal line Vref2 between the 2nth pixel column 13_2n and the 2n+1th pixel column 13_2n+1, which can significantly reduce the number of second reset signal lines Vref2 set between pixel columns 13.

[0097] Furthermore, such as Figure 7 As shown, Figure 7 This is a schematic diagram of another film layer structure of the display panel provided in an embodiment of the present invention. The first sub-reset transistor M11 is also electrically connected to the first scan signal line Scan1. The first connecting line 15 and the first reset signal line Vref1 connected to it are located on the same side of the first scan signal line Scan1. At this time, the first connecting line 15 does not need to cross the first scan signal line Scan1 to connect with the first reset signal line Vref1. The first connecting line 15 and the first scan signal line Scan1 do not overlap, thus reducing the signal interference between the first connecting line 15 and the first scan signal line Scan1. Moreover, this can also reduce the extension length of the first connecting line 15.

[0098] In one feasible implementation, combined with Figure 2 The pixel circuit group 11 includes a first pixel circuit group 14, and the first pixel circuit group 14 includes a pair of adjacent pixel circuits 2 in two adjacent pixel columns 13. Figures 8-10 As shown, Figure 8 This is a schematic diagram of another film layer structure of the display panel provided in an embodiment of the present invention. Figure 9 This is a schematic diagram of a film structure for the auxiliary power signal line 18, the power signal line PVDD, the first signal line 3, and the anode 10 provided in an embodiment of the present invention. Figure 10This is a schematic diagram of the film positions of the auxiliary power signal line 18, the power signal line PVDD, the first signal line 3, and the anode 10 provided in an embodiment of the present invention. The first signal line 3 is located between the driving transistor M0 in the 2nth pixel column 13_2n and the 2n+1th pixel column 13_2n+1.

[0099] The pixel circuit 2 also includes a first light-emitting control transistor M4, which is electrically connected to a power signal line PVDD. The power signal line PVDD extends along the second direction y. The first light-emitting control transistor M4 in the 2nth pixel column 13_2n and the 2n+1th pixel column 13_2n+1 is adjacent to each other, and the two power signal lines PVDD connected to the 2nth pixel column 13_2n and the 2n+1th pixel column 13_2n+1 are adjacent to each other.

[0100] The display panel also includes an auxiliary power connection line 18, which is located on the side of the first signal line 3 and the second connection signal line 8 that faces away from the light-emitting surface of the display panel. For example, the auxiliary power connection line 18 can be arranged on the same layer as the first connection signal line 7. The auxiliary power connection line 18 includes a first line segment 19 and a first carrier portion 20. The dimension of the first carrier portion 20 in the second direction y is larger than the dimension of the first line segment 19 in the second direction y, and the first carrier portion 20 is electrically connected to the power signal line PVDD. In the direction perpendicular to the plane of the display panel, the first carrier portion 20 overlaps with the two adjacent first signal lines 3.

[0101] The portion of the first signal line 3 that overlaps with the first carrier portion 20 is the first trace segment 21. In a direction perpendicular to the plane where the display panel is located, a portion of the anode 10 overlaps with the first trace segment 21 of two adjacent first signal lines 3.

[0102] It should be noted that, see Figure 10 The display panel also includes a substrate 22 and an insulating layer 23. At least one insulating layer 23 may be included between the auxiliary power signal line 18 and the first signal line 3, and between the first signal line 3 and the anode 10.

[0103] The first support portion 20 in the auxiliary power connection line 18 can support the first trace segment 21 of the two adjacent first signal lines 3, making the location and surrounding area of ​​the first trace segment 21 relatively flat. Consequently, when the anode 10 is placed above the first trace segment 21, this part of the anode 10 will also be flatter. In addition, the large block metal structure formed by the first support portion 20 can also reduce the load on the power signal line PVDD.

[0104] Furthermore, such as Figure 11 As shown, Figure 11This is a schematic diagram of another film structure of the auxiliary power signal line 18, power signal line PVDD, first signal line 3 and anode 10 provided in an embodiment of the present invention. The auxiliary power connection line 18 also includes a second carrier portion 24. The size of the second carrier portion 24 in the second direction y is larger than the size of the first line segment 19 in the second direction y. In the direction perpendicular to the plane where the display panel is located, the second carrier portion 24 overlaps with two adjacent second connection signal lines 8.

[0105] Among them, the portion of the second connecting signal line 8 that overlaps with the second carrier portion 24 is the second trace segment 25. In the direction perpendicular to the plane where the display panel is located, a portion of the anode 10 overlaps with the second trace segment 25 of the two adjacent second connecting signal lines 8.

[0106] Similar to the first carrier 20, the second carrier 24 in the auxiliary power connection line 18 can support the second trace segment 25 in two adjacent two connection lines, thereby improving the flatness of the film layer of the anode 10 above the second trace segment 25, so that the film layer of more anodes 10 in the display panel is flatter.

[0107] In one feasible implementation, such as Figure 12 As shown, Figure 12 This is a schematic diagram of another film layer structure of the display panel provided in an embodiment of the present invention. The gate of the driving transistor M0 is electrically connected to the first node N1. The auxiliary power connection line 18 also includes a first protrusion 26 protruding from the first line segment 19. In a direction perpendicular to the plane of the display panel, the first protrusion 26 overlaps with the first node N1.

[0108] It is understandable that in pixel circuit 2, the operational stability of driving transistor M0 greatly affects the accuracy of the driving current transmitted from pixel circuit 2 to light-emitting element 9. In this embodiment of the invention, by further providing a first protrusion 26 overlapping with the first node N1 on the auxiliary power connection line 18, the fixed power supply voltage transmitted on the first protrusion 26 can be used to stabilize the potential of the gate of driving transistor M0, thereby improving the reliability of the operating state of driving transistor M0.

[0109] In one feasible implementation, such as Figure 13 As shown, Figure 13 This is a schematic diagram of another film layer structure of the display panel provided in an embodiment of the present invention. The first light-emitting control transistors M4 adjacent in the 2nth pixel column 13_2n and the 2n+1th pixel column 13_2n+1 are connected by the second semiconductor connection line 27.

[0110] The power signal line PVDD includes multiple second segments 28, with a gap between adjacent second segments 28 in a single power signal line PVDD. The first carrier portion 20 includes a main body portion 29 and a protrusion 30, with the ends of two adjacent second segments 28 near the protrusion 30 connected via a first connecting trace 31. A second semiconductor connection line 27 is electrically connected to the first connecting trace 31 via a first via 32, and the first connecting trace 31 is electrically connected to the protrusion 30 via a second via 33.

[0111] In the above configuration, while the first carrier portion 20 improves the flatness of the anode 10, the first carrier portion 20 also serves as a connection between two adjacent second segments 28 in the power signal line PVDD, forming a continuous signal transmission path in the power signal line PVDD.

[0112] Furthermore, it should be noted that the film layer structure of the display panel includes a semiconductor layer, a first metal layer, a second metal layer, and a third metal layer. The semiconductor layer may include structures such as the first semiconductor interconnect 12 and the second semiconductor interconnect 27; the first metal layer may include structures such as the first scan signal line Scan1 and the second scan signal line Scan2; the second metal layer may include structures such as the first reset signal line Vref1, the second reset signal line Vref2, and the electrode of the storage capacitor C in the pixel circuit 2; and the third metal layer may include structures such as the power signal line PVDD. In existing display panel manufacturing processes, holes are typically drilled between the third metal layer and the second metal layer, and between the third metal layer and the semiconductor layer.

[0113] Based on the above configuration, since the first connection trace 31 connecting two adjacent second segments 28 is also located in the third metal layer, when two adjacent first light-emitting control transistors M4 are connected through the second semiconductor connection line 27, the first via 32 connecting the second semiconductor connection line 27 and the first connection trace 31 can be formed simultaneously when forming a via between the third metal layer and the semiconductor layer. Furthermore, when forming a connection via between the third metal layer and the semiconductor layer, the insulating layers between the third metal layer and the second metal layer, the second metal layer and the first metal layer, and the first metal layer and the semiconductor layer can be perforated using the same mask, thereby saving the number of masks required.

[0114] Furthermore, based on the above configuration, two adjacent first light-emitting control transistors M4 are connected together via a second semiconductor interconnect 27, and then connected to the protrusion 30 via a first via 32 and a second via 33. This eliminates the need for the two first light-emitting control transistors M4 to be connected to the power signal line PVDD vias separately. Therefore, when designing the vias between the first light-emitting control transistors M4 and the power signal line PVDD, the area of ​​the vias can be appropriately increased to improve the voltage drop during power signal transmission within the vias.

[0115] Furthermore, an organic film with a thickness greater than 500 nm can be deposited on the side of the protrusion 30 near the substrate to reduce the PVDD load. The thickness of the organic film can be 500 nm, 600 nm, 1 μm, or even thicker.

[0116] It should be noted that, Figure 13 The illustration only shows the case where a protrusion 30 is provided on one side of the main body 29. In other configurations of the present invention, protrusions 30 may also be provided on both sides of the main body 29.

[0117] Furthermore, see again Figure 13 In the direction perpendicular to the plane of the display panel, the first via 32 and the second via 33 do not overlap, that is, the first via 32 and the second via 33 are staggered.

[0118] The first via 32 and the second via 33 employ the aforementioned non-overlapping design, which avoids the vias becoming too deep due to overlap, thereby preventing issues such as etching residue or breaks in the upper metal layer during the manufacturing process. Furthermore, based on this design, the protrusion 30 extends beyond the second semiconductor interconnect 27, providing greater shielding of the second semiconductor interconnect 27. This allows the power supply voltage transmitted through the protrusion 30 to more effectively stabilize the potential of the second terminals of the two first light-emitting control transistors M4, optimizing the display effect.

[0119] In one feasible implementation, such as Figure 14 and Figure 15 As shown, Figure 14 This is a schematic diagram of another partial structure of the display panel provided in an embodiment of the present invention. Figure 15This is a schematic diagram of another film layer structure of a display panel provided in an embodiment of the present invention. The display panel includes a plurality of pixel rows 17 arranged along a second direction y, and the pixel rows 17 include a plurality of pixel circuits 2 arranged along a first direction x. The pixel circuit group 11 includes a second pixel circuit group 34, and the second pixel circuit group 34 includes a pair of adjacent pixel circuits 2 in two adjacent pixel rows 17. That is, the pixel circuits 2 in two adjacent pixel rows 17 are symmetrically arranged, and any two adjacent pixel circuits 2 in two adjacent pixel rows 17 can form a second pixel circuit group 34.

[0120] For clarity, in the accompanying drawings of this embodiment of the invention, the k2th pixel row along the second direction y is represented by the reference numeral 17_k2. Figure 14 The image only shows four pixel rows 17: the 2p-1 pixel row 17_2p-1, the 2p pixel row 17_2p, the 2p+1 pixel row 17_2p+1, and the 2p+2 pixel row 17_2p+2.

[0121] The first reset transistor M1 includes a first sub-reset transistor M11 and a second sub-reset transistor M12. The reset signal line Vref includes a first reset signal line Vref1 electrically connected to the first sub-reset transistor M11 and a second reset signal line Vref2 electrically connected to the second sub-reset transistor M12.

[0122] The first semiconductor interconnect 12 includes a third interconnect 35 and a fourth interconnect 36.

[0123] In this configuration, the first sub-reset transistors M11 in the (2n-1)th pixel row 17_2n-1 and the 2nth pixel row 17_2n are arranged adjacently, and the two adjacent first sub-reset transistors M11 are connected by a third connecting line 35, which is electrically connected to the first reset signal line Vref1; the second sub-reset transistors M12 in the 2nth pixel row 17_2n and the 2n+1th pixel row 17_2n+1 are arranged adjacently, and the two adjacent second sub-reset transistors M12 are connected by a fourth connecting line 36, which is electrically connected to the second reset signal line Vref2, and n takes values ​​of 1, 2, 3, 4, 5, ... in sequence.

[0124] That is, in the embodiments of the present invention, the first sub-reset transistor M11 in the first pixel row 17_1 and the second pixel row 17_2 are arranged adjacent to each other, the first sub-reset transistor M11 in the third pixel row 17_3 and the fourth pixel row 17_4 are arranged adjacent to each other, the first sub-reset transistor M11 in the fifth pixel row 17_5 and the sixth pixel row 17_6 are arranged adjacent to each other, and so on; the second sub-reset transistor M12 in the second pixel row 17_2 and the third pixel row 17_3 are arranged adjacent to each other, the second sub-reset transistor M12 in the fourth pixel row 17_4 and the fifth pixel row 17_5 are arranged adjacent to each other, the second sub-reset transistor M12 in the sixth pixel row 17_6 and the seventh pixel row 17_7 are arranged adjacent to each other, and so on.

[0125] The above configuration employs a row-symmetrical design for the pixel circuit 2. This design allows the first sub-reset transistors M11 in the (2n-1)th pixel row 17_2n-1 and the 2nth pixel row 17_2n to be very close together. Adjacent first sub-reset transistors M11 in these pixel rows 17 can be connected only by a short third connection line 35. Therefore, while achieving via sharing, the extension length of the semiconductor connection lines between adjacent first sub-reset transistors M11 is further reduced, thereby reducing the occlusion of ambient light by these semiconductor connection lines. Simultaneously, the second sub-reset transistors M12 in the 2nth pixel row 17_2n and the (2n+1)th pixel row 17_2n+1 are also very close together. This also reduces the extension length of the fourth connection line 36 between adjacent second sub-reset transistors M12 in these pixel rows 17, further reducing the occlusion of ambient light by these semiconductor connection lines and improving the light transmittance of the display panel.

[0126] Furthermore, combined Figure 14 The first reset signal line Vref1 and the second reset signal line Vref2 extend along the first direction x, respectively. The first reset signal line Vref1 and the second reset signal line Vref2 are arranged alternately, and there is a driving transistor M0 in pixel row 17 between two adjacent first reset signal lines Vref1 and Vref2. The first reset signal line Vref1 is located between the driving transistor M0 in the (2n-1)th pixel row 17_2n-1 and the 2nth pixel row 17_2n.

[0127] In this embodiment of the invention, the wiring of the first reset signal line Vref1 and the second reset signal line Vref2 is also matched with the symmetrical design of the pixel circuit 2, so that the first reset signal line Vref1 and the first sub-reset transistor M11 connected to it are closer together, and the second reset signal line Vref2 and the second sub-reset transistor M12 connected to it are closer together. This reduces the extension length of the third connecting line 35 and the fourth connecting line 36, thereby further improving the light transmittance of the display panel.

[0128] In one feasible implementation, combined with Figure 15 ,like Figure 16 and Figure 17 As shown, Figure 16 for Figure 15 A schematic diagram of a local membrane structure. Figure 17 for Figure 16 A cross-sectional view along the A1-A2 direction shows that the first reset signal line Vref1 includes a first break 37. In a direction perpendicular to the plane where the display panel is located, the first break 37 overlaps with the third connecting line 35, that is, the first reset signal line Vref1 is disconnected above the third connecting line 35.

[0129] The display panel also includes a second connection trace 38, which is located on the side of the first reset signal line Vref1 facing the light-emitting surface of the display panel. The second connection trace 38 and the portions of the first reset signal line Vref1 located on both sides of the first break 37 are electrically connected through a third via 39. The second connection trace 38 is also electrically connected to the third connection line 35 through a fourth via 40. In the direction perpendicular to the plane of the display panel, the fourth via 40 is located inside the first break 37.

[0130] It is understood that the film structure of the display panel includes a semiconductor layer, a first metal layer, a second metal layer, and a third metal layer. The semiconductor layer may include structures such as the first semiconductor interconnect 12; the first metal layer may include structures such as the first scan signal line Scan1 and the second scan signal line Scan2; the second metal layer may include structures such as the first reset signal line Vref1, the second reset signal line Vref2, and the electrode of the storage capacitor C in the pixel circuit 2; and the third metal layer may include structures such as the second interconnect trace 38 and the power signal line PVDD.

[0131] In current display panel manufacturing processes, vias are typically drilled between the third and second metal layers, and between the third metal layer and the semiconductor layer. For example, vias need to be formed between the third and second metal layers to connect the power signal line PVDD and the electrode of the storage capacitor C.

[0132] When designing the connection between the first reset signal line Vref1 and the third connection line 35, if a via is directly placed between the second metal layer where the first reset signal line Vref1 is located and the semiconductor layer where the third connection line 35 is located, an additional drilling process is required on top of the original process flow. However, in the embodiment of the present invention, by adopting the "three-hole design" consisting of two third vias 39 and one fourth via 40, in the process of manufacturing the display panel, it is only necessary to simultaneously drill the third via 39 between the second connection line 38 and the first reset signal line Vref1 when drilling other vias between the third metal layer and the second metal layer, and simultaneously drill the fourth via 40 between the second connection line 38 and the third connection line 35 when drilling other vias between the third metal layer and the semiconductor layer. No additional process flow is required, and therefore no increase in process cost is added.

[0133] In one feasible implementation, combined with Figure 15 ,like Figure 18 and Figure 19 As shown, Figure 18 for Figure 15 Another schematic diagram of a local membrane structure. Figure 19 for Figure 18 A cross-sectional view along the B1-B2 direction shows that the second reset signal line Vref2 includes a second break 41. In a direction perpendicular to the plane where the display panel is located, the second break 41 overlaps with the fourth connecting line 36, that is, the second reset signal line Vref2 is disconnected above the fourth connecting line 36.

[0134] The display panel also includes a third connection trace 42, which is located on the side of the second reset signal line Vref2 facing the light-emitting surface of the display panel. The third connection trace 42 and the portions of the second reset signal line Vref2 located on both sides of the second break 41 are electrically connected through a fifth via 43. The third connection trace 42 is also electrically connected to the fourth connection line 36 through a sixth via 44. In the direction perpendicular to the plane of the display panel, the sixth via 44 is located inside the second break 41.

[0135] Similar to the above configuration, when designing the connection between the second reset signal line Vref2 and the fourth connection line 36, this embodiment of the invention adopts a "three-hole design" consisting of two fifth vias 43 and one sixth via 44, which eliminates the need for additional drilling processes in the manufacturing process of the display panel.

[0136] In one feasible implementation, such as Figure 20 As shown, Figure 20This is a partial structural diagram of a display panel provided in an embodiment of the present invention. The display panel further includes a first auxiliary reset signal line Vref1′ extending along the second direction y, the first auxiliary reset signal line Vref1′ being electrically connected to the first reset signal line Vref1, and / or, the display panel further includes a second auxiliary reset signal line Vref2′ extending along the second direction y, the second auxiliary reset signal line Vref2′ being electrically connected to the second reset signal line Vref2.

[0137] The first auxiliary reset signal line Vref1′ and the first reset signal line Vref1 intersect to form a grid structure, and the second auxiliary reset signal line Vref2′ and the second reset signal line Vref2 intersect to form a grid structure, which can effectively reduce the routing load of the reset signal line Vref and reduce the voltage drop of the reset voltage during transmission.

[0138] Furthermore, the first auxiliary reset signal line Vref1′ and the second auxiliary reset signal line Vref2′ can be located between two adjacent pixel columns 13, and the first auxiliary reset signal line Vref1′ and the second auxiliary reset signal line Vref2′ are arranged alternately. There can be only one first auxiliary reset signal line Vref1′ or one second auxiliary reset signal line Vref2′ between two adjacent pixel columns 13.

[0139] Furthermore, it should be noted that in this embodiment of the invention, when the pixel circuit 2 adopts a row-symmetric design, see [reference needed]. Figure 15 Two second scan signal lines Scan2 can be set at the intersection of the 2nth pixel row 17_2n and the 2n+1th pixel row 17_2n+1 to electrically connect to the gate of the second sub-reset transistor M12, thereby shortening the connection distance between the gate of the second sub-reset transistor M12 and the second scan signal line Scan2.

[0140] In one feasible implementation, such as Figure 21 and Figure 22 As shown, Figure 21 This is a schematic diagram of an arrangement of the anode 10 provided in an embodiment of the present invention. Figure 22 This is a schematic diagram of another film layer structure of the display panel provided in an embodiment of the present invention. The light-emitting element 9 includes a red light-emitting element 45, a green light-emitting element 46 and a blue light-emitting element 47, and the anode 10 includes a first anode 48 located on the red light-emitting element 45, a second anode 49 located on the green light-emitting element 46 and a third anode 50 located on the blue light-emitting element 47.

[0141] The display panel also includes a first anode group 51 and a second anode group 52 arranged alternately along a first direction x, wherein the first anode group 51 includes anode units 53 arranged along a second direction y, the anode unit 53 includes a first anode 48 and a second anode 49, and the first anode 48 or the second anode 49 in two adjacent anode units 53 are adjacent to each other, and the second anode group 52 includes a plurality of third anodes 50 arranged along the second direction y.

[0142] Based on the above arrangement, in the two adjacent anode units 53 of the first anode group 51, either the two first anodes 48 are close to each other, or the two second anodes 49 are close to each other. In this way, in the process of manufacturing the display panel, the light-emitting layers above the two first anodes 48 that are close to each other can share one opening in the mask for vapor deposition, and the light-emitting layers above the two second anodes 49 that are close to each other can also share one opening in the mask for vapor deposition. Compared with the method that one light-emitting layer corresponds to only one mask opening, this can increase the light-emitting area and thus improve the aperture ratio.

[0143] Furthermore, see again Figure 22 Each pixel row 17 is respectively provided with a first connection signal line 7, and two adjacent pixel rows 17 and their corresponding two first connection signal lines 7 are symmetrical along the first axis of symmetry 90. In the direction perpendicular to the plane where the display panel is located, only one of the first anode 48 and the second anode 49 overlaps with the first connection signal line 7.

[0144] For example, see again Figure 22 In a direction perpendicular to the plane of the display panel, the first anode 48 overlaps with the first connection signal line 7, while the second anode 49 does not overlap with the first connection signal line 7. Alternatively, as... Figure 23 As shown, Figure 23 This is a schematic diagram of another film layer structure of the display panel provided in an embodiment of the present invention. The second anode 49 overlaps with the first connection signal line 7, while the first anode 48 does not overlap with the first connection signal line 7.

[0145] In this embodiment of the invention, the arrangement of the anode 10 is also designed to match the arrangement of the pixel circuit 2, see [link to relevant documentation]. Figure 22 and Figure 23 The first connection signal line 7 is typically located on one side of the first scan signal line Scan1. When the pixel circuit 2 adopts a row-symmetrical design, the two first scan signal lines Scan1 and the two first connection signal lines 7 corresponding to the two adjacent pixel rows 17 are also symmetrically arranged. Taking the overlap of the first anode 48 and the first connection signal line 7 as an example, Figure 24 As shown, Figure 24This is another structural schematic diagram of the display panel provided in the embodiment of the present invention. When two adjacent second anodes 49 are located between two corresponding first connection signal lines 7 corresponding to two adjacent pixel rows 17, the two adjacent second anodes 49 are far away from the first connection signal lines 7, while the two adjacent first anodes 48 will overlap with the first connection signal lines 7.

[0146] When the first anode 48 does not overlap with the first connection signal line 7, the first anode 48 can avoid the via between the first connection signal line 7 and the second connection signal line 8, thereby preventing the via from affecting the flatness of the first anode 48. When the second anode 49 does not overlap with the first connection signal line 7, the second anode 49 can avoid the via between the first connection signal line 7 and the second connection signal line 8, thereby preventing the via from affecting the flatness of the second anode 49.

[0147] The above configuration allows the anode 10 in the same color light-emitting element 9 to avoid the via between the first connection signal line 7 and the second connection signal line 8, resulting in better flatness of the anode 10 in the color light-emitting element 9, thereby significantly improving the color shift of that color. For example, since green light is more easily visible to the human eye, the second anode 49 in the green light-emitting element 46 can be made to not overlap with the first connection signal line 7, thus significantly improving the color shift of green light.

[0148] In one feasible implementation, such as Figure 25 As shown, Figure 25 This is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention. At least a portion of the second connection signal line 8 includes a first sub-connection line segment 54 and a second sub-connection line segment 55 arranged along a second direction y, with a break between the first sub-connection line segment 54 and the second sub-connection line segment 55. The first sub-connection line segment 54 receives a fixed voltage; for example, the first connection signal line 7 can be electrically connected to a negative power signal line in the display panel, and the second sub-connection line segment 55 is electrically connected to the first connection signal line 7.

[0149] The light-emitting element 9 includes a red light-emitting element 45, a green light-emitting element 46 and a blue light-emitting element 47. In a direction perpendicular to the plane of the display panel, the anode 10 (second anode 49) in a portion of the green light-emitting element 46 overlaps with the first sub-connection segment 54 in two adjacent second connection signal lines 8.

[0150] In at least a portion of the second connection signal lines 8, the second sub-connection segment 55 is used to electrically connect to the indirect signal line 5 via the first connection trace 7, while the first sub-connection segment 54 is used to improve the reflection uniformity of the display panel at different locations. Compared to red and blue, green is more easily visible to the human eye. Therefore, in this embodiment of the invention, by placing the second anode 49 in a portion of the green light-emitting elements 46 above the first connection trace 31, the fixed voltage transmitted on the first connection trace 31 can be used to stabilize the potential on the second anode 49, improving the potential stability of the second anode 49, thereby improving the luminous stability of this portion of the green light-emitting elements 46.

[0151] In one feasible implementation, such as Figure 26 and Figure 27 As shown, Figure 26 This is a schematic diagram of another film layer structure of the display panel provided in an embodiment of the present invention. Figure 27 This is a schematic diagram of a film structure of a threshold compensation transistor M3, a second light-emitting control transistor M5, and a second connection signal line 8 provided in an embodiment of the present invention. The pixel circuit group 11 includes a first pixel circuit group 14, which includes a pair of adjacent pixel circuits 2 in two adjacent pixel columns 13.

[0152] Pixel circuit 2 includes a threshold compensation transistor M3 and a second light-emitting control transistor M5. The second light-emitting control transistor M5 is electrically connected to the anode 10 of the light-emitting element 9 through an anode connection via 56. The threshold compensation transistor M3 is adjacent to the second light-emitting control transistor M5 in the (2n-1)th pixel column 13_2n-1 and the 2nth pixel column 13_2n. Two second connection signal lines 8 are included between the (2n-1)th pixel column 13_2n-1 and the 2nth pixel column 13_2n.

[0153] The threshold compensation transistor M3 and the second light-emitting control transistor M5 are electrically connected through the third semiconductor connection line 57, and the portion of the two adjacent third semiconductor connection lines 57 extending along the second direction y is located between the two adjacent second connection signal lines 8.

[0154] In the above configuration, the portions of the second connection signal line 8 and the third semiconductor connection line 57 extending along the second direction y are kept apart from each other, which can reduce the mutual interference of signals transmitted on the second connection signal line 8 and the third semiconductor connection line 57, thereby avoiding potential fluctuations on the third semiconductor connection line 57 and improving the stability of the driving current transmitted from the second light-emitting control transistor M5 to the anode 10.

[0155] Furthermore, such as Figure 28 As shown, Figure 28This is a schematic diagram of another film structure for the threshold compensation transistor M3, the second light-emitting control transistor M5, and the second connection signal line 8 provided in an embodiment of the present invention. The threshold compensation transistor M3 includes a first gate g1 and a second gate g2. In this case, the threshold compensation transistor M3 is a dual-gate transistor. The off-state leakage current of the threshold compensation transistor M3 is low, which can reduce the influence of the off-state leakage current of the threshold compensation transistor M3 on the gate potential of the driving transistor M0. The second connection signal line 8 is located between the first gate g1 and the second gate g2 of the threshold compensation transistor M3, thereby reducing the overlap area between the second connection signal line 8 and the gate of the threshold compensation transistor M3, reducing the influence of the signal on the second connection signal line 8 on the gate potential of the threshold compensation transistor M3, and improving the stability of the operating state of the threshold compensation transistor M3.

[0156] Furthermore, it should be noted that, provided that the second connection signal line 8 is located between the first gate g1 and the second gate g2 of the threshold compensation transistor M3, the distance between two adjacent second connection signal lines 8 may be equal to or unequal to the distance between two adjacent first signal lines 3.

[0157] In one feasible implementation, such as Figure 29 As shown, Figure 29 This is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention. The pixel circuit group 11 includes a first pixel circuit group 14, and the first pixel circuit group 14 includes a pair of adjacent pixel circuits 2 in two adjacent pixel columns 13.

[0158] The second connection signal line 8 includes a first sub-connection segment 54 and a second sub-connection segment 55 arranged along the second direction y. There is a break between the first sub-connection segment 54 and the second sub-connection segment 55. The first sub-connection segment 54 receives a fixed voltage, and the second sub-connection segment 55 is electrically connected to the indirect signal line 5.

[0159] Pixel circuit 2 includes a second light-emitting control transistor M5, which is electrically connected to the anode 10 of light-emitting element 9 through an anode connection via 56. The second light-emitting control transistors M5 in the (2n-1)th pixel column 13_2n-1 and the 2nth pixel column 13_2n are adjacent. In the second connection signal line 8, the distance between the first sub-connection segment 54 and the anode connection via 56 is less than the distance between the second sub-connection segment 55 and the anode connection via 56.

[0160] When the pixel circuit 2 adopts a column symmetrical design, the anode connection via 56 will be close to the second connection signal line 8. Since the first sub-connection segment 54 in the second connection signal line 8 receives a fixed voltage, the first sub-connection segment 54 is brought closer to the anode connection via 56. The first sub-connection segment 54 can be used to improve the node potential stability of the anode connection via 56, thereby improving the potential stability on the anode 10.

[0161] Furthermore, it should be noted that after adjusting the position of the first sub-connection segment 54 in the second connection signal line 8, in one configuration, the spacing between the second sub-connection segments 55 in two adjacent second connection signal lines 8 can be less than the spacing between two adjacent first signal lines 3, while the spacing between the first sub-connection segments 54 in two adjacent second connection signal lines 8 can be less than, equal to or greater than the spacing between two adjacent first signal lines 3.

[0162] In one feasible implementation, such as Figure 30 As shown, Figure 30 This is a schematic diagram of another film layer structure of the display panel provided in an embodiment of the present invention. The indirect signal line 5 and the first connection signal line 7 are electrically connected through the first connection via 58, and the first connection signal line 7 and the second connection signal line 8 are electrically connected through the second connection via 59. It should be noted that in the film layer structure of the display panel, when vias are set on the metal traces, in order to ensure connection reliability, the size of the metal trace at the location of the via is significantly larger than the size at the conventional location.

[0163] In a direction perpendicular to the plane of the display panel, at least a portion of the anode 10 also overlaps with at least two first structures 61. The first structures 61 are located on the side of the anode 10 facing away from the light-emitting surface of the display panel. The first structure 61 includes a second connection via 59 and / or a pad metal 60, wherein the width of the pad metal 60 in the second direction y is greater than the line width of the first connection signal line 7, and the width of the pad metal 60 in the first direction x is greater than the line width of the second connection signal line 8.

[0164] In this embodiment of the invention, when at least a portion of the anode 10 overlaps with at least two first structures 61, these at least two first structures 61 can be used to increase the area of ​​the anode 10 that is raised, weaken the difference in film undulation in different regions, thereby effectively improving the flatness of the film of this portion of the anode 10 and effectively improving the color shift phenomenon.

[0165] It should be noted that, Figure 30 The shape of the anode 10 shown is for illustrative purposes only. In other alternative embodiments, the shape of the anode 10 may also be a rounded rectangle, a circle, etc.

[0166] In one feasible implementation, see Figure 30 , combined Figure 31 , Figure 31 This is a schematic diagram of a film layer stacking for a display panel provided in an embodiment of the present invention. The second connection signal line 8 includes adjacent first-type second connection signal lines 91 and second-type second connection signal lines 92. The first-type second connection signal lines 91 and second-type second connection signal lines 92 are respectively electrically connected to the same first connection signal line 7 through a second connection via 59. In a direction perpendicular to the plane of the display panel, a portion of the anode 10_1 overlaps with the second connection via 59 connected to the first-type second connection signal lines 91 and second-type second connection signal lines 92. For clarity, Figure 30 and Figure 31 The anode 10 in this part is indicated by reference numeral 10_1 in the attached drawing.

[0167] In this setup method, see Figure 31 When the anode 10_1 overlaps with a portion of semiconductor traces 81 or metal traces 82, these traces may cause a small-area localized arching of the anode 10_1, resulting in significant film undulations at different locations on the anode 10_1. However, based on the aforementioned configuration, when a portion of the anode 10_1 overlaps with at least two second connection vias 59, the larger area of ​​the metal film layer of the first connection signal line 7 at the second connection via 59, and the larger area of ​​the metal film layer of the first type of second connection signal line 91 and the second type of second connection signal line 92 at the second connection via 59, can uniformly and significantly raise the anode 10_1, thereby effectively reducing the film undulations of the anode 10_1 and improving the flatness of the film layer in this portion of the anode 10_1.

[0168] It should be noted that, taking the connection of the first signal line 3 to the fan-out line as an example, even if the first type of second connection signal line 91 and the second type of second connection signal line 92 are electrically connected to the same first connection signal line 7, when designing the fan-out line, only one of the first type of second connection signal line 91 and the second type of second connection signal line 92 can be connected to the fan-out line, and this will not affect the normal transmission of the signal.

[0169] In addition, the first type of second connection signal line 91 and the second type of second connection signal line 92 can also be connected to multiple first connection signal lines 7, so that more anodes 10 can overlap with the two second connection vias 59. At this time, it is only necessary to ensure that only one of these multiple first connection signal lines 7 has a connection relationship with the indirect signal line 5, and the normal transmission of the signal will not be affected.

[0170] In one feasible implementation, see Figure 30 , combined Figure 32 , Figure 32This is another schematic diagram of film layer stacking for a display panel provided in an embodiment of the present invention. In the direction perpendicular to the plane of the display panel, a portion of the anode 10_2 overlaps with the second connection via 59 and the pad metal 60, respectively. This allows the first connection signal line 7 and the second connection signal line 8 to simultaneously and uniformly raise this portion of the anode 10_2 over a large area using the larger metal film layer at the second connection via 59 and the pad metal 60, thus reducing the film layer undulation of the anode 10_2 and improving the flatness of this portion of the anode 10. For clarity, Figure 30 and Figure 32 The anode 10 in this part is indicated by reference numeral 10_2 in the attached drawing.

[0171] In one feasible implementation, see Figure 30 , combined Figure 33 , Figure 33 This is another schematic diagram of film layer stacking for a display panel provided in an embodiment of the present invention. In the direction perpendicular to the plane of the display panel, a portion of the anode 10_3 does not overlap with the second connecting via 59 but overlaps with the pad metal 60. This allows at least two pad metals 60 to uniformly and extensively raise this portion of the anode 10_3, improving the flatness of the film layer of this portion of the anode 10_3. For clarity, Figure 30 and Figure 33 The anode 10 in this part is indicated by reference numeral 10_3 in the attached drawing.

[0172] Furthermore, see again Figure 32 and Figure 33 The pad metal 60 includes a first metal pad 63 and a second metal pad 64. The first metal pad 63 is disposed in the same layer as the second connection signal line 8, and the second metal pad 64 is disposed in the same layer as the first connection signal line 7.

[0173] This configuration simplifies the process by allowing the first pad metal 60 and the second connection signal line 8 to be formed using the same patterning process, and vice versa. Furthermore, when a portion of the anode 10 overlaps with the second connection via 59, the total film thickness of the first and second pad metal 60 is consistent with the total film thickness of the second connection signal line 8 and the first connection signal line 7, resulting in a flatter surface for that portion of the anode 10.

[0174] In one feasible implementation, such as Figure 34 and Figure 35 As shown, Figure 34 This is a schematic diagram showing an overlap between the anode 10 and the first structure 61 provided in an embodiment of the present invention. Figure 35This is another schematic diagram showing the overlap between the anode 10 and the first structure 61 provided in an embodiment of the present invention. In a direction perpendicular to the plane of the display panel, the anode 10 is symmetrical along a second axis of symmetry 65, dividing it into a first part 66 and a second part 67. The number of first structures 61 overlapping the first part 66 is equal to the number of first structures 61 overlapping the second part 67. In this case, the symmetrical first part 66 and the second part 67 of the anode 10 overlap with the same number of first structures 61, resulting in a more consistent overall height for both parts and improved flatness of the anode 10.

[0175] In one feasible implementation, such as Figure 36 and Figure 37 As shown, Figure 36 This is another overlapping schematic diagram of the anode 10 and the first structure 61 provided in an embodiment of the present invention. Figure 37 This is another overlapping schematic diagram of the anode 10 and the first structure 61 provided in the embodiment of the present invention. In the direction perpendicular to the plane where the display panel is located, the anode 10 is symmetrical along the second axis of symmetry 65, and the orthographic projections of at least two first structures 61 overlapping with the anode 10 are symmetrical along the second axis of symmetry 65, so as to further improve the flatness of the film layer of the anode 10.

[0176] In one feasible implementation, see again Figure 35 and Figure 37 The number of first structures 61 overlapping with the anode 10 is m, m≥4, so that the anode 10 overlaps with a sufficient number of first structures 61, raising more positions of the anode 10 and making the surface of the anode 10 more flat.

[0177] It should be noted that the overlap between the anode 10 and the first structure 61 shown in the accompanying drawings of this embodiment is merely illustrative and does not represent a limitation on the number of second connecting vias 59 and pad metal 60 overlapping with the anode 10. In other optional embodiments of this invention, the anode 10 may also overlap with other numbers of second connecting vias 59 and other numbers of pad metal 60.

[0178] In one feasible implementation, such as Figure 38 As shown, Figure 38 This is another schematic diagram of the structure of the display panel provided in the embodiment of the present invention. The pixel circuit 2 includes a second light-emitting control transistor M5, and the second light-emitting control transistor M5 is electrically connected to the anode 10 of the light-emitting element 9 through an anode connection via 56.

[0179] The display panel includes multiple pixel rows 17 arranged along a second direction y, and each pixel row 17 includes multiple pixel circuits 2 arranged along a first direction x. Pixel circuit group 11 includes a second pixel circuit group 34, which includes a pair of adjacent pixel circuits 2 in two adjacent pixel rows 17. The second light-emitting control transistors M5 in the 2n-2n and 2n+1 pixel rows 17-2n+1 are arranged adjacently, and n takes values ​​of 1, 2, 3, 4, 5, ...

[0180] Interconnect signal line 5 is electrically connected to first connection signal line 7 through first connection via 58, and first connection signal line 7 is electrically connected to second connection signal line 8 through second connection via 59. Second connection via 59 is located near the boundary between the (2n-1)th pixel row 17_2n-1 and the 2nth pixel row 17_2n. Furthermore, in a direction perpendicular to the plane of the display panel, at least a portion of the anode 10 does not overlap with the second connection via 59.

[0181] When the pixel circuit 2 is designed with row symmetry, the anode connection vias 56 between the second light-emitting control transistor M5 and the anode 10 are arranged in a relatively concentrated manner. When designing the second connection via 59, by making the second connection via 59 avoid the anode connection via 56 and setting it at a position far away from it, at least part of the anode 10 can avoid the second connection via 59, thereby avoiding the second connection via 59 from affecting the flatness of the anode 10.

[0182] In one feasible implementation, such as Figure 39 As shown, Figure 39 This is another schematic diagram of the structure of the display panel provided in an embodiment of the present invention. The first signal line 3 includes a first type of first signal line 70. In the first type of first signal line 70, the indirect signal line 5 is located on both sides of the direct signal line 6 in the first direction x. The second connecting signal line 8 connected to the indirect signal line 5 is located on the side of the indirect signal line 5 closer to the direct signal line 6, thereby leading the indirect signal line 5 to the middle position of the display area 1. As a result, when setting the fan-out line 71, the fan-out line 71 can be concentrated in the area directly opposite the driver chip 72, reducing the width of the bezel corner and optimizing the narrow bezel design.

[0183] In one feasible implementation, such as Figure 40 As shown, Figure 40 This is another schematic diagram of the structure of the display panel provided in an embodiment of the present invention. The display area 1 includes an opening 74. The first signal line 3 includes a second type of first signal line 73. In the second type of first signal line 73, some inter-connecting signal lines 5 are located on both sides of the opening 74 in the first direction x. The inter-connecting signal lines 5 on both sides of the opening 74 are electrically connected by connecting signal lines 4, thereby connecting the disconnected inter-connecting signal lines 5 on both sides by using connecting signal lines 4 to form a continuous signal transmission path.

[0184] In one feasible implementation, the first signal line 3 includes a data line (Data) and / or a power signal line (PVDD). When the first signal line 3 includes a data line (Data), the data line (Data) can be... Figure 39 In the connection method shown, when the first signal line 3 includes the power signal line PVDD, the power signal line PVDD can be used as follows: Figure 40 The connection method shown.

[0185] It should be noted that when the first signal line 3 includes a data line, see [reference needed]. Figure 5 The pixel circuit 2 also includes a data writing transistor M2, which is electrically connected to the data line Data. When the pixel circuit 2 adopts a column symmetrical design, the data line Data is located between the driving transistors M0 in the 2nth pixel column 13_2n and the 2n+1th pixel column 13_2n+1. At the same time, the data writing transistors M2 in the 2nth pixel column 13_2n and the 2n+1th pixel column 13_2n+1 are arranged adjacent to each other so that the position of the data writing transistor M2 matches the data line Data.

[0186] Furthermore, embodiments of the present invention use Figure 2 Taking the circuit structure shown as an example, the specific structure and working principle of the pixel circuit will be explained.

[0187] The pixel circuit may specifically include a driving transistor M0, a first sub-reset transistor M11, a second sub-reset transistor M12, a data writing transistor M2, a threshold compensation transistor M3, a first light-emitting control transistor M4, a second light-emitting control transistor M5, and a storage capacitor C.

[0188] In this configuration, the gate of the first sub-reset transistor M11 is electrically connected to the first scan signal line Scan1, the first terminal of the first sub-reset transistor M11 is electrically connected to the first reset signal line Vref1, and the second terminal of the first sub-reset transistor M11 is electrically connected to the gate of the driving transistor M0. The first sub-reset transistor M11 is used to perform a reset operation on the gate of the driving transistor M0 when it is turned on.

[0189] The gate of the second sub-reset transistor M12 is electrically connected to the second scan signal line Scan2, the first terminal of the second sub-reset transistor M12 is electrically connected to the second reset signal line Vref2, and the second terminal of the second sub-reset transistor M12 is electrically connected to the anode of the light-emitting element 9. The second sub-reset transistor M12 is used to perform a reset operation on the anode of the light-emitting element 9 when it is turned on.

[0190] The gates of data writing transistor M2 and threshold compensation transistor M3 are electrically connected to the second scan signal line Scan2. The first terminal of data writing transistor M2 is electrically connected to the data line Data, and the second terminal of data writing transistor M2 is electrically connected to the first terminal of driving transistor M0. The first terminal of threshold compensation transistor M3 is electrically connected to the second terminal of driving transistor M0, and the second terminal of threshold compensation transistor M3 is electrically connected to the gate of driving transistor M0. Data writing transistor M2 and threshold compensation transistor M3 are used to charge the gate of driving transistor M0 and perform threshold compensation when it is turned on.

[0191] The gates of the first light-emitting control transistor M4 and the second light-emitting control transistor M5 are electrically connected to the light-emitting control signal line Emit, respectively. The first terminal of the first light-emitting control transistor M4 is electrically connected to the power supply signal line PVDD, and the second terminal of the first light-emitting control transistor M4 is electrically connected to the first terminal of the driving transistor M0. The first terminal of the second light-emitting control transistor M5 is electrically connected to the second terminal of the driving transistor M0, and the second terminal of the second light-emitting control transistor M5 is electrically connected to the anode of the light-emitting element 9. The first light-emitting control transistor M4 and the second light-emitting control transistor M5 are used to transmit the driving current converted by the driving transistor M0 to the light-emitting element 9 when they are turned on, thereby driving the light-emitting element 9 to emit light.

[0192] Based on the same inventive concept, embodiments of the present invention also provide a display device, such as... Figure 41 As shown, Figure 41 This is a schematic diagram of a display device provided in an embodiment of the present invention. The display device includes the aforementioned display panel 100. The specific structure of the display panel 100 has been described in detail in the above embodiments and will not be repeated here. Figure 41 The display device shown is for illustrative purposes only. The display device can be any electronic device with display function, such as a mobile phone, tablet computer, laptop computer, e-reader or television.

[0193] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0194] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, include: Display area; A pixel circuit located in the display area, the pixel circuit including a driving transistor and a first reset transistor electrically connected to a reset signal line; A first signal line located in the display area, the first signal line including an indirect signal line and a direct signal line; The connection signal line located in the display area is electrically connected to the inter-connection signal line in at least a portion. The connection signal line includes a first connection signal line extending along a first direction and a second connection signal line extending along a second direction, the second direction intersecting the first direction. A light-emitting element located in the display area, the light-emitting element including an anode; A pixel circuit group, the pixel circuit group including at least a partially symmetrical and adjacent pair of pixel circuits, and the first reset transistors of the pair of pixel circuits in the pixel circuit group are adjacent to each other, the adjacent first reset transistors are connected by a first semiconductor connection line, and the first semiconductor connection line is connected to the reset signal line. A plurality of pixel columns arranged along the first direction, the pixel columns including a plurality of pixel circuits arranged along the second direction, wherein the driving transistors in the pixel columns are respectively provided with two first signal lines and two second connection signal lines on both sides of the first direction, and in a direction perpendicular to the plane of the display panel, at least a portion of the anodes overlaps with two adjacent first signal lines, and / or, at least a portion of the anodes overlaps with two adjacent second connection signal lines. The pixel circuit group includes a first pixel circuit group, which includes a pair of adjacent pixel circuits in two adjacent pixel columns; the first reset transistor includes a first sub-reset transistor and a second sub-reset transistor, and the reset signal line includes a first reset signal line electrically connected to the first sub-reset transistor and a second reset signal line electrically connected to the second sub-reset transistor; the first semiconductor connection line includes a first connection line and a second connection line; wherein, the second sub-reset transistors in the (2n-1)th pixel column and the 2nth pixel column are arranged adjacently, and two adjacent second sub-reset transistors are connected through the second connection line, and the second connection line is electrically connected to the second reset signal line; the first sub-reset transistors in the 2nth pixel column and the (2n+1)th pixel column are arranged adjacently, and two adjacent first sub-reset transistors are connected through the first connection line, and the first connection line is electrically connected to the first reset signal line, and n takes values ​​of 1, 2, 3, 4, 5, ... in sequence; Alternatively, the display panel includes a plurality of pixel rows arranged along the second direction, each pixel row including a plurality of pixel circuits arranged along the first direction, the pixel circuit group including a second pixel circuit group, the second pixel circuit group including a pair of adjacent pixel circuits in two adjacent pixel rows; the first reset transistor includes a first sub-reset transistor and a second sub-reset transistor, the reset signal line including a first reset signal line electrically connected to the first sub-reset transistor and a second reset signal line electrically connected to the second sub-reset transistor; the first semiconductor connection line includes a third connection line and a fourth connection line; wherein, the first sub-reset transistors in the (2n-1)th pixel row and the 2nth pixel row are arranged adjacently, and two adjacent first sub-reset transistors are connected through the third connection line, the third connection line being electrically connected to the first reset signal line; the second sub-reset transistors in the 2nth pixel row and the (2n+1)th pixel row are arranged adjacently, and two adjacent second sub-reset transistors are connected through the fourth connection line, the fourth connection line being electrically connected to the second reset signal line, and n taking values ​​of 1, 2, 3, 4, 5, ... in sequence.

2. The display panel according to claim 1, characterized in that, The pixel circuit group includes the first pixel circuit group; The first reset signal line includes a first sub-reset line and a second sub-reset line that are electrically connected, and the second reset signal line includes a third sub-reset line and a fourth sub-reset line that are electrically connected, wherein the first sub-reset line and the third sub-reset line extend along the first direction, and the second reset line and the fourth reset line extend along the second direction; The second sub-reset line and the fourth sub-reset line are arranged alternately, with a pixel column between two adjacent second sub-reset lines and the fourth sub-reset line, and the fourth sub-reset line is located between the 2n-1th pixel column and the 2nth pixel column; The first connecting line is electrically connected to the second sub-reset line, and the second connecting line is electrically connected to the fourth sub-reset line.

3. The display panel according to claim 2, characterized in that, The display panel further includes a plurality of pixel rows arranged along the second direction, the pixel rows including a plurality of pixel circuits arranged along the first direction; The first sub-reset line and the third sub-reset line are arranged alternately, and there is a driving transistor in the pixel row between two adjacent first sub-reset lines and the third sub-reset line.

4. The display panel according to claim 1, characterized in that, The pixel circuit group includes the first pixel circuit group; The display panel further includes a plurality of pixel rows arranged along the second direction, the pixel rows including a plurality of pixel circuits arranged along the first direction; The first reset signal line extends along the first direction, and one first reset signal line is provided for each pixel row. The second reset signal line extends along the second direction, and the second reset signal line is located between the (2n-1)th pixel column and the 2nth pixel column.

5. The display panel according to claim 4, characterized in that, The first sub-reset transistor is also electrically connected to the first scan signal line, and the first connection line and the first reset signal line connected thereto are located on the same side of the first scan signal line.

6. The display panel according to claim 1, characterized in that, The pixel circuit group includes a first pixel circuit group, which includes a pair of adjacent pixel circuits in two adjacent pixel columns, and the first signal line is located between the driving transistors in the 2nth pixel column and the 2n+1th pixel column; The pixel circuit further includes a first light-emitting control transistor electrically connected to a power signal line extending along the second direction, wherein the first light-emitting control transistor in the 2nth pixel column and the 2n+1th pixel column are adjacent to each other, and the two power signal lines connected to the 2nth pixel column and the 2n+1th pixel column are adjacent to each other. The display panel further includes an auxiliary power connection line, which is located on the side of the first signal line and the second connection signal line facing away from the light-emitting surface of the display panel. The auxiliary power connection line includes a first line segment and a first carrier portion. The first carrier portion is electrically connected to the power signal line. The size of the first carrier portion in the second direction is larger than the size of the first line segment in the second direction. In the direction perpendicular to the plane of the display panel, the first carrier portion overlaps with two adjacent first signal lines. The portion of the first signal line that overlaps with the first carrier portion is the first trace segment. In a direction perpendicular to the plane where the display panel is located, a portion of the anode overlaps with two adjacent first trace segments.

7. The display panel according to claim 6, characterized in that, The auxiliary power connection cable also includes a second carrier portion, the second carrier portion having a larger dimension in the second direction than the first line segment having a larger dimension in the second direction, and the second carrier portion overlapping with two adjacent second connection signal lines in a direction perpendicular to the plane of the display panel. The portion of the second connection signal line that overlaps with the second carrier portion is the second trace segment. In a direction perpendicular to the plane where the display panel is located, a portion of the anode overlaps with two adjacent second trace segments.

8. The display panel according to claim 6, characterized in that, The gate of the driving transistor is electrically connected to the first node; The auxiliary power connection cable also includes a first protrusion protruding from the first line segment, and the first protrusion overlaps with the first node in a direction perpendicular to the plane where the display panel is located.

9. The display panel according to claim 6, characterized in that, The first light-emitting control transistors adjacent in the 2nth pixel column and the 2n+1th pixel column are connected by a second semiconductor connection line; The power signal line includes a plurality of second segments, with a gap between two adjacent second segments; The first carrier portion includes a main body portion and a protrusion portion. The ends of the second line segments of two adjacent power signal lines near the protrusion portion are connected by a first connecting trace. The second semiconductor connection line is electrically connected to the first connecting trace through a first via. The first connecting trace is electrically connected to the protrusion portion through a second via.

10. The display panel according to claim 9, characterized in that, In a direction perpendicular to the plane of the display panel, the first via and the second via do not overlap.

11. The display panel according to claim 1, characterized in that, The pixel circuit group includes a second pixel circuit group; The first reset signal line and the second reset signal line extend along the first direction, the first reset signal line and the second reset signal line are arranged alternately, and there is a driving transistor in the pixel row between two adjacent first reset signal lines and second reset signal lines; The first reset signal line is located between the driving transistors in the (2n-1)th pixel row and the 2nth pixel row.

12. The display panel according to claim 11, characterized in that, The first reset signal line includes a first break, and in a direction perpendicular to the plane where the display panel is located, the first break overlaps with the third connecting line; The display panel further includes a second connection trace, which is located on the side of the first reset signal line facing the light-emitting surface of the display panel. The second connection trace and the portions of the first reset signal line located on both sides of the first break are electrically connected through a third via. The second connection trace is also electrically connected to the third connection line through a fourth via. In a direction perpendicular to the plane of the display panel, the fourth via is located within the first break.

13. The display panel according to claim 11, characterized in that, The second reset signal line includes a second break, which overlaps with the fourth connecting line in a direction perpendicular to the plane of the display panel. The display panel further includes a third connection trace, which is located on the side of the second reset signal line facing the light-emitting surface of the display panel. The third connection trace and the portions of the second reset signal line located on both sides of the second break are electrically connected through a fifth via. The third connection trace is also electrically connected to the fourth connection line through a sixth via. In a direction perpendicular to the plane of the display panel, the sixth via is located within the second break.

14. The display panel according to claim 11, characterized in that, The display panel further includes a first auxiliary reset signal line extending along the second direction, the first auxiliary reset signal line being electrically connected to the first reset signal line; And / or, the display panel further includes a second auxiliary reset signal line extending along the second direction, the second auxiliary reset signal line being electrically connected to the second reset signal line.

15. The display panel according to claim 1, characterized in that, The pixel circuit group includes a second pixel circuit group; The light-emitting elements include a red light-emitting element, a green light-emitting element, and a blue light-emitting element, and the anode includes a first anode located in the red light-emitting element, a second anode located in the green light-emitting element, and a third anode located in the blue light-emitting element; The display panel further includes a first anode group and a second anode group arranged alternately along the first direction, wherein the first anode group includes anode units arranged along the second direction, each anode unit including a first anode and a second anode, and the first anodes or the second anodes in two adjacent anode units are adjacent to each other, and the second anode group includes a plurality of third anodes arranged along the second direction.

16. The display panel according to claim 15, characterized in that, Each pixel row is respectively provided with a first connection signal line, and two adjacent pixel rows and the two corresponding first connection signal lines are symmetrical along a first axis of symmetry. In a direction perpendicular to the plane of the display panel, only one of the first anode and the second anode overlaps with the first connection signal line.

17. The display panel according to claim 1, characterized in that, At least a portion of the second connection signal line includes a first sub-connection segment and a second sub-connection segment arranged along the second direction, with a break between the first sub-connection segment and the second sub-connection segment, the first sub-connection segment receiving a fixed voltage, and the second sub-connection segment being electrically connected to the first connection signal line; The light-emitting elements include red light-emitting elements, green light-emitting elements and blue light-emitting elements. In a direction perpendicular to the plane of the display panel, the anode of a portion of the green light-emitting elements overlaps with the first sub-connection segment of two adjacent second connection signal lines.

18. The display panel according to claim 1, characterized in that, The pixel circuit group includes a first pixel circuit group, which includes a pair of adjacent pixel circuits in two adjacent pixel columns. The pixel circuit includes a threshold compensation transistor and a second light-emitting control transistor. The second light-emitting control transistor is electrically connected to the anode of the light-emitting element through an anode connection via. The threshold compensation transistors in the (2n-1)th pixel column and the 2nth pixel column are adjacent to each other, and the second light-emitting control transistors are adjacent to each other. Two second connection signal lines are included between the (2n-1)th pixel column and the 2nth pixel column; The threshold compensation transistor and the second light-emitting control transistor are electrically connected through a third semiconductor connection line, and the portion of the two adjacent third semiconductor connection lines extending along the second direction is located between the two adjacent second connection signal lines.

19. The display panel according to claim 18, characterized in that, The threshold compensation transistor includes a first gate and a second gate; The second connection signal line is located between the first gate and the second gate of the threshold compensation transistor.

20. The display panel according to claim 1, characterized in that, The pixel circuit group includes a first pixel circuit group, which includes a pair of adjacent pixel circuits in two adjacent pixel columns. The second connection signal line includes a first sub-connection line segment and a second sub-connection line segment arranged along the second direction. There is a break between the first sub-connection line segment and the second sub-connection line segment. The first sub-connection line segment receives a fixed voltage, and the second sub-connection line segment is electrically connected to the inter-connection signal line. The pixel circuit includes a second light-emitting control transistor, which is electrically connected to the anode of the light-emitting element through an anode connection via. The second light-emitting control transistors in the (2n-1)th pixel column and the 2nth pixel column are adjacent to each other. In the second connection signal line, the distance between the first sub-connection segment and the anode connection via is less than the distance between the second sub-connection segment and the anode connection via.

21. The display panel according to claim 1, characterized in that, The inter-connection signal line is electrically connected to the first connection signal line through a first connection via, and the first connection signal line is electrically connected to the second connection signal line through a second connection via; In a direction perpendicular to the plane of the display panel, at least a portion of the anode also overlaps with at least two first structures. The first structures are located on the side of the anode facing away from the light-emitting surface of the display panel. The first structures include the second connection via and / or pad metal, wherein the width of the pad metal in the second direction is greater than the line width of the first connection signal line, and the width of the pad metal in the first direction is greater than the line width of the second connection signal line.

22. The display panel according to claim 21, characterized in that, The second connection signal line includes adjacent first type second connection signal lines and second type second connection signal lines, and the first type second connection signal lines and the second type second connection signal lines are respectively electrically connected to the same first connection signal line through the second connection via; In a direction perpendicular to the plane of the display panel, a portion of the anode overlaps with the second connection vias connected to the first type of second connection signal line and the second type of second connection signal line, respectively.

23. The display panel according to claim 21, characterized in that, In a direction perpendicular to the plane of the display panel, a portion of the anode overlaps with the second connecting via and the pad metal, respectively.

24. The display panel according to claim 21, characterized in that, In a direction perpendicular to the plane of the display panel, a portion of the anode does not overlap with the second connection via but overlaps with the pad metal.

25. The display panel according to claim 21, characterized in that, The padding metal includes a first metal padding layer and a second metal padding layer. The first metal padding layer is disposed in the same layer as the second connection signal line, and the second metal padding layer is disposed in the same layer as the first connection signal line.

26. The display panel according to claim 21, characterized in that, In a direction perpendicular to the plane of the display panel, the anode is symmetrical along a second axis of symmetry. The anode is divided into a first part and a second part by the second axis of symmetry. The number of first structures overlapping the first part and the number of first structures overlapping the second part are equal.

27. The display panel according to claim 21, characterized in that, In a direction perpendicular to the plane of the display panel, the anode is symmetrical along the second axis of symmetry, and the orthographic projections of at least two of the first structures overlapping the anode are symmetrical along the second axis of symmetry.

28. The display panel according to claim 21, characterized in that, The number of the first structures overlapping the anode is m, where m ≥ 4.

29. The display panel according to claim 1, characterized in that, The pixel circuit includes a second light-emitting control transistor, and the second light-emitting control transistor is electrically connected to the anode of the light-emitting element through an anode connection via. The display panel includes a plurality of pixel rows arranged along the second direction, the pixel rows include a plurality of pixel circuits arranged along the first direction, the pixel circuit group includes a second pixel circuit group, the second pixel circuit group includes a pair of adjacent pixel circuits in two adjacent pixel rows, wherein the second light-emitting control transistors in the 2nth pixel row and the 2n+1th pixel row are arranged adjacently, and n takes values ​​of 1, 2, 3, 4, 5, ... in sequence; The inter-connection signal line is electrically connected to the first connection signal line through a first connection via, and the first connection signal line is electrically connected to the second connection signal line through a second connection via. The second connection via is located near the boundary between the (2n-1)th pixel row and the 2nth pixel row, and at least a portion of the anode does not overlap with the second connection via in a direction perpendicular to the plane of the display panel.

30. The display panel according to claim 1, characterized in that, The first signal line includes a first type of first signal line. In the first type of first signal line, the indirect signal line is located on both sides of the direct signal line in the first direction, and the second connecting signal line connected to the indirect signal line is located on the side of the indirect signal line closer to the direct signal line.

31. The display panel according to claim 1, characterized in that, The display area includes an opening; The first signal line includes a second type of first signal line, in which some of the inter-connecting signal lines are located on both sides of the opening in the first direction, and the inter-connecting signal lines on both sides of the opening are electrically connected by connecting signal lines.

32. The display panel according to claim 1, characterized in that, The first signal line includes a data line and / or a power signal line.

33. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 32.

Images