A semiconductor device structure and its fabrication method
By using (110) single-crystal silicon substrates and selective region epitaxial growth technology in HEMT devices, the problems of HEMT device density and dislocation density were solved, and high-density integration and high-performance HEMT device fabrication were realized.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-11-01
- Publication Date
- 2026-04-03
AI Technical Summary
Existing HEMT devices have low fabrication density per unit wafer and high dislocation density in the epitaxial layer, resulting in insufficient device performance reliability.
Using (110) single-crystal silicon as the substrate, a ridge epitaxial portion of a III-V compound semiconductor layer is grown by setting a growth barrier layer on the sidewall of the groove and combining selective region epitaxial growth technology to reduce dislocation density and improve space utilization.
This improves the density and performance of HEMT devices per unit wafer, reduces the dislocation density of the epitaxial structure, and improves the device's operating performance and fabrication yield.
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Figure CN115911103B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing technology, and in particular relates to a semiconductor device structure and its fabrication method. Background Technology
[0002] High electron mobility transistors (HEMTs) are a type of field-effect transistor (FET) used to provide high performance levels at microwave frequencies. HEMTs offer low noise figures and the ability to operate at extremely high microwave frequencies, making them suitable for applications in radio frequency (RF) and ultra-high-speed fields. With the rapid development of 5G communication, the structures and processes for improving HEMT application performance have attracted significant attention.
[0003] Existing HEMT devices are mostly fabricated through planar integration on wafers, which significantly limits the density of integrateable HEMT devices due to wafer area, resulting in a limited number of HEMT devices that can be produced per wafer. Furthermore, the limited availability of single-crystal substrates makes growing effective HEMT epitaxial layers on existing substrates a major challenge. Although nucleation layers can be used to achieve epitaxial growth between materials with different lattice constants, this still generates a significant number of lattice dislocations, affecting device reliability. Therefore, it is necessary to improve existing technologies to overcome these shortcomings.
[0004] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating the understanding of those skilled in the art. It should not be assumed that the above technical solutions are known to those skilled in the art simply because these solutions have been described in the background section of this application. Summary of the Invention
[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a semiconductor device structure and its fabrication method, which solves the problems of low density of HEMT devices that can be fabricated on a single wafer and high dislocation density of epitaxial layers in HEMT devices in the prior art.
[0006] To achieve the above objectives, the present invention provides a method for fabricating a semiconductor device structure, the method comprising the following steps:
[0007] A substrate layer is provided, which is made of (110) monocrystalline silicon;
[0008] The substrate layer is patterned to form a plurality of alternating grooves, each groove including a first sidewall and a second sidewall disposed opposite to each other;
[0009] A growth barrier layer is provided on the first sidewall of the plurality of grooves;
[0010] An epitaxial structure is provided on the second sidewall of a plurality of grooves covered with the growth barrier layer. The epitaxial structure protrudes from the groove to form a ridge-shaped epitaxial portion, and the ridge-shaped epitaxial portions are isolated from each other. The epitaxial structure includes a III-V compound semiconductor layer.
[0011] Optionally, the fabrication method further includes: disposing a gate on the ridge-shaped epitaxial portion; the gate being formed on the ridge-shaped epitaxial portion at a preset angle to the second sidewall; and forming a source and a drain by embedding or embedding them within or outside the ridge-shaped epitaxial portion.
[0012] Optionally, before the extensional structure is provided on the second sidewall of the groove, the groove is cleaned with boiling aqua regia.
[0013] Optionally, after cleaning the groove with boiling aqua regia, the groove is then cleaned with a hydrofluoric acid solution with a concentration of less than or equal to 0.5%.
[0014] The present invention also provides a semiconductor device structure, which is prepared by any of the above-described preparation methods, and the semiconductor device structure includes:
[0015] Substrate layer, growth barrier layer, epitaxial structure;
[0016] The substrate layer is provided with a plurality of alternating grooves, each groove including a first sidewall and a second sidewall disposed opposite to each other; the material of the substrate layer is (110) monocrystalline silicon.
[0017] The growth barrier layer covers the first sidewall of the plurality of grooves, the epitaxial structure is disposed on the second sidewall of the plurality of grooves covered by the growth barrier layer, and protrudes from the grooves to form a ridge-shaped epitaxial portion, the ridge-shaped epitaxial portions being isolated from each other, and the epitaxial structure comprising a III-V compound semiconductor layer.
[0018] Optionally, a device structure is also formed on the epitaxial structure, the device structure including one or more of HEMT devices, detector devices or LED light-emitting devices based on the III-V compound semiconductor layer.
[0019] Optionally, a platform is included between two adjacent grooves, the groove includes a bottom surface, and the growth barrier layer covers the first sidewall, the bottom surface and the platform connected to the first sidewall of the plurality of grooves; the ridge-shaped extension portion of the epitaxial structure is disposed on the growth barrier layer of the platform along the second direction.
[0020] Optionally, the length of the bottom surface along the first direction is set to 2-10 micrometers, the length of the first sidewall along the second direction is 5-15 micrometers, the length of the second sidewall along the second direction is 5-15 micrometers, the length of the platform along the first direction is 1-10 micrometers, the length of the bottom surface along the first direction is less than the length of the first sidewall along the second direction, and the first direction is perpendicular to the second direction.
[0021] Optionally, the epitaxial structure includes a nucleation layer and a III-V compound semiconductor layer; the nucleation layer is in contact with the second sidewall, and the nucleation layer material is aluminum nitride; the III-V compound semiconductor layer is disposed on the surface of the nucleation layer, and the III-V compound semiconductor layer includes a barrier structure formed by an AlGaN layer and a GaN layer.
[0022] Optionally, when the device structure is a HEMT device based on the III-V compound semiconductor layer, the semiconductor device structure further includes an electrode layer, which is disposed on each epitaxial structure. The electrode layer includes a gate, a source, and a drain. The gate is mounted on the ridge epitaxial portion of the epitaxial structure, and the gates corresponding to different ridge epitaxial portions are independently separated from each other or formed into an effective electrical connection according to a preset combination.
[0023] Both the source and the drain are embedded or externally in the ridge-shaped extension portion. The source and the drain corresponding to different ridge-shaped extension portions are independently separated from each other or formed into an effective electrical connection according to a preset combination.
[0024] As described above, the semiconductor device structure and its fabrication method of the present invention have the following beneficial effects:
[0025] By using (110) single-crystal silicon, the epitaxial structure can grow an effective epitaxial surface on the sidewall, improving the space utilization of the device on the wafer and increasing the density of HEMT devices that can be accommodated per unit wafer.
[0026] The present invention utilizes the epitaxial growth structure on (110) single crystal silicon, so that the ridge epitaxial part can be in no contact with the substrate layer, thereby reducing the probability of dislocation caused by interlayer stress and reducing the device's dependence on the buffer layer.
[0027] This invention reduces the dislocation density generated during epitaxial growth of epitaxial structures and improves the quality of device epitaxial structures by using sidewall selected area epitaxial growth technology. Attached Figure Description
[0028] Figure 1 The diagram shown is a schematic representation of the structure of the substrate layer provided in step 1) of Embodiment 1 of the present invention.
[0029] Figure 2The diagram shows the structure of the anti-corrosion layer deposited in step 2) of Embodiment 1 of the present invention.
[0030] Figure 3 The diagram shows the structure of the photoresist layer deposited in step 2) of Embodiment 1 of the present invention.
[0031] Figure 4 The diagram shows the structure of the patterned photoresist layer in step 2) of Embodiment 1 of the present invention.
[0032] Figure 5 The diagram shows the structure of the etching resist layer in step 2) of Embodiment 1 of the present invention.
[0033] Figure 6 The diagram shows the structure after removing the photoresist layer in step 2) of Embodiment 1 of the present invention.
[0034] Figure 7 The diagram shows the structure of the substrate layer etched in step 2) of Embodiment 1 of the present invention.
[0035] Figure 8 The diagram shows the structure after removing the anti-corrosion layer in step 2) of Embodiment 1 of the present invention.
[0036] Figure 9 The diagram shown is a schematic representation of the growth barrier layer in step 3) of Embodiment 1 of the present invention.
[0037] Figure 10 The diagram shown is a schematic representation of the structure presented in step 4) of Embodiment 1 of the present invention, which involves setting the extension structure.
[0038] Figure 11 The diagram shown is a schematic representation of the structure with a gate in an optional example of Embodiment 1 of the present invention.
[0039] Figure 12 The diagram shown is a top view of the device structure in Embodiment 2 of the present invention.
[0040] Component designation explanation
[0041] 100 substrate layer
[0042] 101 Anti-corrosion layer
[0043] 102 Photoresist layer
[0044] 200 grooves
[0045] 201 First sidewall
[0046] 202 Second sidewall
[0047] 203 Bottom
[0048] 204 countertop
[0049] 300 growth barrier layer
[0050] 4011 Source
[0051] 4012 Drain
[0052] 4013 gate
[0053] 402 Ridge-shaped extension
[0054] Y Second Direction
[0055] X First Direction Detailed Implementation
[0056] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0057] In the detailed description of embodiments of the present invention, for ease of explanation, the schematic diagrams illustrating the device structure may be partially enlarged and not to scale. Furthermore, these schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.
[0058] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the accompanying drawings for devices in use or operation.
[0059] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
[0060] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0061] In the prior art, multiple devices are usually fabricated on a single wafer. The devices typically use (111) single-crystal silicon as a substrate. This type of substrate can only grow device epitaxial crystal structures laterally. In the vertical direction, since the sidewalls obtained after etching are amorphous, effective epitaxial structures cannot be grown. Laterally grown devices often occupy a large wafer area, which limits the number of devices that can be fabricated on a unit wafer to the device epitaxial area. This is not conducive to high-density device integration and results in low fabrication efficiency.
[0062] Example 1
[0063] To solve the above problems, such as Figure 1 As shown, and see Figure 1-10 This invention provides a method for fabricating a semiconductor device structure, the method comprising the following steps:
[0064] Step 1): Provide a substrate layer 100 made of (110) monocrystalline silicon;
[0065] Step 2): The substrate layer 100 is patterned to form a plurality of alternating grooves 200, each groove 200 including a first sidewall 201 and a second sidewall 202 disposed opposite to each other;
[0066] Step 3): A growth barrier layer 300 is provided on the first sidewall 201 of the plurality of grooves 200;
[0067] Step 4): An epitaxial structure is provided on the second sidewall 202 of a plurality of grooves 200 covered with a growth barrier layer 300. The epitaxial structure protrudes from the grooves 200 to form a ridge-shaped epitaxial portion 402. The ridge-shaped epitaxial portions 402 are isolated from each other. The epitaxial structure includes a III-V compound semiconductor layer.
[0068] The method for fabricating the semiconductor device structure of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that the above order does not strictly represent the order of the fabrication method for the semiconductor device structure protected by the present invention, and those skilled in the art can modify it according to the actual measurement steps. Figure 1-10 The fabrication steps of a semiconductor device structure are shown in only one example.
[0069] First, such as Figure 1 As shown, in step 1), a substrate 100 is provided with (110) monocrystalline silicon.
[0070] The present invention uses (110) single crystal silicon as a substrate. After being etched, this type of material can form a plane perpendicular to the first direction X. This plane is a (111) crystal plane. Therefore, the sidewalls of the groove 200 formed on its surface can also grow an effective epitaxial structure, thereby reducing the area of the wafer surface occupied by the epitaxial structure of the device, increasing the number of devices that can be fabricated per unit wafer, and improving the device fabrication efficiency.
[0071] Next, as Figures 2-8 As shown, in step 2), the substrate layer 100 is patterned to form a plurality of alternating grooves 200, each groove 200 including a first sidewall 201 and a second sidewall 202 disposed opposite to each other.
[0072] As an example, the process of patterning the substrate 100 is as follows: Figure 2 As shown, a resist layer 101 is deposited on the substrate layer 100; as Figure 3 As shown, a photoresist layer 102 is deposited on the resist layer 101; as Figure 4 As shown, the photoresist layer 102 is patterned to expose a portion of the resist layer 101; as Figure 5 As shown, the etching exposes the resist layer 101; as Figure 6 As shown, the remaining photoresist layer 102 is removed to expose a portion of the substrate layer 100; as Figure 7 As shown, the substrate layer 100 is exposed by etching; as Figure 8 As shown, the resist layer 101 is removed. Specifically, the resist layer 101 is made of silicon dioxide; the resist layer 101 is deposited by PECVD (plasma-enhanced chemical vapor deposition); the exposed resist layer 101 is etched by RIE (reactive ion etching); and the exposed substrate layer 100 is wet-etched with potassium hydroxide.
[0073] Then, as Figure 9 As shown, in step 3), a growth barrier layer 300 is provided on the first sidewall 201 of the plurality of grooves 200. Specifically, a platform 204 is included between two adjacent grooves 200, and a groove 200 includes a bottom surface 203. The growth barrier layer 300 covers the first sidewall 201, the bottom surface 203, and the platform 204 connected to the first sidewall 201 of the plurality of grooves 200.
[0074] Optionally, the growth barrier layer 300 may not completely cover the bottom surface 203. Preferably, the growth barrier layer 300 completely covers the bottom surface 203 so that the epitaxial structure grows only on the second sidewall 202 as much as possible, thereby reducing the contact area between the epitaxial structure and the substrate layer 100.
[0075] Optionally, the growth barrier layer 300 may also cover part of the second sidewall 202 to reduce the contact area between the epitaxial structure and the substrate layer 100, thereby reducing the dislocation density. At the same time, in order to ensure that the growth surface between the ridge epitaxial portion 402 and the substrate layer 100 is sufficiently firm and not easily detached or broken, the contact area between the epitaxial structure and the substrate layer 100 needs to reach a certain preset value. The specific value needs to be adjusted according to the actual device structure and performance requirements.
[0076] Optionally, the growth barrier layer 300 may be made of materials including, but not limited to, silicon oxide or silicon nitride, which are suitable materials that can prevent the growth of epitaxial structures and can be grown on silicon. Preferably, silicon oxide is used, which can form a tighter interface with the silicon material of the substrate layer 100, making the barrier effect more reliable.
[0077] Optionally, the method for setting the growth barrier layer 300 includes, but is not limited to, electron beam evaporation or vacuum evaporation.
[0078] As an example, the length of the bottom surface 203 along the first direction X is set to 2 micrometers to 10 micrometers, the length of the first sidewall 201 along the second direction Y is 5 micrometers to 15 micrometers, the length of the second sidewall 202 along the second direction Y is 5 micrometers to 15 micrometers, the length of the platform 204 along the first direction X is 1 micrometer to 10 micrometers, and the length of the bottom surface 203 along the first direction X is less than the length of the first sidewall 201 along the second direction Y.
[0079] Preferably, the ratio of the length of the bottom surface 203 along the first direction X to the length of the first sidewall 201 along the second direction Y is less than 0.7, so as to ensure the crystal quality of the grown device epitaxial structure.
[0080] Optionally, the ratio of the length of the bottom surface 203 along the first direction X to the length of the first sidewall 201 along the second direction Y can be 0.5.
[0081] Next, as Figure 10 As shown, in step 4), an epitaxial structure is provided on the second sidewall 202 of a plurality of grooves 200 covered with a growth barrier layer 300. The epitaxial structure protrudes from the grooves 200 to form a ridge-shaped epitaxial portion 402. The ridge-shaped epitaxial portions 402 are isolated from each other. The epitaxial structure includes a III-V compound semiconductor layer.
[0082] This invention reduces the dislocation density of the epitaxial structure grown on the inner wall of the groove 200 by using selective region epitaxial growth, thereby improving the quality of the epitaxial structure and improving the working performance and fabrication yield of the device.
[0083] As an example, the epitaxial structure includes a nucleation layer and a III-V compound semiconductor layer; the nucleation layer is in contact with the second sidewall 202, and the nucleation layer material is aluminum nitride; the III-V compound semiconductor layer is disposed on the surface of the nucleation layer, and the III-V compound semiconductor layer includes a barrier structure formed by an AlGaN layer and a GaN layer.
[0084] This invention utilizes AlN (aluminum nitride) as a nucleation layer, which enables rapid lateral filling of the nucleation layer, thereby further improving the crystal quality of the epitaxial structure growth of the device and reducing charge accumulation effect and lattice dislocation density.
[0085] Preferably, the growth of the nucleation layer can employ high-temperature AlN stress control technology to obtain high crystal quality and achieve stress balance, thereby growing a high-quality III-V compound semiconductor layer. Specifically, during the nucleation layer growth process, the growth temperature is reduced from 1020℃ to 920℃ to improve the wettability between the device epitaxial structure and the substrate layer 100, promoting the subsequent growth of the III-V compound semiconductor layer in a two-dimensional layered growth mode. Specifically, the thickness of the AlN nucleation layer is adjusted to achieve stress balance among the layers in the device epitaxial structure, preventing the tensile stress experienced by the device epitaxial structure during growth from exceeding a critical value and causing cracking.
[0086] Specifically, the epitaxial structure is grown under a combination of low and high temperatures and a low V / III ratio. The low temperature is 1200℃, and the high temperature is 1300℃. The thickness ratio of the epitaxial structure can be adjusted as needed. Specifically, the V / III ratio is the molar mass ratio of group V and group III compounds introduced per second during the epitaxial structure growth process.
[0087] Optionally, the growth V / III ratio of the group III-V compound semiconductor layer is less than 500.
[0088] Preferably, the V / III ratio is maintained at 136 to ensure that the growth rate of the top of the ridge-shaped epitaxial portion 402 is as uniform and stable as possible in the first direction X and the second direction Y.
[0089] Optionally, the material of the nucleation layer includes, but is not limited to, GaN (gallium nitride), AlN (aluminum nitride), AlGaN (aluminum gallium nitride), or a combination of any one or more of the above materials.
[0090] Optionally, a buffer layer can be added between the nucleation layer and the barrier structure in the epitaxial structure. However, since the ridge epitaxial portion 402 in the present invention is grown on the growth barrier layer 300, the dislocation density has been greatly reduced. Omitting the buffer layer here will not significantly affect the device performance.
[0091] Optionally, the growth temperature of the III-V compound semiconductor layer is higher than 1080°C.
[0092] As an example, epitaxial structures are formed via MOCVD (organic metal chemical vapor deposition).
[0093] As an example, before setting the extension structure on the second sidewall 202 of the groove 200, the groove 200 is cleaned with boiling aqua regia.
[0094] Specifically, boiling aqua regia is used to clean the groove 200 for 10-30 minutes at an ambient temperature greater than 60°C to remove metal particles from the surface of the groove 200.
[0095] As an example, after cleaning the groove 200 with boiling aqua regia, the groove 200 is then cleaned with a hydrofluoric acid solution with a concentration of less than or equal to 0.5%.
[0096] As an example, the concentration of the hydrofluoric acid solution is 0.1%. Specifically, the groove 200 is cleaned with hydrofluoric acid solution for 5-10 seconds to remove residual growth barrier layer 300, then cleaned with deionized water, and finally dried.
[0097] As an example, such as Figure 11 As shown, the fabrication method further includes: setting a gate 4013 on the ridge epitaxial portion 402; the gate 4013 being formed on the ridge epitaxial portion 402 at a preset angle with the second sidewall 202; and forming a source 4011 and a drain 4012 by embedding or embedding them in the ridge epitaxial portion 402.
[0098] Optionally, the gate 4013 may be a Schottky gate that is in direct contact with the surface of the barrier structure; it may also be a gate 4013 that is in contact with the surface of the growth barrier layer 300; or it may be a gate 4013 of a field plate structure that is partially in contact with the surface of the barrier structure and partially in contact with the surface of the growth barrier layer 300.
[0099] The above steps are an example description for HEMT devices with an epitaxial structure. Optionally, other device types such as detector devices and LED light-emitting devices can also be fabricated, and the fabrication steps can be adjusted according to the corresponding structural characteristics.
[0100] Example 2
[0101] like Figure 11 As shown, this embodiment provides a semiconductor device structure, which is prepared using any of the methods described in Embodiment 1. The semiconductor device structure includes:
[0102] Substrate layer 100, growth barrier layer 300, epitaxial structure;
[0103] The substrate 100 is provided with a plurality of alternating grooves 200, each groove 200 including a first sidewall 201 and a second sidewall 202 disposed opposite to each other; the material of the substrate 100 is (110) monocrystalline silicon.
[0104] A growth barrier layer 300 covers the first sidewall 201 of a plurality of grooves 200. An epitaxial structure is disposed on the second sidewall 202 of the plurality of grooves 200 covered by the growth barrier layer 300 and protrudes from the grooves 200 to form a ridge epitaxial portion 402. The ridge epitaxial portions 402 are isolated from each other. The epitaxial structure includes a III-V compound semiconductor layer.
[0105] As an example, a device structure is also formed on the epitaxial structure, which includes one or more of HEMT devices, detector devices, or LED light-emitting devices based on a III-V compound semiconductor layer.
[0106] Alternatively, the HEMT device can be an enhancement-mode or depletion-mode device structure.
[0107] Alternatively, the device epitaxial structure can also be configured as other semiconductor devices with epitaxially formed device layers, such as MOSFET (metal-oxide-semiconductor field-effect transistor), JFET (junction field-effect transistor), MESFET (metal-semiconductor field-effect transistor), and MISFET (metal-insulator-semiconductor field-effect transistor), as required.
[0108] As an example, a platform 204 is included between two adjacent grooves 200. The groove 200 includes a bottom surface 203. The growth barrier layer 300 covers the first sidewall 201, the bottom surface 203 and the platform 204 connected to the first sidewall 201 of the plurality of grooves 200. The ridge-shaped extension portion 402 of the extension structure is disposed on the growth barrier layer 300 of the platform 204 along the second direction Y.
[0109] By using (110) single-crystal silicon, the ridge-shaped epitaxial portion 402 grown on the growth barrier layer 300 covering the mesa 204 does not contact the substrate layer 100, which greatly reduces the interlayer dislocation density of the epitaxial structure grown at this location, and it can work normally without a buffer layer.
[0110] Optionally, the growth barrier layer 300 may not completely cover the bottom surface 203. Preferably, the growth barrier layer 300 completely covers the bottom surface 203 so that the epitaxial structure grows only on the second sidewall 202 as much as possible, thereby reducing the contact area between the epitaxial structure and the substrate layer 100.
[0111] Optionally, the growth barrier layer 300 may also cover part of the second sidewall 202 to reduce the contact area between the epitaxial structure and the substrate layer 100, thereby reducing the dislocation density. At the same time, in order to ensure that the growth surface between the ridge epitaxial portion 402 and the substrate layer 100 is sufficiently firm and not easily detached or broken, the contact area between the epitaxial structure and the substrate layer 100 needs to reach a certain preset value. The specific value needs to be adjusted according to the actual device structure and performance requirements.
[0112] Optionally, the growth barrier layer 300 may be made of materials including, but not limited to, silicon oxide or silicon nitride, which are suitable materials that can prevent the growth of epitaxial structures and can be grown on silicon. Preferably, silicon oxide is used, which can form a tighter interface with the silicon material of the substrate layer 100, making the barrier effect more reliable.
[0113] As an example, the length of the bottom surface 203 along the first direction X is set to 2 micrometers to 10 micrometers, the length of the first sidewall 201 along the second direction Y is 5 micrometers to 15 micrometers, the length of the second sidewall 202 along the second direction Y is 5 micrometers to 15 micrometers, the length of the platform 204 along the first direction X is 1 micrometer to 10 micrometers, and the length of the bottom surface 203 along the first direction X is less than the length of the first sidewall 201 along the second direction Y.
[0114] Preferably, the ratio of the length of the bottom surface 203 along the first direction X to the length of the first sidewall 201 along the second direction Y is less than 0.7, so as to ensure the crystal quality of the grown device epitaxial structure.
[0115] Optionally, the ratio of the length of the bottom surface 203 along the first direction X to the length of the first sidewall 201 along the second direction Y can be 0.5.
[0116] As an example, the epitaxial structure includes a nucleation layer and a III-V compound semiconductor layer; the nucleation layer is in contact with the second sidewall 202, and the nucleation layer material is aluminum nitride; the III-V compound semiconductor layer is disposed on the surface of the nucleation layer, and the III-V compound semiconductor layer includes a barrier structure formed by an AlGaN layer and a GaN layer.
[0117] This invention utilizes AlN (aluminum nitride) as a nucleation layer, which enables rapid lateral filling of the nucleation layer, thereby further improving the crystal quality of the epitaxial structure growth of the device and reducing charge accumulation effect and lattice dislocation density.
[0118] Preferably, the growth of the nucleation layer can employ high-temperature AlN stress control technology to obtain high crystal quality and achieve stress balance, thereby growing a high-quality III-V compound semiconductor layer. Specifically, during the nucleation layer growth process, the growth temperature is reduced from 1020℃ to 920℃ to improve the wettability between the device epitaxial structure and the substrate layer 100, promoting the subsequent growth of the III-V compound semiconductor layer in a two-dimensional layered growth mode. Specifically, the thickness of the AlN nucleation layer is adjusted to achieve stress balance among the layers in the device epitaxial structure, preventing the tensile stress experienced by the device epitaxial structure during growth from exceeding a critical value and causing cracking.
[0119] Optionally, the material of the nucleation layer includes, but is not limited to, GaN (gallium nitride), AlN (aluminum nitride), AlGaN (aluminum gallium nitride), or a combination of any one or more of the above materials.
[0120] Optionally, a buffer layer can be added between the nucleation layer and the barrier structure in the epitaxial structure. However, since the ridge epitaxial portion 402 in the present invention is grown on the growth barrier layer 300, the dislocation density has been greatly reduced. Omitting the buffer layer here will not significantly affect the device performance.
[0121] Optionally, the growth temperature of the III-V compound semiconductor layer is higher than 1080°C.
[0122] As an example, such as Figures 11-12 As shown, when the device structure is a HEMT device based on a III-V compound semiconductor layer, the semiconductor device structure also includes an electrode layer. The electrode layer is disposed on each epitaxial structure and includes a gate 4013, a source 4011, and a drain 4012. The gate 4013 is mounted on the ridge-shaped epitaxial portion 402 of the epitaxial structure. The gates 4013 corresponding to different ridge-shaped epitaxial portions 402 are independently separated from each other or formed into an effective electrical connection according to a preset combination. The source 4011 and drain 4012 are both embedded or externally within the ridge-shaped epitaxial portion 402. The source 4011 and drain 4012 corresponding to different ridge-shaped epitaxial portions 402 are independently separated from each other or formed into an effective electrical connection according to a preset combination. Specifically, the positions of the source 4011 and drain 4012 shown in the figure can be interchanged, depending on the actual design requirements.
[0123] Optionally, the gate 4013 may be a Schottky gate that is in direct contact with the surface of the barrier structure; it may also be a gate 4013 that is in contact with the surface of the growth barrier layer 300; or it may be a gate 4013 of a field plate structure that is partially in contact with the surface of the barrier structure and partially in contact with the surface of the growth barrier layer 300.
[0124] In summary, the semiconductor device structure and its fabrication method of the present invention can improve the space utilization of the device on the wafer and increase the HEMT device density that can be accommodated per unit wafer by using (110) single crystal silicon, which allows the epitaxial structure to grow an effective epitaxial surface on the sidewall. At the same time, by utilizing the epitaxial growth structure on (110) single crystal silicon, the ridge epitaxial portion can be without contact with the substrate layer, thereby reducing the probability of dislocations generated by interlayer stress and reducing the device's dependence on the buffer layer. In addition, by using the sidewall selected area epitaxial growth technology, the dislocation density generated by the epitaxial growth of the epitaxial structure is reduced, and the quality of the device epitaxial structure is improved.
[0125] Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.
[0126] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A method for fabricating a semiconductor device structure, characterized in that, The preparation method includes the following steps: A substrate layer is provided, which is made of (110) monocrystalline silicon; The substrate layer is patterned to form a plurality of alternating grooves, each groove including a first sidewall and a second sidewall disposed opposite to each other, the plane in which the second sidewall is located is a (111) crystal plane; A growth barrier layer is provided on the first sidewall of the plurality of grooves; a platform is included between two adjacent grooves, and each groove includes a bottom surface. The growth barrier layer covers the first sidewall, the bottom surface, and the platform that is in contact with the first sidewall of the plurality of grooves. An epitaxial structure is provided on the second sidewall of a plurality of grooves covered by the growth barrier layer. The epitaxial structure protrudes from the groove to form a ridge-shaped epitaxial portion, which is isolated from each other. The ridge-shaped epitaxial portion of the epitaxial structure is disposed on the growth barrier layer of the mesa along a second direction, which is perpendicular to the bottom surface of the groove. The growth barrier layer completely covers the bottom surface of the groove so that the epitaxial structure grows only on the second sidewall. The epitaxial structure includes a III-V compound semiconductor layer.
2. The method for fabricating a semiconductor device structure according to claim 1, characterized in that, The preparation method further includes: setting a gate on the ridge-shaped epitaxial portion; the gate being formed on the ridge-shaped epitaxial portion at a preset angle to the second sidewall; and forming a source and a drain by embedding or embedding them in the ridge-shaped epitaxial portion.
3. The method for fabricating a semiconductor device structure according to claim 1, characterized in that, Before the extension structure is provided on the second sidewall of the groove, the groove is cleaned with boiling aqua regia.
4. The method for fabricating a semiconductor device structure according to claim 3, characterized in that, After cleaning the groove with boiling aqua regia, the groove is then cleaned with a hydrofluoric acid solution with a concentration of less than or equal to 0.5%.
5. A semiconductor device structure, characterized in that, The semiconductor device structure is prepared using the fabrication method according to any one of claims 1-4, and the semiconductor device structure comprises: Substrate layer, growth barrier layer, epitaxial structure; The substrate layer is provided with a plurality of alternating grooves, each groove including a first sidewall and a second sidewall disposed opposite to each other; the material of the substrate layer is (110) monocrystalline silicon. The growth barrier layer covers the first sidewall of the plurality of grooves, and the epitaxial structure is disposed on the second sidewall of the plurality of grooves covered by the growth barrier layer. The plane of the second sidewall is a (111) crystal plane and protrudes from the groove to form a ridge epitaxial portion. The ridge epitaxial portions are isolated from each other. The epitaxial structure includes a III-V compound semiconductor layer. A platform is included between two adjacent grooves. Each groove includes a bottom surface. The growth barrier layer covers the first sidewall, the bottom surface, and the platform that is in contact with the first sidewall of the plurality of grooves. The ridge-shaped epitaxial portion of the epitaxial structure is disposed on the growth barrier layer on the platform along a second direction, which is perpendicular to the bottom surface of the groove. The growth barrier layer completely covers the bottom surface of the groove so that the epitaxial structure grows only on the second sidewall.
6. The semiconductor device structure according to claim 5, characterized in that, The epitaxial structure also forms a device structure, which includes one or more of the following: HEMT device, detector device, or LED light-emitting device based on the III-V compound semiconductor layer.
7. The semiconductor device structure according to claim 6, characterized in that, The length of the bottom surface along the first direction is set to 2 micrometers-10 micrometers, the length of the first sidewall along the second direction is 5 micrometers-15 micrometers, and the first direction is perpendicular to the second sidewall; the length of the second sidewall along the second direction is 5 micrometers-15 micrometers, the length of the platform along the first direction is 1 micrometer-10 micrometers, the length of the bottom surface along the first direction is less than the length of the first sidewall along the second direction, and the first direction is perpendicular to the second direction.
8. The semiconductor device structure according to claim 5, characterized in that, The epitaxial structure includes a nucleation layer and a III-V compound semiconductor layer; the nucleation layer is in contact with the second sidewall, and the nucleation layer material is aluminum nitride; the III-V compound semiconductor layer is disposed on the surface of the nucleation layer, and the III-V compound semiconductor layer includes a barrier structure formed by an AlGaN layer and a GaN layer.
9. The semiconductor device structure according to claim 6, characterized in that, When the device structure is a HEMT device based on the III-V compound semiconductor layer, the semiconductor device structure further includes an electrode layer, which is disposed on each epitaxial structure, and the electrode layer includes a gate, a source, and a drain. The gate is mounted on the ridge-shaped epitaxial portion of the epitaxial structure, and the gates corresponding to different ridge-shaped epitaxial portions are independently separated from each other or formed into an effective electrical connection according to a preset combination; Both the source and the drain are embedded or externally in the ridge-shaped extension portion. The source and the drain corresponding to different ridge-shaped extension portions are independently separated from each other or formed into an effective electrical connection according to a preset combination.
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