An adaptive double back gate high-speed broadband graphene light detector and a preparation method thereof
By adjusting the carrier type within graphene and forming a PN junction through an adaptive dual-back-gate structure, the problems of weak light absorption and low responsivity in graphene photodetectors are solved, thereby improving photocurrent response and miniaturizing the device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NO 55 INST CHINA ELECTRONIC SCI & TECHNOLOGYGROUP CO LTD
- Filing Date
- 2022-12-19
- Publication Date
- 2026-06-02
AI Technical Summary
Existing graphene photodetectors have weak light absorption, low responsivity, and easy recombination of photogenerated electron-hole pairs, resulting in insufficient device performance.
An adaptive dual-back-gate structure is adopted, which controls the carrier type in graphene by adjusting the back-gate voltage and forms a PN junction in the photodetector region to prevent the recombination of photogenerated electron-hole pairs, while enhancing the light absorption of graphene. This is achieved by combining graphene with a dielectric layer and a metal electrode.
It improves photocurrent response, enhances light absorption, simplifies device control circuitry, and facilitates device miniaturization and performance improvement.
Smart Images
Figure CN115911172B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to photodetectors, and more particularly to an adaptive dual-back-grid high-speed broadband graphene photodetector structure and its fabrication method. Background Technology
[0002] A photodetector is a device that converts incident light energy into electrical energy based on the photoelectric effect, thereby enabling the detection of incident light. With the increasing demand for miniaturization, integration, and high performance in optoelectronic devices, graphene, as a high-performance two-dimensional material with excellent electrical and optical properties, has attracted considerable attention.
[0003] Graphene possesses high electron mobility and a unique band structure, enabling high-speed, broadband photodetection. However, single-layer graphene exhibits only 2.3% visible light absorption, indicating weak light absorption, few photogenerated electron-hole pairs, and easy recombination, resulting in low device responsivity. Therefore, it is necessary to enhance the light response of graphene and improve device performance. Based on graphene's unique band structure, adjusting the Fermi level can alter its light absorption; furthermore, adjusting the gate voltage can change the Fermi level, thereby regulating the type of charge carriers within the graphene. Summary of the Invention
[0004] Purpose of the invention: The purpose of this invention is to provide an adaptive dual-back-gate high-speed broadband graphene photodetector structure and fabrication method that can effectively improve response photocurrent and enhance light absorption.
[0005] Technical solution: The graphene photodetector of the present invention comprises, from bottom to top: a substrate, a first back gate and a second back gate, a dielectric layer, a first interconnect metal electrode and a second interconnect metal electrode, and a graphene photodetector layer, and further includes a source electrode and a drain electrode disposed on the graphene photodetector layer; wherein, the first interconnect metal electrode is directly disposed on the first back gate, the second interconnect metal electrode is directly disposed on the second back gate, and the first interconnect metal electrode and the second interconnect metal electrode are in direct contact with the graphene photodetector layer; the dielectric layer is disposed around the two back gates and the two interconnect metal electrodes; the source electrode and the drain electrode are in direct contact with the graphene photodetector layer; the photodetector region is the graphene photodetector layer between the source electrode and the drain electrode.
[0006] Furthermore, the first back gate and the second back gate have the same structure, with a width of 500nm-1um and a spacing of 100nm-500nm between them.
[0007] Furthermore, the first interconnect metal electrode and the second interconnect metal electrode have the same structure, and the thickness of the two interconnect metal electrodes is the same as the thickness of the dielectric layer, wherein the thickness of the dielectric layer is 10nm-50nm.
[0008] Furthermore, the source and drain electrodes have the same thickness, ranging from 200 nm to 1 μm; the distance between the source and drain electrodes is 1 μm to 3 μm.
[0009] A method for fabricating an adaptive dual-back-gate high-speed broadband graphene photodetector includes the following steps:
[0010] S1, using a wet transfer process, the back gate material is transferred onto an insulating substrate. The entire insulating substrate and the process structure on it are called the sample.
[0011] S2, a back gate pattern is prepared on the surface of the back gate material using planar photolithography and development technology, and then the back gate material outside the two back gate pattern areas is removed by oxidation;
[0012] S3, a dielectric layer is grown on the sample surface using a dry growth process to cover the back gate surface;
[0013] S4. Electrode patterns are prepared on the sample surface using planar photolithography and development technology. The electrode patterns are located above the back gate pattern. The dielectric layer under the pattern is removed to the back gate surface using a wet etching process. Metallization is completed by evaporation. Interconnect metal electrodes are prepared by sol-gel stripping technology.
[0014] S5 uses a wet transfer process to transfer graphene onto the sample surface as a photodetector material.
[0015] S6. On the surface of the graphene photodetector material, a source / drain pattern is prepared using planar photolithography and development technology. The source / drain pattern is located on the completed interconnect metal electrode. Metallization is completed by evaporation, and the source / drain is prepared by sol-gel lift-off technology to form an adaptive structure.
[0016] S7. A graphene photodetector pattern is fabricated between the source and drain electrodes on the sample surface using planar photolithography and development technology. Then, the graphene outside the patterned area is removed by oxidation to complete the fabrication of the graphene photodetector.
[0017] Furthermore, in step S2, the width of a single back gate is 500nm-1um, and the spacing between two back gates is 100nm-500nm.
[0018] Furthermore, the material of the dielectric layer is Al2O3 or HfO2.
[0019] Furthermore, the material of the interconnect metal electrode is Au, or Ag, or Cu, or Pd.
[0020] Furthermore, the material of the back gate is graphene, or MoS2, or MoSe2, or WS2, or WSe2.
[0021] Compared with the prior art, the significant advantages of this invention are as follows:
[0022] 1. In this invention, the dual back gates are connected to the source and drain respectively, and the back gates are regulated by the source / drain voltage to achieve adaptive operation, simplify the device control circuit, and facilitate device miniaturization.
[0023] 2. This invention utilizes different back gate voltages to adjust the type of charge carriers within graphene, which can form a PN junction within the graphene. When light irradiates the graphene to generate photogenerated electron-hole pairs, the local electric field within the PN junction will separate the photogenerated electron-hole pairs, preventing the generated electron-hole pairs from recombinating, thus effectively improving the response photocurrent.
[0024] 3. The back gate in this invention uses graphene and other materials to form a double-layer structure (or a double-layer graphene structure) with graphene photodetector material, which enhances the light absorption of graphene. Moreover, the single-layer back gate is very thin, so it will not affect the surface flatness of the device and is beneficial to the flatness of the graphene photodetector material transfer.
[0025] 4. The manufacturing process of this invention is simple and controllable, which can simplify the device control circuit, facilitate device miniaturization, and improve the photocurrent response of the detector. Attached Figure Description
[0026] Figure 1 This is a schematic diagram of the structure of the photodetector of the present invention;
[0027] Figure 2 This is a schematic diagram of the transfer of graphene back grid material in this invention;
[0028] Figure 3 This is a schematic diagram of the graphene back grid pattern of the present invention;
[0029] Figure 4 This is a schematic diagram of the growth medium layer of the present invention;
[0030] Figure 5 This is a schematic diagram illustrating the fabrication of the interconnected metal electrode of the present invention;
[0031] Figure 6 This is a schematic diagram of the transfer of the graphene photodetector material of the present invention;
[0032] Figure 7 This is a schematic diagram of the source and drain electrode fabrication process of the present invention;
[0033] Figure 8 This is a schematic diagram of the graphene photodetector region of the present invention. Detailed Implementation
[0034] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.
[0035] like Figure 1The diagram shows the structure of the graphene photodetector of the present invention. Taking graphene as an example, the back gate material includes, from bottom to top: a substrate 1, a first back gate 2 and a second back gate 3, a dielectric layer 4, a first interconnect metal electrode 5 and a second interconnect metal electrode 6, and a graphene photodetector layer 7. It also includes a source electrode 8 and a drain electrode 9 disposed on the graphene photodetector layer 7. The first interconnect metal electrode 5 is directly disposed on the first graphene back gate 2, and the second interconnect metal electrode 6 is directly disposed on the second graphene back gate 3. The dielectric layer 3 is disposed around the two graphene back gates and the two interconnect metal electrodes. The source electrode 8 and the drain electrode 9 are in direct contact with the graphene photodetector layer 7. The graphene photodetector layer between the source electrode 8 and the drain electrode 9 is the graphene photodetector region, and L is the width of the graphene photodetector region.
[0036] The working principle is as follows:
[0037] This invention employs an adaptive dual back gate, namely two graphene back gates. The source 8 is connected to the first graphene back gate 2 via a graphene photodetector layer 7 and a first interconnecting metal electrode 5. The drain 9 is connected to the second graphene back gate 3 via a graphene photodetector layer 7 and a second interconnecting metal electrode 6. When the device is working, the external voltages of the source 8 and drain 9 are different. The two graphene back gates are interconnected with the source / drain respectively. The voltage of the first graphene back gate is the same as the voltage of the source 8, and the voltage of the second graphene back gate is the same as the voltage of the drain 9. This allows the back gates to be controlled by the source / drain voltage, simplifying the device control circuit and facilitating device miniaturization. The dual-back-gate design utilizes different back-gate voltages to adjust the type of charge carriers within the graphene. When the back-gate voltage is <0.5V, holes dominate in the graphene of the photodetector region; when the back-gate voltage is >0.5V, electrons dominate. Different back-gate voltages on the two graphene back gates adjust the charge carrier type in the corresponding photodetector region, forming a PN junction. When light irradiates the graphene of the photodetector region, generating photogenerated electron-hole pairs, the local electric field within the PN junction separates these pairs, preventing recombination and effectively improving the response photocurrent. The back gates are made of graphene material, forming a bilayer graphene structure with the upper graphene layer, enhancing graphene light absorption. Furthermore, the single-layer graphene is very thin, so its use as a back gate does not affect the surface flatness of the device, which is beneficial for the flatness of the graphene photodetector material transfer.
[0038] The method for fabricating a graphene photodetector according to the present invention includes the following steps:
[0039] Step 1, Graphene Back Grid Material Transfer: Graphene is grown by CVD on a Cu substrate. PMMA adhesive is spin-coated onto the graphene. The Cu substrate is then etched away. A wet transfer process is used to transfer the graphene and the PMMA adhesive transfer carrier onto a Si / SiO2 insulating substrate. The surface PMMA carrier is removed using acetone sol. Figure 2 As shown.
[0040] Step 2, Graphene Back Gate Patterning: A back gate pattern is fabricated on the graphene surface using planar photolithography. Then, dry oxidation (oxygen plasma) is used to remove the graphene outside the back gate pattern area. The thickness of a single graphene back gate is 0.3 nm, and its width is 500 nm-1 μm. The spacing between graphene double back gates is 100 nm-500 nm. Figure 3 As shown.
[0041] Step 3, Growth of the dielectric layer: An alumina dielectric layer is grown on the graphene surface using the ALD growth process. The dielectric layer thickness is 10nm-50nm. Figure 4 As shown.
[0042] Step 4, Interconnected Metal Electrode Fabrication: Metal electrode patterns are fabricated on the sample surface using planar photolithography. The electrode patterns are located at the edge region of the graphene back gate pattern. A wet etching process is used to remove the dielectric layer beneath the pattern down to the graphene back gate surface. Au is evaporated to complete metallization, and sol-gel lift-off technology is used to fabricate the Au electrode. The thickness of the Au electrode is the same as the dielectric layer thickness, ranging from 10nm to 50nm. Figure 5 As shown.
[0043] Step 5, Graphene Photodetector Material Transfer: Graphene is grown by CVD on a Cu substrate. PMMA adhesive is spin-coated onto the graphene, the Cu substrate is etched away, and a wet transfer process is used to transfer the graphene and the PMMA transfer carrier onto an insulating substrate. The surface PMMA carrier is removed using acetone sol. Figure 6 As shown.
[0044] Step 6, Source / Drain Fabrication: Source / drain patterns are fabricated on the graphene surface using planar photolithography. These patterns are located on the pre-formed Au metal electrodes. Au is evaporated to complete metallization, and sol-gel lift-off is used to fabricate the source / drain electrodes. The metal thickness of the source / drain Au electrodes is 200 nm to 1 μm. Figure 7 As shown.
[0045] Step 7, Graphene Photodetector Patterning: A graphene photodetector pattern is fabricated on the sample surface using planar photolithography. The pattern is located between the source and drain electrodes. Then, dry oxidation (oxygen plasma) is used to remove the graphene outside the back grid pattern area, completing the fabrication of the graphene photodetector. Figure 8 As shown.
Claims
1. An adaptive dual-back-grid high-speed broadband graphene photodetector, characterized in that, The structure, from bottom to top, comprises: a substrate, a first back gate and a second back gate, a dielectric layer, a first interconnect metal electrode and a second interconnect metal electrode, and a graphene photodetector layer. It also includes a source electrode and a drain electrode disposed on the graphene photodetector layer. The first interconnect metal electrode is directly disposed on the first back gate, and the second interconnect metal electrode is directly disposed on the second back gate. The first and second interconnect metal electrodes are in direct contact with the graphene photodetector layer. The dielectric layer is disposed around the two back gates and the two interconnect metal electrodes. The source electrode and the drain electrode are in direct contact with the graphene photodetector layer. The photodetector region is the graphene photodetector layer between the source electrode and the drain electrode. The first and second back gates have the same structure. The material of the back gate is graphene, or MoS2, or MoSe2, or WS2, or WSe2.
2. The adaptive dual-back-grid high-speed broadband graphene photodetector according to claim 1, characterized in that, The width of both the first and second back gates is 500nm-1um, and the spacing between the two back gates is 100nm-500nm.
3. The adaptive dual-back-grid high-speed broadband graphene photodetector according to claim 1, characterized in that, The first interconnect metal electrode and the second interconnect metal electrode have the same structure, and the thickness of the two interconnect metal electrodes is the same as the thickness of the dielectric layer, which is 10 nm - 50 nm thick.
4. The adaptive dual-back-grid high-speed broadband graphene photodetector according to claim 1, characterized in that, The source and drain electrodes have the same thickness, ranging from 200 nm to 1 μm; the distance between the source and drain electrodes is 1 μm to 3 μm.
5. The method for fabricating the adaptive dual-back-gate high-speed broadband graphene photodetector as described in any one of claims 1-3, characterized in that, Includes the following steps: S1, using a wet transfer process, the back gate material is transferred onto an insulating substrate. The entire insulating substrate and the process structure on it are called the sample. S2, a back gate pattern is prepared on the surface of the back gate material using planar photolithography and development technology, and then the back gate material outside the two back gate pattern areas is removed by oxidation; S3, a dielectric layer is grown on the sample surface using a dry growth process to cover the back gate surface; S4. Electrode patterns are prepared on the sample surface using planar photolithography and development technology. The electrode patterns are located above the back gate pattern. The dielectric layer under the pattern is removed to the back gate surface using a wet etching process. Metallization is completed by evaporation. Interconnect metal electrodes are prepared by sol-gel stripping technology. S5 uses a wet transfer process to transfer graphene onto the sample surface as a photodetector material. S6. On the surface of the graphene photodetector material, a source / drain pattern is prepared using planar photolithography and development technology. The source / drain pattern is located on the completed interconnect metal electrode. Metallization is completed by evaporation, and the source / drain is prepared by sol-gel lift-off technology to form an adaptive structure. S7. A graphene photodetector pattern is fabricated between the source and drain electrodes on the sample surface using planar photolithography and development technology. Then, the graphene outside the patterned area is removed by oxidation to complete the fabrication of the graphene photodetector.
6. The method for fabricating the adaptive dual-back-gate high-speed broadband graphene photodetector according to claim 5, characterized in that, In step S2, the width of a single back gate is 500nm-1um, and the spacing between two back gates is 100nm-500nm.
7. The method for fabricating the adaptive dual-back-grid high-speed broadband graphene photodetector according to claim 5, characterized in that, The material of the dielectric layer is Al2O3 or HfO2.
8. The method for fabricating the adaptive dual-back-gate high-speed broadband graphene photodetector according to claim 5, characterized in that, The interconnect metal electrode is made of Au, Ag, Cu, or Pd.