Method, device and system for parallel selection of fifth generation (5G) new radio information

Abstract

The present disclosure relates to parallel selection of fifth generation (5G) new radio information. Devices, systems, and techniques for selecting fifth generation (5G) new radio data. In at least one embodiment, a processor includes one or more circuits for parallel selection of 5G new radio signal information.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Greek patent application No. 20210100648, filed on September 30, 2021, entitled “PARALLEL SELECTION OF FIFTH GENERATION (5G) NEW RADIO INFORMATION”, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] At least one embodiment relates to selecting radio signal information for fifth generation (5G) radio signals.For example, at least one embodiment relates to determining a receiver rate in parallel based on a transmit rate. Background Art

[0004] Performing computational operations for radio signal transmission can introduce significant lag when performed sequentially. Performing computational operations for radio signal transmission in parallel can reduce the amount of lag introduced by performing computational operations sequentially. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 An example data transmission service is shown in accordance with at least one embodiment;

[0006] Figure 2 illustrates exemplary data transmission rate matching method selection according to at least one embodiment;

[0007] Figure 3 An example process for selecting bits in data transmission rate matching according to at least one embodiment is shown;

[0008] Figure 4 illustrates an example data transmission rate matching data flow in accordance with at least one embodiment;

[0009] Figure 5 An example process for encoding a data block in data transmission rate matching according to at least one embodiment is shown;

[0010] Figure 6 An example process for data transmission rate matching according to at least one embodiment is shown;

[0011] Figure 7 An example coded data block processing data flow for data transmission rate matching according to at least one embodiment is shown;

[0012] Figure 8 shows example bit selection data stream data for data transmission rate matching according to at least one embodiment;

[0013] Figure 9 An example process for sequentially selecting bits in data transmission rate matching according to at least one embodiment is shown;

[0014] Figure 10 An example thread allocation diagram for processing data blocks in data transfer rate matching according to at least one embodiment is shown;

[0015] Figure 11 An example data retransmission diagram for processing data blocks in data transmission rate matching according to at least one embodiment is shown;

[0016] Figure 12 An example process for retransmitting a data block in data transmission rate matching according to at least one embodiment is shown;

[0017] Figure 13 An example process for parallel selection of bits in data rate matching according to at least one embodiment is shown;

[0018] Figure 14 An example data center system is shown in accordance with at least one embodiment;

[0019] Figure 15A An example of an autonomous vehicle according to at least one embodiment is shown;

[0020] Figure 15B According to at least one embodiment, Figure 15A Examples of camera positions and fields of view for autonomous vehicles;

[0021] Figure 15C According to at least one embodiment Figure 15A A block diagram of an example system architecture for an autonomous vehicle;

[0022] Figure 15D is a diagram illustrating a method for one or more cloud-based servers and Figure 15A A diagram of a system for communicating between autonomous vehicles;

[0023] Figure 16 is a block diagram illustrating a computer system according to at least one embodiment;

[0024] Figure 17 is a block diagram illustrating a computer system according to at least one embodiment;

[0025] Figure 18 A computer system according to at least one embodiment is shown;

[0026] Figure 19 A computer system according to at least one embodiment is shown;

[0027] Figure 20A A computer system according to at least one embodiment is shown;

[0028] Figure 20B A computer system according to at least one embodiment is shown;

[0029] Figure 20C A computer system according to at least one embodiment is shown;

[0030] Figure 20D A computer system according to at least one embodiment is shown;

[0031] Figure 20E and Figure 20F illustrates a shared programming model according to at least one embodiment;

[0032] Figure 21 An exemplary integrated circuit and associated graphics processor are shown in accordance with at least one embodiment;

[0033] Figure 22A and Figure 22B An exemplary integrated circuit and associated graphics processor are shown in accordance with at least one embodiment;

[0034] Figure 23A and Figure 23B Additional exemplary graphics processor logic is shown in accordance with at least one embodiment;

[0035] Figure 24 A computer system according to at least one embodiment is shown;

[0036] Figure 25A A parallel processor according to at least one embodiment is shown;

[0037] Figure 25B shows a partition unit according to at least one embodiment;

[0038] Figure 25C illustrates a processing cluster according to at least one embodiment;

[0039] Figure 25D A graphics multiprocessor is shown in accordance with at least one embodiment;

[0040] Figure 26 A multi-graphics processing unit (GPU) system is shown in accordance with at least one embodiment;

[0041] Figure 27 A graphics processor according to at least one embodiment is shown;

[0042] Figure 28is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment;

[0043] Figure 29 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0044] Figure 30 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0045] Figure 31 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0046] Figure 32 is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment;

[0047] Figure 33 is a block diagram of at least a portion of a graphics processor core according to at least one embodiment;

[0048] Figure 34A and Figure 34B Thread execution logic including an array of processing elements of a graphics processor core is shown in accordance with at least one embodiment;

[0049] Figure 35 illustrates a parallel processing unit ("PPU") in accordance with at least one embodiment;

[0050] Figure 36 illustrates a general processing cluster ("GPC") in accordance with at least one embodiment;

[0051] Figure 37 illustrates a memory partitioning unit of a parallel processing unit ("PPU") according to at least one embodiment;

[0052] Figure 38 A streaming multiprocessor is shown in accordance with at least one embodiment;

[0053] Figure 39 A network for communicating data within a 5G wireless communication network is shown in accordance with at least one embodiment;

[0054] Figure 40 illustrates a network architecture for a 5G LTE wireless network according to at least one embodiment;

[0055] Figure 41 is a diagram illustrating some basic functionality of a mobile telecommunications network / system operating according to LTE and 5G principles, according to at least one embodiment;

[0056] Figure 42illustrates a radio access network that may be part of a 5G network architecture in accordance with at least one embodiment;

[0057] Figure 43 An example illustration of a 5G mobile communication system in which multiple different types of devices are used is provided according to at least one embodiment;

[0058] Figure 44 An example high-level system according to at least one embodiment is shown;

[0059] Figure 45 shows the architecture of a network system according to at least one embodiment;

[0060] Figure 46 illustrates example components of a device according to at least one embodiment;

[0061] Figure 47 illustrates an example interface for a baseband circuit according to at least one embodiment;

[0062] Figure 48 An example of an uplink channel according to at least one embodiment is shown;

[0063] Figure 49 shows the architecture of a network system according to at least one embodiment;

[0064] Figure 50 illustrates a control plane protocol stack according to at least one embodiment;

[0065] Figure 51 illustrates a user plane protocol stack according to at least one embodiment;

[0066] Figure 52 illustrates components of a core network according to at least one embodiment; and

[0067] Figure 53 Components of a system supporting network functions virtualization (NFV) are shown in accordance with at least one embodiment. DETAILED DESCRIPTION

[0068] Figure 1 1 shows an example data transmission service 100 according to at least one embodiment. In at least one embodiment, a network (e.g., network 3900, radio access network (RAN) 4004, core network 4102, RAN 4200, Figure 432. The data transmission resources 102 of the mobile communication network shown in FIG. 1 , or other networks such as those described herein, may be used for transmission of network data using systems and methods such as those described herein. In at least one embodiment, the data transmission resources 102 are shared resources, and at least a portion of the data transmission resources 102 are used resources 104, which may be used by other data 108. In at least one embodiment, the other data 108 may be 3G, 4G, and / or Long Term Evolution (LTE) data from third generation (3G), fourth generation (4G), and / or LTE data transmitted using systems and methods such as those described herein. In at least one embodiment, a wireless transceiver such as wireless transceiver 2926 may be used to transmit the other data 108. In at least one embodiment, the data transmission resources 102 may be used to broadcast, multicast, or narrowcast data using systems and methods such as those described herein.

[0069] In at least one embodiment, data transmission resources 102 may be used to transmit fifth generation (5G) data. In at least one embodiment, available resources 106 of data transmission resources 102 are resources that are not used resources 104. In at least one embodiment, at least a portion of available resources 106 may be used to transmit 5G data 110. In at least one embodiment, data transmission resources 102 are shared between other data 108 and 5G data 110. In at least one embodiment, data transmission resources 102 shared between other data 108 and 5G data 110 include one or more wireless spectrums that may be used by hardware (i.e., base stations, devices, etc.) such as described herein. In at least one embodiment, an air interface such as an air interface in radio access network 4200 may use and share one or more wireless spectrums as described herein. In at least one embodiment, one or more wireless spectrums of data transmission resources 102 may be dynamically shared such that, when 5G transmission occurs, the amount and bandwidth of spectrum available as available resources 106 for 5G data 110 may be based at least in part on the spectrum and bandwidth consumed as used resources 104 for other data 108. In at least one embodiment, Dynamic Spectrum Sharing (DSS) is provided by Figure 1 A process (not shown) is enabled whereby, when 5G transmission occurs, the amount and bandwidth of spectrum available for use as available resources 106 for 5G data 110 are dynamically calculated based, at least in part, on the spectrum and bandwidth consumed as used resources 104 for other data 108. In at least one embodiment, in the DSS, the amount and bandwidth of spectrum available for use as available resources 106 for 5G data 110 are continuously calculated based, at least in part, on the spectrum and bandwidth consumed as used resources 104 for other data 108, such that, for example, the amount and bandwidth of spectrum available for use as available resources 106 for 5G data 110 is continuously available.

[0070] In at least one embodiment, the DSS calculation determines a 5G transmission rate 112 that can be used to transmit 5G data 110 based at least in part on the available resources 106. In at least one embodiment, the 5G transmission rate 112 includes a bit rate in units of bits per second, kilobits per second, megabits per second, etc. In at least one embodiment, the 5G transmission rate 112 includes a frequency in units of hertz, kilohertz, megahertz, gigahertz, etc. In at least one embodiment, the 5G transmission rate 112 includes a determined portion of one or more frequency spectra of the data transmission resources 102 that can be shared by the used resources 104 and the available resources 106.

[0071] In at least one embodiment, as described herein, the amount and bandwidth of spectrum available as available resources 106 for 5G data 110 is dynamically and / or continuously calculated, and the 5G transmission rate 112 can be dynamically and / or continuously updated based at least in part on the updated calculation of the amount and bandwidth of spectrum available as available resources 106 for 5G data 110. In at least one embodiment, a rate matching 114 process is used to analyze the transmission of 5G data 110 to determine the 5G transmission rate 112. In at least one embodiment, rate matching 114 can use one or more processes, such as example process 500, example process 600, example process 900, example process 1200, and / or example process 1300 described herein.

[0072] In at least one embodiment, the processor 124 performs rate matching 114. In at least one embodiment, the processor 124 may use the memory 126 to store calculations and / or results of the rate matching 114 process. In at least one embodiment, the processor 124 may be a central processing unit (CPU), or may be a graphics processing unit (GPU), or may be a parallel processing unit (PPU), or may be a texture processing unit (TPU), or may be a general-purpose graphics processing unit (GPGPU), or may be a general-purpose processing cluster (GPC). In at least one embodiment, processor 124 may be processor 1510, CPU 1516, GPU 1520, processor 1602, CPU 1506, GPU 1508, one or more of CPUs 1580 (AB), one or more of GPUs 1584 (AH), processor 1710, CPU 1802, PPU 1814, processing unit 1930, multi-core processors 2005 and / or 2006, GPU 2010, GPU 2011, GPU 2012 and / or GPU 2013, processor 2002, processor 2007, application processor 2105, graphics processor 2110, image processor 2115, video processor 2120, graphics processor 2210, graphics processor 2240, graphics processor 2300, GPGPU 2330, parallel processor 2412, processor 2402, parallel processing unit 2502, graphics multiprocessor 2534, GPGPU 2606(AD), processor 2602, graphics processor 2700, processor 2800, processor 2902, graphics processor 2908, processor 3000, graphics processor 3008, graphics processor 3100, PPU 3500, GPC 3600, streaming multiprocessor 3800, or processors such as those described herein.

[0073] In at least one embodiment, memory 126 may be memory associated with a CPU, GPU, PPU, TPU, GPGPU, and / or GPC. In at least one embodiment, memory 126 may be memory 1620, main memory 1804, processor memory 2001, processor memory 2002, GPU memory 2020-2023, memory 2165, cache / shared memory 2320, memories 2344A-B, system memory 2404, parallel processing memory 2522, shared memory 2570, cache 2572, embedded memory module 3018, shared memory / cache 3312, memory 3504, or other memory such as described herein.

[0074] In at least one embodiment, the processor 124 includes instructions thereon that, when executed, perform rate matching 114. In at least one embodiment, the instructions that, when executed, perform rate matching 114 are loaded from memory 126. In at least one embodiment, the instructions that, when executed, perform rate matching 114 are loaded from a computer system, such as computer system 1600. In at least one embodiment, the instructions for the processor 124 to, when executed, perform rate matching 114 are stored in memory 126. In at least one embodiment, the instructions that, when executed, perform rate matching 114 are executed by a process, processor, thread, thread group, or some other such entity that has access to memory 126. In at least one embodiment, the instructions for the process, processor, thread, thread group, or some other such entity to, when executed, perform rate matching 114 are stored in memory 126. In at least one embodiment, when the instructions that perform rate matching 114 are executed, data associated with rate matching 114 is generated, including, but not limited to, data blocks, padded data blocks, coded data blocks, sparsely placed data blocks, and / or circular buffer representations of data blocks. In at least one embodiment, data associated with rate matching 114 is stored in other memory associated with processor 124 , including, for example, external storage devices associated with processor 124 , such as those described herein.

[0075] In at least one embodiment, rate matching 114 can be used to determine a matched 5G rate 116. In at least one embodiment, rate matching 114 can be performed using elements of the graphics processing engine 3210. In at least one embodiment, rate matching 114 can be performed using elements of the graphics processor core 3300. In at least one embodiment, rate matching 114 can be performed using thread execution logic 3400. In at least one embodiment, the matched 5G rate can be used by the receiver so that available resources 120 of the data reception resources 118 can use the matched 5G rate 116 to receive and process received 5G data 122 using systems and methods such as those described herein.

[0076] In at least one embodiment, processor 124 includes one or more circuits to enable fifth generation (5G) new radio signal information to be selected in parallel. In at least one embodiment, processor 102 includes instructions thereon that, when executed, enable fifth generation (5G) new radio signal information to be selected in parallel.

[0077] Figure 2An example data transmission rate matching method selection 200 according to at least one embodiment is illustrated. In at least one embodiment, as shown in the first rate matching algorithm 202, the second rate matching algorithm 204, and the third rate matching algorithm 206, an initial index (K0), an index of the beginning of the empty region of length F (K d ) and a bit array of length N, where F is less than N. In at least one embodiment, the 5G standard denotes N as Ncb and defines Ncb as the value of N for the selected code block (i.e., the array length). In at least one embodiment, N refers to the value of N for the code block (i.e., the array length).

[0078] In at least one embodiment, the initial index K0 can be at index K d At or before (i.e., when K d >=K0) select the first rate matching algorithm 202. In at least one embodiment, the first rate matching algorithm 202 may be selected at the initial index K0 and the index K d Before (that is, when K d >v K0) select the first rate matching algorithm 202. In at least one embodiment, the first rate matching algorithm 202 may select d , skipping the bits in the empty region of length F, selecting bits after the empty region to length N, and wrapping around to the beginning of the bit array to select bits from the beginning of the bit array to K0, as combined Figure 3 The example process 300 is described in step 308. In at least one embodiment, the first rate matching algorithm 202 may select a value from K0 to K d , skipping the bits in the empty region of length F, selecting the bits after the empty region to the length N, and not wrapping around to the beginning of the bit array. Selecting the bits from the beginning of the bit array to K0, as combined Figure 3 The example process 300 is described in step 308. In at least one embodiment, the first rate matching algorithm 202 may select a value from K0 to K d , skipping the bits in the empty region of length F, selecting bits after the empty region to length N, and wrapping around to the beginning of the bit array multiple times to select bits from the beginning of the bit array to K0, as combined Figure 3 The example process 300 is described in step 308. In at least one embodiment, the first rate matching algorithm 202 can be implemented by selecting a value from K0 to K d The number of bits is selected by skipping the bits in the empty region of length F, selecting the bits after the empty region to the length N, and wrapping around to the beginning of the bit array as needed (i.e., once or more times) to select bits from the beginning of the bit array to K0, so as to select a predetermined number of bits, as combined Figure 3 308 of the example process 300 shown.

[0079] In at least one embodiment, when the initial index K0 is at or after an empty region of length F (ie, when K0>=(K d +F)) the second rate matching algorithm 204 may be selected. In at least one embodiment, when the initial index K0 is in an empty region of length F (ie, when K0>(K d +F), the second rate matching algorithm 204 may be selected. In at least one embodiment, the second rate matching algorithm 204 may select bits from K0 to length N, wrapping around to the beginning of the bit array to select bits from the beginning of the bit array to K. d The bits in the empty area of ​​length F are skipped, and the bits after the empty area to K0 are selected, as combined Figure 3 The example process 300 is described in step 312. In at least one embodiment, the second rate matching algorithm 204 may select bits from K0 to length N without wrapping around to the beginning of the bit array. d The bits in the empty area of ​​length F are skipped, and the bits after the empty area to K0 are selected, as combined Figure 3 In at least one embodiment, the second rate matching algorithm 204 may select bits from K0 to length N, wrapping around to the beginning of the bit array multiple times to select bits from the beginning of the bit array to K. d The bits in the empty area of ​​length F are skipped, and the bits after the empty area to K0 are selected, as combined Figure 3 In at least one embodiment, the second rate matching algorithm 204 can select a number of bits from K0 to length N by wrapping around to the beginning of the bit array as needed (i.e., one or more times) to select a number of bits from the beginning of the bit array to K0. d The bits in the empty area of ​​length F are skipped, and the bits after the empty area to K0 are selected to select a predetermined number of bits, such as combining Figure 3 312 of the example process 300 shown.

[0080] In at least one embodiment, when the initial index K0 is within an empty region of length F (ie, when K0 <= (K d +F) and K0>=K d In at least one embodiment, when the initial index K0 is completely within the empty region of length F (ie, when K0 < (K d +F) and K0>K d In at least one embodiment, the third rate matching algorithm 206 may skip the process from K0 to (K d+F) bit, select from (K d +F) to length N bits, wrapping around to select from 0 to K d bits and skip from K d To K0 bit, such as combined Figure 3 In at least one embodiment, the third rate matching algorithm 206 may skip the steps from K0 to (K d +F) bit, select from (K d +F) to length N, without wrapping, select from 0 to K d bits, and skip from K d To K0 bit, such as combined Figure 3 In at least one embodiment, the third rate matching algorithm 206 may skip the steps from K0 to (K d +F) bit, select from (K d +F) to length N, wrapping around multiple times to select bits from 0 to K d bits and skip from K d To K0 bit, such as combined Figure 3 In at least one embodiment, the third rate matching algorithm 206 skips the steps from K0 to (K d +F) bit, select from (K d + F) to length N bits, wrapping around (i.e., one or more times) as needed to select bits from 0 to K d bits and skip from K d to K0, to select a predetermined number of bits, such as Figure 3 In at least one embodiment, the third rate matching algorithm 206 may select a value from 0 to K after wrapping around, if necessary. d bits (i.e., you can not skip from K d to K0 position) and then stops.

[0081] In at least one embodiment, for example, when the index (K d ) is less than F bits from index N-1, the empty region of length F wraps around the bit array of length N. In at least one embodiment, when the initial index K0 is at index K d At or before (i.e., when K d >=K0), the fourth rate matching algorithm 208 (which may be the first rate matching algorithm 202 with wraparound) may be selected, where the index K d is F1 bits starting from index N-1, where F=F1+F2. In at least one embodiment, the fourth rate matching algorithm 210 may select from K0 to Kd bits, skipping from K at the end of a bit array of length N d to F1 bits of N-1, wrap around to skip F2 bits from 0 to F2 at the beginning of the bit array of length N, and select bits to K0 after the empty area of ​​length F2.

[0082] In at least one embodiment, Figure 2 Not shown, when the index of the beginning of the empty area of ​​length F (K d ) is less than F bits from index N-1 and the initial index K0 is at or after an empty region of length F2 at the beginning of the bit array (i.e., when K0>=F2), the second rate matching algorithm 204 can be executed.

[0083] In at least one embodiment, Figure 2 Not shown, when the index of the beginning of the empty area of ​​length F (K d ) is less than F bits from index N-1 and in the case where the initial index K0 is within an empty region of length F (i.e., when K0 is between K d and N-1 or when K0 is between 0 and F2), a third rate matching algorithm 206 may be executed.

[0084] Figure 3 An example process 300 for selecting bits in data transmission rate matching according to at least one embodiment is shown. In at least one embodiment, a processor, such as processor 124, executes instructions to perform example process 300. In at least one embodiment, at step 302 of example process 300, one or more data blocks are received. In at least one embodiment, one or more received data blocks are data blocks generated for rate matching using systems and methods such as those described herein. In at least one embodiment, after step 302, execution of example process 300 proceeds to step 304.

[0085] In at least one embodiment, in step 304 of the example process 300, one or more factors associated with rate matching are determined. In at least one embodiment, an initial index K0 is determined. In at least one embodiment, the initial index K0 is determined according to one or more 5G standards. In at least one embodiment, one or more other factors that can be used for rate matching are determined. In at least one embodiment, the process for rate matching described herein is used for the uplink (i.e., transmission). In at least one embodiment, the process for rate matching described herein is used for the downlink (i.e., reception). In at least one embodiment, the process for rate matching for the downlink is also referred to as a process for down-rate matching. In at least one embodiment, the uplink process may perform steps that conform to the steps of the downlink process. In at least one embodiment, after step 304, execution of the example process 300 proceeds to step 306.

[0086] In at least one embodiment, at step 306 of the example process 300, it is determined whether the initial index K0 is at or before the beginning of an empty region of the bit array, such as Figure 2 In at least one embodiment, in step 306, the initial index K0 is compared to the index K at the beginning of the empty region of the bit array. d A comparison is performed to determine whether the initial index K0 is at or before the beginning of the empty region of the bit array. In at least one embodiment, if it is determined at step 306 that the initial index K0 is at or before the beginning of the empty region of the bit array (the "yes" branch), execution of the example process 300 proceeds to step 308. In at least one embodiment, if it is determined at step 306 that the initial index K0 is not at or before the beginning of the empty region of the bit array (the "no" branch), execution of the example process 300 proceeds to step 310.

[0087] In at least one embodiment, at step 308 of the exemplary process 300, bit selection using the first rate matching algorithm 202 is performed. In at least one embodiment, bit selection is performed by selecting bits from K0 to K from a bit array of length N. d bits, by selecting from an array of length N (K d

[0045] In at least one embodiment, the bit selection using the first rate matching algorithm 202 is performed by selecting bits from the length-N array of bits (N+F) to N-1, and by selecting bits from 0 to K0 from the array of length N. In at least one embodiment, the bit selection using the first rate matching algorithm 202 is performed by selecting a predetermined number of bits (E) as defined by the 5G standard. In at least one embodiment, the selection of bits from the length-N array of bits using the first rate matching algorithm 202 includes wrapping as described herein. In at least one embodiment, the selection of bits from the length-N array of bits using the first rate matching algorithm 202 includes multiple wrapping as described herein. In at least one embodiment, the selection of bits from the length-N array of bits using the first rate matching algorithm 202 does not include wrapping as described herein. In at least one embodiment, after step 308, execution of the example process 300 continues at step 302 to receive more data.

[0088] In at least one embodiment, at step 310 of the example process 300, it is determined whether the initial index K0 is at or after the end of the empty region of the bit array, such as Figure 2 In at least one embodiment, in step 306, the initial index K0 is added to the beginning of the empty region plus the length of the empty region (K d +F) to determine whether the initial index K0 is at or after the end of the empty region of the bit array. In at least one embodiment, if it is determined at step 310 that the initial index K0 is at or after the end of the empty region of the bit array (the "yes" branch), execution of the example process 300 proceeds to step 312. In at least one embodiment, if it is determined at step 310 that the initial index K0 is not at or after the end of the empty region of the bit array (the "no" branch), execution of the example process 300 proceeds to step 314.

[0089] In at least one embodiment, at step 312 of the exemplary process 300, bit selection using the second rate matching algorithm 204 is performed. In at least one embodiment, bits are selected from K0 to N-1 from a bit array of length N, and bits are selected from 0 to K from a bit array of length N. d bits, and by selecting from a bit array of length N (K d+F) to K0 to perform bit selection using the second rate matching algorithm 204. In at least one embodiment, bit selection using the second rate matching algorithm 204 is performed by selecting a predetermined number of bits (E) as defined by the 5G standard. In at least one embodiment, selecting bits from the bit array of length N using the second rate matching algorithm 204 includes wrapping as described herein. In at least one embodiment, selecting bits from the bit array of length N using the second rate matching algorithm 204 includes multiple wrapping as described herein. In at least one embodiment, selecting bits from the bit array of length N using the second rate matching algorithm 204 does not include wrapping as described herein. In at least one embodiment, after step 312, execution of the example process 300 continues at step 302 to retrieve more data.

[0090] In at least one embodiment, at step 314 of the example process 300, since the “no” branch of step 306 (i.e., K0 is not before the empty region) and the “no” branch of step 308 (i.e., K0 is not after the empty region) are followed, it is determined that the initial index K0 is within the empty region of the bit array, as shown in FIG. Figure 2 In at least one embodiment, after step 314 , execution of the example process 300 proceeds to step 316 .

[0091] In at least one embodiment, at step 316 of the example process 300, bit selection using the third rate matching algorithm 206 is performed. In at least one embodiment, the bit selection is performed by selecting from a bit array of length N (K d +F) to N-1 and by selecting from the bit array of length N from 0 to K d The bit selection using the third rate matching algorithm 206 is performed based on the number of bits. In at least one embodiment, the bit selection using the third rate matching algorithm 206 is performed by selecting a predetermined number of bits (E) as defined by the 5G standard. In at least one embodiment, selecting bits from the bit array of length N using the third rate matching algorithm 206 includes wrapping as described herein. In at least one embodiment, selecting bits from the bit array of length N using the third rate matching algorithm 206 includes multiple wrapping as described herein. In at least one embodiment, selecting bits from the bit array of length N using the third rate matching algorithm 206 does not include wrapping as described herein. In at least one embodiment, after step 316, execution of the example process 300 continues at step 302 to retrieve more data.

[0092] Figure 4An example data transmission rate matching data stream 400 is shown according to at least one embodiment. In at least one embodiment, an input sequence 402 of data is received. In at least one embodiment, the input sequence 402 of data is B bits long and has bits (b0, b1, b2, ..., b B-1 ). In at least one embodiment, the input sequence 402 is assigned 404 to one or more code blocks. In at least one embodiment, the 5G standard may specify a maximum length for a code block. In at least one embodiment, if B is less than the specified maximum length for a code block, the input sequence 402 may be assigned 404 to a single code block. In at least one embodiment, if B is greater than the specified maximum length for a code block, the input sequence 402 may be assigned 404 to multiple code blocks. In at least one embodiment, the input sequence 402 may be evenly assigned 404 to the multiple code blocks such that the code blocks contain a similar number of bits from the input sequence 402.

[0093] In at least one embodiment, code block 406 is one of one or more code blocks that contain bits from input sequence 402. In at least one embodiment, for example, if input sequence 402 includes 65,536 bits and the maximum block size defined by the 5G standard is 8,448 bits, code block 406 can be one of eight code blocks, seven of which have 8,448 bits and the eighth has 6,400 bits and 2,048 empty bits. In at least one embodiment, a code block with the maximum code block size can store bits that are less than the maximum code block size, so that encoding information such as a cyclic redundancy check (CRC) code can be calculated for the code block and included therein. In at least one embodiment, a 24-bit CRC code can be stored in the code block, allowing the code block to store 8,424 bits from the input sequence. In at least one embodiment, for example, if the input sequence 402 includes 65,536 bits, the maximum code block size is 8,448 bits, and a 24-bit CRC code is stored in each code block, the code block 406 can be one of eight code blocks, seven of which store 8,424 bits of the input sequence 402 and a 24-bit CRC, and one code block stores 6,568 bits of the input sequence 402, a 24-bit CRC, and 1856 empty bits.

[0094] In at least one embodiment, for example, if the input sequence 402 includes 65,536 bits and the maximum block size as defined by the 5G standard is 3,840 bits, then the code block 406 can be one of eighteen code blocks, seventeen of which have 3,840 bits from the input sequence 402, and the eighteenth code block has 256 bits from the input sequence 402 and 3,584 empty bits. In at least one embodiment, a code block with the maximum code block size can store bits that are less than the maximum code block size, so that encoding information such as a cyclic redundancy check (CRC) code can be calculated for the code block and included therein. In at least one embodiment, a 24-bit CRC code can be stored in the code block, so that the code block can store 3,816 bits from the input sequence. In at least one embodiment, for example, if the input sequence 402 includes 65,536 bits, the maximum code block size is 3,840 bits, and a 24-bit CRC code is stored in each code block, the code block 406 can be one of eighteen code blocks, where 17 code blocks store 3,816 bits of the input sequence 402 and a 24-bit CRC, and one code block stores 664 bits of the input sequence 402, a 24-bit CRC, and 3152 empty bits.

[0095] In at least one embodiment, code block 406 can be filled 408 with null values ​​to generate a filling code block 410 with a maximum code block size. In at least one embodiment, for example, a code block with 6,568 bits can add 1880 null values ​​to form 8,448 bits. In at least one embodiment, code block 406 can be filled 408 with null values ​​to generate a filling code block 410 before adding a CRC code, thereby using the code block with the added null values ​​to calculate the CRC code. In at least one embodiment, code block 406 can be filled 408 with null values ​​to generate a filling code block 410 after adding a CRC code, thereby using the code block without adding null values ​​to calculate the CRC code.

[0096] In at least one embodiment, the padding code block 410 may be encoded 412 to generate an encoded code block 414. In at least one embodiment, the padding code block 410 may be encoded 412 using parameters specified in the 5G standard to generate the encoded code block 414. In at least one embodiment, the encoded code block 414 includes N bits (d0, d1, d2, ..., d N-1 ), where N is the product of multiple factors specified in the 5G standard, and the bits (d0, d1, d2, ..., d N-1 ) are selected from the padding code block 410 according to the 5G standard. In at least one embodiment, N is greater than the maximum block size of the padding code block 410. In at least one embodiment, the bits (d0, d1, d2, ..., dN-1 ) are further processed for rate matching using systems and methods such as those described herein.

[0097] Figure 5 An example process 500 for encoding a data block in data transmission rate matching according to at least one embodiment is shown. In at least one embodiment, a processor, such as processor 124, executes instructions to perform the example process 500. In at least one embodiment, at step 502 of the example process 500, an input sequence of bits (b0, b1, b2, ..., b B-1 In at least one embodiment, after step 502 , execution of the example process 500 proceeds to step 504 .

[0098] In at least one embodiment, at step 504 of example process 500, a block size is determined. In at least one embodiment, the block size is determined based at least in part on a 5G standard. In at least one embodiment, after step 504, execution of example process 500 proceeds to step 506.

[0099] In at least one embodiment, at step 506 of the example process 500, the number of blocks is determined based, at least in part, on the number of bits in the input sequence and the determined block size. In at least one embodiment, for example, if the input sequence includes 65,536 bits and the maximum block size is 8,192 bits, there may be eight code blocks. In at least one embodiment, where a code block with the maximum code block size can store bits less than the maximum code block size so that a CRC code can be calculated for the code, the code block can store 8,168 bits, as described above. In at least one embodiment, for example, if the input sequence includes 65,536 bits, the maximum code block size is 8,192 bits, and a 24-bit CRC code is stored in each code block, the code block 406 can be one of nine code blocks that store 7,281 bits (in two code blocks) or 7,282 bits (in seven code blocks) from the input sequence and also store 24 bits of the CRC code, for a total of two 7,305-bit code blocks and seven 7,306-bit code blocks. In at least one embodiment, after step 506 , execution of the example process 500 proceeds to step 508 .

[0100] In at least one embodiment, at step 508 of the example process 500, a determination is made as to whether one code block or multiple code blocks can be used. In at least one embodiment, at step 508, if the number of bits in the input sequence is less than the maximum code block size, a determination is made as to whether one code block or multiple code blocks can be used. In at least one embodiment, if at step 508 it is determined that one code block can be used ("yes" branch), execution of the example process 500 proceeds to step 510. In at least one embodiment, if at step 508 it is determined that multiple code blocks can be used ("no" branch), execution of the example process 500 proceeds to step 512.

[0101] In at least one embodiment, at step 510 of the example process 500 , a single code block is generated that can be used to store bits from the input sequence. In at least one embodiment, after step 510 , execution of the example process 500 proceeds to step 522 .

[0102] In at least one embodiment, at step 512 of the example process 500 , a first block of a plurality of code blocks that can be used to store bits from the input sequence is generated. In at least one embodiment, after step 512 , execution of the example process 500 proceeds to step 514 .

[0103] In at least one embodiment, at step 514 of the example process 500, as described herein, bits (c0, c1, c2, ..., c K-1 ) fills the generated code block in the plurality of code blocks. In at least one embodiment, after step 514, execution of the example process 500 proceeds to step 516.

[0104] In at least one embodiment, at step 516 of the example process 500, a CRC code is generated for the generated code block that is filled with bits (c0, c1, c2, ..., c K-1 In at least one embodiment, after step 516 , execution of the example process 500 proceeds to step 518 .

[0105] In at least one embodiment, at step 518 of the example process 500, the generated code block is padded with null values ​​up to a maximum block size determined using the 5G standard. In at least one embodiment, step 518 is performed before step 516. In at least one embodiment, step 518 is performed after step 516. In at least one embodiment, after step 518, execution of the example process 500 proceeds to step 520.

[0106] In at least one embodiment, at step 520 of the example process 500, a single code block is encoded to produce bits (d0, d1, d2, ..., d N-1 In at least one embodiment, after step 520 , execution of the example process 500 proceeds to step 528 .

[0107] In at least one embodiment, at step 522 of the example process 500, a single code block is filled with bits (c0, c1, c2, ..., c K-1 In at least one embodiment, after step 522 , execution of the example process 500 proceeds to step 524 .

[0108] In at least one embodiment, at step 524 of the example process 500, the single code block is filled with null values ​​up to a maximum block size determined using the 5G standard. In at least one embodiment, after step 524, execution of the example process 500 proceeds to step 526.

[0109] In at least one embodiment, at step 526 of the example process 500, a single code block is encoded to produce the bits (d0, d1, d2, ..., d N-1 In at least one embodiment, after step 526 , execution of the example process 500 proceeds to step 530 .

[0110] In at least one embodiment, at step 528 of the example process 500, a determination is made as to whether more code blocks in the plurality of code blocks can be generated. In at least one embodiment, if it is determined at step 528 that more code blocks in the plurality of code blocks can be generated (the "yes" branch), execution of the example process 500 continues at step 512, where the next block to be processed can be generated. In at least one embodiment, if it is determined at step 528 that no more code blocks in the plurality of code blocks can be generated (the "no" branch), execution of the example process 500 proceeds to step 530.

[0111] In at least one embodiment, at step 530 of the example process 500, one or more code blocks are returned for further processing using systems and methods such as those described herein. In at least one embodiment, if it is determined at step 508 that one code block can be used (the "yes" branch), a single code block can be returned at step 530. In at least one embodiment, if it is determined at step 508 that more than one code block can be used (the "no" branch), multiple code blocks can be returned at step 530. In at least one embodiment, after step 530, execution of the example process 500 terminates. In at least one embodiment, after step 530, execution of the example process 500 restarts at step 502 with a new input sequence.

[0112] Figure 6 An example process 600 for data transmission rate matching according to at least one embodiment is shown. In at least one embodiment, a processor, such as processor 124, executes instructions to perform the example process 600. In at least one embodiment, a processor, such as processor 124, executes instructions to perform the example process 600 sequentially. In at least one embodiment, a processor, such as processor 124, executes instructions to perform the example process 600 in parallel. In at least one embodiment, at step 602 of the example process 600, a datagram comprising bits (d0, d1, d2, ..., d N-1 ) for processing. In at least one embodiment, after step 602, execution of the example process 600 proceeds to step 604.

[0113] In at least one embodiment, at step 604 of example process 600, one or more common factors associated with rate matching are determined. In at least one embodiment, the one or more common factors associated with rate matching are determined based on a 5G standard. In at least one embodiment, after step 604, execution of example process 600 proceeds to step 606.

[0114] In at least one embodiment, at step 606 of example process 600, a first block of the one or more received blocks is selected for processing. In at least one embodiment, if a block is received, that block may be selected for processing. In at least one embodiment, if multiple data blocks are received, the first block selected for processing may be the first block of multiple encoded data blocks. In at least one embodiment, if multiple data blocks are received, the first block selected for processing may be a later block of the multiple encoded data blocks. In at least one embodiment, the first block selected for processing may be selected based at least in part on a priority associated with the selected block. In at least one embodiment, after step 606, execution of example process 600 proceeds to step 608.

[0115] In at least one embodiment, at step 608 of example process 600, the blocks selected for processing can be treated as a circular buffer to enable wrapping as described herein. In at least one embodiment, the blocks selected for processing can be treated as a circular buffer by using a modulo operation for indexing during processing. In at least one embodiment, the blocks selected for processing can be copied to the circular buffer to enable wrapping as described herein. In at least one embodiment, after step 610, execution of example process 600 proceeds to step 612.

[0116] In at least one embodiment, at step 610 of the example process 600, an initial index K0 for selecting bits for rate matching as described herein is determined based at least in part on the 5G standard. In at least one embodiment, a new initial index K0 is determined for each selected code block. In at least one embodiment, after step 610, execution of the example process 600 proceeds to step 612.

[0117] In at least one embodiment, at step 612 of the example process 600, a vector e is generated for the selected code block based at least in part on the 5G standard. k In at least one embodiment, after step 612 , execution of the example process 600 proceeds to step 614 .

[0118] In at least one embodiment, at step 614 of example process 600 , a modulation order Qm is generated for the selected code block based at least in part on the 5G standard. In at least one embodiment, after step 614 , execution of example process 600 proceeds to step 616 .

[0119] In at least one embodiment, at step 616 of the example process 600, the vector e k Use the bits (d0, d1, d2, ..., d N-1) are sparsely placed to generate f based at least in part on the modulation order Qm defined by the 5G standard k In at least one embodiment, after step 616 , execution of the example process 600 proceeds to step 618 .

[0120] In at least one embodiment, at step 618 of the example process 600, a determination is made as to whether there are more blocks to be selected for processing. In at least one embodiment, if at step 618, it is determined that there are more blocks to be selected for processing (the "yes" branch), execution of the example process 600 continues at step 606, where the next block can be selected. In at least one embodiment, if at step 618, it is determined that there are no more blocks to be selected for processing (the "no" branch), execution of the example process 600 proceeds to step 620.

[0121] In at least one embodiment, at step 620 of the example process 600, one or more f k In at least one embodiment, after step 620, execution of the example process 600 terminates. In at least one embodiment, after step 620, execution of the example process 600 restarts at step 602 with a new set of blocks.

[0122] Figure 7 An example encoded data block processing data flow 700 for data transmission rate matching according to at least one embodiment is illustrated. In at least one embodiment, a padding code block 702 is encoded to produce an encoded code block 704 as described herein. In at least one embodiment, the encoded code block 704 can be treated as a circular buffer 706 to enable wrapping of indices using modular arithmetic as described herein. In at least one embodiment, the encoded code block 704 can be copied to the circular buffer 706 to enable wrapping of indices using modular arithmetic as described herein. In at least one embodiment, data element cn0 can be associated 708 with the first position of the circular buffer 706, and data element cn Kn-1 may be associated 710 with the second position of the circular buffer 706 such that the data elements of the encoded code block 704 may be contiguous in the circular buffer 706. In at least one embodiment, the zero elements of the encoded code block 704 may also be contiguous in the circular buffer 706.

[0123] Figure 8An example bit selection data stream data 800 for data transmission rate matching according to at least one embodiment is shown. In at least one embodiment, index K0 804 is generated based at least in part on the 5G standard using systems and methods such as those described herein. In at least one embodiment, index K0 804 is generated such that index K0 804 is within the region of null values ​​of a circular buffer 802 as described herein. In at least one embodiment, index K0 804 is generated such that index K0 804 is located before the region of null values ​​of a circular buffer 802 as described herein. In at least one embodiment, index K0 804 is generated such that index K0 804 is located after the region of null values ​​of a circular buffer 802 as described herein.

[0124] In at least one embodiment, the index is incremented starting from index K0 until index K i-1 806 is a null value, but this is the last null value before the consecutive non-null values ​​(ie, the next value is not a null value). In at least one embodiment, the circular buffer 802 is at index K i The value at 808 is the first non-null value, and the circular buffer 802 is at index K. i+1 The value at 810 is the second non-null value, and the circular buffer 802 is at index K i+Kn-1 The value at 812 is the last non-null value (i.e., at index K i+Kn-1 The next value after that is null).

[0125] Figure 9 An example process 900 for sequentially selecting bits in data transmission rate matching according to at least one embodiment is shown. In at least one embodiment, a processor, such as processor 124, executes instructions to perform example process 900. In at least one embodiment, example process 900 includes a step (not shown) of skipping bits as described herein. In at least one embodiment, for an uplink rate matching algorithm, bits may be placed in a buffer and one or more sequential positions within the buffer may be skipped (i.e., may have null values). In at least one embodiment, for a downlink rate matching algorithm, bits may be selected from the buffer and null values ​​may be skipped when selected. In at least one embodiment, at step 902 of example process 900, a circular buffer is received. In at least one embodiment, after step 902, execution of example process 900 proceeds to step 904.

[0126] In at least one embodiment, at step 904 of the example process 900, an initial index K0 is determined based at least in part on the 5G standard, as described herein. In at least one embodiment, after step 904, execution of the example process 900 proceeds to step 906.

[0127] In at least one embodiment, at step 906 of the example process 900 , an index for locating non-null values ​​is generated, starting from an initial index K 0 . In at least one embodiment, after step 906 , execution of the example process 900 proceeds to step 908 .

[0128] In at least one embodiment, at step 908 of the example process 900 , data is read at the index used to locate a non-null value in the circular buffer. In at least one embodiment, after step 908 , execution of the example process 900 proceeds to step 910 .

[0129] In at least one embodiment, at step 910 of the example process 900, a determination is made as to whether the data at the index used to locate a non-null value in the circular buffer is a null or zero value. In at least one embodiment, if at step 910 it is determined that the data at the index used to locate a non-null value in the circular buffer is a null or zero value (the "yes" branch), execution of the example process 900 proceeds to step 912. In at least one embodiment, if at step 910 it is determined that the data at the index used to locate a non-null value in the circular buffer is not a null or zero value (the "no" branch), execution of the example process 900 proceeds to step 914.

[0130] In at least one embodiment, at step 912 of example process 900, the index used to locate the non-null value in the circular buffer is incremented using modulo arithmetic such that the incremented index wraps around the circular buffer, as described herein. In at least one embodiment, after step 912, execution of example process 900 continues at step 908 to examine the data at the incremented index.

[0131] In at least one embodiment, at step 914 of the example process 900, the non-null value K i At the index used to locate a non-null value in the circular buffer. In at least one embodiment, after step 914, execution of the example process 900 proceeds to step 916.

[0132] In at least one embodiment, at step 916 of the example process 900, the Figure 3 and Figure 4 The algorithm described in selects bits from the circular buffer. In at least one embodiment, after step 916, execution of the example process 900 terminates.

[0133] Figure 10An example thread allocation diagram 1000 for processing data blocks in data transfer rate matching according to at least one embodiment is illustrated. In at least one embodiment, a stream of data blocks 1002 is received. In at least one embodiment, data block B1 is allocated for processing using resources of thread 1004, data block B2 is allocated for processing using resources of thread 1006, data block B3 is allocated for processing using resources of thread 1012, and data block B4 is allocated for processing using resources of thread 1014.

[0134] In at least one embodiment, after thread 1004 completes processing data block B1, data block B5 may be allocated for processing using thread 1004's resources, and after thread 1006 completes processing data block B2, data block B6 may be allocated for processing using thread 1006's resources. In at least one embodiment, thread 1006's processing of data block B2 may result in error 1008. In at least one embodiment, if thread 1006's processing of data block B2 results in error 1008, data block B2 may be returned 1010 to stream 1002 for reprocessing. In at least one embodiment, after thread 1012 completes processing data block B3, data block B2 may be allocated for reprocessing using thread 1012's resources. In at least one embodiment, after thread 1014 completes processing data block B4, data block B7 may be allocated for processing using thread 1014's resources. In at least one embodiment, a single thread may process multiple bits in a data block. In at least one embodiment, multiple threads may process a single bit in a data block. In at least one embodiment, a thread may process a single bit in a block of data.

[0135] Figure 11 An example data retransmission diagram 1100 for processing a data block in data transmission rate matching according to at least one embodiment is shown. In at least one embodiment, the data retransmission diagram is shown as a circular queue 1102. In at least one embodiment, a transmission order 1104 may be determined based at least in part on the 5G standard. In at least one embodiment, for example, if there are four transmissions for a data block, the transmission order 1104 may be first, third, fourth, and second (denoted as {RV0, RV2, RV3, RV1}). In at least one embodiment, the first transmission 1106 may occur in RV0. In at least one embodiment, the third transmission 1108 may occur in RV2 after the first transmission 1106. In at least one embodiment, the data in the third transmission 1108 may be scrambled using techniques specified in the 5G standard such that the data in the third transmission 1108 may differ from the data in the first transmission 1106.

[0136] In at least one embodiment, the fourth transmission 1110 may occur at RV3 after the third transmission 1108. In at least one embodiment, the data in the fourth transmission 1110 may also be scrambled using techniques specified in the 5G standard, such that the data in the fourth transmission 1110 may be different from the data in the first transmission 1106, and thus the data in the fourth transmission 1110 may be different from the data in the third transmission 1108.

[0137] In at least one embodiment, the second transmission 1112 may occur at RV1 after the fourth transmission 1110. In at least one embodiment, the data in the second transmission 1112 may also be scrambled using techniques specified in the 5G standard, such that the data in the second transmission 1112 may be different from the data in the first transmission 1106, such that the data in the second transmission 1112 may be different from the data in the third transmission 1108, and such that the data in the second transmission 1112 may be different from the data in the fourth transmission 1110.

[0138] Figure 12 An example process 1200 for retransmitting a data block in data transmission rate matching according to at least one embodiment is shown. In at least one embodiment, a processor, such as processor 124, executes instructions to perform the example process 1200. In at least one embodiment, at step 1202 of the example process 1200, a data block for retransmission is received. In at least one embodiment, after step 1202, execution of the example process 1200 proceeds to step 1204.

[0139] In at least one embodiment, at step 1204 of example process 1200, data RV0 is generated for the first transmission of the data block. In at least one embodiment, data RV0 is scrambled using techniques specified in the 5G standard such that data RV0 for the first transmission of the data block is different from data in the received data block. In at least one embodiment, data RV0 in the data block is not scrambled such that data RV0 for the first transmission of the data block is the same as data in the received data block. In at least one embodiment, after step 1204, execution of example process 1200 proceeds to step 1206.

[0140] In at least one embodiment, at step 1206 of the example process 1200 , data RV0 for a first transmission of the data block is transmitted. In at least one embodiment, after step 1206 , execution of the example process 1200 proceeds to step 1208 .

[0141] In at least one embodiment, at step 1208 of the example process 1200, a determination is made as to whether a second transmission of the data in the received data block may occur. In at least one embodiment, if it is determined at step 1208 that a second transmission of the data in the received data block may occur (the "yes" branch), execution of the example process 1200 proceeds to step 1210. In at least one embodiment, if it is determined at step 1208 that a second transmission of the data in the received data block may not occur (the "no" branch), execution of the example process 1200 proceeds to step 1216.

[0142] In at least one embodiment, at step 1210 of example process 1200, data RV2 is generated for a second transmission of the data block. In at least one embodiment, data RV2 is scrambled using techniques specified in the 5G standard such that data RV2 for the second transmission of the data block is different from data in the received data block. In at least one embodiment, data RV2 is scrambled using techniques specified in the 5G standard such that data RV2 for the second transmission of the data block is different from data RV0 for the first transmission of the data block. In at least one embodiment, after step 1210, execution of example process 1200 proceeds to step 1212.

[0143] In at least one embodiment, data RV2 for the second transmission of the data block is transmitted at step 1212 of the example process 1200. In at least one embodiment, after step 1212, execution of the example process 1200 proceeds to step 1214.

[0144] In at least one embodiment, at step 1214 of the example process 1200, a determination is made as to whether a third transmission of the data in the received data block may occur. In at least one embodiment, if it is determined at step 1214 that a third transmission of the data in the received data block may occur (the "yes" branch), execution of the example process 1200 proceeds to step 1218. In at least one embodiment, if it is determined at step 1214 that a third transmission of the data in the received data block may not occur (the "no" branch), execution of the example process 1200 proceeds to step 1216.

[0145] In at least one embodiment, at step 1216 of the example process 1200, the process 1200 returns. In at least one embodiment, at step 1216, an indication of successful completion of the process 1200 is returned. In at least one embodiment, the indication of successful completion of the process 1200 is returned to the calling process. In at least one embodiment, the indication of successful completion of the process 1200 is returned using a reporting API. In at least one embodiment, after step 1216, execution of the example process 1200 terminates. In at least one embodiment, after step 1216, execution of the example process 1200 continues with a new block at step 1202.

[0146] In at least one embodiment, at step 1218 of example process 1200, data RV3 for a third transmission of the data block is generated. In at least one embodiment, data RV3 is perturbed using techniques specified in the 5G standard such that data RV3 for the third transmission of the data block is different from data in the received data block. In at least one embodiment, data RV3 is perturbed using techniques specified in the 5G standard such that data RV3 for the third transmission of the data block is different from data RV0 for the first transmission of the data block. In at least one embodiment, data RV3 is perturbed using techniques specified in the 5G standard such that data RV3 for the third transmission of the data block is different from data RV2 for the second transmission of the data block. In at least one embodiment, after step 1218, execution of example process 1200 proceeds to step 1220.

[0147] In at least one embodiment, at step 1220 of the example process 1200, data RV3 for the third transmission of the data block is transmitted. In at least one embodiment, after step 1220, execution of the example process 1200 proceeds to step 1222.

[0148] In at least one embodiment, at step 1222 of the example process 1200, a determination is made as to whether a fourth transmission of the data in the received data block may occur. In at least one embodiment, if at step 1222 it is determined that a fourth transmission of the data in the received data block may occur (the "yes" branch), execution of the example process 1200 proceeds to step 1224. In at least one embodiment, if at step 1222 it is determined that a fourth transmission of the data in the received data block may not occur (the "no" branch), execution of the example process 1200 proceeds to step 1216 (described above).

[0149] In at least one embodiment, at step 1224 of example process 1200, data RV1 for the fourth transmission of the data block is generated. In at least one embodiment, data RV1 is scrambled using techniques specified in the 5G standard such that data RV1 for the fourth transmission of the data block is different from data in the received data block. In at least one embodiment, data RV4 is scrambled using techniques specified in the 5G standard such that data RV1 for the fourth transmission of the data block is different from data RV0 for the first transmission of the data block. In at least one embodiment, data RV1 is scrambled using techniques specified in the 5G standard such that data RV1 for the fourth transmission of the data block is different from data RV2 for the second transmission of the data block. In at least one embodiment, data RV1 is scrambled using techniques specified in the 5G standard such that data RV1 for the fourth transmission of the data block is different from data RV3 for the third transmission of the data block. In at least one embodiment, after step 1224, execution of example process 1200 proceeds to step 1226.

[0150] In at least one embodiment, data RV1 for the fourth transmission of the data block is transmitted at step 1226 of the example process 1200. In at least one embodiment, after step 1226, execution of the example process 1200 proceeds to step 1216 (described above).

[0151] Figure 13 An example process 1300 for selecting bits in data rate matching in parallel according to at least one embodiment is shown. In at least one embodiment, a processor, such as processor 124, executes instructions to perform the example process 1300. In at least one embodiment, at step 1302 of the example process 1300, a circular buffer having N elements is received as described herein. In at least one embodiment, after step 1302, execution of the example process 1300 proceeds to step 1304.

[0152] In at least one embodiment, at step 1304 of example process 1300, multiple threads are generated to execute example process 1300 in parallel. In at least one embodiment, a total of E threads are generated to execute example process 1300 in parallel, where E is based on N (the number of data values ​​in the received circular buffer). In at least one embodiment, E can be equal to N, so that, for example, one thread can process one data value in the received circular buffer in parallel. In at least one embodiment, E can be greater than N, so that, for example, one or more threads can process one data value in the received circular buffer in parallel. In at least one embodiment, E can be less than N, so that, for example, one thread can process one or more data values ​​in the received circular buffer in parallel with other threads that may also process one or more data values ​​in the received circular buffer. In at least one embodiment, after step 1304, execution of example process 1300 proceeds to step 1306.

[0153] In at least one embodiment, multiple threads begin processing the data values ​​received in the circular buffer at step 1306 of the example process 1300. In at least one embodiment, after step 1306, execution of the example process 1300 proceeds to step 1310 for thread 0. In at least one embodiment, after step 1306, execution of the example process 1300 also proceeds to step 1322 to process threads 1 ... E-1 in parallel using the techniques described in conjunction with steps 1310-1320.

[0154] In at least one embodiment, at step 1310 of the example process 1300, an initial index K0 for thread 0 is determined based at least in part on the 5G standard and using systems and methods such as those described herein. In at least one embodiment, after step 1310, execution of the example process 1300 proceeds to step 1312 for thread 0. In at least one embodiment, although not in Figure 13 , but the steps for the other threads (ie, thread 1, thread 2, etc.) are performed in parallel using processes similar to those described in conjunction with step 1310.

[0155] In at least one embodiment, at step 1312 of the example process 1300, it is determined whether the initial index K0 is within the K0 of thread 0 as described herein. d Before or K d In at least one embodiment, if the initial index K0 is determined to be in the K of thread 0 at step 1312, d Before or K d At step 1312 ("yes" branch), execution of the example process 1300 proceeds to step 1314 of thread 0. In at least one embodiment, if it is determined at step 1312 that the initial index K0 is not in the Kd Before 0 or K d ("No" branch), execution of the example process 1300 proceeds to step 1316 of thread 0. In at least one embodiment, although not in Figure 13 , but the steps for the other threads (ie, thread 1, thread 2, etc.) are performed in parallel using processes similar to those described in connection with step 1312.

[0156] In at least one embodiment, at step 1314, example process 1300 uses Algorithm 1 to locate the selectable bit for thread 0. In at least one embodiment, InIdx is an input index that can range from 0 to E-1, as defined by the 5G standard. In at least one embodiment, for a single code block, InIdx can indicate which thread can be used to select the data value. In at least one embodiment, for multiple code blocks, InIdx can indicate which thread can be used to select the data value of the code block. In at least one embodiment, Ncb is the array length of the code block. In at least one embodiment, OutIdx is the output index returned by Algorithm 1. In at least one embodiment, Algorithm 1 is implemented as follows:

[0157]

[0158] In at least one embodiment, although not in Figure 13 , but the steps for the other threads (ie, thread 1, thread 2, etc.) are performed in parallel using processes similar to those described in conjunction with step 1314.

[0159] In at least one embodiment, after step 1314, execution of the example process 1300 terminates for thread 0. In at least one embodiment, after step 1314, execution of the example process 1300 continues with the new circular buffer at step 1302. In at least one embodiment, processor resources associated with executing the example process 1300 for thread 0 may be used to process data from another thread (i.e., thread 1, thread 2, etc.), and after step 1314, execution of the example process 1300 may continue with the new thread data after step 1306.

[0160] In at least one embodiment, at step 1316 of the example process 1300, it is determined whether K0 of thread 0 is in (K d +F) or later. In at least one embodiment, if it is determined in step 1316 that K0 of thread 0 is at (K d +F) at or after ("yes" branch), execution of the example process 1300 proceeds to step 1318 of thread 0. In at least one embodiment, if it is determined at step 1316 that K0 of thread 0 is not at (Kd +F) at or after ("No" branch), execution of the example process 1300 proceeds to step 1320 of thread 0. In at least one embodiment, although not in Figure 13 , but the steps for the other threads (ie, thread 1, thread 2, etc.) are performed in parallel using processes similar to those described in conjunction with step 1316.

[0161] In at least one embodiment, at step 1318, example process 1300 uses Algorithm 2 to locate the selectable bit for thread 0. In at least one embodiment, InIdx is an input index that can range from 0 to E-1, as defined by the 5G standard. In at least one embodiment, for a single code block, InIdx can indicate which thread can be used to select the data value. In at least one embodiment, for multiple code blocks, InIdx can indicate which thread can be used to select the data value of the code block. In at least one embodiment, Ncb is the array length of the code block. In at least one embodiment, OutIdx is the output index returned by Algorithm 2. In at least one embodiment, Algorithm 2 is implemented as follows:

[0162]

[0163]

[0164] In at least one embodiment, although not in Figure 13 , but the steps for the other threads (ie, thread 1, thread 2, etc.) are performed in parallel using processes similar to those described in conjunction with step 1318.

[0165] In at least one embodiment, after step 1318, execution of the example process 1300 terminates for thread 0. In at least one embodiment, after step 1318, execution of the example process 1300 continues with the new circular buffer at step 1302. In at least one embodiment, processor resources associated with executing the example process 1300 for thread 0 may be used to process data from another thread (i.e., thread 1, thread 2, etc.), and after step 1318, execution of the example process 1300 may continue with the new thread data after step 1306.

[0166] In at least one embodiment, at step 1320 of example process 1300, algorithm three is used for thread 0. In at least one embodiment, InIdx is an input index that can range from 0 to E-1, as defined by the 5G standard. In at least one embodiment, for a single code block, InIdx can indicate which thread can be used to select the data value. In at least one embodiment, for multiple code blocks, InIdx can indicate which thread can be used to select the data value of the code block. In at least one embodiment, Ncb is the array length of the code block. In at least one embodiment, OutIdx is the output index returned by algorithm three. In at least one embodiment, since the "no" branch is executed in steps 1312 and 1316 of thread 0, algorithm three is used for thread 0 as the default case. In at least one embodiment, algorithm three is implemented according to the following code:

[0167]

[0168]

[0169] In at least one embodiment, although not in Figure 13 , but the steps for the other threads (ie, thread 1, thread 2, etc.) are performed in parallel using processes similar to those described in conjunction with step 1320.

[0170] In at least one embodiment, after step 1320, execution of the example process 1300 terminates for thread 0. In at least one embodiment, after step 1320, execution of the example process 1300 continues with the new circular buffer at step 1302. In at least one embodiment, processor resources associated with executing the example process 1300 for thread 0 may be used to process data from another thread (i.e., thread 1, thread 2, etc.), and after step 1320, execution of the example process 1300 may continue with the new thread data after step 1306.

[0171] Data Center

[0172] Figure 14 An example data center 1400 is shown in which at least one embodiment may be used. In at least one embodiment, the data center 1400 includes a data center infrastructure layer 1410, a framework layer 1420, a software layer 1430, and an application layer 1440.

[0173] In at least one embodiment, Figure 14As shown, the data center infrastructure layer 1410 may include a resource coordinator 1412, grouped computing resources 1414, and node computing resources ("node CRs") 1416(1)-1416(N), where "N" represents any integer, positive integer. In at least one embodiment, the node CRs 1416(1)-1416(N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory devices (e.g., dynamic read-only memories), storage devices (e.g., solid-state drives or disk drives), network input / output ("NW I / O") devices, network switches, virtual machines ("VMs"), power modules, and cooling modules. In at least one embodiment, one or more of the node CRs 1416(1)-1416(N) may be servers having one or more of the aforementioned computing resources.

[0174] In at least one embodiment, the grouped computing resources 1414 may include separate groups of node CRs housed in one or more racks (not shown), or may include many racks (also not shown) housed in data centers at various geographic locations. In at least one embodiment, the separate groups of node CRs within the grouped computing resources 1414 may include computing, networking, memory, or storage resources that may be configured or allocated to support groupings of one or more workloads. In at least one embodiment, several node CRs including CPUs or processors may be grouped in one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0175] In at least one embodiment, resource coordinator 1412 may configure or otherwise control one or more nodes CR 1416(1)-1416(N) and / or grouped computing resources 1414. In at least one embodiment, resource coordinator 1412 may comprise a software design infrastructure ("SDI") management entity for data center 1400. In at least one embodiment, resource coordinator may comprise hardware, software, or some combination thereof.

[0176] In at least one embodiment, Figure 14As shown, the framework layer 1420 includes a job scheduler 1432, a configuration manager 1434, a resource manager 1436, and a distributed file system 1438. In at least one embodiment, the framework layer 1420 may include a framework that supports the software 1432 of the software layer 1430 and / or one or more applications 1442 of the application layer 1440. In at least one embodiment, the software 1432 or the application 1442 may include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 1420 may be, but is not limited to, a free and open source software web application framework, such as Apache Spark, which may utilize the distributed file system 1438 for large-scale data processing (e.g., "big data"). TM (hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 1432 may include a Spark driver to facilitate scheduling workloads supported by the various layers of the data center 1400. In at least one embodiment, the configuration manager 1434 may be capable of configuring the various layers, such as the software layer 1430 and the framework layer 1420 including Spark and a distributed file system 1438 for supporting large-scale data processing. In at least one embodiment, the resource manager 1436 may be capable of managing the cluster or group computing resources mapped to or allocated to support the distributed file system 1438 and the job scheduler 1432. In at least one embodiment, the cluster or group computing resources may include the group computing resources 1414 on the data center infrastructure layer 1410. In at least one embodiment, the resource manager 1436 may coordinate with the resource coordinator 1412 to manage these mapped or allocated computing resources.

[0177] In at least one embodiment, the software 1432 included in the software layer 1430 may include software used by at least a portion of the node CRs 1416(1)-1416(N), the grouped computing resources 1414, and / or the distributed file system 1438 of the framework layer 1420. In at least one embodiment, the one or more types of software may include, but are not limited to, Internet web search software, email virus scanning software, database software, and streaming video content software.

[0178] In at least one embodiment, the one or more applications 1442 included in the application layer 1440 may include one or more types of applications used by at least a portion of the node CRs 1416(1)-1416(N), the grouped computing resources 1414, and / or the distributed file system 1438 of the framework layer 1420. In at least one embodiment, the one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0179] In at least one embodiment, any of configuration manager 1434, resource manager 1436, and resource coordinator 1412 can implement any number and type of self-modification actions based on any number and type of data obtained in any technically feasible manner. In at least one embodiment, the self-modification actions can relieve a data center operator of data center 1400 from making potentially poor configuration decisions and can avoid underutilized and / or poorly performing portions of the data center.

[0180] In at least one embodiment, data center 1400 may include tools, services, software, or other resources to train one or more machine learning models or use one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model can be trained by calculating weight parameters according to a neural network architecture using the software and computing resources described above with respect to data center 1400. In at least one embodiment, using the weight parameters calculated using one or more training techniques described herein, a trained machine learning model corresponding to one or more neural networks can be used to infer or predict information using the resources described above with respect to data center 1400.

[0181] In at least one embodiment, a data center can use a CPU, application-specific integrated circuit (ASIC), GPU, FPGA, or other hardware to use the above resources to perform training and / or reasoning. In addition, one or more of the above software and / or hardware resources can be configured as a service to allow users to train or perform information reasoning, such as image recognition, speech recognition, or other artificial intelligence services.

[0182] In at least one embodiment, Figure 14 At least one component shown or described is used to implement the combination Figure 1-13In at least one embodiment, at least one of group computing resources 1414 and node CRs 1416(1-N) is configured to perform rate matching. In at least one embodiment, rate matching includes causing 5G New Radio signal information to be selected in parallel using parameters based at least in part on a 5G standard. In at least one embodiment, at least one of group computing resources 1414 and node CRs 1416(1-N) is configured to perform at least one aspect of rate matching 114, example process 300, data flow 400, example process 500, example process 600, example process 900, graph 1100, example process 1200, example process 1300, algorithm 1 described in at least conjunction with step 1314 of example process 1300, algorithm 2 described in at least conjunction with step 1316 of example process 1300, and / or algorithm 3 described in at least conjunction with step 1320 of example process 1300.

[0183] Figure 15A An example of an autonomous vehicle 1500 is shown, according to at least one embodiment. In at least one embodiment, autonomous vehicle 1500 (alternatively referred to herein as "vehicle 1500") can be, but is not limited to, a passenger vehicle, such as a car, truck, bus, and / or another type of vehicle that can accommodate one or more passengers. In at least one embodiment, vehicle 1500 can be a semi-tractor-trailer for hauling cargo. In at least one embodiment, vehicle 1500 can be an aircraft, a robotic vehicle, or another type of vehicle.

[0184] Automated driving vehicles may be described according to the levels of automation defined by the National Highway Traffic Safety Administration ("NHTSA") and the Society of Automotive Engineers ("SAE") under the U.S. Department of Transportation, "Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles" (e.g., Standard No. J3016-201806, dated June 15, 2018, Standard No. J3016-201609, dated September 30, 2016, and previous and future versions of this standard). In one or more embodiments, the vehicle 1500 may be capable of functioning according to one or more of the levels 1 to 5 of automated driving. For example, in at least one embodiment, the vehicle 1500 may be capable of conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5), depending on the embodiment.

[0185] In at least one embodiment, vehicle 1500 may include, but is not limited to, components such as a chassis, a body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of the vehicle. In at least one embodiment, vehicle 1500 may include, but is not limited to, a propulsion system 1550, such as an internal combustion engine, a hybrid power plant, an all-electric engine, and / or another type of propulsion system. In at least one embodiment, propulsion system 1550 may be connected to a drive train of vehicle 1500, which may include, but is not limited to, a transmission, to enable propulsion of vehicle 1500. In at least one embodiment, propulsion system 1550 may be controlled in response to receiving a signal from throttle / accelerator 1552.

[0186] In at least one embodiment, when propulsion system 1550 is operating (e.g., when the vehicle is traveling), a steering system 1554 (which may include, but is not limited to, a steering wheel) is used to steer vehicle 1500 (e.g., along a desired path or route). In at least one embodiment, steering system 1554 may receive signals from steering actuator 1556. In at least one embodiment, a steering wheel may be optional for fully automated (Level 5) functionality. In at least one embodiment, brake sensor system 1546 may be used to operate the vehicle brakes in response to signals received from brake actuator 1548 and / or brake sensors.

[0187] In at least one embodiment, the controller 1536 may include, but is not limited to, one or more system-on-chips ("SoCs") ( Figure 15A) and / or a graphics processing unit (“GPU”) provides signals (e.g., representing commands) to one or more components and / or systems of vehicle 1500. For example, in at least one embodiment, controller 1536 can send signals to operate vehicle brakes via brake actuator 1548, operate steering system 1554 via one or more steering actuators 1556, and operate propulsion system 1550 via one or more throttles / accelerators 1552. In at least one embodiment, one or more controllers 1536 can include one or more onboard (e.g., integrated) computing devices (e.g., supercomputers) that process sensor signals and output operational commands (e.g., signals representing commands) to implement autonomous driving and / or assist a driver in driving vehicle 1500. In at least one embodiment, the one or more controllers 1536 may include a first controller 1536 for autonomous driving functionality, a second controller 1536 for functional safety functionality, a third controller 1536 for artificial intelligence functionality (e.g., computer vision), a fourth controller 1536 for infotainment functionality, a fifth controller 1536 for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller 1536 may handle two or more of the aforementioned functions, two or more controllers 1536 may handle a single function, and / or any combination thereof.

[0188] In at least one embodiment, the one or more controllers 1536 provide signals for controlling one or more components and / or systems of the vehicle 1500 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, the sensor data can be received from sensors such as, but not limited to, one or more global navigation satellite system ("GNSS") sensors 1558 (e.g., one or more global positioning system sensors), one or more RADAR sensors 1560, one or more ultrasonic sensors 1562, one or more LIDAR sensors 1564, one or more inertial measurement unit (IMU) sensors 1566 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 1596, one or more stereo cameras 1568, one or more wide angle cameras 1570 (e.g., fisheye cameras), one or more infrared cameras 1572, one or more surround cameras 1574 (e.g., 360 degree cameras), telemetry cameras (e.g., 360 degree cameras), and the like. Figure 15A Not shown), mid-range camera ( Figure 15A), one or more speed sensors 1544 (e.g., for measuring the speed of the vehicle 1500), one or more vibration sensors 1542, one or more steering sensors 1540, one or more brake sensors (e.g., as part of a brake sensor system 1546), and / or other sensor types are received.

[0189] In at least one embodiment, one or more controllers 1536 may receive input (e.g., represented by input data) from a dashboard 1532 of the vehicle 1500 and provide output (e.g., represented by output data, display data, etc.) via a human machine interface ("HMI") display 1534, an audible annunciator, a speaker, and / or other components of the vehicle 1500. In at least one embodiment, the output may include information such as vehicle speed, velocity, time, map data (e.g., high definition map ( Figure 15A ), location data (e.g., the location of the vehicle 1500, such as on a map), directions, the locations of other vehicles (e.g., occupancy barriers), information about objects and the states of objects sensed by the one or more controllers 1536, etc. For example, in at least one embodiment, the HMI display 1534 can display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about the driving maneuvers the vehicle has made, is making, or will make (e.g., changing lanes now, taking exit 34B in two miles, etc.).

[0190] In at least one embodiment, the vehicle 1500 further includes a network interface 1524 that can communicate over one or more networks using one or more wireless antennas 1526 and / or one or more modems. For example, in at least one embodiment, the network interface 1524 may be capable of communicating over Long Term Evolution ("LTE"), Wideband Code Division Multiple Access ("WCDMA"), Universal Mobile Telecommunications System ("UMTS"), Global System for Mobile Communications ("GSM"), IMT-CDMA Multi-Carrier ("CDMA2000") networks, etc. In at least one embodiment, the one or more wireless antennas 1526 can also use one or more local area networks (e.g., Bluetooth, Bluetooth Low Energy (LE), Z-Wave, ZigBee, etc.) and / or one or more low-power wide area networks (hereinafter referred to as "LPWAN") (e.g., protocols such as LoRaWAN and SigFox) to enable communication between objects in the environment (e.g., vehicles, mobile devices).

[0191] In at least one embodiment, Figure 15A At least one component shown or described is used to implement the combination Figure 1-13In at least one embodiment, in combination with the techniques and / or functions described herein, Figure 1-13 The described techniques and / or functionality may perform rate matching on data received from the vehicle 1500 for its autonomous operation and / or may be used by the vehicle 1500 to perform rate matching on data received in connection with its autonomous operation.

[0192] Figure 15B According to at least one embodiment, Figure 15A An example of camera locations and fields of view for autonomous vehicle 1500 is shown. In at least one embodiment, the cameras and respective fields of view are an example embodiment and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or the cameras may be located in different locations on vehicle 1500.

[0193] In at least one embodiment, the camera type used for the camera may include, but is not limited to, a digital camera that may be suitable for use with components and / or systems of the vehicle 1500. In at least one embodiment, one or more cameras may operate at Automotive Safety Integrity Level ("ASIL") B and / or other ASILs. In at least one embodiment, the camera type may have any image capture rate, such as 60 frames per second (fps), 120fps, 240fps, etc., depending on the embodiment. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, another type of shutter, or a combination thereof. In at least one embodiment, the color filter array may include a red-clear-clear ("RCCC") filter array, a red-clear-clear-blue ("RCCB") filter array, a red-blue-green-clear ("RBGC") filter array, a Foveon X3 filter array, a Bayer sensor ("RGGB") filter array, a monochrome sensor filter array, and / or other types of filter arrays. In at least one embodiment, a clear pixel camera, such as one having an RCCC, RCCB, and / or RBGC color filter array, may be used in an effort to increase photosensitivity.

[0194] In at least one embodiment, one or more cameras can be used to perform advanced driver assistance system ("ADAS") functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-function mono camera can be installed to provide functions including lane departure warning, traffic sign assistance, and intelligent headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) can simultaneously record and provide image data (e.g., video).

[0195] In at least one embodiment, one or more cameras can be mounted in a mounting assembly, such as a custom designed (three-dimensional ("3D") printed) assembly, so as to cut out stray light and reflections from within the car (e.g., reflections from the dashboard reflecting in the windshield mirror) that may interfere with the camera's ability to capture image data. With respect to the rearview mirror mounting assembly, in at least one embodiment, the rearview mirror assembly can be 3D printed custom so that the camera mounting plate matches the shape of the rearview mirror. In at least one embodiment, one or more cameras can be integrated into the rearview mirror. In at least one embodiment, for side-view cameras, one or more cameras can also be integrated into the four pillars at each corner of the car.

[0196] In at least one embodiment, a camera (e.g., a forward-facing camera) having a field of view that includes a portion of the environment in front of the vehicle 1500 can be used for surround vision, as well as to help identify the forward path and obstacles with the assistance of one or more controllers 1536 and / or control SoCs, thereby providing information that is critical for generating an occupancy grid and / or determining a preferred vehicle path. In at least one embodiment, the forward-facing camera can be used to perform many of the same ADAS functions as LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the forward-facing camera can also be used for ADAS functions and systems, including but not limited to lane departure warning ("LDW"), automatic cruise control ("ACC"), and / or other functions (e.g., traffic sign recognition).

[0197] In at least one embodiment, various cameras can be used in a forward-facing configuration, including, for example, a monocular camera platform including a CMOS ("Complementary Metal Oxide Semiconductor") color imager. In at least one embodiment, a wide-angle camera 1570 can be used to sense objects entering from the periphery (e.g., pedestrians, people crossing the road, or bicycles). Although Figure 15B Only one wide-angle camera 1570 is shown in the figure, however, in other embodiments, any number (including zero) of wide-angle cameras can be present on the vehicle 1500. In at least one embodiment, any number of remote cameras 1598 (e.g., a remote stereo camera pair) can be used for depth-based object detection, particularly for objects for which a neural network has not yet been trained. In at least one embodiment, the remote cameras 1598 can also be used for object detection and classification, as well as basic object tracking.

[0198] In at least one embodiment, any number of stereo cameras 1568 may also be included in the forward-facing configuration. In at least one embodiment, one or more stereo cameras 1568 may include an integrated control unit including a scalable processing unit that may provide programmable logic (“FPGA”) and a multi-core microprocessor with a controller area network (“CAN”) or Ethernet interface integrated on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the vehicle 1500's environment, including distance estimates for all points in the image. In at least one embodiment, one or more stereo cameras 1568 may include, but are not limited to, a compact stereo vision sensor, which may include, but are not limited to, two camera lenses (one on each side) and an image processing chip that may measure the distance from the vehicle 1500 to the target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 1568 may be used in addition to those described herein.

[0199] In at least one embodiment, a camera having a field of view of a portion of the environment including the sides of the vehicle 1500 (e.g., a side-view camera) can be used for surround viewing to provide information for creating and updating occupancy grids and generating side collision warnings. For example, in at least one embodiment, surround cameras 1574 (e.g., Figure 15B Four surround cameras 1574 (shown) can be positioned on the vehicle 1500. In at least one embodiment, the one or more surround cameras 1574 can include, but are not limited to, any number and combination of wide-angle cameras 1570, one or more fish-eye lenses, one or more 360-degree cameras, and / or the like. For example, in at least one embodiment, four fish-eye lens cameras can be located on the front, rear, and sides of the vehicle 1500. In at least one embodiment, the vehicle 1500 can use three surround cameras 1574 (e.g., left, right, and rear), and can utilize one or more other cameras (e.g., a forward-facing camera) as a fourth surround-view camera.

[0200] In at least one embodiment, a camera having a field of view that includes a portion of the environment behind the vehicle 1500 (e.g., a rearview camera) can be used for parking assistance, surround view, rear collision warning, and creating and updating occupancy grids. In at least one embodiment, a variety of cameras can be used, including but not limited to cameras that are also suitable as one or more forward-facing cameras (e.g., long-range camera 1598 and / or one or more mid-range cameras 1576, one or more stereo cameras 1568, one or more infrared cameras 1572, etc.), as described herein.

[0201] In at least one embodiment, Figure 15B At least one component shown or described is used to implement the combination Figure 1-13 In at least one embodiment, in combination with the techniques and / or functions described herein, Figure 1-13 The described techniques and / or functionality may perform rate matching on data received from the vehicle 1500 for its autonomous operation and / or may be used by the vehicle 1500 to perform rate matching on data received in connection with its autonomous operation.

[0202] Figure 15C According to at least one embodiment, Figure 15A A block diagram of an example system architecture for an autonomous vehicle 1500 is provided. In at least one embodiment, Figure 15C Each of one or more components, one or more features, and one or more systems of vehicle 1500 is shown as being connected via bus 1502. In at least one embodiment, bus 1502 may include, but is not limited to, a CAN data interface (alternatively referred to herein as a "CAN bus"). In at least one embodiment, CAN may be a network internal to vehicle 1500 that facilitates control of various features and functions of vehicle 1500, such as brake actuation, acceleration, braking, steering, wipers, and the like. In one embodiment, bus 1502 may be configured with dozens or even hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). In at least one embodiment, bus 1502 may be read to find steering wheel angle, ground speed, engine revolutions per minute ("RPM"), button positions, and / or other vehicle status indicators. In at least one embodiment, bus 1502 may be an ASIL B compliant CAN bus.

[0203] In at least one embodiment, FlexRay and / or Ethernet may be used in addition to or in addition to CAN. In at least one embodiment, there may be any number of buses 1502, which may include, but are not limited to, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using other protocols. In at least one embodiment, two or more buses 1502 may be used to perform different functions and / or may be used for redundancy. For example, a first bus 1502 may be used for collision avoidance functionality, and a second bus 1502 may be used for actuation control. In at least one embodiment, each bus 1502 may communicate with any component of vehicle 1500, and two or more buses 1502 may communicate with the same component. In at least one embodiment, each of any number of system-on-chips ("SoCs") 1504, each of one or more controllers 1536, and / or each computer within the vehicle may have access to the same input data (e.g., input from sensors in vehicle 1500) and may be connected to a common bus, such as a CAN bus.

[0204] In at least one embodiment, the vehicle 1500 may include one or more controllers 1536, such as those described herein with respect to Figure 15A In at least one embodiment, controller 1536 can be used for a variety of functions. In at least one embodiment, controller 1536 can be coupled to any of the various other components and systems of vehicle 1500 and can be used to control vehicle 1500, the artificial intelligence of vehicle 1500, infotainment, and / or other functions of vehicle 1500.

[0205] In at least one embodiment, the vehicle 1500 may include any number of SoCs 1504. Each of the SoCs 1504 may include, but is not limited to, a central processing unit ("CPU(s)") 1506, a graphics processing unit ("GPU(s")) 1508, one or more processors 1510, one or more caches 1512, one or more accelerators 1514, one or more data stores 1516, and / or other components and features not shown. In at least one embodiment, the one or more SoCs 1504 may be used to control the vehicle 1500 in various platforms and systems. For example, in at least one embodiment, the one or more SoCs 1504 may be combined in a system (e.g., a system of the vehicle 1500) with a high-definition ("HD") map 1522 that may be downloaded from one or more servers (e.g., a system of the vehicle 1500) via a network interface 1524. Figure 15C ) to obtain map refreshes and / or updates.

[0206] In at least one embodiment, one or more CPUs 1506 may include a CPU cluster or CPU complex (alternatively referred to herein as a "CCPLEX"). In at least one embodiment, one or more CPUs 1506 may include multiple cores and / or a level 2 ("L2") cache. For example, in at least one embodiment, one or more CPUs 1506 may include eight cores in a multi-processor configuration coupled to one another. In at least one embodiment, one or more CPUs 1506 may include four dual-core clusters, each with a dedicated L2 cache (e.g., a 2MB L2 cache). In at least one embodiment, one or more CPUs 1506 (e.g., CCPLEX) may be configured to support simultaneous cluster operations such that any combination of clusters of one or more CPUs 1506 may be active at any given time.

[0207] In at least one embodiment, one or more CPUs 1506 can implement power management functionality including, but not limited to, one or more of the following features: automatic clock gating of various hardware modules when idle to conserve dynamic power; clock gating of each core when the core is not actively executing instructions due to executing a wait for interrupt ("WFI") / wait for event ("WFE") instruction; each core can be independently powered; each core cluster can be independently clock gated when all cores are clock gated or power gated; and / or each core cluster can be independently power gated when all cores are power gated. In at least one embodiment, one or more CPUs 1506 can further implement an enhanced algorithm for managing power states, wherein allowed power states and expected wakeup times are specified, and hardware / microcode determines the optimal power state for the core, cluster, and CCPLEX input. In at least one embodiment, the processing core can support a simplified power state entry sequence in software, where the work is offloaded to the microcode.

[0208] In at least one embodiment, one or more GPUs 1508 may include an integrated GPU (or alternatively referred to herein as an "iGPU"). In at least one embodiment, one or more GPUs 1508 may be programmable and may be efficient for parallel workloads. In at least one embodiment, one or more GPUs 1508 may utilize an enhanced tensor instruction set. In one embodiment, one or more GPUs 1508 may include one or more streaming microprocessors, wherein each streaming microprocessor may include a level 1 ("L1") cache (e.g., an L1 cache having at least 96KB of storage capacity), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache having 512KB of storage capacity). In at least one embodiment, one or more GPUs 1508 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 1508 may utilize a computing application programming interface (API). In at least one embodiment, one or more GPUs 1508 may utilize one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA).

[0209] In at least one embodiment, one or more GPUs 1508 can be power-optimized for optimal performance in automotive and embedded use cases. For example, in one embodiment, one or more GPUs 1508 can be fabricated on fin field-effect transistors (“FinFETs”). In at least one embodiment, each streaming microprocessor can include multiple mixed-precision processing cores partitioned into multiple blocks. For example, but not limited to, 64 PF32 cores and 32 PF64 cores can be partitioned into four processing blocks. In at least one embodiment, each processing block can be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA Tensor Cores for deep learning matrix arithmetic, a level-0 (“L0”) instruction cache, a warp scheduler, a dispatch unit, and / or a 64KB register file. In at least one embodiment, the streaming microprocessor can include independent parallel integer and floating-point datapaths to provide efficient execution of workloads that mix compute and addressing operations. In at least one embodiment, the streaming microprocessor can include independent thread scheduling capabilities to enable finer-grained synchronization and collaboration between parallel threads. In at least one embodiment, a streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0210] In at least one embodiment, one or more GPUs 1508 may include high bandwidth memory ("HBM") and / or a 16GB HBM2 memory subsystem to provide a peak memory bandwidth of approximately 900 GB / s in some examples. In at least one embodiment, synchronous graphics random access memory ("SGRAM"), such as graphics double data rate type five synchronous random access memory ("GDDR5"), may be used in addition to or in lieu of HBM memory.

[0211] In at least one embodiment, the one or more GPUs 1508 may include unified memory technology. In at least one embodiment, address translation services ("ATS") support may be used to allow the one or more GPUs 1508 to directly access the one or more CPU 1506 page tables. In at least one embodiment, when the one or more GPU 1508 memory management units ("MMUs") experience a miss, an address translation request may be sent to the one or more CPUs 1506. In response, in at least one embodiment, the one or more CPUs 1506 may look up the virtual-to-physical mapping of the address in its page table and transmit the translation back to the one or more GPUs 1508. In at least one embodiment, unified memory technology may allow a single unified virtual address space to be used for memory for both the one or more CPUs 1506 and the one or more GPUs 1508, thereby simplifying programming the one or more GPUs 1508 and porting applications to the one or more GPUs 1508.

[0212] In at least one embodiment, one or more GPUs 1508 may include any number of access counters that can track the frequency with which one or more GPUs 1508 access the memory of other processors. In at least one embodiment, the one or more access counters can help ensure that memory pages are moved to the physical memory of the processor that accesses the page most frequently, thereby improving the efficiency of memory ranges shared between processors.

[0213] In at least one embodiment, one or more SoCs 1504 may include any number of caches 1512, including those described herein. For example, in at least one embodiment, one or more caches 1512 may include a level 3 ("L3") cache available to one or more CPUs 1506 and one or more GPUs 1508 (e.g., connected to CPUs 1506 and GPUs 1508). In at least one embodiment, one or more caches 1512 may include a write-back cache that can track the state of a line, for example, by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, the L3 cache may include 4MB or more, depending on the embodiment, although smaller cache sizes may be used.

[0214] In at least one embodiment, one or more SoCs 1504 may include one or more accelerators 1514 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, one or more SoCs 1504 may include a hardware acceleration cluster that may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4MB of SRAM) may enable the hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, the hardware acceleration cluster may be used to supplement one or more GPUs 1508 and offload some tasks of one or more GPUs 1508 (e.g., freeing up more cycles of one or more GPUs 1508 to perform other tasks). In at least one embodiment, one or more accelerators 1514 may be used for target workloads that are sufficiently stable to withstand acceleration testing (e.g., perception, convolutional neural networks (“CNNs”), recurrent neural networks (“RNNs”), etc.). In at least one embodiment, CNNs may include region-based or region-based convolutional neural networks (“RCNNs”) and fast RCNNs (e.g., as used for object detection) or other types of CNNs.

[0215] In at least one embodiment, one or more accelerators 1514 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators ("DLAs"). One or more DLAs may include, but are not limited to, one or more Tensor Processing Units ("TPUs"), which may be configured to provide an additional 10 trillion operations per second for deep learning applications and reasoning. In at least one embodiment, a TPU may be an accelerator configured and optimized to perform image processing functions (e.g., for CNN, RCNN, etc.). One or more DLAs may be further optimized for a specific set of neural network types and floating-point operations and reasoning. In at least one embodiment, the design of one or more DLAs may provide higher performance per millimeter than a typical general-purpose GPU, and generally significantly exceeds the performance of a CPU. In at least one embodiment, one or more TPUs may perform several functions, including single-instance convolution functions that support, for example, INT8, INT16, and FP16 data types for features and weights, as well as post-processor functions. In at least one embodiment, one or more DLAs can quickly and efficiently execute neural networks, particularly CNNs, on processed or unprocessed data for any of a variety of functions, including, for example, but not limited to: a CNN for object recognition and detection using data from a camera sensor; a CNN for distance estimation using data from a camera sensor; a CNN for emergency vehicle detection and identification and detection using data from a microphone 1596; a CNN for face recognition and vehicle owner recognition using data from a camera sensor; and / or a CNN for safety and / or security-related events.

[0216] In at least one embodiment, a DLA can perform any function of one or more GPUs 1508, and by using an inference accelerator, for example, a designer can target any function to either one or more DLAs or one or more GPUs 1508. For example, in at least one embodiment, a designer can focus CNN processing and floating-point operations on one or more DLAs and leave other functions to one or more GPUs 1508 and / or other one or more accelerators 1514.

[0217] In at least one embodiment, one or more accelerators 1514 (e.g., a hardware acceleration cluster) may include a programmable vision accelerator ("PVA"), which may be referred to herein alternatively as a computer vision accelerator. In at least one embodiment, one or more PVAs may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems ("ADAS") 1538, autonomous driving, augmented reality ("AR") applications, and / or virtual reality ("VR") applications. In at least one embodiment, one or more PVAs may strike a balance between performance and flexibility. For example, in at least one embodiment, each of the one or more PVAs may include, for example, but not limited to, any number of reduced instruction set computer ("RISC") cores, direct memory access ("DMA"), and / or any number of vector processors.

[0218] In at least one embodiment, the RISC core can interact with an image sensor (e.g., an image sensor of any camera described herein), an image signal processor, and the like. In at least one embodiment, each RISC core can include any amount of memory. In at least one embodiment, the RISC core can use any of a variety of protocols, depending on the embodiment. In at least one embodiment, the RISC core can execute a real-time operating system ("RTOS"). In at least one embodiment, the RISC core can be implemented using one or more integrated circuit devices, application specific integrated circuits ("ASICs"), and / or memory devices. For example, in at least one embodiment, the RISC core can include an instruction cache and / or tightly coupled RAM.

[0219] In at least one embodiment, the DMA can enable components of the PVA to access system memory independently of the one or more CPUs 1506. In at least one embodiment, the DMA can support any number of features for providing optimizations to the PVA, including, but not limited to, support for multi-dimensional addressing and / or circular addressing. In at least one embodiment, the DMA can support up to six or more dimensions of addressing, which can include, but are not limited to, block width, block height, block depth, horizontal block stride, vertical block stride, and / or depth stride.

[0220] In at least one embodiment, the vector processor can be a programmable processor that can be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA can include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core can include a processor subsystem, a DMA engine (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, the vector processing subsystem can serve as the main processing engine of the PVA and can include a vector processing unit ("VPU"), an instruction cache, and / or a vector memory (e.g., "VMEM"). In at least one embodiment, the VPU core can include a digital signal processor, such as a single instruction multiple data ("SIMD"), a very long instruction word ("VLIW") digital signal processor. In at least one embodiment, the combination of SIMD and VLIW can increase throughput and speed.

[0221] In at least one embodiment, each vector processor may include an instruction cache and may be coupled to a dedicated memory. As a result, in at least one embodiment, each vector processor may be configured to execute independently of the other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to exploit data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute the same computer vision algorithm, but on different regions of an image. In at least one embodiment, the vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on the same image, or even execute different algorithms on sequenced images or portions of images. In at least one embodiment, any number of PVAs may be included in the hardware acceleration cluster, and any number of vector processors may be included in each PVA, among other things. In at least one embodiment, the PVAs may include additional error correction code ("ECC") memory to enhance overall system security.

[0222] In at least one embodiment, one or more accelerators 1514 (e.g., a hardware acceleration cluster) may include an on-chip computer vision network and static random access memory ("SRAM") to provide high bandwidth, low latency SRAM to one or more accelerators 1514. In at least one embodiment, the on-chip memory may include at least 4MB of SRAM, including, for example, but not limited to, eight field-configurable memory blocks that can be accessed by both the PVA and the DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus ("APB") interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and the DLA may access the memory via a backbone network that provides high-speed access to the memory to the PVA and the DLA. In at least one embodiment, the backbone network may include an on-chip computer vision network that interconnects the PVA and the DLA to the memory (e.g., using APB).

[0223] In at least one embodiment, the on-chip computer vision network may include an interface that determines that both the PVA and DLA provide ready and valid signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for sending control signals / addresses / data, as well as burst-type communication for continuous data transmission. In at least one embodiment, the interface may comply with the International Organization for Standardization ("ISO") 26262 or International Electrotechnical Commission ("IEC") 61508 standards, although other standards and protocols may be used.

[0224] In at least one embodiment, one or more SoCs 1504 may include a real-time gaze tracking hardware accelerator. In at least one embodiment, the real-time gaze tracking hardware accelerator may be used to quickly and efficiently determine the position and range of objects (e.g., within a world model) to generate real-time visual simulations for use in RADAR signal interpretation, for sound propagation synthesis and / or analysis, for simulation of SONAR systems, for general wave propagation simulations, for comparison with LIDAR data for positioning and / or other functions, and / or for other uses.

[0225] In at least one embodiment, one or more accelerators 1514 (e.g., a hardware acceleration cluster) have a wide range of uses for autonomous driving. In at least one embodiment, the PVA can be a programmable vision accelerator that is used in key processing stages in ADAS and autonomous vehicles. In at least one embodiment, the capabilities of the PVA at low power and low latency are well matched to algorithmic domains that require predictable processing. In other words, the PVA excels at semi-intensive or intensive conventional computations, even on small data sets, which may require predictable runtimes with low latency and low power. In at least one embodiment, an autonomous vehicle, such as in vehicle 1500, may be designed to run classic computer vision algorithms because they can be efficient at object detection and integer math.

[0226] For example, according to at least one embodiment of the technology, PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm can be used in some examples, although this is not meant to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use dynamic estimation / stereo matching on the fly (e.g., structure from motion, pedestrian recognition, lane detection, etc.). In at least one embodiment, PVA can perform computer stereo vision functions on input from two monocular cameras.

[0227] In at least one embodiment, the PVA can be used to perform dense optical flow. For example, in at least one embodiment, the PVA can process raw RADAR data (e.g., using a 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, the PVA is used for time-of-flight depth processing, for example, by processing raw time-of-flight data to provide processed time-of-flight data.

[0228] In at least one embodiment, the DLA can be used to run any type of network to enhance control and driving safety, including, for example, but not limited to, a neural network that outputs a confidence score for each object detection. In at least one embodiment, the confidence score can be expressed or interpreted as a probability, or as providing a relative "weight" of each detection relative to other detections. In at least one embodiment, the confidence score enables the system to make further decisions about which detections should be considered true positive detections rather than false positive detections. In at least one embodiment, the system can set a threshold for the confidence score and only consider detections that exceed the threshold as true positive detections. In embodiments using an automatic emergency braking ("AEB") system, a false positive detection will cause the vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, a highly confident detection can be considered a trigger for AEB. In at least one embodiment, the DLA can run a neural network for regressing the confidence score. In at least one embodiment, the neural network may take as its input at least some subset of parameters, such as bounding box dimensions, a ground plane estimate obtained (e.g., from another subsystem), outputs of one or more IMU sensors 1566 associated with vehicle 1500 heading, distance, 3D position estimates of objects obtained from the neural network and / or other sensors (e.g., one or more LIDAR sensors 1564 or one or more RADAR sensors 1560), etc.

[0229] In at least one embodiment, one or more SoCs 1504 (e.g., a hardware acceleration cluster) may include one or more data stores 1516 (e.g., memory). In at least one embodiment, one or more data stores 1516 may be on-chip memory of one or more SoCs 1504 that may store neural networks to be executed on one or more GPUs 1508 and / or DLAs. In at least one embodiment, one or more data stores 1516 may have a capacity large enough to store multiple instances of a neural network for redundancy and safety. In at least one embodiment, one or more data stores 1512 may include an L2 or L3 cache.

[0230] In at least one embodiment, one or more SoCs 1504 may include any number of processors 1510 (e.g., embedded processors). In at least one embodiment, one or more processors 1510 may include a boot and power management processor, which may be a dedicated processor and subsystem to handle boot power and management functions and related security implementations. In at least one embodiment, the boot and power management processor may be part of the boot sequence of one or more SoCs 1504 and may provide runtime power management services. In at least one embodiment, the boot power and management processor may provide clock and voltage programming, assist in system low-power state transitions, manage one or more SoCs 1504 thermal and temperature sensors, and / or manage one or more SoCs 1504 power states. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and one or more SoCs 1504 may use the ring oscillator to detect the temperature of one or more CPUs 1506, one or more GPUs 1508, and / or one or more accelerators 1514. In at least one embodiment, if the temperature is determined to exceed a threshold, the boot and power management processor may enter a temperature fault routine and place one or more SoCs 1504 into a lower power consumption state and / or place the vehicle 1500 into a driver's safe parking pattern (e.g., bringing the vehicle 1500 to a safe stop).

[0231] In at least one embodiment, one or more processors 1510 may further include a set of embedded processors that can be used as an audio processing engine. In at least one embodiment, the audio processing engine can be an audio subsystem that can provide full hardware support for multi-channel audio through multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core that has a digital signal processor with dedicated RAM.

[0232] In at least one embodiment, one or more processors 1510 may further include an always-on processor engine. In at least one embodiment, the automatic processing engine may provide the necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, the processors on the always-on processor engine may include, but are not limited to, a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0233] In at least one embodiment, one or more processors 1510 may further include a safety cluster engine, which may include but is not limited to a dedicated processor subsystem for handling safety management of automotive applications. In at least one embodiment, the safety cluster engine may include but is not limited to two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.) and / or routing logic. In safety mode, in at least one embodiment, the two or more cores may operate in lockstep mode and may function as a single core with comparison logic to detect any differences between their operations. In at least one embodiment, one or more processors 1510 may further include a real-time camera engine, which may include but is not limited to a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, one or more processors 1510 may further include a high dynamic range signal processor, which may include but is not limited to an image signal processor, which is a hardware engine that is part of the camera processing pipeline.

[0234] In at least one embodiment, one or more processors 1510 may include a video image synthesizer, which may be a processing block (e.g., implemented on a microprocessor) that implements the video post-processing functions required by a video playback application to produce the final video, thereby generating the final image for the player window. In at least one embodiment, the video image synthesizer may perform lens distortion correction on one or more wide-angle cameras 1570, one or more surround cameras 1574, and / or one or more in-cabin monitoring camera sensors. In at least one embodiment, the in-cabin monitoring camera sensors are preferably monitored by a neural network running on another instance of SoC 1504, the neural network being configured to identify cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform, but is not limited to, lip reading to activate cellular service and place calls, dictate emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, or provide voice-activated web surfing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in autonomous mode, but are otherwise disabled.

[0235] In at least one embodiment, the video image compositor may include enhanced temporal noise reduction for simultaneous spatial and temporal noise reduction. For example, in at least one embodiment, where motion occurs in the video, the noise reduction appropriately weights the spatial information, thereby reducing the weight of information provided by adjacent frames. In at least one embodiment, where an image or portion of an image does not include motion, the temporal noise reduction performed by the video image compositor may use information from previous images to reduce noise in the current image.

[0236] In at least one embodiment, the video image compositor can also be configured to perform stereoscopic rectification on the input stereoscopic lens frames. In at least one embodiment, the video image compositor can also be used for user interface composition when using an operating system desktop, without requiring one or more GPUs 1508 to continuously render new surfaces. In at least one embodiment, when one or more GPUs 1508 are powered and actively performing 3D rendering, the video image compositor can be used to offload one or more GPUs 1508 to improve performance and responsiveness.

[0237] In at least one embodiment, one or more of the SoCs 1504 may further include a Mobile Industry Processor Interface ("MIPI") camera serial interface for receiving video and input from a camera, a high-speed interface, and / or a video input block that may be used for a camera and associated pixel input functionality. In at least one embodiment, one or more of the SoCs 1504 may further include an input / output controller that may be controlled by software and may be used to receive I / O signals that are not assigned to a specific role.

[0238] In at least one embodiment, one or more of the SoCs 1504 may further include a wide range of peripheral interfaces to enable communication with peripheral devices, audio encoders / decoders (“CODECs”), power management, and / or other devices. The one or more SoCs 1504 may be configured to process data from cameras (e.g., via Gigabit multimedia serial links and Ethernet connections), sensors (e.g., one or more LIDAR sensors 1564, one or more RADAR sensors 1560, etc., which may be connected via Ethernet), data from the bus 1502 (e.g., vehicle 1500 speed, steering wheel position, etc.), data from one or more GNSS sensors 1558 (e.g., via Ethernet or CAN bus connections), and the like. In at least one embodiment, one or more of the SoCs 1504 may further include dedicated high-performance mass storage controllers, which may include their own DMA engines and may be used to offload the one or more CPUs 1506 from routine data management tasks.

[0239] In at least one embodiment, one or more SoCs 1504 can be an end-to-end platform with a flexible architecture that spans automation levels 3-5, thereby providing a comprehensive functional safety architecture that leverages and effectively uses computer vision and ADAS technologies to achieve diversity and redundancy, providing a platform that can provide a flexible and reliable driving software stack and deep learning tools. In at least one embodiment, one or more SoCs 1504 can be faster, more reliable, and even more energy and space efficient than conventional systems. For example, in at least one embodiment, one or more accelerators 1514, when combined with one or more CPUs 1506, one or more GPUs 1508, and one or more data storage devices 1516, can provide a fast and efficient platform for Level 3-5 autonomous driving vehicles.

[0240] In at least one embodiment, computer vision algorithms can be executed on a CPU, which can be configured using a high-level programming language (e.g., the C programming language) to execute a variety of processing algorithms on a variety of visual data. However, in at least one embodiment, CPUs generally cannot meet the performance requirements of many computer vision applications, such as those related to execution time and power consumption. In at least one embodiment, many CPUs are unable to execute complex object detection algorithms in real time, which are used in in-vehicle ADAS applications and actual Level 3-5 autonomous driving vehicles.

[0241] The embodiments described herein allow for the execution of multiple neural networks simultaneously and / or sequentially, and for the results to be combined to achieve Level 3-5 autonomous driving functionality. For example, in at least one embodiment, a CNN executed on a DLA or a discrete GPU (e.g., one or more GPUs 1520) may include text and word recognition, thereby allowing the supercomputer to read and understand traffic signs, including signs for which the neural network has not been specifically trained. In at least one embodiment, the DLA may also include a neural network that can recognize, interpret, and provide semantic understanding of the signs and pass this semantic understanding to a path planning module running on the CPU Complex.

[0242] In at least one embodiment, for Level 3, 4, or 5 driving, multiple neural networks can be run simultaneously. For example, in at least one embodiment, a warning sign consisting of "Caution: flashing lights indicate icy conditions" along with connected lights can be interpreted independently or collectively by multiple neural networks. In at least one embodiment, the sign itself can be identified as a traffic sign by a first deployed neural network (e.g., a trained neural network), and the text "flashing lights indicate icy conditions" can be interpreted by a second deployed neural network, which notifies the vehicle's path planning software (preferably executing on a CPU Complex) that icy conditions exist when flashing lights are detected. In at least one embodiment, flashing lights can be identified by operating a third deployed neural network over multiple frames, notifying the vehicle's path planning software of the presence (or absence) of flashing lights. In at least one embodiment, all three neural networks can run simultaneously, for example within the DLA and / or on one or more GPUs 1508.

[0243] In at least one embodiment, a CNN for facial recognition and vehicle owner identification can use data from the camera sensor to identify the presence of an authorized driver and / or owner of the vehicle 1500. In at least one embodiment, an always-on sensor processor engine can be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and, in security mode, can be used to disable the vehicle when the owner leaves the vehicle. In this way, one or more SoCs 1504 provide protection against theft and / or carjacking.

[0244] In at least one embodiment, a CNN for emergency vehicle detection and identification can use data from microphone 1596 to detect and identify emergency vehicle sirens. In at least one embodiment, one or more SoCs 1504 use the CNN to classify environmental and urban sounds, as well as classify visual data. In at least one embodiment, the CNN running on the DLA is trained to identify the relative approaching speed of the emergency vehicle (e.g., by using the Doppler effect). In at least one embodiment, the CNN can also be trained to identify emergency vehicles for the area in which the vehicle is operating, as identified by one or more GNSS sensors 1558. In at least one embodiment, when operating in Europe, the CNN will seek to detect European sirens, while when operating in the United States, the CNN will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used with the assistance of one or more ultrasonic sensors 1562 to execute emergency vehicle safety routines, slow the vehicle, pull over, stop the vehicle, and / or idle the vehicle until the emergency vehicle passes.

[0245] In at least one embodiment, the vehicle 1500 may include one or more CPUs 1518 (e.g., one or more discrete CPUs or one or more dCPUs) that may be coupled to the one or more SoCs 1504 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, the one or more CPUs 1518 may include an X86 processor, such as one or more CPUs 1518. The one or more CPUs 1518 may be used to perform any of a variety of functions, including, for example, arbitrating potential inconsistent results between ADAS sensors and the one or more SoCs 1504, and / or monitoring the status and health of one or more controllers 1536 and / or an on-chip information system ("information SoC") 1530.

[0246] In at least one embodiment, the vehicle 1500 may include one or more GPUs 1520 (e.g., one or more discrete GPUs or one or more dGPUs) that may be coupled to the one or more SoCs 1504 via a high-speed interconnect (e.g., NVIDIA's NVLINK). In at least one embodiment, the one or more GPUs 1520 may provide additional artificial intelligence functionality, such as by executing redundant and / or different neural networks, and may be used to train and / or update the neural networks based at least in part on input from sensors of the vehicle 1500 (e.g., sensor data).

[0247] In at least one embodiment, vehicle 1500 may further include a network interface 1524, which may include, but is not limited to, one or more wireless antennas 1526 (e.g., one or more wireless antennas 1526 for different communication protocols, such as cellular antennas, Bluetooth antennas, etc.). In at least one embodiment, network interface 1524 may be used to enable wireless connectivity with other vehicles and / or computing devices (e.g., a passenger's client device) via the internet with a cloud (e.g., using a server and / or other network devices). In at least one embodiment, to communicate with other vehicles, a direct link and / or an indirect link (e.g., via a network and the internet) may be established between vehicle 1500 and the other vehicle. In at least one embodiment, a vehicle-to-vehicle communication link may be used to provide the direct link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 1500 with information about vehicles in its vicinity (e.g., vehicles in front of, to the sides of, and / or behind vehicle 1500). In at least one embodiment, this functionality may be part of the cooperative adaptive cruise control functionality of vehicle 1500.

[0248] In at least one embodiment, the network interface 1524 may include a SoC that provides modulation and demodulation functionality and enables one or more controllers 1536 to communicate over a wireless network. In at least one embodiment, the network interface 1524 may include a radio frequency front end for up-conversion from baseband to radio frequency and down-conversion from radio frequency to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed by well-known processes and / or using a superheterodyne process. In at least one embodiment, the radio frequency front end functionality may be provided by a separate chip. In at least one embodiment, the network interface may include wireless functionality for communicating over LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0249] In at least one embodiment, the vehicle 1500 may further include one or more data stores 1528, which may include, but are not limited to, off-chip (e.g., one or more SoCs 1504) storage. In at least one embodiment, the one or more data stores 1528 may include, but are not limited to, one or more storage elements including RAM, SRAM, dynamic random access memory ("DRAM"), video random access memory ("VRAM"), flash memory, a hard disk, and / or other components and / or devices that can store at least one bit of data.

[0250] In at least one embodiment, the vehicle 1500 may further include one or more GNSS sensors 1558 (e.g., GPS and / or assisted GPS sensors) to assist with mapping, perception, occupancy raster generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 1558 may be used, including, for example, but not limited to, GPS connected to a serial interface (e.g., RS-232) bridge using a USB connector with Ethernet.

[0251] In at least one embodiment, the vehicle 1500 may further include one or more RADAR sensors 1560. The one or more RADAR sensors 1560 may be used by the vehicle 1500 for remote vehicle detection, even in darkness and / or in adverse weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. The one or more RADAR sensors 1560 may use a CAN bus and / or bus 1502 (e.g., to transmit data generated by the one or more RADAR sensors 1560) for control and access to object tracking data, and in some examples may access an Ethernet channel to access raw data. In at least one embodiment, a variety of RADAR sensor types may be used. For example, but not limited to, one or more of the RADAR sensors 1560 may be suitable for front, rear, and side RADAR use. In at least one embodiment, the one or more RADAR sensors 1560 are pulsed Doppler RADAR sensors.

[0252] In at least one embodiment, one or more RADAR sensors 1560 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, short-range side coverage, and the like. In at least one embodiment, long-range RADAR can be used for adaptive cruise control functionality. In at least one embodiment, a long-range RADAR system can provide a wide field of view achieved through two or more independent scans (e.g., within a range of 250 meters). In at least one embodiment, one or more RADAR sensors 1560 can help distinguish between static and moving objects and can be used by the ADAS system 1538 for emergency brake assistance and forward collision warning. In at least one embodiment, the one or more sensors 1560 included in the long-range RADAR system may include, but are not limited to, a monostatic multimode RADAR with multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In at least one embodiment, having six antennas, with the four central antennas, can create a focused beam pattern designed to record the surroundings of the vehicle 1500 at higher speeds with minimal interference from traffic in adjacent lanes. In at least one embodiment, the additional two antennas can extend the field of view, allowing for quick detection of vehicles entering or leaving the vehicle's 1500 lane.

[0253] In at least one embodiment, as an example, a medium-range RADAR system may include, for example, a range of up to 160m (front) or 80m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, a short-range RADAR system may include, but is not limited to, any number of RADAR sensors 1560 designed to be mounted on both ends of the rear bumper. When mounted on both ends of the rear bumper, in at least one embodiment, the RADAR sensor system can generate two light beams that continuously monitor the rear of the vehicle and nearby blind spots. In at least one embodiment, the short-range RADAR system can be used in the ADAS system 1538 for blind spot detection and / or lane change assistance.

[0254] In at least one embodiment, the vehicle 1500 may further include one or more ultrasonic sensors 1562. In at least one embodiment, one or more ultrasonic sensors 1562, which may be positioned on the front, rear, and / or sides of the vehicle 1500, may be used for parking assistance and / or for creating and updating occupancy barriers. In at least one embodiment, a variety of ultrasonic sensors 1562 may be used, and different ultrasonic sensors 1562 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, the ultrasonic sensors 1562 may operate at an ASIL B functional safety level.

[0255] In at least one embodiment, the vehicle 1500 can include one or more LIDAR sensors 1564. The one or more LIDAR sensors 1564 can be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, the one or more LIDAR sensors 1564 can be functional safety level ASIL B. In at least one embodiment, the vehicle 1500 can include multiple (e.g., two, four, six, etc.) LIDAR sensors 1564 that can use Ethernet (e.g., provide data to a Gigabit Ethernet switch).

[0256] In at least one embodiment, one or more LIDAR sensors 1564 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, commercially available one or more LIDAR sensors 1564 may, for example, have an advertised range of approximately 100 meters, an accuracy of 2-3 cm, and support a 100 Mbps Ethernet connection. In at least one embodiment, one or more non-obtrusive LIDAR sensors 1564 may be used. In such an embodiment, one or more LIDAR sensors 1564 may be implemented as small devices embedded in the front, rear, sides, and / or corners of vehicle 1500. In at least one embodiment, one or more LIDAR sensors 1564 may provide a horizontal field of view of up to 120 degrees and a vertical field of view of 35 degrees, even for low-reflectivity objects, and a range of 200 meters. In at least one embodiment, the forward-facing one or more LIDAR sensors 1564 may be configured for a horizontal field of view between 45 and 135 degrees.

[0257] In at least one embodiment, LIDAR technology (such as 3D flash LIDAR) may also be used. 3D flash LIDAR uses a laser flash as a transmission source to illuminate approximately 200 meters around vehicle 1500. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receiver that records the laser pulse propagation time and the reflected light at each pixel, which in turn corresponds to the range from vehicle 1500 to the object. In at least one embodiment, flash LIDAR can enable the generation of a highly accurate and distortion-free image of the surrounding environment with each laser flash. In at least one embodiment, four flash LIDAR sensors can be deployed, one on each side of vehicle 1500. In at least one embodiment, the 3D flash LIDAR system includes, but is not limited to, a solid-state 3D line-of-sight array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device can use 5 nanosecond Class I (eye-safe) laser pulses per frame and can capture the reflected laser light in the form of a 3D range point cloud and co-registered intensity data.

[0258] In at least one embodiment, vehicle 1500 may also include one or more IMU sensors 1566. In at least one embodiment, one or more IMU sensors 1566 may be located at the center of the rear axle of vehicle 1500. In at least one embodiment, one or more IMU sensors 1566 may include, for example, but not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, one or more magnetic compasses, and / or other sensor types. In at least one embodiment, for example, in a six-axis application, one or more IMU sensors 1566 may include, but not limited to, accelerometers and gyroscopes. In at least one embodiment, for example, in a nine-axis application, one or more IMU sensors 1566 may include, but not limited to, accelerometers, gyroscopes, and magnetometers.

[0259] In at least one embodiment, one or more IMU sensors 1566 can be implemented as a miniature, high-performance GPS-aided inertial navigation system ("GPS / INS") that combines microelectromechanical system ("MEMS") inertial sensors, a high-sensitivity GPS receiver, and advanced Kalman filtering algorithms to provide estimates of position, velocity, and attitude; in at least one embodiment, one or more IMU sensors 1566 can enable vehicle 1500 to estimate heading without input from a magnetic sensor by directly observing and correlating velocity changes from GPS to one or more IMU sensors 1566. In at least one embodiment, one or more IMU sensors 1566 and one or more GNSS sensors 1558 can be combined in a single integrated unit.

[0260] In at least one embodiment, vehicle 1500 can include one or more microphones 1596 positioned within and / or around vehicle 1500. In at least one embodiment, one or more microphones 1596 can be used for emergency vehicle detection and identification, among other things.

[0261] In at least one embodiment, the vehicle 1500 may further include any number of camera types, including one or more stereo cameras 1568, one or more wide angle cameras 1570, one or more infrared cameras 1572, one or more surround cameras 1574, one or more long range cameras 1598, one or more mid range cameras 1576, and / or other camera types. In at least one embodiment, the cameras may be used to capture image data around the entire periphery of the vehicle 1500. In at least one embodiment, the type of camera used depends on the vehicle 1500. In at least one embodiment, any combination of camera types may be used to provide the necessary coverage around the vehicle 1500. In at least one embodiment, the number of cameras deployed may vary depending on the embodiment. For example, in at least one embodiment, the vehicle 1500 may include six cameras, seven cameras, ten cameras, twelve cameras, or another number of cameras. In at least one embodiment, the cameras may, by way of example but not limitation, support Gigabit Multimedia Serial Link ("GMSL") and / or Gigabit Ethernet. In at least one embodiment, the present disclosure previously referred to herein may provide a plurality of cameras. Figure 15A and Figure 15B Each camera can be described in more detail.

[0262] In at least one embodiment, vehicle 1500 may further include one or more vibration sensors 1542. In at least one embodiment, one or more vibration sensors 1542 may measure vibration of a component (e.g., an axle) of vehicle 1500. For example, in at least one embodiment, a change in vibration may indicate a change in the road surface. In at least one embodiment, when two or more vibration sensors 1542 are used, the difference between the vibrations may be used to determine friction or slippage in the road surface (e.g., when there is a vibration difference between a powered drive shaft and a freely rotating shaft).

[0263] In at least one embodiment, the vehicle 1500 may include an ADAS system 1538. The ADAS system 1538 may include, but is not limited to, an SoC. In at least one embodiment, the ADAS system 1538 may include, but is not limited to, any number of autonomous / adaptive / automatic cruise control ("ACC") systems, cooperative adaptive cruise control ("CACC") systems, forward collision warning ("FCW") systems, automatic emergency braking ("AEB") systems, lane departure warning ("LDW") systems, lane keeping assist ("LKA") systems, blind spot alert ("BSW") systems, rear cross traffic alert ("RCTW") systems, collision warning ("CW") systems, lane centering ("LC") systems, and / or other systems, features, and / or functions, and combinations thereof.

[0264] In at least one embodiment, the ACC system may utilize one or more RADAR sensors 1560, one or more LIDAR sensors 1564, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to the vehicle immediately ahead of the vehicle 1500 and automatically adjusts the speed of the vehicle 1500 to maintain a safe distance from the vehicle ahead. In at least one embodiment, the lateral ACC system performs distance keeping and recommends that the vehicle 1500 change lanes when necessary. In at least one embodiment, lateral ACC is associated with other ADAS applications, such as LC and CW.

[0265] In at least one embodiment, the CACC system uses information from other vehicles, which may be received from the other vehicles via a wireless link or indirectly via a network connection (e.g., via the Internet) via a network interface 1524 and / or one or more wireless antennas 1526. In at least one embodiment, the direct link may be provided by a vehicle-to-vehicle ("V2V") communication link, while the indirect link may be provided by an infrastructure-to-vehicle ("I2V") communication link. Typically, the V2V communication concept provides information about the vehicle immediately ahead (e.g., the vehicle immediately ahead of vehicle 1500 and in the same lane as it), while the I2V communication concept provides information about traffic further ahead. In at least one embodiment, the CACC system may include one or both of the I2V and V2V information sources. In at least one embodiment, given information about vehicles ahead of vehicle 1500, the CACC system may be more reliable and have the potential to improve the smoothness of traffic flow and reduce road congestion.

[0266] In at least one embodiment, the FCW system is designed to warn the driver of hazards so that the driver can take corrective action. In at least one embodiment, the FCW system uses a forward-facing camera and / or one or more RADAR sensors 1560, coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to driver feedback, such as a display, speaker, and / or vibration component. In at least one embodiment, the FCW system can provide warnings, such as in the form of audible and visual warnings, vibrations, and / or rapid braking pulses.

[0267] In at least one embodiment, an AEB system detects an impending forward collision with another vehicle or other object and can automatically apply the brakes if the driver does not take corrective action within specified time or distance parameters. In at least one embodiment, the AEB system can utilize one or more forward-facing cameras and / or one or more RADAR sensors 1560 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, the AEB system typically first warns the driver to take corrective action to avoid the collision, and, if the driver does not take corrective action, the AEB system can automatically apply the brakes to attempt to prevent or at least mitigate the effects of the predicted collision. In at least one embodiment, the AEB system can include technologies such as dynamic brake support and / or braking on impending collisions.

[0268] In at least one embodiment, the LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibrations, to alert the driver when vehicle 1500 crosses a lane marking. In at least one embodiment, the LDW system is inactive when the driver indicates an intentional lane departure, such as by activating a turn signal. In at least one embodiment, the LDW system may utilize a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to driver feedback such as a display, speaker, and / or vibration assembly. In at least one embodiment, a LKA system is a variation of the LDW system. If vehicle 1500 begins to leave its lane, the LKA system provides steering input or braking to correct vehicle 1500.

[0269] In at least one embodiment, the BSW system detects and warns the driver of vehicles in the car's blind spot. In at least one embodiment, the BSW system can provide visual, audible, and / or tactile alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system can provide additional warnings when the driver uses a turn signal. In at least one embodiment, the BSW system can use one or more rear-facing cameras and / or one or more RADAR sensors 1560 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to driver feedback, such as a display, speaker, and / or vibration component.

[0270] In at least one embodiment, the RCTW system can provide visual, audible, and / or tactile notifications when an object is detected outside the rear camera range while the vehicle 1500 is in reverse. In at least one embodiment, the RCTW system includes an AEB system to ensure application of vehicle brakes to avoid a collision. In at least one embodiment, the RCTW system can use one or more rear-facing RADAR sensors 1560 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to driver feedback such as a display, speaker, and / or vibration component.

[0271] In at least one embodiment, conventional ADAS systems can be prone to generating false positives, which can be annoying and distracting to the driver but are generally not catastrophic because conventional ADAS systems alert the driver and allow the driver to decide whether a safe condition truly exists and take appropriate action. In at least one embodiment, in the event of conflicting results, the vehicle 1500 itself decides whether to follow the results of the primary or secondary computer (e.g., the first controller 1536 or the second controller 1536). For example, in at least one embodiment, the ADAS system 1538 can be a backup and / or secondary computer that provides perception information to a backup computer rationality module. In at least one embodiment, the backup computer rationality monitor can run redundant software on hardware components to detect failures in perception and dynamic driving tasks. In at least one embodiment, the output from the ADAS system 1538 can be provided to a supervisory MCU. In at least one embodiment, if the outputs from the primary and secondary computers conflict, the supervisory MCU determines how to reconcile the conflict to ensure safe operation.

[0272] In at least one embodiment, the primary computer can be configured to provide a confidence score to the supervisory MCU to indicate the primary computer's confidence in the selected result. In at least one embodiment, if the confidence score exceeds a threshold, the supervisory MCU can follow the primary computer's instructions regardless of whether the secondary computer provides conflicting or inconsistent results. In at least one embodiment, if the confidence score does not meet the threshold, and if the primary and secondary computers indicate different results (e.g., a conflict), the supervisory MCU can arbitrate between the computers to determine the appropriate result.

[0273] In at least one embodiment, the supervisory MCU can be configured to run a neural network that is trained and configured to determine, based at least in part on outputs from the primary and secondary computers, conditions under which the secondary computer provides a false alarm. In at least one embodiment, the neural network in the supervisory MCU can learn when the output of the secondary computer can be trusted and when it cannot. For example, in at least one embodiment, when the secondary computer is a RADAR-based FCW system, the neural network in the supervisory MCU can learn when the FCW system identifies a metallic object that is not actually a danger, such as a drain grate or manhole cover, that would trigger an alarm. In at least one embodiment, when the secondary computer is a camera-based LDW system, the neural network in the supervisory MCU can learn to override the LDW when a cyclist or pedestrian is present and lane departure is actually the safest maneuver. In at least one embodiment, the supervisory MCU can include at least one of a DLA or a GPU suitable for running a neural network with associated memory. In at least one embodiment, the supervisory MCU can include and / or be included as a component of one or more SoCs 1504.

[0274] In at least one embodiment, the ADAS system 1538 may include an auxiliary computer that uses traditional computer vision rules to perform ADAS functions. In at least one embodiment, the auxiliary computer may use classical computer vision rules (if-then), and the presence of a neural network in the supervisory MCU may improve reliability, safety, and performance. For example, in at least one embodiment, the diverse implementations and intentional non-identity make the entire system more fault-tolerant, especially for failures caused by software (or software-hardware interface) functions. For example, in at least one embodiment, if there is a software vulnerability or bug in the software running on the main computer, and a different software code running on the auxiliary computer provides the same overall result, the supervisory MCU can be more confident that the overall result is correct and that the vulnerability in the software or hardware on the main computer did not cause a significant error.

[0275] In at least one embodiment, the output of the ADAS system 1538 can be input into the primary computer's perception module and / or the primary computer's dynamic driving task module. For example, in at least one embodiment, if the ADAS system 1538 indicates a forward collision warning due to an object directly ahead, the perception module can use this information when identifying the object. In at least one embodiment, as described herein, the secondary computer can have its own neural network that has been trained to reduce the risk of false positives.

[0276] In at least one embodiment, the vehicle 1500 may further include an infotainment SoC 1530 (e.g., an in-vehicle infotainment system (IVI)). Although shown and described as an SoC, in at least one embodiment, the infotainment system 1530 may not be an SoC and may include, but is not limited to, two or more discrete components. In at least one embodiment, the infotainment SoC 1530 may include, but is not limited to, a combination of hardware and software that can be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), phone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.), and / or information services (e.g., a navigation system, rear parking assist, radio data system, vehicle-related information such as fuel level, total distance covered, brake fuel level, oil level, door open / closed, air filter information, etc.) to the vehicle 1500. For example, the infotainment SoC 1530 may include a radio, a disk player, a navigation system, a video player, USB and Bluetooth connectivity, a car, an in-vehicle entertainment system, WiFi, steering wheel audio controls, hands-free voice control, a heads-up display ("HUD"), an HMI display 1534, a telematics device, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. In at least one embodiment, the infotainment SoC 1530 may be further configured to provide information (e.g., visual and / or auditory) to a user of the vehicle, such as information from an ADAS system 1538, autonomous driving information (such as planned vehicle maneuvers), trajectory, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0277] In at least one embodiment, the infotainment SoC 1530 can include any number and type of GPU functionality. In at least one embodiment, the infotainment SoC 1530 can communicate with other devices, systems, and / or components of the vehicle 1500 via a bus 1502 (e.g., a CAN bus, Ethernet, etc.). In at least one embodiment, the infotainment SoC 1530 can be coupled to a supervisory MCU so that the infotainment system's GPU can perform some autonomous driving functions in the event of a failure of the main controller 1536 (e.g., the vehicle 1500's main computer and / or backup computer). In at least one embodiment, the infotainment SoC 1530 can cause the vehicle 1500 to enter a driver-to-safety stop mode, as described herein.

[0278] In at least one embodiment, the vehicle 1500 may further include an instrument panel 1532 (e.g., a digital instrument panel, an electronic instrument panel, a digital instrument panel, etc.). In at least one embodiment, the instrument panel 1532 may include, but is not limited to, a controller and / or a supercomputer (e.g., a discrete controller or a supercomputer). In at least one embodiment, the instrument panel 1532 may include, but is not limited to, any number and combination of a set of instruments, such as a speedometer, fuel level, oil pressure, a tachometer, an odometer, a turn indicator, a gear position indicator, one or more seat belt warning lights, one or more parking brake warning lights, one or more engine check lights, supplemental restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between the infotainment SoC 1530 and the instrument panel 1532. In at least one embodiment, the instrument panel 1532 may be included as part of the infotainment SoC 1530, or vice versa.

[0279] In at least one embodiment, Figure 15C At least one component shown or described is used to implement the combination Figure 1-13 In at least one embodiment, in combination with the techniques and / or functions described herein, Figure 1-13 The described techniques and / or functionality may perform rate matching on data received from the vehicle 1500 for its autonomous operation and / or may be used by the vehicle 1500 to perform rate matching on data received in connection with its autonomous operation.

[0280] Figure 15D In accordance with at least one embodiment, a cloud-based server and Figure 15A15. In at least one embodiment, system 1577 may include, but is not limited to, one or more servers 1578, one or more networks 1590, and any number and type of vehicles, including vehicle 1500. One or more servers 1578 may include, but are not limited to, multiple GPUs 1584(A)-1584(H) (collectively referred to herein as GPUs 1584), PCIe switches 1582(A)-1582(D) (collectively referred to herein as PCIe switches 1582), and / or CPUs 1580(A)-1580(B) (collectively referred to herein as CPUs 1580). GPUs 1584, CPUs 1580, and PCIe switches 1582 may be interconnected with high-speed connections, such as, but not limited to, NVLink interfaces 1588 developed by NVIDIA and / or PCIe connections 1586. The GPUs 1584 are connected via NVLink and / or NVSwitch SoC, and the GPUs 1584 and PCIe switches 1582 are connected via a PCIe interconnect. In at least one embodiment, although eight GPUs 1584, two CPUs 1580, and four PCIe switches 1582 are shown, this is not intended to be limiting. In at least one embodiment, each of the one or more servers 1578 may include, but is not limited to, any number of GPUs 1584, CPUs 1580, and / or PCIe switches 1582 in any combination. For example, in at least one embodiment, one or more servers 1578 may each include eight, sixteen, thirty-two, and / or more GPUs 1584.

[0281] In at least one embodiment, one or more servers 1578 may receive image data representing an image from a vehicle via one or more networks 1590 that depicts unexpected or altered road conditions, such as recently begun road construction. In at least one embodiment, one or more servers 1578 may transmit a neural network 1592, an updated neural network 1592, and / or map information 1594, including, but not limited to, information regarding traffic and road conditions, to the vehicle via one or more networks 1590. In at least one embodiment, updates to the map information 1594 may include, but not limited to, updates to the HD map 1522, such as information regarding construction sites, potholes, service roads, flooding, and / or other obstacles. In at least one embodiment, the neural network 1592, the updated neural network 1592, and / or the map information 1594 may be generated by new training and / or experience represented by data received from any number of vehicles in the environment, and / or may be based at least on training performed at a data center (e.g., using one or more servers 1578 and / or other servers).

[0282] In at least one embodiment, one or more servers 1578 can be used to train a machine learning model (e.g., a neural network) based at least in part on the training data. In at least one embodiment, the training data can be generated by the vehicle and / or can be generated in simulation (e.g., using a game engine). In at least one embodiment, any amount of the training data is labeled (e.g., where the associated neural network benefits from supervised learning) and / or undergoes other pre-processing. In at least one embodiment, no amount of the training data is labeled and / or pre-processed (e.g., where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model can be used by the vehicle (e.g., transmitted to the vehicle via one or more networks 1590, and / or the machine learning model can be used by one or more servers 1578 to remotely monitor the vehicle.

[0283] In at least one embodiment, one or more servers 1578 can receive data from the vehicle and apply the data to the latest real-time neural networks for real-time intelligent reasoning. In at least one embodiment, one or more servers 1578 can include a deep learning supercomputer and / or a dedicated AI computer powered by one or more GPUs 1584, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, one or more servers 878 can include the deep learning infrastructure of a data center using CPU power.

[0284] In at least one embodiment, the deep learning infrastructure of one or more servers 1578 may be capable of rapid, real-time inference and may use this capability to assess and verify the health of the processors, software, and / or associated hardware in vehicle 1500. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from vehicle 1500, such as an image sequence and / or objects located within that image sequence by vehicle 1500 (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them to those identified by vehicle 1500, and if the results do not match and the deep learning infrastructure concludes that the AI ​​in vehicle 1500 is malfunctioning, one or more servers 1578 may send a signal to vehicle 1500 instructing the vehicle's 1500 fail-safe computer to take control, notify passengers, and complete a safe parking maneuver.

[0285] In at least one embodiment, one or more servers 1578 may include one or more GPUs 1584 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3). In at least one embodiment, the combination of GPU-powered servers and inference acceleration can enable real-time responses. In at least one embodiment, for example, in situations where performance is less critical, servers powered by CPUs, FPGAs, and other processors can be used for inference.

[0286] Computer system

[0287] Figure 16 16 is a block diagram illustrating an exemplary computer system according to at least one embodiment, which may be a system of interconnected devices and components, a system on a chip (SOC), or some combination thereof formed with a processor that may include execution units to execute instructions. In at least one embodiment, according to the present disclosure, such as the embodiments described herein, computer system 1600 may include, but is not limited to, components such as processor 1602, whose execution units include logic to execute algorithms for processing data. In at least one embodiment, computer system 1600 may include a processor such as the Intel® processor 1602 available from Intel Corporation of Santa Clara, California. Processor family, XeonTM, XScaleTM and / or StrongARMTM, Core TM or Nervana TM microprocessor, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 1600 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0288] Embodiments may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor ("DSP"), a system on a chip, a network computer ("NetPC"), a set-top box, a network hub, a wide area network ("WAN") switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0289] In at least one embodiment, computer system 1600 may include, but is not limited to, a processor 1602, which may include, but is not limited to, one or more execution units 1608 to perform machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, system 1600 is a single-processor desktop or server system, but in another embodiment, system 1600 may be a multi-processor system. In at least one embodiment, processor 1602 may include, but is not limited to, a complex instruction set computer ("CISC") microprocessor, a reduced instruction set computing ("RISC") microprocessor, a very long instruction word ("VLIW") microprocessor, a processor that implements a combination of instruction sets, or any other processor device, such as a digital signal processor. In at least one embodiment, processor 1602 may be coupled to a processor bus 1610, which may transmit data signals between processor 1602 and other components in computer system 1600.

[0290] In at least one embodiment, processor 1602 may include, but is not limited to, level 1 ("L1") internal cache memory ("cache") 1604. In at least one embodiment, processor 1602 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside external to processor 1602. Other embodiments may include a combination of internal and external caches, depending on the specific implementation and requirements. In at least one embodiment, register file 1606 may store different types of data in various registers, including, but not limited to, integer registers, floating point registers, status registers, and an instruction pointer register.

[0291] In at least one embodiment, an execution unit 1608, including but not limited to logic for performing integer and floating-point operations, is also located within processor 1602. In at least one embodiment, processor 1602 may also include a microcode ("ucode") read-only memory ("ROM") for storing microcode for certain macroinstructions. In at least one embodiment, execution unit 1608 may include logic for processing a packed instruction set 1609. In at least one embodiment, by including packed instruction set 1609 in the instruction set of a general-purpose processor, along with associated circuitry to execute the instructions, operations used by many multimedia applications may be performed using packed data within general-purpose processor 1602. In one or more embodiments, many multimedia applications may be accelerated and executed more efficiently by using the full width of the processor's data bus to perform operations on packed data, which may eliminate the need to transfer smaller units of data across the processor's data bus to perform one or more operations one data element at a time.

[0292] In at least one embodiment, execution unit 1608 may also be used in a microcontroller, an embedded processor, a graphics device, a DSP, and other types of logic circuits. In at least one embodiment, computer system 1600 may include, but is not limited to, memory 1620. In at least one embodiment, memory 1620 may be implemented as a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or other storage device. In at least one embodiment, memory 1620 may store instructions 1619 and / or data 1621 represented by data signals that may be executed by processor 1602.

[0293] In at least one embodiment, the system logic chip can be coupled to the processor bus 1610 and the memory 1620. In at least one embodiment, the system logic chip can include, but is not limited to, a memory controller hub ("MCH") 1616, and the processor 1602 can communicate with the MCH 1616 via the processor bus 1610. In at least one embodiment, the MCH 1616 can provide a high-bandwidth memory path 1618 to the memory 1620 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 1616 can initiate data signals between the processor 1602, the memory 1620, and other components in the computer system 1600, and bridge data signals between the processor bus 1610, the memory 1620, and the system I / O 1622. In at least one embodiment, the system logic chip can provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1616 may be coupled to the memory 1620 via a high-bandwidth memory path 1618 , and the graphics / video card 1612 may be coupled to the MCH 1616 via an Accelerated Graphics Port (“AGP”) interconnect 1614 .

[0294] In at least one embodiment, computer system 1600 may use system I / O 1622, which is a proprietary hub interface bus, to couple MCH 1616 to I / O controller hub ("ICH") 1630. In at least one embodiment, ICH 1630 may provide direct connection to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus used to connect peripheral devices to memory 1620, chipset, and processor 1602. Examples may include, but are not limited to, an audio controller 1629, a firmware hub ("Flash BIOS") 1628, a wireless transceiver 1626, data storage 1624, a traditional I / O controller 1623 including a user input and keyboard interface, a serial expansion port 1627 (e.g., a universal serial bus (USB)), and a network controller 1634. In at least one embodiment, data storage 1624 may include a hard drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0295] In at least one embodiment, Figure 16 The system is shown as comprising interconnected hardware devices or "chips", while in other embodiments, Figure 16 A system on a chip (SoC) may be shown. In at least one embodiment, Figure 16The devices shown in can be interconnected with a proprietary interconnect, a standardized interconnect (eg, PCIe), or some combination thereof. In at least one embodiment, one or more components of system 1600 are interconnected using a Compute Express Link (CXL) interconnect.

[0296] In at least one embodiment, Figure 16 At least one component shown or described is used to implement the combination Figure 1-13 The techniques and / or functions described herein are described herein. In at least one embodiment, at least one of processor 1602 and graphics card 1612 is configured to perform rate matching. In at least one embodiment, rate matching includes enabling 5G New Radio signal information to be selected in parallel using parameters based at least in part on a 5G standard. In at least one embodiment, at least one of processor 1602 and graphics card 1612 is configured to perform at least one aspect described with respect to rate matching 114, example process 300, data flow 400, example process 500, example process 600, example process 900, graph 1100, example process 1200, example process 1300, algorithm 1 described in conjunction with at least step 1314 of example process 1300, algorithm 2 described in conjunction with at least step 1316 of example process 1300, and / or algorithm 3 described in conjunction with at least step 1320 of example process 1300. In at least one embodiment, processor 1602 executes a kernel launch function that passes parameters to at least one kernel on graphics card 1612 that performs rate matching as described with reference to FIGs. 1-13.

[0297] Figure 17 1 is a block diagram illustrating an electronic device 1700 for utilizing a processor 1710 in accordance with at least one embodiment. In at least one embodiment, the electronic device 1700 may be, for example, but not limited to, a notebook computer, a tower server, a rack server, a blade server, a laptop computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0298] In at least one embodiment, system 1700 may include, but is not limited to, a processor 1710 communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. In at least one embodiment, processor 1710 is coupled using a bus or interface, such as an I2C bus, a system management bus ("SMBus"), a low pin count (LPC) bus, a serial peripheral interface ("SPI"), a high-definition audio ("HDA") bus, a serial advanced technology attachment ("SATA") bus, a universal serial bus ("USB") (versions 1, 2, 3, etc.), or a universal asynchronous receiver / transmitter ("UART") bus. In at least one embodiment, Figure 17shows a system comprising interconnected hardware devices or "chips", while in other embodiments, Figure 17 An exemplary system on a chip (SoC) may be shown. In at least one embodiment, Figure 17 The devices shown in can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 17 One or more components of the system are interconnected using Compute Express Link (CXL) interconnect lines.

[0299] In at least one embodiment, Figure 17 It may include a display 1724, a touch screen 1725, a touchpad 1730, a near field communication unit (“NFC”) 1745, a sensor hub 1740, a thermal sensor 1746, a fast chipset (“EC”) 1735, a trusted platform module (“TPM”) 1738, a BIOS / firmware / flash memory (“BIOS, FW Flash”) 1722, a DSP 1760, a drive “SSD or HDD” 1720 (e.g., a solid state disk (“SSD”) or a hard disk drive (“HDD”)), a wireless local area network unit (“WLAN”) 1750, a Bluetooth unit 1752, a wireless wide area network unit (“WWAN”) 1756, a global positioning system (GPS) 1755, a camera (“USB 3.0 camera”) 1754 (e.g., a USB 3.0 camera), or a low power double data rate (“LPDDR”) memory unit (“LPDDR3”) 1715 implemented with, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0300] In at least one embodiment, other components may be communicatively coupled to processor 1710 via the components described above. In at least one embodiment, accelerometer 1741, ambient light sensor (“ALS”) 1742, compass 1743, and gyroscope 1744 may be communicatively coupled to sensor hub 1740. In at least one embodiment, thermal sensor 1739, fan 1737, keyboard 1746, and touchpad 1730 may be communicatively coupled to EC 1735. In at least one embodiment, speaker 1763, earphone 1764, and microphone (“mic”) 1765 may be communicatively coupled to audio unit (“audio codec and class-D amplifier”) 1764, which in turn may be communicatively coupled to DSP 1760. In at least one embodiment, audio unit 1764 may include, for example, but not limited to, an audio codec / decoder (“codec”) and a class-D amplifier. In at least one embodiment, SIM card (“SIM”) 1757 may be communicatively coupled to WWAN unit 1756. In at least one embodiment, components such as the WLAN unit 1750 and the Bluetooth unit 1752 and the WWAN unit 1756 may be implemented as a next generation form factor (NGFF).

[0301] In at least one embodiment, Figure 17 At least one component shown or described is used to implement the combination Figure 1-13 In at least one embodiment, at least one of processors 1710 is configured to perform rate matching. In at least one embodiment, rate matching includes causing 5G new radio signal information to be selected in parallel using parameters based at least in part on the 5G standard. In at least one embodiment, processor 1710 is configured to perform at least one aspect described with respect to rate matching 114, example process 300, data flow 400, example process 500, example process 600, example process 900, chart 1100, example process 1200, example process 1300, algorithm 1 described at least in conjunction with step 1314 of example process 1300, algorithm 2 described at least in conjunction with step 1316 of example process 1300, and / or algorithm 3 described at least in conjunction with step 1320 of example process 1300.

[0302] Figure 18 A computer system 1800 is shown in accordance with at least one embodiment. In at least one embodiment, the computer system 1800 is configured to implement the various processes and methods described throughout this disclosure.

[0303] In at least one embodiment, computer system 1800 includes, but is not limited to, at least one central processing unit ("CPU") 1802 connected to a communication bus 1810 implemented using any suitable protocol, such as PCI ("Peripheral Component Interconnect"), Peripheral Component Interconnect Express ("PCI-Express"), AGP ("Accelerated Graphics Port"), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, computer system 1800 includes, but is not limited to, main memory 1804 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data may be stored in main memory 1804 in the form of random access memory ("RAM"). In at least one embodiment, a network interface subsystem ("network interface") 1822 provides an interface to other computing devices and networks for receiving data from computer system 1800 and transmitting data to other systems.

[0304] In at least one embodiment, computer system 1800 includes, but is not limited to, input device 1808, parallel processing system 1812, and display device 1806, which can be implemented using conventional cathode ray tubes ("CRTs"), liquid crystal displays ("LCDs"), light emitting diodes ("LEDs"), plasma displays, or other suitable display technologies. In at least one embodiment, user input is received from input device 1808 (such as a keyboard, mouse, touchpad, microphone, etc.). In at least one embodiment, each of the aforementioned modules can be located on a single semiconductor platform to form a processing system.

[0305] In at least one embodiment, Figure 18 At least one component shown or described is used to implement the combination Figure 1-13Techniques and / or functions described herein. In at least one embodiment, at least one of parallel processing system 1812 and CPU 1802 is used to perform rate matching. In at least one embodiment, rate matching includes causing 5G new radio signal information to be selected in parallel using parameters based at least in part on the 5G standard. In at least one embodiment, at least one of parallel processing system 1812 and CPU 1802 is used to perform at least one aspect described with respect to rate matching 114, example process 300, data flow 400, example process 500, example process 600, example process 900, chart 1100, example process 1200, example process 1300, algorithm one described at least in conjunction with step 1314 of example process 1300, algorithm two described at least in conjunction with step 1316 of example process 1300, and / or algorithm three described at least in conjunction with step 1320 of example process 1300. In at least one embodiment, CPU 1802 executes a kernel launch function that passes parameters to the kernel that executes the kernel in conjunction with Figure 1-13 Describes rate matching for at least one core on PPU 1814.

[0306] Figure 19 A computer system 1900 is shown in accordance with at least one embodiment. In at least one embodiment, computer system 1900 includes, but is not limited to, a computer 1910 and a USB stick 1920. In at least one embodiment, computer 1910 may include, but is not limited to, any number and type of processors (not shown) and memory (not shown). In at least one embodiment, computer 1910 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

[0307] In at least one embodiment, USB stick 1920 includes, but is not limited to, a processing unit 1930, a USB interface 1940, and USB interface logic 1950. In at least one embodiment, processing unit 1930 can be any instruction execution system, device, or apparatus capable of executing instructions. In at least one embodiment, processing unit 1930 can include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, processing core 1930 comprises an application-specific integrated circuit ("ASIC") that is optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, processing core 1930 is a tensor processing unit ("TPC") that is optimized to perform machine learning inference operations. In at least one embodiment, processing core 1930 is a vision processing unit ("VPU") that is optimized to perform machine vision and machine learning inference operations.

[0308] In at least one embodiment, USB interface 1940 can be any type of USB connector or USB receptacle. For example, in at least one embodiment, USB interface 1940 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, USB interface 1940 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 1950 can include any number and type of logic that enables processing unit 1930 to connect to a device (e.g., computer 1910) via USB connector 1940.

[0309] In at least one embodiment, Figure 19 At least one component shown or described is used to implement the combination Figure 1-13 The techniques and / or functions described herein are described. In at least one embodiment, computer 1910 is configured to perform rate matching. In at least one embodiment, rate matching includes causing 5G new radio signal information to be selected in parallel using parameters based at least in part on the 5G standard. In at least one embodiment, computer 1910 is configured to perform at least one aspect described with respect to rate matching 114, example process 300, data flow 400, example process 500, example process 600, example process 900, chart 1100, example process 1200, example process 1300, algorithm 1 described at least in conjunction with step 1314 of example process 1300, algorithm 2 described at least in conjunction with step 1316 of example process 1300, and / or algorithm 3 described at least in conjunction with step 1320 of example process 1300.

[0310] Figure 20A An exemplary architecture is shown in which multiple GPUs 2010-2013 are communicatively coupled to multiple multi-core processors 2005-2006 via high-speed links 2040-2043 (e.g., buses / point-to-point interconnects, etc.). In one embodiment, high-speed links 2040-2043 support communication throughput of 4 GB / s, 30 GB / s, 80 GB / s, or higher. Various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0.

[0311] Furthermore, in one embodiment, two or more GPUs 2010-2013 are interconnected via high-speed links 2029-2030, which can be implemented using the same or different protocols / links as used for high-speed links 2040-2043. Similarly, two or more multi-core processors 2005-2006 can be connected via high-speed link 2028, which can be a symmetric multiprocessor (SMP) bus running at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, the same protocol / links can be used (e.g., via a common interconnect fabric) to accomplish this. Figure 20A All communications between the various system components shown in .

[0312] In one embodiment, each multi-core processor 2005-2006 is communicatively coupled to processor memory 2001-2002 via memory interconnects 2026-2027, respectively, and each GPU 2010-2013 is communicatively coupled to GPU memory 2020-2023 via GPU memory interconnects 2050-2053, respectively. Memory interconnects 2026-2027 and 2050-2053 can utilize the same or different memory access technologies. By way of example and not limitation, processor memory 2001-2002 and GPU memory 2020-2023 can be volatile memory, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or can be non-volatile memory, such as 3D XPoint or Nano-Ram. In one embodiment, some portion of the processor memory 2001-2002 may be volatile memory, while another portion may be non-volatile memory (eg, using a two-level memory (2LM) hierarchy).

[0313] As described herein, although the various processors 2005-2006 and GPUs 2010-2013 may each be physically coupled to a specific memory 2001-2002, 2020-2023, a unified memory architecture may be implemented in which the same virtual system address space (also referred to as an "effective address" space) is distributed across the various physical memories. For example, the processor memories 2001-2002 may each contain 64GB of system memory address space, and the GPU memories 2020-2023 may each contain 32GB of system memory address space (resulting in a total addressable memory size of 256GB in this example).

[0314] Figure 20B2046. Additional details are shown for the interconnection between the multi-core processor 2007 and the graphics acceleration module 2046 according to an exemplary embodiment. The graphics acceleration module 2046 may include one or more GPU chips integrated on a line card that is coupled to the processor 2007 via the high-speed link 2040. Alternatively, the graphics acceleration module 2046 may be integrated on the same package or chip as the processor 2007.

[0315] In at least one embodiment, the illustrated processor 2007 includes a plurality of cores 2060A-2060D, each having a translation lookaside buffer 2061A-2061D and one or more caches 2062A-2062D. In at least one embodiment, the cores 2060A-2060D may include various other components, not shown, for executing instructions and processing data. In at least one embodiment, the caches 2062A-2062D may include level 1 (L1) and level 2 (L2) caches. In addition, one or more shared caches 2056 may be included in the caches 2062A-2062D and shared by each group of cores 2060A-2060D. For example, one embodiment of the processor 2007 includes 24 cores, each having its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. The processor 2007 and the graphics acceleration module 2046 are connected to the system memory 2014, which may include Figure 20A Processor memory 2001-2002 in.

[0316] Coherence is maintained for data and instructions stored in the various caches 2062A-2062D, 2056 and system memory 2014 via inter-core communication over the coherence bus 2064. For example, each cache may have cache coherence logic / circuitry associated therewith to communicate over the coherence bus 2064 in response to detecting a read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented over the coherence bus 2064 to snoop cache accesses.

[0317] In one embodiment, proxy circuitry 2025 communicatively couples graphics acceleration module 2046 to coherence bus 2064, thereby allowing graphics acceleration module 2046 to participate in a cache coherence protocol as a peer of cores 2060A-2060D. In particular, in at least one embodiment, interface 2035 provides connectivity to proxy circuitry 2025 via high-speed link 2040 (e.g., a PCIe bus, NVLink, etc.), and interface 2037 connects graphics acceleration module 2046 to link 2040.

[0318] In one implementation, the accelerator integrated circuit 2036 provides cache management, memory access, context management, and interrupt management services on behalf of the multiple graphics processing engines 2031, 2032, N of the graphics acceleration module. The graphics processing engines 2031, 2032, N may each comprise a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 2031, 2032, N may selectively comprise different types of graphics processing engines within the GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blur engine. In at least one embodiment, the graphics acceleration module 2046 may be a GPU having multiple graphics processing engines 2031-2032, N, or the graphics processing engines 2031-2032, N may be individual GPUs integrated into a common package, line card, or chip.

[0319] In one embodiment, the accelerator integrated circuit 2036 includes a memory management unit (MMU) 2039 for performing various memory management functions, such as virtual-to-physical memory translation (also known as effective-to-real memory translation), and a memory access protocol for accessing system memory 2014. The MMU 2039 may also include a translation lookaside buffer ("TLB") (not shown) for caching virtual / effective-to-physical / real address translations. In one implementation, cache 2038 may store commands and data for efficient access by graphics processing engines 2031-2032, N. In at least one embodiment, data stored in cache 2038 and graphics memory 2033-2034, M is kept consistent with core caches 2062A-2062D, 2056, and system memory 2014. As previously described, this task may be accomplished via proxy circuitry 2025 acting on behalf of cache 2038 and graphics memory 2033-2034, M (e.g., sending updates related to modifications / accesses of cache lines on processor caches 2062A-2062D, 2056 to cache 2038 and receiving updates from cache 2038).

[0320] A set of registers 2045 stores context data for threads executed by graphics processing engines 2031-2032, N, and context management circuitry 2048 manages thread contexts. For example, context management circuitry 2048 can perform save and restore operations to save and restore the context of various threads during context switches (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, context management circuitry 2048 can store current register values ​​to a designated area in memory (e.g., identified by a context pointer) upon context switching. The register values ​​can then be restored upon returning to context. In one embodiment, interrupt management circuitry 2047 receives and processes interrupts received from system devices.

[0321] In one implementation, the MMU 2039 converts virtual / effective addresses from the graphics processing engine 2031 into real / physical addresses in the system memory 2014. One embodiment of the accelerator integrated circuit 2036 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 2046 and / or other accelerator devices. The graphics accelerator module 2046 can be dedicated to a single application executing on the processor 2007, or can be shared among multiple applications. In one embodiment, a virtualized graphics execution environment is presented in which the resources of the graphics processing engines 2031-2032, N are shared with multiple applications or virtual machines (VMs). In at least one embodiment, the resources can be subdivided into "slices" that are allocated to different VMs and / or applications based on processing requirements and priorities associated with the VMs and / or applications.

[0322] In at least one embodiment, the accelerator integrated circuit 2036 acts as a bridge to the system for the graphics acceleration module 2046 and provides address translation and system memory caching services. In addition, the accelerator integrated circuit 2036 can provide virtualization facilities for the host processor to manage virtualization, interrupts, and memory management for the graphics processing engines 2031-2032.

[0323] Because the hardware resources of graphics processing engines 2031-2032, N are explicitly mapped into the real address space seen by host processor 2007, any host processor can directly address these resources using effective address values. In at least one embodiment, one function of accelerator integrated circuit 2036 is to physically separate graphics processing engines 2031-2032, N so that they appear as independent units to the system.

[0324] In at least one embodiment, one or more graphics memories 2033-2034, M are respectively coupled to each graphics processing engine 2031-2032, N. Graphics memories 2033-2034, M store instructions and data, which are processed by each graphics processing engine 2031-2032, N. Graphics memories 2033-2034, M can be volatile memory, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memory, such as 3D XPoint or Nano-Ram.

[0325] In one embodiment, to reduce data traffic on link 2040, a biasing technique can be used to ensure that the data stored in graphics memory 2033-2034, M is the data most frequently used by graphics processing engines 2031-2032, N, and preferably not used (at least not frequently) by cores 2060A-2060D. Similarly, in at least one embodiment, the biasing mechanism attempts to keep data needed by the cores (and preferably not graphics processing engines 2031-2032, N) in the cores' caches 2062A-2062D, 2056 and system memory 2014.

[0326] Figure 20C Another exemplary embodiment is shown in which an accelerator integrated circuit 2036 is integrated into the processor 2007. In this embodiment, the graphics processing engines 2031-2032, N communicate directly with the accelerator integrated circuit 2036 via the interface 2037 and the interface 2035 (which may also utilize any form of bus or interface protocol) through the high-speed link 2040. The accelerator integrated circuit 2036 can perform operations related to the Figure 20B The operations described above are identical to those described above. However, due to its close proximity to the coherence bus 2064 and caches 2062A-2062D, 2056, higher throughput is possible. One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which can include a programming model controlled by the accelerator integrated circuit 2036 and a programming model controlled by the graphics acceleration module 2046.

[0327] In at least one embodiment, graphics processing engines 2031-2032, N are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel other application requests to graphics processing engines 2031-2032, N, thereby providing virtualization within a VM / partition.

[0328] In at least one embodiment, graphics processing engines 2031-2032,N can be shared by multiple VM / application partitions. In at least one embodiment, this sharing model can utilize a hypervisor to virtualize graphics processing engines 2031-2032,N, allowing each operating system to access them. For a single-partition system without a hypervisor, the operating system owns graphics processing engines 2031-2032,N. In at least one embodiment, the operating system can virtualize graphics processing engines 2031-2032,N to provide access to each process or application.

[0329] In at least one embodiment, the graphics acceleration module 2046 or individual graphics processing engines 2031-2032,N use a process handle to select a process element. In one embodiment, the process element is stored in the system memory 2014 and can be addressed using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle can be an implementation-specific value that is provided to the host process when registering its context with the graphics processing engine 2031-2032,N (i.e., calling system software to add the process element to the process element linked list). In at least one embodiment, the lower 16 bits of the process handle can be the offset of the process element in the process element linked list.

[0330] Figure 20D An exemplary accelerator integrated slice 2090 is shown. As used herein, a "slice" comprises a designated portion of the processing resources of an accelerator integrated circuit 2036. An application is an effective address space 2082 in system memory 2014 that stores process elements 2083. In one embodiment, process elements 2083 are stored in response to a GPU call 2081 from an application 2080 executing on a processor 2007. Process elements 2083 contain the process state of the corresponding application 2080. A work descriptor (WD) 2084 contained in process element 2083 may be a single job requested by the application, or may contain a pointer to a job queue. In at least one embodiment, WD 2084 is a pointer to a job request queue in the application's address space 2082.

[0331] The graphics acceleration module 2046 and / or the individual graphics processing engines 2031-2032, N can be shared by all processes or a subset of processes in the system. In at least one embodiment, an infrastructure for setting process state and sending WD 2084 to the graphics acceleration module 2046 to start a job in a virtualized environment can be included.

[0332] In at least one embodiment, a dedicated process programming model is implementation-specific. In this model, a single process owns a graphics acceleration module 2046 or an individual graphics processing engine 2031. Since the hypervisor initializes the accelerator integrated circuit for the owned partition when the graphics acceleration module 2046 is owned by a single process, the operating system initializes the accelerator integrated circuit 2036 for the owned process when the graphics acceleration module 2046 is assigned.

[0333] In operation, the WD fetch unit 2091 in the accelerator integrated slice 2090 fetches the next WD 2084, which includes an indication of work to be completed by one or more graphics processing engines of the graphics acceleration module 2046. Data from the WD 2084 can be stored in registers 2045 and used by the MMU 2039, interrupt management circuitry 2047, and / or context management circuitry 2048, as shown. For example, one embodiment of the MMU 2039 includes segment / page roaming circuitry for accessing segment / page tables 2086 within the OS virtual address space 2085. The interrupt management circuitry 2047 can process interrupt events 2092 received from the graphics acceleration module 2046. When executing graphics operations, effective addresses 2093 generated by the graphics processing engines 2031-2032, N are converted into real addresses by the MMU 2039.

[0334] In one embodiment, the same set of registers 2045 is replicated for each graphics processing engine 2031-2032, N, and / or graphics acceleration module 2046, and the registers 2045 can be initialized by the hypervisor or operating system. Each of these replicated registers can be included in the accelerator integration slice 2090. Example registers that can be initialized by the hypervisor are shown in Table 1.

[0335]

[0336] Example registers that may be initialized by the operating system are shown in Table 2.

[0337]

[0338] In one embodiment, each WD 2084 is specific to a particular graphics acceleration module 2046 and / or graphics processing engine 2031-2032, N. It contains all the information needed by the graphics processing engine 2031-2032, N to complete the work, or it can be a pointer to a memory location where the application has set up a command queue for the work to be done.

[0339] Figure 20E2096 , which virtualizes the graphics acceleration module engine for the operating system 2095 .

[0340] In at least one embodiment, the shared programming model allows all processes or a subset of processes from all partitions or a subset of partitions in the system to use the graphics acceleration module 2046. There are two programming models where the graphics acceleration module 2046 is shared by multiple processes and partitions: time-sliced ​​sharing and graphics-directed sharing.

[0341] In this model, the hypervisor 2096 owns the graphics acceleration module 2046 and makes its functionality available to all operating systems 2095. For the graphics acceleration module 2046 to support virtualization through the hypervisor 2096, the graphics acceleration module 2046 may adhere to the following: (1) the application's job requests must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 2046 must provide a context save and restore mechanism, (2) the graphics acceleration module 2046 guarantees that the application's job requests are completed within a specified amount of time, including any transition errors, or the graphics acceleration module 2046 provides the ability to preempt job processing, and (3) fairness between graphics acceleration module 2046 processes must be ensured when operating in a directed shared programming model.

[0342] In at least one embodiment, an application 2080 is required to make an operating system 2095 system call using a graphics acceleration module 2046 type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore region pointer (CSRP). In at least one embodiment, the graphics acceleration module 2046 type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module 2046 type can be a system-specific value. In at least one embodiment, the WD is formatted specifically for the graphics acceleration module 2046 and can take the form of a graphics acceleration module 2046 command, an effective address pointer to a user-defined structure, an effective address pointer to a command queue, or any other data structure describing work to be performed by the graphics acceleration module 2046. In one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to that of an application setting the AMR. If the implementation of the accelerator integrated circuit 2036 and graphics acceleration module 2046 does not support the User Authority Mask Override Register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. Hypervisor 2096 can optionally apply the current privilege mask overwrite register (AMOR) value before placing the AMR into process element 2083. In at least one embodiment, CSRP is one of registers 2045 that contains the effective address of an area in the application's address space 2082 for graphics acceleration module 2046 to save and restore context state. This pointer is optional if state does not need to be saved between jobs or when a job is preempted. In at least one embodiment, the context save / restore area can be fixed system memory.

[0343] Upon receiving the system call, the operating system 2095 may verify that the application 2080 has been registered and granted permission to use the graphics acceleration module 2046. The operating system 2095 then calls the hypervisor 2096 using the information shown in Table 3.

[0344]

[0345] Upon receiving the hypervisor call, the hypervisor 2096 verifies that the operating system 2095 has registered and been granted permission to use the graphics acceleration module 2046. The hypervisor 2096 then places the process element 2083 into a linked list of process elements of the corresponding graphics acceleration module 2046 type. The process element may include the information shown in Table 4.

[0346]

[0347] In at least one embodiment, the hypervisor initializes the plurality of accelerator integrated slice 2090 registers 2045 .

[0348] like Figure 20F As shown, in at least one embodiment, a unified memory is used that is addressable via a common virtual memory address space for accessing physical processor memories 2001-2002 and GPU memories 2020-2023. In this implementation, operations executed on GPUs 2010-2013 utilize the same virtual / effective memory address space to access processor memories 2001-2002, and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 2001, a second portion is allocated to second processor memory 2002, a third portion is allocated to GPU memory 2020, and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memories 2001-2002 and GPU memories 2020-2023, thereby allowing any processor or GPU to access the memory using a virtual address mapped to any physical memory.

[0349] In one embodiment, bias / coherency management circuitry 2094A-2094E within one or more MMUs 2039A-2039E ensures cache coherency between the caches of one or more host processors (e.g., 2005) and GPUs 2010-2013 and implements biasing techniques that indicate the physical memory where certain types of data should be stored. Figure 20F Multiple instances of bias / coherence management circuits 2094A- 2094E are shown in , but bias / coherence circuits may be implemented within an MMU of one or more host processors 2005 and / or within an accelerator integrated circuit 2036 .

[0350] One embodiment allows GPU-attached memory 2020-2023 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology, but without suffering the performance drawbacks associated with full system cache coherence. In at least one embodiment, the ability to access GPU-attached memory 2020-2023 as system memory without the heavy cache coherence overhead provides a favorable operating environment for GPU offloading. This arrangement allows software on the host processor 2005 to set operands and access computation results without the overhead of traditional I / O DMA data copies. Such traditional copies include driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are less efficient than simple memory accesses. In at least one embodiment, the ability to access GPU-attached memory 2020-2023 without cache coherence overhead may be critical to the execution time of offloaded computations. For example, in situations with large amounts of streaming write memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPUs 2010-2013. In at least one embodiment, efficiency of operand setup, efficiency of result access, and efficiency of GPU computation may play a role in determining the effectiveness of GPU offloading.

[0351] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table can be used, which can be a page-granular structure (e.g., controlled at the granularity of a memory page) that includes 1 or 2 bits per GPU-attached memory page. In at least one embodiment, the bias table can be implemented in the stolen memory range of one or more GPU-attached memories 2020-2023, with or without a bias cache in GPUs 2010-2013 (e.g., to cache frequently / recently used entries in the bias table). Alternatively, the entire bias table can be maintained within the GPU.

[0352] In at least one embodiment, before actually accessing the GPU memory, the bias table entry associated with each access to the GPU additional memory 2020-2023 is accessed, resulting in the following operations. First, local requests from GPUs 2010-2013 that find their pages in the GPU bias are directly forwarded to the corresponding GPU memory 2020-2023. Local requests from GPUs that find their pages in the host bias are forwarded to processor 2005 (e.g., via a high-speed link as described above). In one embodiment, the request from processor 2005 to find the requested page in the host processor bias completes a request similar to a normal memory read. Alternatively, a request pointing to the GPU bias page can be forwarded to GPUs 2010-2013. In at least one embodiment, if the GPU is not currently using the page, the GPU can subsequently migrate the page to the host processor bias. In at least one embodiment, the bias state of the page can be changed by a software-based mechanism, a hardware-assisted software-based mechanism, or in limited cases by a purely hardware-based mechanism.

[0353] One mechanism for changing the bias state employs an API call (e.g., OpenCL), which in turn calls the GPU's device driver, which in turn sends a message (or queues a command descriptor) to the GPU, directing the GPU to change the bias state and, in some migrations, to perform a cache flush operation in the host. In at least one embodiment, the cache flush operation is used for migrations from the host processor 2005 bias to the GPU bias, but not for the reverse migration.

[0354] In one embodiment, cache coherence is maintained by temporarily rendering GPU-biased pages that cannot be cached by host processor 2005. To access these pages, processor 2005 may request access from GPU 2010, which may or may not immediately grant access. Therefore, to reduce communication between processor 2005 and GPU 2010, it is beneficial to ensure that GPU-biased pages are pages required by the GPU and not by host processor 2005, and vice versa.

[0355] In at least one embodiment, Figure 20A -F At least one component shown or described is used to achieve the combination Figure 1-13 In at least one embodiment, at least one GPU and / or multi-core processor shown or described with respect to FIG. 20A-F is used to perform rate matching. In at least one embodiment, rate matching includes causing 5G New Radio signal information to be selected in parallel using parameters based at least in part on the 5G standard. In at least one embodiment, Figure 20A At least one GPU and / or multi-core processor shown or described in FIG. 1 is configured to perform at least one aspect of rate matching 114, example process 300, data flow 400, example process 500, example process 600, example process 900, graph 1100, example process 1200, example process 1300, algorithm 1 described at least in conjunction with step 1314 of example process 1300, algorithm 2 described at least in conjunction with step 1316 of example process 1300, and / or algorithm 3 described at least in conjunction with step 1320 of example process 1300. In at least one embodiment, a multi-core processor (e.g., multi-core processor 2005) executes a kernel launch function that passes parameters to a kernel executing in conjunction with the kernel. Figure 1-13 The described rate matching is performed on at least one core on a graphics processor, such as GPU 2010.

[0356] Figure 21 An exemplary integrated circuit and associated graphics processor according to various embodiments described herein are shown, which can be manufactured using one or more IP cores. In addition to the illustrations, other logic and circuitry may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0357] Figure 21 is a block diagram illustrating an exemplary system on a chip integrated circuit 2100 that can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, integrated circuit 2100 includes one or more application processors 2105 (e.g., CPUs), at least one graphics processor 2110, and may additionally include an image processor 2115 and / or a video processor 2120, any of which may be modular IP cores. In at least one embodiment, integrated circuit 2100 includes peripheral or bus logic, including a USB controller 2125, a UART controller 2130, an SPI / SDIO controller 2135, and an I.sup.2S / I.sup.2C controller 2140. In at least one embodiment, integrated circuit 2100 may include a display device 2145 coupled to one or more of a High-Definition Multimedia Interface (HDMI) controller 2150 and a Mobile Industry Processor Interface (MIPI) display interface 2155. In at least one embodiment, storage may be provided by a flash memory subsystem 2160, including flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 2165 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 2170 .

[0358] In at least one embodiment, Figure 21 At least one component shown or described is used to implement the combination Figure 1-13 The techniques and / or functions described herein are described. In at least one embodiment, the graphics processor 2110 is configured to perform rate matching. In at least one embodiment, the rate matching includes causing 5G new radio signal information to be selected in parallel using parameters based at least in part on the 5G standard. In at least one embodiment, the graphics processor 2110 is configured to perform at least one aspect described with respect to rate matching 114, example process 300, data flow 400, example process 500, example process 600, example process 900, chart 1100, example process 1200, example process 1300, algorithm 1 described at least in conjunction with step 1314 of example process 1300, algorithm 2 described at least in conjunction with step 1316 of example process 1300, and / or algorithm 3 described at least in conjunction with step 1320 of example process 1300.

[0359] Figures 22A-22B An exemplary integrated circuit and associated graphics processor according to various embodiments described herein are shown, which can be manufactured using one or more IP cores. In addition to the illustrations, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0360] Figures 22A-22B is a block diagram illustrating an exemplary graphics processor for use within a SoC according to embodiments described herein. Figure 22A An exemplary graphics processor 2210 of a system-on-chip integrated circuit is shown that can be fabricated using one or more IP cores in accordance with at least one embodiment. Figure 22B Another exemplary graphics processor 2240 of a system-on-chip integrated circuit that can be manufactured using one or more IP cores according to at least one embodiment is shown. In at least one embodiment, the graphics processor 2210 of FIG. 22A is a low-power graphics processor core. In at least one embodiment, Figure 22B The graphics processor 2240 is a higher performance graphics processor core. In at least one embodiment, each graphics processor 2210, 2240 can be Figure 21 A variant of the graphics processor 2110.

[0361] In at least one embodiment, the graphics processor 2210 includes a vertex processor 2205 and one or more fragment processors 2215A-2215N (e.g., 2215A, 2215B, 2215C, 2215D through 2215N-1 and 2215N). In at least one embodiment, the graphics processor 2210 can execute different shader programs via separate logic, such that the vertex processor 2205 is optimized to perform operations for the vertex shader program, while the one or more fragment processors 2215A-2215N perform fragment (e.g., pixel) shading operations for the fragment or pixel or shader program. In at least one embodiment, the vertex processor 2205 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the one or more fragment processors 2215A-2215N use the primitives and vertex data generated by the vertex processor 2205 to generate a frame buffer for display on a display device. In at least one embodiment, one or more fragment processors 2215A-2215N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs provided in the Direct 3D API.

[0362] In at least one embodiment, the graphics processor 2210 additionally includes one or more memory management units (MMUs) 2220A-2220B, one or more caches 2225A-2225B, and one or more circuit interconnects 2230A-2230B. In at least one embodiment, the one or more MMUs 2220A-2220B provide a mapping of virtual to physical addresses for the graphics processor 2210, including for the vertex processor 2205 and / or the fragment processors 2215A-2215N, which may reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in the one or more caches 2225A-2225B. In at least one embodiment, the one or more MMUs 2220A-2220B may synchronize with other MMUs within the system, including with the one or more MMUs 2220A-2220B. Figure 21 One or more MMUs associated with one or more application processors 2105, graphics processor 2115, and / or video processor 2120 enable each processor 2105-2120 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 2230A-2230B enable the graphics processor 2210 to connect to other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0363] In at least one embodiment, graphics processor 2240 includes Figure 22A One or more MMUs 2220A-2220B, caches 2225A-2225B, and circuit interconnects 2230A-2230B of the graphics processor 2210. In at least one embodiment, the graphics processor 2240 includes one or more shader cores 2255A-2255N (e.g., 2255A, 2255B, 2255C, 2255D, 2255E, 2255F through 2255N-1 and 2255N) that provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 2240 includes an inter-core task manager 2245 that acts as a thread dispatcher to dispatch execution threads to one or more shader cores 2255A-2255N and a tiling unit 2258 to accelerate tile-based rendering operations in which rendering operations of a scene are subdivided in image space, for example, to exploit local spatial coherence within a scene or to optimize use of internal caches.

[0364] In at least one embodiment, Figure 22A and 22B At least one component shown or described is used to implement the combination Figure 1-13 The techniques and / or functionality described herein are described. In at least one embodiment, at least one graphics processor 2210 is configured to perform rate matching. In at least one embodiment, rate matching includes causing 5G New Radio signal information to be selected in parallel using parameters based at least in part on a 5G standard. In at least one embodiment, at least one graphics processor 2210 is configured to perform at least one aspect described with respect to rate matching 114, example process 300, data flow 400, example process 500, example process 600, example process 900, chart 1100, example process 1200, example process 1300, algorithm 1 described in conjunction with at least step 1314 of example process 1300, algorithm 2 described in conjunction with at least step 1316 of example process 1300, and / or algorithm 3 described in conjunction with at least step 1320 of example process 1300.

[0365] Figure 23A and 23B Additional exemplary graphics processor logic according to embodiments described herein is shown. In at least one embodiment, Figure 23A Shows that can be included in Figure 21 Graphics core 2300 within graphics processor 2110, and in at least one embodiment, may be such as Figure 22B Unified shader cores 2255A-2255N are shown. Figure 23B A highly parallel, general-purpose graphics processing unit 2330 suitable for deployment on a multi-chip module in at least one embodiment is shown.

[0366] In at least one embodiment, graphics core 2300 includes a shared instruction cache 2302, texture units 2318, and cache / shared memory 2320, which are common to execution resources within graphics core 2300. In at least one embodiment, graphics core 2300 may include multiple slices 2301A-2301N, or partitions of each core, and a graphics processor may include multiple instances of graphics core 2300. Slices 2301A-2301N may include support logic including local instruction caches 2304A-2304N, thread schedulers 2306A-2306N, thread dispatchers 2308A-2308N, and a set of registers 2310A-2310N. In at least one embodiment, the slices 2301A-2301N may include a set of additional function units (AFUs 2312A-2312N), floating point units (FPUs 2314A-2314N), integer arithmetic logic units (ALUs 2316A-2316N), address calculation units (ACUs 2313A-2313N), double precision floating point units (DPFPUs 2315A-2315N), and matrix processing units (MPUs 2317A-2317N).

[0367] In at least one embodiment, the FPUs 2314A-2314N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPUs 2315A-2315N perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 2316A-2316N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPUs 2317A-2317N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPUs 2317-2317N can perform various matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated general matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFUs 2312A-2312N can perform additional logical operations not supported by the floating-point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

[0368] In at least one embodiment, Figure 23A At least one component shown or described is used to implement the combination Figure 1-13In at least one embodiment, at least one graphics processor 2300 is configured to perform rate matching. In at least one embodiment, rate matching includes causing 5G new radio signal information to be selected in parallel using parameters based at least in part on a 5G standard.

[0369] In at least one embodiment, at least one graphics processor 2300 is used to perform at least one aspect described with respect to rate matching 114, example process 300, data flow 400, example process 500, example process 600, example process 900, chart 1100, example process 1200, example process 1300, algorithm one described at least in conjunction with step 1314 of example process 1300, algorithm two described at least in conjunction with step 1316 of example process 1300, and / or algorithm three described at least in conjunction with step 1320 of example process 1300.

[0370] Figure 23B A general purpose graphics processing unit (GPGPU) 2330 is shown in at least one embodiment, which can be configured to enable highly parallel computing operations to be performed by a group of graphics processing units. In at least one embodiment, GPGPU 2330 can be directly linked to other instances of GPGPU 2330 to create a multi-GPU cluster to increase the training speed for deep neural networks. In at least one embodiment, GPGPU 2330 includes a host interface 2332 to enable connection to a host processor. In at least one embodiment, host interface 2332 is a PCI Express interface. In at least one embodiment, host interface 2332 can be a vendor-specific communication interface or communication structure. In at least one embodiment, GPGPU 2330 receives commands from the host processor and uses a global scheduler 2334 to assign execution threads associated with those commands to a group of compute clusters 2336A-2336H. In at least one embodiment, compute clusters 2336A-2336H share cache memory 2338. In at least one embodiment, cache memory 2338 may be used as a higher level cache for cache memory within compute clusters 2336A-2336H.

[0371] In at least one embodiment, the GPGPU 2330 includes memory 2344A-2344B coupled to the compute cluster 2336A-2336H via a set of memory controllers 2342A-2342B. In at least one embodiment, the memory 2344A-2344B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), which includes graphics double data rate (GDDR) memory.

[0372] In at least one embodiment, computing clusters 2336A-2336H each include a set of graphics cores, e.g. Figure 23A The graphics core 2300 may include multiple types of integer and floating-point logic units that can perform computational operations at various precision ranges, including precision suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each of the compute clusters 2336A-2336H may be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of the floating-point units may be configured to perform 64-bit floating-point operations.

[0373] In at least one embodiment, multiple instances of GPGPU 2330 can be configured to function as a compute cluster. In at least one embodiment, the communication used by compute clusters 2336A-2336H for synchronization and data exchange varies between embodiments. In at least one embodiment, multiple instances of GPGPU 2330 communicate via host interface 2332. In at least one embodiment, GPGPU 2330 includes an I / O hub 2339 that couples GPGPU 2330 to a GPU link 2340, enabling direct connections to other instances of GPGPU 2330. In at least one embodiment, GPU link 2340 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 2330. In at least one embodiment, GPU link 2340 is coupled to a high-speed interconnect to send and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 2330 reside in separate data processing systems and communicate via a network device accessible through host interface 2332. In at least one embodiment, GPU link 2340 may be configured to enable connection to a host processor in addition to or as an alternative to host interface 2332 .

[0374] In at least one embodiment, the GPGPU 2330 can be configured to train a neural network. In at least one embodiment, the GPGPU 2330 can be used within an inference platform. In at least one embodiment, where the GPGPU 2330 is used for inference, the GPGPU can include fewer compute clusters 2336A-2336H than when the GPGPU is used to train a neural network. In at least one embodiment, the memory technology associated with the memories 2344A-2344B can differ between the inference and training configurations, with higher-bandwidth memory technology being dedicated to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 2330 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which can be used during inference operations of a deployed neural network.

[0375] In at least one embodiment, Figure 23B At least one component shown or described is used to implement the combination Figure 1-13 The techniques and / or functionality described herein are described. In at least one embodiment, at least one GPGPU 2330 is configured to perform rate matching. In at least one embodiment, rate matching includes enabling 5G New Radio signal information to be selected in parallel using parameters based at least in part on a 5G standard. In at least one embodiment, at least one GPGPU 2330 is configured to perform at least one aspect described with respect to rate matching 114, example process 300, data flow 400, example process 500, example process 600, example process 900, graph 1100, example process 1200, example process 1300, algorithm 1 described in at least conjunction with step 1314 of example process 1300, algorithm 2 described in at least conjunction with step 1316 of example process 1300, and / or algorithm 3 described in at least conjunction with step 1320 of example process 1300.

[0376] Figure 24A block diagram of a computer system 2400 according to at least one embodiment is shown. In at least one embodiment, computer system 2400 includes a processing subsystem 2401 having one or more processors 2402 and a system memory 2404, which communicates via an interconnect path that may include a memory hub 2405. In at least one embodiment, memory hub 2405 may be a separate component within a chipset assembly or may be integrated within one or more processors 2402. In at least one embodiment, memory hub 2405 is coupled to an I / O subsystem 2411 via a communication link 2406. In one embodiment, I / O subsystem 2411 includes an I / O hub 2407, which enables computer system 2400 to receive input from one or more input devices 2408. In at least one embodiment, I / O hub 2407 may enable a display controller, which may be included in one or more processors 2402, to provide output to one or more display devices 2410A. In at least one embodiment, the one or more display devices 2410A coupled to the I / O hub 2407 may include local, internal, or embedded display devices.

[0377] In at least one embodiment, the processing subsystem 2401 includes one or more parallel processors 2412 coupled to a memory hub 2405 via a bus or other communication link 2413. In at least one embodiment, the communication link 2413 can be any of a number of standard-based communication link technologies or protocols, such as, but not limited to, PCI Express, or can be a vendor-specific communication interface or communication structure. In at least one embodiment, the one or more parallel processors 2412 form a computationally focused parallel or vector processing system that can include a large number of processing cores and / or processing clusters, such as a multi-integrated core (MIC) processor. In at least one embodiment, the one or more parallel processors 2412 form a graphics processing subsystem that can output pixels to one of one or more display devices 2410A coupled via an I / O hub 2407. In at least one embodiment, the one or more parallel processors 2412 can also include a display controller and display interface (not shown) to enable direct connection to one or more display devices 2410B.

[0378] In at least one embodiment, a system storage unit 2414 can be connected to the I / O hub 2407 to provide a storage mechanism for the computer system 2400. In at least one embodiment, an I / O switch 2416 can be used to provide an interface mechanism to enable connections between the I / O hub 2407 and other components, such as a network adapter 2418 and / or a wireless network adapter 2417 that can be integrated into the platform, as well as various other devices that can be added via one or more add-on devices 2420. In at least one embodiment, the network adapter 2418 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 2419 can include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more radio devices.

[0379] In at least one embodiment, computer system 2400 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to I / O hub 2407. In at least one embodiment, interconnection may be achieved using any suitable protocol, such as a PCI (Peripheral Component Interconnect)-based protocol (e.g., PCI-Express) or other bus or point-to-point communication interface and / or protocol. Figure 24 Communication paths for various components in a chip, such as NV-Link high-speed interconnect or interconnect protocol.

[0380] In at least one embodiment, one or more parallel processors 2412 include circuits optimized for graphics and video processing, including, for example, video output circuitry, and constitute a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 2412 include circuits optimized for general-purpose processing. In at least one embodiment, the components of computer system 2400 can be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 2412, memory hub 2405, processor 2402, and I / O hub 2407 can be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, the components of computer system 2400 can be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of computer system 2400 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules to form a modular computer system.

[0381] In at least one embodiment, Figure 24 At least one component shown or described is used to implement the combination Figure 1-13 Techniques and / or functions described herein. In at least one embodiment, at least one of processor 2402 and parallel processor 2412 is used to perform rate matching. In at least one embodiment, rate matching includes causing 5G new radio signal information to be selected in parallel using parameters based at least in part on the 5G standard. In at least one embodiment, at least one of processor 2402 and parallel processor 2412 is used to perform at least one aspect described with respect to rate matching 114, example process 300, data flow 400, example process 500, example process 600, example process 900, chart 1100, example process 1200, example process 1300, algorithm one described at least in conjunction with step 1314 of example process 1300, algorithm two described at least in conjunction with step 1316 of example process 1300, and / or algorithm three described at least in conjunction with step 1320 of example process 1300. In at least one embodiment, processor 2402 executes a kernel launch function that passes parameters to the kernel that executes the kernel in conjunction with Figure 1-13 The described rate matching is performed on at least one core of the parallel processor 2412 .

[0382] processor

[0383] Figure 25A 25. The parallel processor 2500 is shown in accordance with at least one embodiment. In at least one embodiment, the various components of the parallel processor 2500 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). In at least one embodiment, the parallel processor 2500 is shown in accordance with an exemplary embodiment. Figure 24 A variation of the one or more parallel processors 2412 is shown.

[0384] In at least one embodiment, parallel processor 2500 includes parallel processing unit 2502. In at least one embodiment, parallel processing unit 2502 includes an I / O unit 2504 that enables communication with other devices, including other instances of parallel processing unit 2502. In at least one embodiment, I / O unit 2504 can be directly connected to other devices. In at least one embodiment, I / O unit 2504 connects to other devices using a hub or switch interface (e.g., memory hub 2405). In at least one embodiment, the connection between memory hub 2405 and I / O unit 2504 forms communication link 2413. In at least one embodiment, I / O unit 2504 is connected to a host interface 2506 and a memory crossbar switch 2516, where host interface 2506 receives commands for performing processing operations, and memory crossbar switch 2516 receives commands for performing memory operations.

[0385] In at least one embodiment, when host interface 2506 receives command buffers via I / O unit 2504, host interface 2506 can direct work operations to execute those commands to front end 2508. In at least one embodiment, front end 2508 is coupled to scheduler 2510, which is configured to distribute commands or other work items to processing cluster array 2512. In at least one embodiment, scheduler 2510 ensures that processing cluster array 2512 is properly configured and in a valid state before distributing tasks to processing cluster array 2512. In at least one embodiment, scheduler 2510 is implemented via firmware logic executed on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 2510 can be configured to perform complex scheduling and work distribution operations at both coarse and fine granularity, thereby enabling fast preemption and context switching of threads executing on processing array 2512. In at least one embodiment, host software can authenticate workloads for scheduling on processing array 2512 via one of multiple graphics processing doorbells. In at least one embodiment, the workload may then be automatically distributed across the processing array 2512 by scheduler 2510 logic within a microcontroller that includes scheduler 2510 .

[0386] In at least one embodiment, the processing cluster array 2512 can include up to "N" processing clusters (e.g., cluster 2514A, cluster 2514B, through cluster 2514N). In at least one embodiment, each cluster 2514A-2514N of the processing cluster array 2512 can execute a large number of concurrent threads. In at least one embodiment, the scheduler 2510 can use various scheduling and / or work distribution algorithms to distribute work to the clusters 2514A-2514N of the processing cluster array 2512, which can vary depending on the workload generated by each program or calculation type. In at least one embodiment, scheduling can be handled dynamically by the scheduler 2510 or can be partially assisted by compiler logic during the compilation of program logic configured to be executed by the processing cluster array 2512. In at least one embodiment, different clusters 2514A-2514N of the processing cluster array 2512 can be assigned to process different types of programs or to perform different types of calculations.

[0387] In at least one embodiment, processing cluster array 2512 can be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster array 2512 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, processing cluster array 2512 can include logic to perform processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0388] In at least one embodiment, processing cluster array 2512 is configured to perform parallel graphics processing operations. In at least one embodiment, processing cluster array 2512 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, processing cluster array 2512 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing units 2502 may transfer data from system memory via I / O units 2504 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2522) during processing and then written back to system memory.

[0389] In at least one embodiment, when parallel processing unit 2502 is used to perform graphics processing, scheduler 2510 can be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations to multiple clusters 2514A-2514N of processing cluster array 2512. In at least one embodiment, portions of processing cluster array 2512 can be configured to perform different types of processing. For example, in at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen-space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of clusters 2514A-2514N can be stored in a buffer to allow the intermediate data to be transferred between clusters 2514A-2514N for further processing.

[0390] In at least one embodiment, processing cluster array 2512 can receive processing tasks to be executed via scheduler 2510, which receives commands defining the processing tasks from front end 2508. In at least one embodiment, a processing task can include an index of data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how to process the data (e.g., what program to execute). In at least one embodiment, scheduler 2510 can be configured to obtain an index corresponding to a task, or can receive the index from front end 2508. In at least one embodiment, front end 2508 can be configured to ensure that processing cluster array 2512 is configured in a valid state before starting a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.).

[0391] In at least one embodiment, each of the one or more instances of parallel processing unit 2502 can be coupled to parallel processor memory 2522. In at least one embodiment, parallel processor memory 2522 can be accessed via memory crossbar 2516, which can receive memory requests from processing cluster array 2512 and I / O unit 2504. In at least one embodiment, memory crossbar 2516 can access parallel processor memory 2522 via memory interface 2518. In at least one embodiment, memory interface 2518 can include multiple partition units (e.g., partition unit 2520A, partition unit 2520B, through partition unit 2520N), which can each be coupled to a portion of parallel processor memory 2522 (e.g., a memory unit). In at least one embodiment, the plurality of partition units 2520A-2520N are configured to be equal to the number of memory cells, such that the first partition unit 2520A has a corresponding first memory cell 2524A, the second partition unit 2520B has a corresponding memory cell 2524B, and the Nth partition unit 2520N has a corresponding Nth memory cell 2524N. In at least one embodiment, the number of partition units 2520A-2520N may not be equal to the number of memory devices.

[0392] In at least one embodiment, memory units 2524A-2524N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 2524A-2524N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, render targets, such as frame buffers or texture maps, may be stored across memory units 2524A-2524N, allowing partition units 2520A-2520N to write portions of each render target in parallel to efficiently use the available bandwidth of parallel processor memory 2522. In at least one embodiment, local instances of parallel processor memory 2522 may be eliminated in favor of a unified memory design utilizing system memory in combination with local cache memory.

[0393] In at least one embodiment, any of the clusters 2514A-2514N in the processing cluster array 2512 can process data to be written to any memory unit 2524A-2524N within the parallel processor memory 2522. In at least one embodiment, the memory crossbar 2516 can be configured to transmit the output of each cluster 2514A-2514N to any partition unit 2520A-2520N or another cluster 2514A-2514N, which can perform other processing operations on the output. In at least one embodiment, each cluster 2514A-2514N can communicate with a memory interface 2518 via the memory crossbar 2516 to read from or write to various external storage devices. In at least one embodiment, memory crossbar 2516 has connections to memory interface 2518 for communicating with I / O unit 2504, and to local instances of parallel processor memory 2522, thereby enabling processing units within different processing clusters 2514A-2514N to communicate with system memory or other memory that is not local to parallel processing unit 2502. In at least one embodiment, memory crossbar 2516 can use virtual channels to separate traffic flows between clusters 2514A-2514N and partition units 2520A-2520N.

[0394] In at least one embodiment, multiple instances of parallel processing unit 2502 can be provided on a single plug-in card, or multiple plug-in cards can be interconnected. In at least one embodiment, different instances of parallel processing unit 2502 can be configured to interoperate with each other, even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit 2502 can include a higher precision floating point unit than other instances. In at least one embodiment, a system incorporating one or more instances of parallel processing unit 2502 or parallel processor 2500 can be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0395] Figure 25B is a block diagram of a partition unit 2520 according to at least one embodiment. In at least one embodiment, the partition unit 2520 is Figure 25A25A-2520N。In at least one embodiment, partition unit 2520 includes an L2 cache 2521, a frame buffer interface 2525, and an ROP 2526 (raster operation unit). L2 cache 2521 is a read / write cache that is configured to execute load and store operations received from memory crossbar switch 2516 and ROP 2526. In at least one embodiment, L2 cache 2521 outputs read misses and urgent writeback requests to frame buffer interface 2525 for processing. In at least one embodiment, updates can also be sent to the frame buffer via frame buffer interface 2525 for processing. In at least one embodiment, frame buffer interface 2525 interacts with one of the memory units in the parallel processor memory, such as memory units 2524A-2524N of FIG. 25A (e.g., within parallel processor memory 2522).

[0396] In at least one embodiment, ROP 2526 is a processing unit that performs raster operations such as stenciling, z-testing, blending, etc. In at least one embodiment, ROP 2526 then outputs processed graphics data that is stored in graphics memory. In at least one embodiment, ROP 2526 includes compression logic to compress depth or color data written to memory and decompress depth or color data read from memory. In at least one embodiment, the compression logic can be lossless compression logic that utilizes one or more of a variety of compression algorithms. In at least one embodiment, the type of compression performed by ROP 2526 can vary based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, incremental color compression is performed on the depth and color data on a per-tile basis.

[0397] In at least one embodiment, ROP 2526 is included within each processing cluster (e.g., clusters 2514A-2514N of FIG. 25 ), rather than within partition unit 2520. In at least one embodiment, read and write requests for pixel data are transferred through memory crossbar 2516 rather than pixel fragment data. In at least one embodiment, processed graphics data may be displayed on a display device such as a Figure 24 2410), routed by processor 2402 for further processing, or by Figure 25A One of the processing entities within parallel processor 2500 is routed for further processing.

[0398] Figure 25C25 . In at least one embodiment, the processing cluster 2514 is an example of one of the processing clusters 2514A-2514N of FIG. 25 . In at least one embodiment, the processing cluster 2514 can be configured to execute many threads in parallel, where the term "thread" refers to an example of a specific program executed on a specific set of input data. In at least one embodiment, single instruction multiple data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction multiple thread (SIMT) technology is used to support the parallel execution of a large number of generally synchronized threads, which uses a common instruction unit that is configured to issue instructions to a group of processing engines in each processing cluster.

[0399] In at least one embodiment, the operation of the processing cluster 2514 can be controlled by a pipeline manager 2532 that distributes processing tasks to SIMT parallel processors. In at least one embodiment, the pipeline manager 2532 receives instructions from the scheduler 2510 of FIG. 25 and manages the execution of these instructions by the graphics multiprocessor 2534 and / or the texture unit 2536. In at least one embodiment, the graphics multiprocessor 2534 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors with different architectures can be included within the processing cluster 2514. In at least one embodiment, one or more instances of the graphics multiprocessor 2534 can be included within the processing cluster 2514. In at least one embodiment, the graphics multiprocessor 2534 can process data, and the data crossbar 2540 can be used to distribute the processed data to one of multiple possible destinations (including other shader units). In at least one embodiment, the pipeline manager 2532 can facilitate the distribution of processed data by specifying the destination of the processed data to be distributed via the data crossbar 2540.

[0400] In at least one embodiment, each graphics multiprocessor 2534 within a processing cluster 2514 can include the same set of function execution logic (e.g., arithmetic logic unit, load-store unit, etc.). In at least one embodiment, the function execution logic can be configured in a pipelined manner, where new instructions can be issued before previous instructions have completed. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, shifts, and calculations of various algebraic functions. In at least one embodiment, the same functional unit hardware can be utilized to perform different operations, and any combination of functional units can be present.

[0401] In at least one embodiment, instructions transmitted to processing cluster 2514 constitute threads. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a program on different input data. In at least one embodiment, each thread within a thread group can be assigned to a different processing engine within graphics multiprocessor 2534. In at least one embodiment, a thread group can include fewer threads than the number of processing engines within graphics multiprocessor 2534. In at least one embodiment, when a thread group includes fewer threads than the number of processing engines, one or more processing engines may be idle during the processing of a loop within the thread group. In at least one embodiment, a thread group can also include more threads than the number of processing engines within graphics multiprocessor 2534. In at least one embodiment, when a thread group includes more threads than the number of processing engines within graphics multiprocessor 2534, processing can be performed within consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on graphics multiprocessor 2534.

[0402] In at least one embodiment, the graphics multiprocessor 2534 includes internal cache memory to perform load and store operations. In at least one embodiment, the graphics multiprocessor 2534 can abandon the internal cache and use cache memory within the processing cluster 2514 (e.g., L1 cache 2548). In at least one embodiment, each graphics multiprocessor 2534 can also access a partition unit (e.g., Figure 25A L2 cache within partition units 2520A-2520N) of the graphics multiprocessor 2534 is shared across all processing clusters 2514 and can be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 2534 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processing unit 2502 can be used as global memory. In at least one embodiment, processing cluster 2514 includes multiple instances of graphics multiprocessor 2534, which can share common instructions and data, which can be stored in L1 cache 2548.

[0403] In at least one embodiment, each processing cluster 2514 may include a memory management unit ("MMU") 2545 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of MMU 2545 may reside within memory interface 2518 of FIG. 25 . In at least one embodiment, MMU 2545 includes a set of page table entries (PTEs) that map virtual addresses to physical addresses of tiles (more on tiling) and, optionally, cache line indices. In at least one embodiment, MMU 2545 may include a translation lookaside buffer (TLB) or cache that may reside within graphics multiprocessor 2534 or an L1 cache or within processing cluster 2514. In at least one embodiment, physical addresses are processed to distribute surface data access locality for efficient request interleaving between partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0404] In at least one embodiment, processing clusters 2514 can be configured such that each graphics multiprocessor 2534 is coupled to a texture unit 2536 to perform texture mapping operations, including determining texture sample locations, reading texture data, and filtering texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2534, and retrieved from an L2 cache, local parallel processor memory, or system memory as needed. In at least one embodiment, each graphics multiprocessor 2534 outputs processed tasks to a data crossbar 2540 to provide the processed tasks to another processing cluster 2514 for further processing or to store the processed tasks in an L2 cache, local parallel processor memory, or system memory via a memory crossbar 2516. In at least one embodiment, a PreROP 2542 (pre-raster operations unit) is configured to receive data from the graphics multiprocessor 2534 and direct the data to a ROP unit, which may be located with a partition unit as described herein (e.g., partition units 2520A-2520N of FIG. 25 ). In at least one embodiment, the PreROP 2542 unit may perform optimizations for color blending, organize pixel color data, and perform address translation.

[0405] In at least one embodiment, Figure 25A -C At least one component shown or described is used to implement the combination Figure 1-13The techniques and / or functions described herein are described. In at least one embodiment, at least one parallel processor 2500 is configured to perform rate matching. In at least one embodiment, rate matching includes causing 5G new radio signal information to be selected in parallel using parameters based at least in part on the 5G standard. In at least one embodiment, at least one parallel processor 2500 is configured to perform at least one aspect described with respect to rate matching 114, example process 300, data flow 400, example process 500, example process 600, example process 900, chart 1100, example process 1200, example process 1300, algorithm 1 described at least in conjunction with step 1314 of example process 1300, algorithm 2 described at least in conjunction with step 1316 of example process 1300, and / or algorithm 3 described at least in conjunction with step 1320 of example process 1300.

[0406] Figure 25D A graphics multiprocessor 2534 is shown in accordance with at least one embodiment. In at least one embodiment, the graphics multiprocessor 2534 is coupled to a pipeline manager 2532 of a processing cluster 2514. In at least one embodiment, the graphics multiprocessor 2534 has an execution pipeline that includes, but is not limited to, an instruction cache 2552, an instruction unit 2554, an address mapping unit 2556, a register file 2558, one or more general purpose graphics processing unit (GPGPU) cores 2562, and one or more load / store units 2566. The GPGPU cores 2562 and the load / store units 2566 are coupled to a cache memory 2572 and a shared memory 2570 via a memory and cache interconnect 2568.

[0407] In at least one embodiment, the instruction cache 2552 receives a stream of instructions to be executed from the pipeline manager 2532. In at least one embodiment, the instructions are cached in the instruction cache 2552 and dispatched for execution by the instruction unit 2554. In one embodiment, the instruction unit 2554 can dispatch instructions as thread groups (e.g., warps), assigning each thread of the thread group to a different execution unit within the GPGPU core 2562. In at least one embodiment, the instructions can access any local, shared, or global address space by specifying an address within the unified address space. In at least one embodiment, the address mapping unit 2556 can be used to convert addresses in the unified address space into different memory addresses that can be accessed by the load / store unit 2566.

[0408] In at least one embodiment, register file 2558 provides a set of registers for the functional units of graphics multiprocessor 2534. In at least one embodiment, register file 2558 provides temporary storage for operands for the data paths of the functional units (e.g., GPGPU core 2562, load / store unit 2566) connected to graphics multiprocessor 2534. In at least one embodiment, register file 2558 is divided between each functional unit such that a dedicated portion of register file 2558 is allocated to each functional unit. In at least one embodiment, register file 2558 is divided between the different warps being executed by graphics multiprocessor 2534.

[0409] In at least one embodiment, the GPGPU cores 2562 may each include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 2534. The GPGPU cores 2562 may be architecturally similar or may differ in architecture. In at least one embodiment, a first portion of the GPGPU core 2562 includes a single-precision FPU and integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. In at least one embodiment, the graphics multiprocessor 2534 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores may also include fixed-function or special-function logic.

[0410] In at least one embodiment, the GPGPU core 2562 includes SIMD logic capable of executing a single instruction on multiple sets of data. In one embodiment, the GPGPU core 2562 can physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for the SIMT execution model can be executed by a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations can be executed in parallel by a single SIMD8 logic unit.

[0411] In at least one embodiment, the memory and cache interconnect 2568 is an interconnect network that connects each functional unit of the graphics multiprocessor 2534 to the register file 2558 and shared memory 2570. In at least one embodiment, the memory and cache interconnect 2568 is a crossbar interconnect that allows the load / store unit 2566 to perform load and store operations between the shared memory 2570 and the register file 2558. In at least one embodiment, the register file 2558 can operate at the same frequency as the GPGPU core 2562, resulting in very low latency for data transfers between the GPGPU core 2562 and the register file 2558. In at least one embodiment, the shared memory 2570 can be used to enable communication between threads executing on the functional units within the graphics multiprocessor 2534. In at least one embodiment, the cache memory 2572 can be used, for example, as a data cache to cache texture data communicated between the functional units and the texture unit 2536. In at least one embodiment, the shared memory 2570 can also be used as a program-managed cache. In at least one embodiment, in addition to automatically cached data stored in cache memory 2572, threads executing on GPGPU core 2562 may also programmatically store data in shared memory.

[0412] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU can be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., internal to the package or chip). In at least one embodiment, regardless of the manner in which the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0413] In at least one embodiment, Figure 25D At least one component shown or described is used to implement the combination Figure 1-13In at least one embodiment, at least one graphics multiprocessor 2534 is configured to perform rate matching. In at least one embodiment, rate matching includes enabling 5G New Radio signal information to be selected in parallel using parameters based at least in part on a 5G standard. In at least one embodiment, at least one graphics multiprocessor 2534 is configured to perform at least one aspect of rate matching 114, example process 300, data flow 400, example process 500, example process 600, example process 900, chart 1100, example process 1200, example process 1300, algorithm 1 described in conjunction with at least step 1314 of example process 1300, algorithm 2 described in conjunction with at least step 1316 of example process 1300, and / or algorithm 3 described in conjunction with at least step 1320 of example process 1300.

[0414] Figure 26 A multi-GPU computing system 2600 is shown in accordance with at least one embodiment. In at least one embodiment, multi-GPU computing system 2600 may include a processor 2602 coupled to multiple general-purpose graphics processing units (GPGPUs) 2606A-D via a host interface switch 2604. In at least one embodiment, host interface switch 2604 is a PCI Express switch device that couples processor 2602 to a PCI Express bus, over which processor 2602 can communicate with GPGPUs 2606A-D. GPGPUs 2606A-D may be interconnected via a set of high-speed P2P GPU-to-GPU links 2616. In at least one embodiment, GPU-to-GPU links 2616 connect to each of GPGPUs 2606A-D via a dedicated GPU link. In at least one embodiment, P2P GPU links 2616 enable direct communication between each GPGPU 2606A-D without requiring communication through host interface bus 2604 to which processor 2602 is connected. In at least one embodiment, with GPU-to-GPU traffic directed to P2P GPU link 2616, host interface bus 2604 remains available for system memory access or for communicating with other instances of multi-GPU computing system 2600, for example, via one or more network devices. While in at least one embodiment, GPGPUs 2606A-D are connected to processor 2602 via host interface switch 2604, in at least one embodiment, processor 2602 includes direct support for P2P GPU link 2616 and can connect directly to GPGPUs 2606A-D.

[0415] In at least one embodiment, Figure 26 At least one component shown or described is used to implement the combination Figure 1-13 Techniques and / or functions described herein. In at least one embodiment, at least one GPGPU 2606 is used to perform rate matching. In at least one embodiment, rate matching includes causing 5G new radio signal information to be selected in parallel using parameters based at least in part on a 5G standard. In at least one embodiment, at least one GPGPU 2606 is used to perform at least one aspect described with respect to rate matching 114, example process 300, data flow 400, example process 500, example process 600, example process 900, chart 1100, example process 1200, example process 1300, algorithm one described at least in conjunction with step 1314 of example process 1300, algorithm two described at least in conjunction with step 1316 of example process 1300, and / or algorithm three described at least in conjunction with step 1320 of example process 1300. In at least one embodiment, processor 2602 executes a kernel launch function that passes parameters to a kernel that executes the kernel in conjunction with Figure 1-13 Described is rate matching of at least one kernel on at least one GPGPU 2606.

[0416] Figure 27 FIG2 is a block diagram of a graphics processor 2700 according to at least one embodiment. In at least one embodiment, graphics processor 2700 includes a ring interconnect 2702, a pipeline front end 2704, a media engine 2737, and graphics cores 2780A-2780N. In at least one embodiment, ring interconnect 2702 couples graphics processor 2700 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor 2700 is one of many processors integrated within a multi-core processing system.

[0417] In at least one embodiment, the graphics processor 2700 receives batches of commands via a ring interconnect 2702. In at least one embodiment, the incoming commands are interpreted by a command streamer 2703 in a pipeline front end 2704. In at least one embodiment, the graphics processor 2700 includes scalable execution logic for performing 3D geometry processing and media processing via graphics cores 2780A-2780N. In at least one embodiment, for 3D geometry processing commands, the command streamer 2703 provides the commands to a geometry pipeline 2736. In at least one embodiment, for at least some media processing commands, the command streamer 2703 provides the commands to a video front end 2734, which is coupled to a media engine 2737. In at least one embodiment, the media engine 2737 includes a video quality engine (VQE) 2730 for video and image post-processing, and a multi-format encoding / decoding (MFX) 2733 engine for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 2736 and the media engine 2737 each generate execution threads for thread execution resources provided by at least one graphics core 2780A.

[0418] In at least one embodiment, the graphics processor 2700 includes scalable thread execution resources featuring modular cores 2780A-2780N (sometimes referred to as core slices), each of which has multiple sub-cores 2750A-2750N, 2760A-2760N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 2700 can have any number of graphics cores 2780A-2780N. In at least one embodiment, the graphics processor 2700 includes a graphics core 2780A having at least a first sub-core 2750A and a second sub-core 2760A. In at least one embodiment, the graphics processor 2700 is a low-power processor having a single sub-core (e.g., 2750A). In at least one embodiment, the graphics processor 2700 includes multiple graphics cores 2780A-2780N, each of which includes a set of first sub-cores 2750A-2750N and a set of second sub-cores 2760A-2760N. In at least one embodiment, each of the first sub-cores 2750A-2750N includes at least a first set of execution units 2752A-2752N and media / texture samplers 2754A-2754N. In at least one embodiment, each of the second sub-cores 2760A-2760N includes at least a second set of execution units 2762A-2762N and samplers 2764A-2764N. In at least one embodiment, each of the sub-cores 2750A-2750N, 2760A-2760N shares a set of shared resources 2770A-2770N. In at least one embodiment, the shared resources include shared cache memory and pixel operation logic.

[0419] In at least one embodiment, Figure 27 At least one component shown or described is used to implement the combination Figure 1-13 The techniques and / or functions described herein are described. In at least one embodiment, at least one graphics processor 2700 is configured to perform rate matching. In at least one embodiment, rate matching includes causing 5G new radio signal information to be selected in parallel using parameters based at least in part on the 5G standard. In at least one embodiment, at least one graphics processor 2700 is configured to perform at least one aspect described with respect to rate matching 114, example process 300, data flow 400, example process 500, example process 600, example process 900, chart 1100, example process 1200, example process 1300, algorithm 1 described at least in conjunction with step 1314 of example process 1300, algorithm 2 described at least in conjunction with step 1316 of example process 1300, and / or algorithm 3 described at least in conjunction with step 1320 of example process 1300.

[0420] Figure 28is a block diagram illustrating a microarchitecture for a processor 2800 that may include logic circuitry for executing instructions, according to at least one embodiment. In at least one embodiment, the processor 2800 may execute instructions including x86 instructions, ARM instructions, specialized instructions for an application-specific integrated circuit (ASIC), and the like. In at least one embodiment, the processor 2810 may include registers for storing packed data, such as the 64-bit wide MMX registers in microprocessors enabled with MMX technology from Intel Corporation of Santa Clara, California. TM Registers. In at least one embodiment, MMX registers available in integer and floating-point form can operate with packed data elements with Single Instruction Multiple Data ("SIMD") and Streaming SIMD Extensions ("SSE") instructions. In at least one embodiment, 128-bit wide XMM registers associated with SSE2, SSE3, SSE4, AVX, or later (generally referred to as "SSEx") technology can hold such packed data operands. In at least one embodiment, processor 2810 can execute instructions to accelerate machine learning or deep learning algorithms, training, or inference.

[0421] In at least one embodiment, processor 2800 includes an in-order front end ("front end") 2801 to fetch instructions for execution and prepare them for later use in the processor pipeline. In at least one embodiment, front end 2801 may include several units. In at least one embodiment, instruction prefetcher 2826 retrieves instructions from memory and provides them to instruction decoder 2828, which in turn decodes or interprets the instructions. For example, in at least one embodiment, instruction decoder 2828 decodes received instructions into one or more so-called "microinstructions" or "micro-operations" (also referred to as "micro-ops" or "microinstructions") that the machine can execute. In at least one embodiment, instruction decoder 2828 parses the instructions into opcodes and corresponding data and control fields, which can be used by the microarchitecture to perform the operations according to at least one embodiment. In at least one embodiment, trace cache 2830 can assemble the decoded microinstructions into a program-ordered sequence or trace in microinstruction queue 2834 for execution. In at least one embodiment, when trace cache 2830 encounters a complex instruction, microcode ROM 2832 provides the microinstructions necessary to complete the operation.

[0422] In at least one embodiment, some instructions may be converted into a single micro-op, while other instructions may require several micro-ops to complete the entire operation. In at least one embodiment, if more than four micro-ops are required to complete an instruction, the instruction decoder 2828 may access the microcode ROM 2832 to execute the instruction. In at least one embodiment, an instruction may be decoded into a smaller number of micro-ops for processing at the instruction decoder 2828. In at least one embodiment, if multiple micro-ops are required to complete the operation, the instruction may be stored in the microcode ROM 2832. In at least one embodiment, the trace cache 2830 references the entry point programmable logic array ("PLA") to determine the correct micro-op pointer for reading the microcode sequence from the microcode ROM 2832 to complete one or more instructions according to at least one embodiment. In at least one embodiment, after the microcode ROM 2832 completes the micro-op sequencing for the instruction, the front end 2801 of the machine may resume fetching micro-ops from the trace cache 2830.

[0423] In at least one embodiment, an out-of-order execution engine ("OOO engine") 2803 can prepare instructions for execution. In at least one embodiment, the OOO logic has multiple buffers to smooth and reorder the instruction flow to optimize performance as instructions flow down the pipeline and are scheduled for execution. The OOO engine 2803 includes, but is not limited to, an allocator / register renamer 2840, a memory microinstruction queue 2842, an integer / floating-point microinstruction queue 2844, a memory scheduler 2846, a fast scheduler 2802, a slow / general purpose floating-point scheduler ("slow / general purpose FP scheduler") 2804, and a simple floating-point scheduler ("simple FP scheduler") 2806. In at least one embodiment, the fast scheduler 2802, the slow / general purpose floating-point scheduler 2804, and the simple floating-point scheduler 2806 are also collectively referred to as "microinstruction schedulers 2802, 2804, 2806." In at least one embodiment, the allocator / register renamer 2840 allocates the machine buffers and resources required for each microinstruction to execute in sequence. In at least one embodiment, the allocator / register renamer 2840 renames logical registers into entries in the register file. In at least one embodiment, the allocator / register renamer 2840 also allocates an entry for each microinstruction in one of two microinstruction queues: a memory microinstruction queue 2842 for memory operations and an integer / floating-point microinstruction queue 2844 for non-memory operations, preceding the memory scheduler 2846 and the microinstruction schedulers 2802, 2804, and 2806. In at least one embodiment, the microinstruction schedulers 2802, 2804, and 2806 determine when a microinstruction is ready to execute based on the readiness of its dependent input register operand sources and the availability of the execution resource microinstructions that need to be completed. The fast scheduler 2802 of at least one embodiment can schedule every half of the main clock cycle, while the slow / general floating-point scheduler 2804 and the simple floating-point scheduler 2806 can schedule once per main processor clock cycle. In at least one embodiment, microinstruction schedulers 2802, 2804, 2806 arbitrate on dispatch ports to schedule microinstructions for execution.

[0424] In at least one embodiment, execution block b11 includes, but is not limited to, an integer register file / branch network 2808, a floating-point register file / branch network ("FP register file / branch network") 2810, address generation units ("AGUs") 2812 and 2814, fast arithmetic logic units ("fast ALUs") 2816 and 2818, a slow arithmetic logic unit ("slow ALU") 2820, a floating-point ALU ("FP") 2822, and a floating-point move unit ("FP move") 2824. In at least one embodiment, integer register file / branch network 2808 and floating-point register file / bypass network 2810 are also referred to herein as "register files 2808, 2810." In at least one embodiment, AGUs 2812 and 2814, fast ALUs 2816 and 2818, slow ALU 2820, floating-point ALU 2822, and floating-point move unit 2824 are also referred to herein as "execution units 2812, 2814, 2816, 2818, 2820, 2822, and 2824." In at least one embodiment, execution block 2811 may include, but is not limited to, any number (including zero) and type of register files, branch networks, address generation units, and execution units (in any combination).

[0425] In at least one embodiment, register files 2808 and 2810 may be arranged between microinstruction schedulers 2802, 2804, and 2806 and execution units 2812, 2814, 2816, 2818, 2820, 2822, and 2824. In at least one embodiment, integer register file / branch network 2808 performs integer operations. In at least one embodiment, floating-point register file / branch network 2810 performs floating-point operations. In at least one embodiment, each of register files 2808 and 2810 may include, but is not limited to, a branch network that can bypass or forward recently completed results that have not yet been written to the register file to new dependent objects. In at least one embodiment, register files 2808 and 2810 can communicate data with each other. In at least one embodiment, integer register file / branch network 2808 may include, but is not limited to, two separate register files: one register file for low-order 32-bit data and a second register file for high-order 32-bit data. In at least one embodiment, floating point register file / branch network 2810 may include, but is not limited to, 128-bit wide entries, as floating point instructions typically have operands that are 64 to 128 bits wide.

[0426] In at least one embodiment, execution units 2812, 2814, 2816, 2818, 2820, 2822, and 2824 can execute instructions. In at least one embodiment, register files 2808 and 2810 store integer and floating-point data operand values ​​required for microinstructions to execute. In at least one embodiment, processor 2800 can include, but is not limited to, any number of execution units 2812, 2814, 2816, 2818, 2820, 2822, and 2824, and any combination thereof. In at least one embodiment, floating-point ALU 2822 and floating-point move unit 2824 can execute floating-point, MMX, SIMD, AVX, SSE, or other operations, including specialized machine learning instructions. In at least one embodiment, floating-point ALU 2822 can include, but is not limited to, a 64-bit by 64-bit floating-point divider to perform division, square root, and remainder micro-operations. In at least one embodiment, floating-point hardware can be used to process instructions involving floating-point values. In at least one embodiment, ALU operations can be passed to fast ALUs 2816 and 2818. In at least one embodiment, fast ALUs 2816 and 2818 can perform fast operations with an effective latency of half a clock cycle. In at least one embodiment, most complex integer operations go to slow ALU 2820, as slow ALU 2820 may include, but is not limited to, integer execution hardware for long-latency operations, such as multipliers, shifts, flag logic, and branch processing. In at least one embodiment, memory load / store operations can be performed by ALUs 2812 and 2814. In at least one embodiment, fast ALUs 2816, 2818, and slow ALU 2820 can perform integer operations on 64-bit data operands. In at least one embodiment, fast ALUs 2816, 2818, and slow ALU 2820 can be implemented to support various data bit sizes, including 16, 32, 128, 256, and the like. In at least one embodiment, the floating point ALU 2822 and floating point shift unit 2824 can be implemented to support a range of operands having bits of various widths. In at least one embodiment, the floating point ALU 2822 and floating point shift unit 2824 can operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

[0427] In at least one embodiment, microinstruction schedulers 2802, 2804, and 2806 schedule dependent operations before the parent load completes execution. In at least one embodiment, because microinstructions can be speculatively scheduled and executed in processor 2800, processor 2800 may also include logic for handling memory misses. In at least one embodiment, if a data load misses in the data cache, there may be dependent operations running in the pipeline, temporarily preventing the scheduler from having the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, it may be necessary to replay dependent operations and allow independent operations to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor may also be designed to capture instruction sequences for text string comparison operations.

[0428] In at least one embodiment, the term "register" may refer to an on-board processor storage location that can be used as part of an instruction to identify an operand. In at least one embodiment, registers may be those that can be used from outside the processor (from a programmer's perspective). In at least one embodiment, registers may not be limited to a particular type of circuit. Instead, in at least one embodiment, registers can store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein can be implemented by circuitry within the processor using a variety of different techniques, such as dedicated physical registers, physical registers dynamically allocated using register renaming, a combination of dedicated and dynamically allocated physical registers, and the like. In at least one embodiment, integer registers store 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for packing data.

[0429] In at least one embodiment, Figure 28 At least one component shown or described is used to implement the combination Figure 1-13 The techniques and / or functions described herein are described. In at least one embodiment, at least one processor 2800 is configured to perform rate matching. In at least one embodiment, rate matching includes causing 5G new radio signal information to be selected in parallel using parameters based at least in part on the 5G standard. In at least one embodiment, at least one processor 2800 is configured to perform at least one aspect described with respect to rate matching 114, example process 300, data flow 400, example process 500, example process 600, example process 900, chart 1100, example process 1200, example process 1300, algorithm 1 described in conjunction with at least step 1314 of example process 1300, algorithm 2 described in conjunction with at least step 1316 of example process 1300, and / or algorithm 3 described in conjunction with at least step 1320 of example process 1300.

[0430] Figure 29 A block diagram of a processing system according to at least one embodiment is shown. In at least one embodiment, system 2900 includes one or more processors 2902 and one or more graphics processors 2908, and can be a single-processor desktop system, a multi-processor workstation system, or a server system with a large number of processors 2902 or processor cores 2907. In at least one embodiment, system 2900 is a processing platform incorporated within a system-on-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

[0431] In at least one embodiment, the system 2900 may include or be incorporated into a server-based gaming platform, including a gaming console, a mobile gaming console, a handheld gaming console, or an online gaming console, including a gaming and media console. In at least one embodiment, the system 2900 is a mobile phone, a smart phone, a tablet computing device, or a mobile internet device. In at least one embodiment, the processing system 2900 may also include a device coupled to or integrated into a wearable device, such as a smartwatch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device. In at least one embodiment, the processing system 2900 is a television or set-top box device having one or more processors 2902 and a graphical interface generated by one or more graphics processors 2908.

[0432] In at least one embodiment, one or more processors 2902 each include one or more processor cores 2907 to process instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of the one or more processor cores 2907 is configured to process a specific instruction set 2909. In at least one embodiment, the instruction set 2909 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction words (VLIW). In at least one embodiment, the processor cores 2907 can each process a different instruction set 2909, which can include instructions that facilitate emulation of other instruction sets. In at least one embodiment, the processor cores 2907 can also include other processing devices, such as a digital ...

Claims

1. A processor, comprising: One or more circuits for matching a transmission rate and a reception rate of fifth generation (5G) new radio (5G NR) signal information based at least in part on selecting the 5G NR signal information in parallel.

2. The processor of claim 1, wherein the 5G NR signal information comprises data values ​​from a sequence for performing rate matching on one or more low density parity check codes.

3. The processor of claim 1 , wherein the 5G NR signal information is selected by a plurality of threads, each of the plurality of threads being configured to select a respective subset of a set of data values ​​from a sequence.

4. The processor of claim 1 , wherein the 5G NR signal information is selected based at least in part on available data transmission resources.

5. The processor of claim 1, wherein the spectrum used for the 5G NR signal information is shared with fourth generation 4G radio signals.

6. The processor of claim 1, wherein the one or more circuits are configured to cause the 5G radio signal information to be selected in parallel using a plurality of parallel threads.

7. The processor of claim 1, wherein the one or more circuits are configured to cause the 5G radio signal information to be selected in parallel using a plurality of threads, wherein each of the plurality of threads selects a corresponding bit from a sequence for rate matching.

8. The processor of claim 1, wherein the processor is a graphics processing unit (GPU).

9. The processor of claim 1, wherein the one or more circuits are configured to select an algorithm for selecting the 5G NR information based at least in part on a sequence of empty positions in a vector.

10. The processor of claim 1, wherein the one or more circuits are configured to cause the 5G NR information to be selected in parallel by launching a plurality of threads, wherein each thread of the plurality of threads is configured to select a bit from the sequence independently of any previously selected bit in the sequence.

11. The processor of claim 1 , wherein the one or more circuits are configured to select an algorithm for selecting the 5G NR information based at least in part on a low density parity check parameter and an incremental redundancy version index.

12. A system comprising: One or more processors configured to match a transmission rate and a reception rate of fifth generation (5G) new radio (5G NR) signal information based at least in part on selecting the 5G NR signal information in parallel.

13. The system of claim 12, wherein the one or more processors cause the 5G NR signal information to be selected using a rate matching algorithm.

14. The system of claim 12, wherein the one or more processors cause the 5G NR signal information to be selected using an initial index.

15. The system of claim 12, wherein the one or more processors cause the 5G NR signal information to be selected based at least in part on determining that an initial index indicates a position within the 5G NR signal information that precedes a group of consecutive null values ​​in the 5G NR signal information.

16. The system of claim 12, wherein the one or more processors cause the 5G NR signal information to be selected based at least in part on determining that an initial index indicates a position within the 5G NR signal information that is located after a group of consecutive null values ​​in the 5G NR signal information.

17. The system of claim 12, wherein the one or more processors cause the 5G NR signal information to be selected based at least in part on determining that an initial index indicates a position within the 5G NR signal information that is within a set of consecutive null values ​​in the 5G NR signal information.

18. The system of claim 12, wherein the 5G NR information is selected from a single code block based at least in part on a maximum code block size associated with the 5G NR information.

19. The system of claim 12, wherein the 5G NR information is selected from a plurality of code blocks based at least in part on a maximum code block size associated with the 5G NR information.

20. The system of claim 12, wherein the 5G NR information is selected from a circular buffer.

21. A non-transitory machine-readable medium having stored thereon a set of instructions that, if executed by one or more processors, cause the one or more processors to at least: The transmission rate and reception rate of the fifth generation 5G new radio 5G NR signal information are matched based at least in part on selecting the 5G NR signal information in parallel.

22. The non-transitory machine-readable medium of claim 21, wherein the 5G NR signal information comprises bits from a sequence for performing rate matching on one or more low-density parity-check codes.

23. The non-transitory machine-readable medium of claim 21 , wherein the set of instructions, if executed, further causes the one or more processors to at least: The 5G NR signal information is selected using a rate matching algorithm.

24. The non-transitory machine-readable medium of claim 21, wherein the set of instructions, if executed, further causes the one or more processors to at least: An algorithm for selecting the 5G NR information is selected based at least in part on a low density parity check parameter and an incremental redundancy version index.

25. The non-transitory machine-readable medium of claim 21, wherein the set of instructions, if executed, further causes the one or more processors to at least: The 5G NR signal information is selected in parallel using multiple threads.

26. The non-transitory machine-readable medium of claim 21, wherein the set of instructions, if executed, further causes the one or more processors to at least: determining the number of data elements in the 5GNR signal; and The 5G NR signal information is selected in parallel using a number of threads equal to the number of the data elements.

27. The non-transitory machine-readable medium of claim 21, wherein the set of instructions, if executed, further causes the one or more processors to at least: Determining the number of data elements in a 5G NR signal; and The 5G NR signal information is selected in parallel using a number of threads that is less than the number of the data elements.

28. The non-transitory machine-readable medium of claim 21, wherein the set of instructions, if executed, further causes the one or more processors to at least: determining the number of data elements in the 5GNR signal; and The 5G NR signal information is selected in parallel using a number of threads greater than the number of data elements.

29. A method comprising: The transmission rate and reception rate of the fifth generation 5G new radio 5G NR signal information are matched based at least in part on selecting the 5G NR signal information in parallel.

30. The method of claim 29, wherein the 5G NR signal information comprises bits from a sequence for performing rate matching on one or more low density parity check codes.

31. The method of claim 29, wherein the 5G NR signal information is selected by a plurality of threads, each of the plurality of threads being used to select a corresponding subset of a set of bits from a sequence.

32. The method of claim 29, wherein the 5G NR signal information is selected based at least in part on available data transmission resources.

33. The method of claim 29, wherein the spectrum used for the 5G NR signal information is shared with fourth generation 4G radio signals.

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