Display panel and display device

Abstract

The present invention relates to a display panel and a display device. The display panel includes pixels arranged in a pixel layout. Each data line group is composed of three consecutively arranged data lines: a data line for a first color, a data line for a second color, and a data line for a third color. An additional data line for the first color is arranged outside the data line group. Each pixel circuit for the first color in each pixel circuit column pair is supplied with a data signal from a data line for the first color that is closer to a data line for the first color in the associated data line group and a pixel circuit outside the associated data line group that is adjacent to a data line for the first color in the associated data line group.

Description

Technical Field

[0001] The present invention relates to a display panel and a display device. Background Art

[0002] Organic light-emitting diode (OLED) display devices have been proposed as an alternative to liquid crystal display devices. OLED elements are current-driven light-emitting elements and therefore do not require a backlight. OLED elements also offer the advantages of low power consumption, wide viewing angles, and high contrast; they are expected to contribute to the development of flat-panel display devices.

[0003] A typical active matrix color OLED display device has a display area consisting of red (R), green (G), and blue (B) sub-pixels arranged on a substrate of a display panel. Various sub-pixel layouts (pixel layouts) have been proposed; for example, RGB stripe layouts and delta- (delta-nabla) layout (also referred to as delta layout). Summary of the Invention

[0004] A display device may include a demultiplexer (DeMUX) circuit to output data signals using a driver circuit with a small number of pins. Each output pin of the driver circuit is associated with multiple data lines, and the demultiplexer circuit selects the multiple data lines one by one to output data signals from the output pins. In a configuration where one data line transmits data signals for pixel circuits of sub-pixels of different colors, insufficient data signals written to the pixel circuits may become a problem.

[0005] One aspect of the present invention is a display panel in which pixels of three colors, namely, a first color, a second color, and a third color, are arranged in a Δ- The display panel is arranged in a layout. The display panel includes: a plurality of pixel circuit columns; and a plurality of data lines. The plurality of pixel circuit columns extend in a first direction and are arranged side by side in a second direction perpendicular to the first direction. Each of the plurality of pixel circuit columns is composed of pixel circuits for three colors arranged in a cycle. Each of the pixel circuits for the three colors is configured to control the light intensity of pixels of the same color assigned to the pixel circuit. The plurality of pixel circuit columns constitute a plurality of pixel circuit column pairs, each pixel circuit column pair consisting of two adjacent pixel circuit columns. The plurality of data lines extend in the first direction and are arranged side by side in the second direction. The plurality of data lines are data lines for the three colors arranged in a cycle. Each of the plurality of data lines is configured to transmit a data signal to the pixel circuit for the same color assigned to the data line. The plurality of data lines includes a plurality of data line groups, each data line group consisting of three data lines arranged in a row: a data line for the first color, a data line for the second color, and a data line for the third color. The plurality of data lines includes an additional data line for the first color arranged outside the plurality of data line groups. Each of the plurality of pixel circuit column pairs is associated with a different data line group. Each pixel circuit for the first color in each of the plurality of pixel circuit column pairs is supplied with a data signal from a data line for the first color that is closer to a pixel circuit between a data line for the first color in the associated data line group and a data line for the first color that is adjacent to a data line for the third color in the associated data line group outside the associated data line group.

[0006] One aspect of the present invention improves display quality.

[0007] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 Schematically shows an example configuration of an OLED display device;

[0009] Figure 2A An example of a pixel circuit is shown;

[0010] Figure 2B Another example of a pixel circuit is shown;

[0011] Figure 3 Shows Δ- Pixel layout in the panel;

[0012] Figure 4 The circuit layout in one embodiment of the present specification is shown, including sub-pixels (light-emitting areas), pixel circuits, scan lines, and data lines;

[0013] Figure 5 A diagram for explaining a lead portion connecting a data line and a pixel circuit;

[0014] Figure 6A Schematically shows the arrangement Figure 4 An example configuration of a demultiplexer circuit between the data lines and the driver IC is shown;

[0015] Figure 6B shows a configuration example of a 1:4 DeMUX circuit;

[0016] Figure 7 Schematically shows the arrangement Figure 4 Another configuration example of a demultiplexer circuit between the data lines and the driver IC shown;

[0017] Figure 8 Shown with Figure 4 The configuration example shown corresponds to an example of a circuit layout near the end of the display area;

[0018] Figure 9 shows a configuration example of a circuit layout in which each pixel circuit for green occupies a larger area than both the pixel circuit for red and the pixel circuit for blue;

[0019] Figure 10 Another example of a circuit layout is shown;

[0020] Figure 11 shows a circuit layout in another embodiment of the present specification;

[0021] Figure 12 Shown according to Figure 11 Wider areas of the circuit layout in the

[0022] Figure 13 Shown is the Figure 12 This is an example configuration of a 1:2 demultiplexer circuit that outputs data signals to the data lines in FIG. DETAILED DESCRIPTION

[0023] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. It should be noted that the embodiments are merely examples for implementing the present invention and do not limit the technical scope of the present invention. The same elements in the accompanying drawings are represented by the same reference numerals.

[0024] The display device may include a demultiplexer (DeMUX) circuit to output data signals using a driver circuit with a smaller number of pins. Each output pin of the driver circuit is associated with a plurality of data lines, and the demultiplexer circuit selects the plurality of data lines one by one to output data signals from the output pins.

[0025] For a configuration known as color rotation (one data line transmits data signals to pixel circuits for sub-pixels of different colors), it is necessary that each pixel circuit for a particular color should not receive a data signal for the wrong color. The scan drive must be controlled so that the data writing periods for pixel circuits for different colors connected to one data line do not overlap. This control can be achieved by specifying intermittent data writing periods for multiple pixel circuits connected to one data line. However, in a display device driven by high resolution or high frame rate, each data writing period is short; the problem of insufficient data signals being written to the pixel circuits may arise.

[0026] Including the existing Δ- The display device supplies data signals by color rotation. In order to supply data signals without color rotation, a complex structure of a wiring portion for connecting a data line and a pixel circuit is required.

[0027] The inventors have studied the Δ- The circuit layout of the display panel, particularly the layout of the pixel circuits used to control pixels and data lines, is disclosed. A display panel in one embodiment of the present disclosure includes a demultiplexer circuit, but obtains data signals without color rotation, with minimal interference with the pixel circuit design. This reduces degradation in display performance caused by insufficient data signal writes.

[0028] Implementation Method 1

[0029] Display device configuration

[0030] refer to Figure 1 The overall configuration of the display device in this embodiment is described. For a clearer understanding of the description, the elements in the drawings may be exaggerated in size or shape. Hereinafter, an organic light-emitting diode (OLED) display device is described as an example of a display device; however, the features of the present invention are applicable to display devices of a type other than an OLED display device. The features of the present invention are particularly advantageous for display devices that display images using self-luminous elements.

[0031] Figure 1The figure schematically illustrates an example configuration of an OLED display device 10. The OLED display device 10 includes an OLED display panel and a control device. The OLED display panel includes a thin film transistor (TFT) substrate 100 on which an OLED element (light-emitting element) is fabricated, an encapsulation substrate 200 for encapsulating the OLED element, and an adhesive (frit sealant) 300 for bonding the TFT substrate 100 and the encapsulation substrate 200.

[0032] The space between the TFT substrate 100 and the encapsulation substrate 200 is filled with dry nitrogen or dry air and sealed with adhesive 300. Instead of the encapsulation substrate 200, a structural encapsulation unit having a different structure, for example, a structural encapsulation unit using thin film encapsulation (TFE) may be used.

[0033] A scan driver 131, a light emitting driver 132, a protection circuit 133, a demultiplexer circuit (DeMUX) 136, and a driver IC 134 are provided on the periphery of the cathode electrode region 114 outside the display region 125 of the TFT substrate 100. These components are connected to an external device via a flexible printed circuit (FPC) 135. The driver IC 134, the scan driver 131, the light emitting driver 132, the protection circuit 133, and the demultiplexer circuit 136 are included in a control device.

[0034] The scanning driver 131 drives the scanning lines on the TFT substrate 100. The light emitting driver 132 drives the light emitting control lines to control the light emitting period of the sub-pixels. The protection circuit 133 protects the elements from electrostatic discharge. The driver IC 134 is mounted with an anisotropic conductive film (ACF), for example.

[0035] The driver IC 134 supplies power and timing signals (control signals) to the scan driver 131 and the light emitting driver 132, and also supplies power, control signals, and data signals to the demultiplexer circuit 136. The demultiplexer circuit 136 sequentially outputs the output of one pin of the driver IC 134 to d data lines (d is an integer greater than 1). The demultiplexer circuit 136 changes the output data line for the data signal from the driver IC 134 d times per scan period to drive d times as many data lines as the output pin of the driver IC 134 (1:d DeMUX).

[0036] exist Figure 1In the figure, the axis extending from left to right is called the X-axis, and the axis extending from top to bottom is called the Y-axis. These axes are orthogonal to each other. The scan line extends along the X-axis, and the data line extends along the Y-axis. These transmission lines can be straight or partially curved. Pixels or sub-pixels arranged along the X-axis in the display area 125 are called pixel rows or sub-pixel rows; pixels or sub-pixels arranged along the Y-axis in the display area 125 are called pixel columns or sub-pixel columns. The circuit for controlling the light emission of the sub-pixels is called a pixel circuit. The following description may simply refer to a light-emitting area or sub-pixel as a pixel.

[0037] In this embodiment, the display area 125 is formed by forming a Δ- The insulating substrate is a flexible or non-flexible substrate made of glass or resin. The details of the layout will be described later. A sub-pixel is a light-emitting area for displaying one of the colors red (R), green (G), and blue (B). The example described below displays an image with a combination of these three colors.

[0038] The light-emitting region is included in an OLED element, which includes an anode electrode as the lower electrode, an organic light-emitting film, and a cathode electrode as the upper electrode. Multiple OLED elements are made up of a cathode electrode, multiple anode electrodes, and multiple organic light-emitting films. The area where the organic light-emitting film contacts the anode electrode is the light-emitting region, or sub-pixel.

[0039] pixel circuit

[0040] A plurality of pixel circuits are fabricated on the TFT substrate 100 to control current to be supplied to anode electrodes of sub-pixels. Figure 2A 1 shows an example configuration of a pixel circuit. Each pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor C. The pixel circuit controls the light emission of the OLED element E1 of the sub-pixel. These transistors are thin film transistors (TFTs). Hereinafter, the first transistor T1 to the third transistor T3 are referred to as transistors T1 to T3.

[0041] The transistor T2 is a switch for selecting a sub-pixel and is a p-channel TFT having a gate terminal connected to the scan line 106, a drain terminal connected to the data line (Vdata) 105, and a source terminal connected to the gate terminal of the transistor T1.

[0042] Transistor T1 is a transistor (driving TFT) for driving OLED element E1. Transistor T1 is a p-channel TFT, and its gate terminal is connected to the source terminal of transistor T2. The source terminal of transistor T1 is connected to power supply line (VDD) 108. Its drain terminal is connected to the source terminal of transistor T3. A storage capacitor C is provided between the gate terminal and source terminal of transistor T1.

[0043] Transistor T3 is a switch for controlling the supply and stop of drive current to OLED element E1. Transistor T3 is a p-channel TFT, and its gate terminal is connected to emission control line 107. The source terminal of transistor T3 is connected to the drain terminal of transistor T1. The drain terminal of transistor T3 is also connected to OLED element E1.

[0044] Next, the operation of the pixel circuit will be described. Scan driver 131 outputs a select pulse to scan line 106 to turn on transistor T2. The data voltage supplied from driver IC 134 via data line 105 is stored in storage capacitor C. Storage capacitor C retains the stored voltage for one frame period. The conductance of transistor T1 changes in an analog manner based on the stored voltage, causing transistor T1 to supply a forward bias current corresponding to the emission grayscale to OLED element E1.

[0045] Transistor T3 is located in the supply path of the drive current. The light-emitting driver 132 outputs a control signal to the light-emitting control line 107 to control the on / off switching of transistor T3. When transistor T3 is on, the drive current is supplied to the OLED element E1. When transistor T3 is off, the supply of drive current is stopped. The lighting period (duty cycle) within a frame period can be controlled by controlling the on / off switching of transistor T3.

[0046] Figure 2B Another configuration example of a pixel circuit in one embodiment of the present specification is shown. The pixel circuit is included in the kth pixel circuit row (k is an integer). The pixel circuit includes six transistors (TFTs) P1 to P6, each of which has a gate, a source, and a drain. All transistors P1 to P6 in this example are p-type TFTs.

[0047] Transistor P1 is a drive transistor for controlling the amount of current flowing to OLED element E1. The source of drive transistor P1 is connected to power line 241, which transmits a positive power supply potential VDD. Drive transistor P1 controls the amount of current supplied from power line 241 to OLED element E1 based on the voltage stored in series-connected storage capacitors C1 and C2. Storage capacitors C1 and C2 hold the written voltage for one frame period. The cathode of OLED element E1 is connected to power line 204, which transmits a negative power supply potential VEE from a cathode power supply.

[0048] Capacitors C1 and C2 are connected in series between power line 241, which transmits a positive power supply potential VDD, and the gate of driver transistor P1. One end of capacitor C1 is connected to power line 241, and the other end of capacitor C1 is connected to one end of capacitor C2. The other end of capacitor C2 is connected to the gate of driver transistor P1. The source / drain of transistor P4 and the source / drain of transistor P2 are connected to an intermediate node between capacitors C1 and C2.

[0049] The composite capacitor of the series-connected storage capacitor elements C1 and C2 stores the voltage between the gate of the drive transistor P1 and the power supply line 241 or the source of the drive transistor P1. The source of the drive transistor P1 is connected to the power supply line 241; the source potential is at the positive power supply potential VDD. Therefore, the storage capacitor elements C1 and C2 store the gate-source voltage of the drive transistor P1.

[0050] Transistor P5 is a light emission control switching transistor that controls the start / stop of the supply of drive current to OLED element E1 and, consequently, the start / stop of light emission from OLED element E1. The source of transistor P5 is connected to the drain of drive transistor P1. Transistor P5 switches the start / stop of the current supply to OLED element E1, which is connected to its drain. The gate of transistor P5 is connected to control signal line 233, which transmits a light emission control signal Em. Transistor P5 is controlled by the light emission control signal Em from light emission driver 132. The light emission control signal Em is a selection signal for controlling the light emission of OLED element E1.

[0051] The transistor P6 is used to supply the reset potential Vrst to the anode of the OLED element E1. One end of the source / drain of the transistor P6 is connected to the power supply line 242 for transmitting the reset potential Vrst, and the other end is connected to the anode of the OLED element E1.

[0052] The gate of transistor P6 is connected to the control signal line 231 for transmitting the selection signal S1, and transistor P6 is controlled by the selection signal S1. When transistor P6 is turned on by the selection signal S1 from the scan driver 131, transistor P6 supplies the reset potential Vrst transmitted by the power line 242 to the anode of the OLED element E1.

[0053] Transistors P5 and P6 also supply a reset potential Vrst to the gate electrode of the driving transistor P1 and one electrode of the storage capacitor element C2 via transistor P3. Therefore, the charge stored in the anode electrode of the OLED element E1 and the storage capacitor elements C1 and C2 in the previous frame is discharged via transistor P6, and the gate potential of the driving transistor P1 is reset (initialized).

[0054] Transistor P3 is a switching transistor (threshold compensation transistor) for writing a voltage for applying threshold calibration (threshold compensation) to drive transistor P1 into storage capacitors C1 and C2. It is also a transistor for resetting the gate potential of drive transistor P1. The source and drain of transistor P3 are connected to the gate and drain of drive transistor P1. Therefore, when transistor P3 is turned on, drive transistor P1 is diode-connected.

[0055] Transistor P4 is used to write the voltage for applying threshold compensation to drive transistor P1 into storage capacitor elements C1 and C2. Transistor P4 controls whether to supply reference potential Vref to storage capacitor elements C1 and C2. Reference potential Vref can be equal to positive power supply potential VDD. Thus, a transmission line (power line) can be shared between reference potential Vref and positive power supply potential VDD. One end of the source / drain of transistor P4 is connected to the power line 202 for transmitting reference potential Vref, and the other end is connected to the intermediate node between capacitor elements C1 and C2. The gate of transistor P4 is connected to the control signal line 231 for transmitting selection signal S1, and transistor P4 is controlled by the selection signal S1 input to its gate from scan driver 131.

[0056] Transistors P3, P6, and P4 are controlled by a select signal S1. Therefore, these transistors P3, P6, and P4 are turned on / off simultaneously. During the period when these transistors are on, transistor P5 is turned on to reset the gate potential of drive transistor P1 and then turned off. When transistors P3 and P4 are on, transistor P1 is a diode-connected transistor. A threshold compensation voltage based on the positive power supply potential VDD and the reference potential Vref is written into storage capacitor elements C1 and C2.

[0057] Transistor P2 is a switching transistor for selecting a pixel circuit to which a data signal is to be supplied and for writing the data signal (data signal voltage) Vdata into the storage capacitor elements C1 and C2. One end of the source / drain of transistor P2 is connected to the storage capacitor elements C2 and C1, and the other end is connected to the data line 237 for transmitting the data signal Vdata.

[0058] The gate of transistor P2 is connected to a control signal line 232 for transmitting a selection signal S2 from scan driver 131. Transistor P2 is controlled by selection signal S2. Selection signal S2 is a signal different from selection signal S1. For this pixel circuit, selection signal S2 is a selection signal for controlling the supply of data signal Vdata to storage capacitor elements C1 and C2. When transistor P2 is turned on, transistor P2 supplies data signal Vdata supplied from driver IC 134 via data line 237 to storage capacitor elements C1 and C2.

[0059] Δ- Pixel layout in panels

[0060] Figure 3 Shows Δ- The layout of pixels (sub-pixels) in the panel. Figure 3 A partial area of ​​the display area 125 is schematically shown. The display area 125 is composed of a plurality of red sub-pixels 41R, a plurality of green sub-pixels 41G, and a plurality of blue sub-pixels 41B arranged in a plane. Each sub-pixel is a light-emitting area for light of one color. Figure 3 , as an example, one of the red sub-pixels, one of the green sub-pixels, and one of the blue sub-pixels are provided with reference numerals. Figure 3 The rounded rectangles of the same shade in the figure represent sub-pixels of the same color. Figure 3 The sub-pixels in FIG have a rectangular shape, but the sub-pixels may have a desired shape, such as a hexagonal or octagonal shape.

[0061] The display area 125 includes a plurality of sub-pixel columns 42 arranged side by side in the X direction. Figure 3 In the example, one of the sub-pixel columns is provided with reference numeral 42. Each sub-pixel column 42 is provided with reference numeral 42. Figure 3 The X direction is composed of sub-pixels arranged up and down in the Y direction. Figure 3 The direction extending from left to right (along the X-axis), the Y-direction is Figure 3 The X direction and the Y direction are perpendicular to each other in the plane where the sub-pixels are arranged.

[0062] Each sub-pixel column 42 is composed of red sub-pixels 41R, green sub-pixels 41G, and blue sub-pixels 41B arranged cyclically at a predetermined pitch. Figure 3 In the example shown in FIG, a cycle consists of a red subpixel 41R, a blue subpixel 41B, and a green subpixel 41G arranged in sequence. Two adjacent subpixel columns 42 are positioned differently in the Y direction; each subpixel in one subpixel column 42 is located between subpixels of the other two colors in the other subpixel column 42 in the Y direction.

[0063] exist Figure 3 In the example shown, each subpixel column is offset by half a pitch relative to the adjacent subpixel column. A pitch is the distance between subpixels of the same color in the Y direction. For example, green subpixel 41G is located midway between red subpixel 41R and blue subpixel 41B in adjacent subpixel column 42 in the Y direction.

[0064] The display area 125 includes a plurality of sub-pixel rows 43 arranged up and down in the Y direction. Figure 3In FIG. 4 , as an example, one of the green sub-pixel rows is provided with reference numeral 43. Each sub-pixel row 43 is composed of sub-pixels arranged side by side at a predetermined pitch in the X direction. Figure 3 In the example of FIG. 4 , each sub-pixel row 43 is composed of sub-pixels of the same color. Each sub-pixel row 43 is sandwiched by sub-pixel rows of two other colors along the Y axis.

[0065] In the X direction, each sub-pixel in the sub-pixel row 43 is located between adjacent sub-pixels in adjacent sub-pixel rows. Figure 3 In the example shown in FIG4 , each subpixel row is offset by half a pitch relative to an adjacent subpixel row. A pitch is the distance between adjacent subpixels in subpixel row 43. In the X direction, a subpixel is located between two adjacent subpixels in adjacent subpixel rows 43.

[0066] In this embodiment, for descriptive purposes, subpixel lines extending along the X-axis are referred to as subpixel rows, and subpixel lines extending along the Y-axis are referred to as subpixel columns; however, the orientations of subpixel rows and subpixel columns are not limited to these examples.

[0067] The display area 125 includes two types of primary pixels arranged in a matrix. The two types of primary pixels are first type primary pixels 51 and second type primary pixels 52. Figure 3 In the example, only one of the primary pixels of the first type is provided with reference numeral 51, and only one of the primary pixels of the second type is provided with reference numeral 52. Δ pixels in the layout, the remaining Pixels.

[0068] exist Figure 3 , some of the first type of primary pixels 51 are indicated by triangles oriented such that one vertex is on the left and the other two vertices are on the right. In addition, some of the second type of primary pixels 52 are indicated by triangles oriented such that one vertex is on the right and the other two vertices are on the left. Figure 3 The right side is the X-direction side, and Figure 3 The left side is the opposite side in the X direction. The primary pixel 51 may be referred to as a second-type primary pixel, and the primary pixel 52 may be referred to as a first-type primary pixel.

[0069] The first-type main pixel 51 and the second-type main pixel 52 are each composed of a green sub-pixel 41G and a red sub-pixel 41R and a blue sub-pixel 41B adjacent to (closest to) the green sub-pixel 41G in the sub-pixel column 42 adjacent to the sub-pixel 41G.

[0070] In the first type main pixel 51, the red sub-pixel 41R and the blue sub-pixel 41B are continuously arranged in the same sub-pixel column 42. The sub-pixel column 42 including the green sub-pixel 41G is on the opposite side or Figure 3 The left side of the pixel 41G is adjacent to the subpixel column 42 including the red subpixel 41R and the blue subpixel 41B. The green subpixel 41G is located between the red subpixel 41R and the blue subpixel 41B along the Y axis, more specifically, in the middle of the red subpixel 41R and the blue subpixel 41B.

[0071] In the second type main pixel 52, the red sub-pixel 41R and the blue sub-pixel 41B are continuously arranged in the same sub-pixel column 42. The sub-pixel column 42 including the green sub-pixel 41G is located on one side or the other in the X direction. Figure 3 The right side of the pixel 41 is adjacent to the subpixel column 42 including the red subpixel 41R and the blue subpixel 41B. The green subpixel 41G is located between the red subpixel 41R and the blue subpixel 41B along the Y axis, more specifically, in the middle of the red subpixel 41R and the blue subpixel 41B.

[0072] The display area 125 includes a plurality of primary pixel rows (pixel lines extending along the X axis), which extend along the X axis and are arranged up and down along the Y axis. The plurality of primary pixel rows include two types of primary pixel rows: a first type of primary pixel row 61 and a second type of primary pixel row 62. Figure 3 , as an example, one of the primary pixel rows of the first type is provided with reference numeral 61. Furthermore, as an example, one of the primary pixel rows of the second type is provided with reference numeral 62.

[0073] The first-type primary pixel rows 61 are composed of the first-type primary pixels 51 arranged side by side in the X direction. The second-type primary pixel rows 62 are composed of the second-type primary pixels 52 arranged side by side in the X direction. In the display area 125, the first-type primary pixel rows 61 and the second-type primary pixel rows 62 are arranged alternately in the Y direction.

[0074] The display area 125 includes a plurality of main pixel columns (pixel lines extending along the Y axis) 63 extending along the Y axis and arranged side by side along the X axis. Figure 3 , as an example, one of the primary pixel columns is provided with reference numeral 63. Each primary pixel column 63 is composed of first-type primary pixels 51 and second-type primary pixels 52 alternately arranged at a predetermined pitch along the Y axis.

[0075] Layout of data lines and pixel circuits

[0076] Figure 4The present invention shows a portion of a circuit layout in one embodiment of the present specification, more specifically, an example of the layout of sub-pixels (light-emitting areas), pixel circuits (only the areas where components are arranged are shown, not the patterns of the individual components), switching transistors for controlling data writing to the pixel circuits, scan lines, and data lines. Figure 4 , a plurality of sub-pixels (light-emitting areas) are represented by dashed rectangles. As an example, one of the red sub-pixels is provided with reference numeral 411R, one of the green sub-pixels is provided with reference numeral 411G, and one of the blue sub-pixels is provided with reference numeral 411B.

[0077] The letters R, G and B in the dotted rectangle represent red, green and blue respectively. A sub-pixel (also referred to as a pixel) is a light emitting area, which is the contact area between the organic light emitting laminate member and the anode electrode. Figure 3 As described, the sub-pixels are Δ- Similarly, the anode electrode is also arranged in Δ- Layout and arrangement.

[0078] Each area including a pixel circuit for controlling the light emission of a sub-pixel is represented by a solid rectangle. These areas are referred to as pixel circuit areas or simply pixel circuits. As an example, one of the pixel circuits for a red sub-pixel is provided with reference numeral 431R, one of the pixel circuits for a green sub-pixel is provided with reference numeral 431G, and one of the pixel circuits for a blue sub-pixel is provided with reference numeral 431B. The letters R, G, and B within the solid rectangle represent the color of the sub-pixel to be controlled by the pixel circuit. Hereinafter, the pixel circuit for a red sub-pixel is referred to as a pixel circuit for red, the pixel circuit for a green sub-pixel is referred to as a pixel circuit for green, and the pixel circuit for a blue sub-pixel is referred to as a pixel circuit for blue.

[0079] The pixel circuits 431R, 431G, and 431B are spaced apart from each other without any overlap. The area included in one pixel circuit is located outside all other pixel circuits. Figure 4 The pixel circuits in the configuration example have a rectangular shape, but other shapes are not excluded. Pixel circuits for controlling sub-pixels of the same color have the same shape, but pixel circuits for controlling sub-pixels of different colors may have different shapes.

[0080] The plurality of pixel circuits 431R, 431G, and 431B are arranged in a layout different from that of the sub-pixels. Figure 4In the example of FIG, a plurality of pixel circuits 431R, 431G, and 431B are arranged in a matrix. The plurality of pixel circuits constitute a plurality of pixel circuit rows or a plurality of pixel circuit columns. Each pixel circuit row is composed of pixel circuits arranged in the X direction, and the plurality of pixel circuit rows are arranged up and down in the Y direction. Each pixel circuit column is composed of pixel circuits arranged in the Y direction, and the plurality of pixel circuit columns are arranged side by side in the X direction.

[0081] exist Figure 4 In the configuration example, all pixel circuits 431R, 431G, and 431B have the same shape and occupy the same area. The centroids of the pixel circuits in one pixel circuit row are located on a straight line extending in the X direction, and the centroids of the pixel circuits in one pixel circuit column are located on a line extending in the Y direction.

[0082] exist Figure 4 In the example, the two left pixel circuit columns control the sub-pixels in the t-th primary pixel column 461t (t is an integer), and the two right pixel circuit columns control the sub-pixels in the (t+1)-th primary pixel column 4601t+1. Figure 3 As described above, a primary pixel column is composed of two adjacent sub-pixel columns. A primary pixel is composed of three sub-pixels of different colors, included in three sub-pixel rows and two sub-pixel columns. From this description, it can be understood that multiple pixel circuit columns constitute multiple pixel circuit column pairs, each pixel circuit column pair being associated with a different primary pixel column.

[0083] In each pixel circuit column, pixel circuits of three colors are arranged cyclically. Figure 4 In the example of , a cycle consisting of a pixel circuit for red, a pixel circuit for green, and a pixel circuit for blue is repeatedly arranged from top to bottom. The positions of two adjacent pixel circuit columns are staggered by one pixel circuit. Therefore, two pixel circuits in the same pixel circuit row in two adjacent pixel circuit columns are used for different colors. In odd-numbered pixel circuit columns, the relationship between the assigned color and the position of each pixel circuit in the Y direction is the same. In even-numbered pixel circuit columns, the relationship between the assigned color and the position of each pixel circuit in the Y direction is the same.

[0084] Each pixel circuit row consists of pixel circuits for two different colors arranged alternately. Two adjacent pixel circuit rows consist of pixel circuits for different color pairs. Figure 4 In the example, the topmost pixel circuit row consists of pixel circuits for red and pixel circuits for blue arranged alternately; the next pixel circuit row consists of pixel circuits for green and pixel circuits for red arranged alternately; and the pixel circuit row after the next pixel circuit row consists of pixel circuits for blue and pixel circuits for green arranged alternately.

[0085] Figure 4 The figure shows a plurality of data lines extending in the Y direction and arranged side by side in the X direction. The data lines for transmitting data signals to the pixel circuits for the three colors are arranged cyclically along the X direction. Figure 4 The data lines in the device run straight, but the data lines can be partially bent.

[0086] The data lines XRt and XRt+1 are the tth data line and the (t+1)th data line for transmitting data signals to the pixel circuit 431R for red. The data lines XRt and XRt+1 are connected to the plurality of pixel circuits 431R for red, and are not connected to pixel circuits for other colors. The data lines for the pixel circuits for red are also referred to as data lines for red.

[0087] The data lines XGt and XGt+1 are the t-th data line and the (t+1)-th data line for transmitting data signals to the pixel circuit 431G for green. The data lines XGt and XGt+1 are connected to the plurality of pixel circuits 431G for green, and are not connected to pixel circuits for other colors. The data lines for the pixel circuits for green are also referred to as data lines for green.

[0088] The data lines XBt and XBt+1 are the tth data line and the (t+1)th data line for transmitting data signals to the pixel circuit 431B for blue. The data lines XBt and XBt+1 are connected to the plurality of pixel circuits 431B for blue and are not connected to pixel circuits for other colors. The data lines for the pixel circuits for blue are also referred to as data lines for blue.

[0089] As described above, in one embodiment of the present disclosure, each data line sequentially transmits data signals to pixel circuits for only one color. Generally speaking, the data for adjacent sub-pixels of the same color used to display an average image have small differences in RGB grayscale. Therefore, even if the data line selection period remains unchanged, the efficiency of writing signals to each data line is improved, thereby reducing image quality degradation caused by insufficient data signals being written to the pixel circuits.

[0090] The data lines XRt, XGt, and XBt constitute a data line group and are associated with a pair of pixel circuit columns for controlling the primary pixel column 461t. Similarly, the data lines XRt+1, XGt+1, and XBt+1 constitute a data line group and are associated with a pair of pixel circuit columns for controlling the primary pixel column 461t+1.

[0091] As can be seen from these examples, each data line group consists of data lines that are different from the data lines that make up any other data line group; each data line group consists of three consecutive data lines for different colors. Each data line group is associated with a different primary pixel column or a different pair of pixel circuit columns.

[0092] exist Figure 4 In the configuration example, data line XGt is the data line closest to the center in the X direction of the pixel circuit column pair associated with primary pixel column 461t, and extends between the sub-pixel columns of primary pixel column 4601t. Data line XRt is the data line closest to the left end of the pixel circuit column pair, and data line XBt is the data line closest to the right end of the pixel circuit column pair.

[0093] The positional relationship between the data lines XRt+1, XGt+1 and XBt+1 and the pixel circuit column pair associated with the main pixel column 461t+1 is the same as the positional relationship between the data lines XRt, XGt and XBt and the pixel circuit column pair associated with the main pixel column 461t. Figure 4 What is shown is an example of the positional relationship between the pixel circuit column pairs and the data line groups, but the positional relationship is not limited to this example.

[0094] Each pixel circuit is connected to a data line through a lead portion including a switching TFT. Figure 4 , some lead portions connecting the data line for red and the pixel circuit for red are provided with reference numerals 471R1 or 471R2. Some lead portions connecting the data line for green and the pixel circuit for green are provided with reference numerals 471G1 or 471G2. Some lead portions connecting the data line for blue and the pixel circuit for blue are provided with reference numerals 471B1 or 471B2.

[0095] The switching TFT in each lead portion is turned on / off by one of the scan lines Yk to Yk+3 (k is an integer). The scan lines Yk to Yk+3 are arranged to extend in the X direction and are positioned vertically along the Y direction. Each scan line activates / disables the connection between the pixel circuit and the data line by turning on / off the switching TFT in the lead portion.

[0096] Figure 5 A diagram for explaining a wiring portion for connecting a data line and a pixel circuit. Figure 5 Data lines XRt, XGt, XBt, and XRt+1, pixel circuits in a main pixel column 461t, and wiring portions between the data lines and the pixel circuits are shown.

[0097] Each data line for green, including the data lines XGt and XGt+1, transmits a data signal to a pixel circuit for green in a pixel circuit column pair constituting a main pixel column associated with the data line. Figure 5 In the configuration example of FIG, the data line XGt for green and the pixel circuit 431G for green in the left pixel circuit column of the pixel circuit column pair associated with the data line XGt are connected by a lead portion 471G1. The data line XGt for green and the pixel circuit 431G for green in the right pixel circuit column of the associated pixel circuit column pair are connected by a lead portion 471G2. Each lead portion connects the data line for green and the pixel circuit for green without crossing any data line.

[0098] Each data line for blue, including the data lines XBt and XBt+1, transmits a data signal to a pixel circuit for blue in a pixel circuit column pair constituting a main pixel column associated with the data line. Figure 5 In the configuration example of FIG, the data line XBt for blue and the pixel circuit 431B for blue in the left pixel circuit column of the pixel circuit column pair associated with the data line XBt are connected by a lead portion 471B2. The data line XBt for blue and the pixel circuit 431B for blue in the right pixel circuit column of the associated pixel circuit column pair are connected by a lead portion 471B1.

[0099] Each lead portion 471B1 for blue connects the data line XBt for blue and the pixel circuit 431B for blue without crossing any data line. In contrast, each lead portion 471B2 for blue is long and crosses the data line XGt for green. Such long lead portions occupy a large area, thereby reducing the practical area of ​​the pixel circuit. In addition, the intersection of the lead portion and the line will interfere with the arrangement of the components and may cause crosstalk. Therefore, it is desirable that the lead portion is short and the number of intersections between the lead portion and the data line is small.

[0100] exist Figure 4 and Figure 5 In a configuration example, a lead portion is provided between a data line for red and a pixel circuit for red to avoid other data lines. The data line for red transmits a data signal to a pixel circuit for red in an associated pixel circuit column pair and to a pixel circuit for red in a pixel circuit column pair adjacent to the associated pixel circuit column pair.

[0101] exist Figure 5In the configuration example of FIG, a pixel circuit for red in the left pixel circuit column of the pixel circuit column pair for the main pixel column 461t is connected to the data line XRt for red via a lead portion 471R1. The data line XRt for red is included in the data line group associated with the pixel circuit column pair. The pixel circuit for red in the right pixel circuit column of the pixel circuit column pair is connected to the data line XRt+1 for red via a lead portion 471R2. The data line XRt+1 is closer to the right pixel circuit column than the data line XRt. All lead portions 471R1 and 471R2 connect the pixel circuits and the data lines without crossing any data lines.

[0102] As can be understood from the above description, each pixel circuit for red in a pixel circuit column pair is powered by a data line for red in an associated data line group and a data line for red that is closest to the pixel circuit among the data lines for red not included in the associated data line group. All lead portions connect the data line for red and the pixel circuit for red without crossing any other data lines.

[0103] Figure 4 and Figure 5 The configuration example connects the pixel circuit for red in the pixel circuit column pair to the data line for red in a different data line group. Another configuration example may configure the lead portion of another color (for example, blue) as described above. The color order of the data lines in the X direction may be different from Figure 4 and Figure 5 , and the lead portions of the colors selected in sequence may be configured similarly to the lead portions 471R1 and 471R2.

[0104] Figure 6A Schematically shows the arrangement Figure 4 An example configuration of a demultiplexer circuit 136 between the data lines and the driver IC 134 is shown. Figure 6A An example of a 1:2 DeMUX circuit that processes the output of the driver IC 134 output by color rotation is shown.

[0105] Figure 6A The three demultiplexers 361, 362, and 363 are associated with the output terminals OUT1, OUT2, and OUT3 of the driver IC 134. The demultiplexer 361 outputs the data signal received from the output terminal OUT1 of the driver IC 134 through its input terminal to a data line selected from the data lines XRt and XGt. The output terminal OUT1 alternately outputs (through color rotation) a data signal for a red pixel circuit and a data signal for a green pixel circuit.

[0106] The demultiplexer 362 outputs the data signal received from the output terminal OUT2 of the driver IC 134 through its input terminal to a data line selected from the data lines XBt and XRt+1. The output terminal OUT2 alternately outputs (through color rotation) a data signal for a blue pixel circuit and a data signal for a red pixel circuit.

[0107] The demultiplexer 363 outputs the data signal received from the output terminal OUT3 of the driver IC 134 through its input terminal to a data line selected from the data lines XGt+1 and XBt+1. The output terminal OUT3 alternately outputs (through color rotation) a data signal for a green pixel circuit and a data signal for a blue pixel circuit.

[0108] The selection of the data line at each demultiplexer is controlled by a selection signal from the control terminals MUX1 and MUX2 . The selection signal may be supplied from the driver IC 134 . Figure 6A The configuration shown facilitates achieving a narrow bezel with simple routing in the demultiplexer circuit 136 .

[0109] Figure 6B An example configuration of a 1:4 DeMUX circuit is shown. In this configuration example, each output terminal of the driver IC 134 sequentially outputs data signals for pixel circuits of different colors (via color rotation). This configuration helps achieve a narrower frame with simple wiring in the demultiplexer circuit 136.

[0110] The demultiplexer circuit 136 includes a plurality of switching TFTs 651 to 662. Switching TFTs 651 and 657 are connected to the data line XRt. Switching TFTs 652 and 658 are connected to the data line XGt. Switching TFTs 653 and 659 are connected to the data line XBt. Switching TFTs 654 and 660 are connected to the data line XRt+1. Switching TFTs 655 and 661 are connected to the data line XGt+1. Switching TFTs 656 and 662 are connected to the data line XBt+1.

[0111] The on / off states of the switching TFTs 651, 653, and 655 are controlled by a selection signal from a control terminal MUX1. The on / off states of the switching TFTs 652, 654, and 656 are controlled by a selection signal from a control terminal MUX2. The on / off states of the switching TFTs 657, 659, and 661 are controlled by a selection signal from a control terminal MUX3. The on / off states of the switching TFTs 658, 660, and 662 are controlled by a selection signal from a control terminal MUX4.

[0112] The control terminals MUX1 to MUX4 cyclically and repeatedly output ON pulses. The control terminals MUX1 and MUX2 sequentially output ON pulses in one horizontal period, and the control terminals MUX3 and MUX4 sequentially output ON pulses in the next horizontal period.

[0113] The demultiplexer connected to the output terminal OUT1 includes switching TFTs 651, 652, 657, and 658. The output terminal OUT1 alternately outputs a data signal for a red pixel circuit and a data signal for a green pixel circuit. The demultiplexer connected to the output terminal OUT2 includes switching TFTs 653, 654, 659, and 660. The output terminal OUT2 alternately outputs a data signal for a blue pixel circuit and a data signal for a red pixel circuit. The demultiplexer connected to the output terminal OUT3 includes switching TFTs 655, 656, 661, and 662. The output terminal OUT3 alternately outputs a data signal for a green pixel circuit and a data signal for a blue pixel circuit.

[0114] Figure 7 Schematically shows the arrangement Figure 4 Another configuration example of a demultiplexer circuit 136 between the data lines and the driver IC 134 is shown. Figure 7 An example of a 1:2 DeMUX circuit is shown for processing the output of the driver IC 134 without color rotation. Since each output terminal of the driver IC 134 outputs a data signal for a fixed color, the time delay from the driver IC 134 to the demultiplexer circuit 136 can be reduced, thereby improving the efficiency of data writing to the pixel circuit.

[0115] Figure 7 The driver IC 134 includes three demultiplexers associated with output terminals OUT1, OUT2, and OUT3. The demultiplexer for the output terminal OUT1 includes switching TFTs 371 and 374. The demultiplexer for the output terminal OUT2 includes switching TFTs 372 and 375. The demultiplexer for the output terminal OUT3 includes switching TFTs 373 and 376. The data signals output from the output terminals OUT1, OUT2, and OUT3 are for red, green, and blue, respectively.

[0116] Similarly, a demultiplexer circuit having a desired ratio of 1:n (n is an integer greater than 2) can be configured for two types of driver ICs with and without color rotation.

[0117] Figure 8 Shown with Figure 4 The configuration example shown corresponds to an example of a circuit layout near an end portion of the display region. Figure 8The T-th primary pixel column 461T at the end of the display area 125 and the data lines XRT, XGT, and XBT in the data line group associated with the primary pixel column 461T are shown. This configuration example also includes an additional data line XRT+1 for red and a dummy circuit 510 connected to the additional data line XRT+1 in the peripheral area 127 outside the display area 125. The data line XRT+1 is provided outside the multiple data line groups in the display area 125.

[0118] As reference Figure 4 and Figure 5 As described above, some pixel circuits for red are supplied with data signals from a data line for red in a data line group adjacent to the data line group associated with the main pixel column. The additional data line XRT+1 for red transmits data signals for pixel circuits for red in a pixel circuit column at the end of the display area 125. The lead portion 517 connects the additional data line XRT+1 for red to the pixel circuits for red in the pixel circuit column at the end of the display area 125. The additional data line XRT+1 for red is the data line for red in the pixel circuit column closest to the end of the display area 125.

[0119] In reference Figure 4 、 Figure 5 and Figure 8 In the described example, the data line for red closest to the pixel circuit for red supplies a data signal to the pixel circuit for red. Each lead portion in this configuration connects the pixel circuit for red and the data line for red without crossing another data line.

[0120] Figure 8 The additional data line XRT+1 for red in the configuration example of FIG. 5 is connected to the dummy circuit 510 . Therefore, the loading to the additional data line XRT+1 for red may be similar to the loading to the other data lines in the display area 125 . Figure 8 The dummy circuit 510 in the configuration example includes a dummy pixel circuit 511 for red connected to the additional data line XRT+1 for red and a dummy pixel circuit 512 not connected to any data line. The dummy circuit 510 includes dummy sub-pixels (anode electrodes) connected to the dummy pixel circuit 510. Figure 8 In FIG, one virtual sub-pixel is provided with reference numeral 513 .

[0121] The dummy pixel circuit 511 has the same configuration as the normal pixel circuit in the display area 125. The number of dummy pixel circuits 511 and normal pixel circuits connected to the additional data line XRT+1 for red is equal to the number of pixel circuits connected to the data lines of the display area 125. These numbers may be different. Pixel circuits not connected to the additional data line XRT+1 for red may be excluded, and sub-pixels including anode electrodes may also be excluded.

[0122] The demultiplexer circuit 136 includes a circuit block for outputting a data signal to the additional data line XRT+1 for red. An example of the demultiplexer circuit 136 may include a demultiplexer block that includes the additional data line XRT+1 for red as an output destination. Thus, loading differences within the demultiplexer circuit 136 can be reduced.

[0123] Implementation Method 2

[0124] In reference Figure 4 、 Figure 5 and Figure 8 In the configuration example described, the pixel circuit for red, the pixel circuit for green, and the pixel circuit for blue have the same shape and occupy an equal area. In the configuration example described below, the pixel circuit for green occupies a larger area than the pixel circuit for red and the pixel circuit for blue. The visibility of green is higher than that of red and blue, so its brightness unevenness is obvious. For example, the variation of the output current between the pixel circuits can be reduced by expanding the storage capacitor or extending the channel length of the driving TFT in each pixel circuit. A circuit configuration for obtaining smaller brightness unevenness is achieved by expanding the area of ​​the pixel circuit for green.

[0125] Figure 9 A configuration example of a circuit layout is shown in which each pixel circuit for green occupies a larger area than the pixel circuit for red and the pixel circuit for blue. As an example, one of the pixel circuits for green is provided with reference numeral 551G, one of the pixel circuits for red is provided with reference numeral 551R, and one of the pixel circuits for blue is provided with reference numeral 551B.

[0126] All pixel circuits 551R, 551G, and 551B have the same length LY in the Y direction. The pixel circuit 551R for red and the pixel circuit 551B for blue have the same length LX1 in the X direction. The pixel circuit 551G for green has a length LX2 in the X direction. Length LX2 is longer than length LX1. Since the length in the Y direction is the same for all pixel circuits, this circuit layout does not affect control lines and power lines that extend in the X direction and are arranged up and down in the Y direction, such as scan lines and anode power lines.

[0127] Implementation 3

[0128] Figure 10 Another example of a circuit layout is shown. Figure 5 Compared to the configuration example in Figure 10 In the configuration example, the data line for blue is swapped with the data line for green. Figure 5 Differences in the configuration examples: A plurality of data lines are cyclically arranged in the order of a data line for red, a data line for blue, and a data line for green. Figure 10 Included are data lines XRt and XRt+1 for red, a data line XBt for blue, and a data line XGt for green.

[0129] Each data line group consists of a data line for red, a data line for blue, and a data line for green arranged in order from the left. The configuration of the lead portion 471R1 between the data line XRt for red and the pixel circuit 431R for red and the lead portion 471R2 between the data line XRt+1 for red and the pixel circuit 431R is the same as that of the data line group. Figure 5 The configuration is the same as in the example.

[0130] The data line XBt for blue in the left pixel circuit column of the pixel circuit column pair associated with the data line XBt and the pixel circuit 431B for blue are connected by a lead portion 571B1. The data line XBt for blue in the right pixel circuit column of the associated pixel circuit column pair and the pixel circuit 431B for blue are connected by a lead portion 571B2. Each lead portion connects the data line for blue and the pixel circuit for blue without crossing any data line.

[0131] The data line XGt for green transmits a data signal to the pixel circuit for green in the pixel circuit column pair constituting the primary pixel column associated with the data line XGt. The data line XGt for green and the pixel circuit 431G for green in the left pixel circuit column of the pixel circuit column pair associated with the data line XGt are connected via a lead portion 571G2. The data line XGt for green and the pixel circuit 431G for green in the right pixel circuit column of the associated pixel circuit column pair are connected via a lead portion 571G1.

[0132] Each lead portion 571G1 for green connects the data line XGt for green and the pixel circuit 431G for green without crossing any data line. In contrast, each lead portion 571G2 for green crosses the data line XBt for blue.

[0133] In another configuration example, the data line group may be composed of a data line for blue, a data line for green, and a data line for red arranged in order from the left. In this configuration, Figure 10 The configurations of the lead portion for red, the lead portion for blue, and the lead portion for green are respectively applied to the lead portion for blue, the lead portion for green, and the lead portion for red.

[0134] Implementation 4

[0135] Hereinafter, a circuit layout in another embodiment of the present specification will be described. Figure 4 、 Figure 5 and Figure 8 In the configuration example described above, only the data line for red transmits data signals to pixel circuits for red in different pixel circuit column pairs. In the configuration example described below, in addition to the data line for red, the data line for blue also transmits data signals to pixel circuits for blue in different pixel circuit column pairs. The data line for red and the data line for blue are data lines at both ends of a data line group associated with a pixel circuit column pair. This configuration eliminates the intersection of the lead portion for blue with the data lines; in other words, all lead portions connect pixel circuits and data lines without crossing any data lines.

[0136] Figure 11 The following mainly describes the circuit layout of an embodiment of the present invention. Figure 5 The configuration examples are different. Figure 11 The data lines XBt-1, XRt, XGt, XBt and XRt+1, the pixel circuits in the main pixel column 461t, and the lead portions between the data lines and the pixel circuits are shown. Figure 5The description provided is applicable. The configuration of the lead part is Figure 5 The configuration in the example shown is different.

[0137] The pixel circuit 431R for red is connected to the data line XRt or XRt+1 for red through the connection of the lead portion 471R1 or 471R2 for red. Figure 5 Regarding the connection of the pixel circuit for green with the data line XGt for green through the lead portion 471G1 or 471G2 for green, refer to Figure 5 The description provided is applicable.

[0138] exist Figure 11 In the configuration example of FIG. 4 , a pixel circuit 431B for blue in the left pixel circuit column of a pixel circuit column pair is supplied with a data signal from a data line XBt-1 for blue in an adjacent data line group. The data line XBt-1 for blue is the data line for blue closest to the left pixel circuit column. The data line XBt-1 for blue in the left pixel circuit column and the pixel circuit 431B for blue are connected via a lead portion 472B2, each including a switching TFT. The lead portion 472B2 does not cross any data lines.

[0139] The blue pixel circuit 431B in the right pixel circuit column of the pixel circuit column pair is supplied with a data signal from the blue data line XBt in the data line group associated with the pixel circuit column pair. The blue data line XBt is the data line for blue closest to the right pixel circuit column. The blue data line XBt in the right pixel circuit column and the blue pixel circuit 431B are connected via a lead portion 471B1, each including a switching TFT. The lead portion 471B1 does not cross any data lines.

[0140] The pixel circuits in display area 125 are included in a plurality of layout units 440. Each layout unit 440 consists of pixel circuits and lead portions for two primary pixels, or three rows and two columns of pixel circuits and lead portions extending from the pixel circuits. Layout unit 440 includes a lead portion protruding to the left and a lead portion protruding to the right; each of these lead portions is connected to a data line in a data line group on either side of the data line group associated with layout unit 440.

[0141] Figure 12 Shown according to Figure 11 Wider area of ​​circuit layout. Figure 12 Included are data lines XBt-1 to XBt+3 for blue, data lines XRt to XRt+4 for red, and data lines XGt to XGt+3 for green. Figure 12It also includes pixel circuit columns from the tth to the (t+3)th main pixel columns. Figure 11 As described above, each pixel circuit is connected to a data line for the same color through a lead portion. Figure 12 In FIG. 1 , each dotted line extending in the Y direction and having a plurality of bends represents a boundary between layout unit patterns. The boundary is formed so that the layout unit patterns are interlocked with each other.

[0142] Each data line is provided with a lead portion extending alternately from the left and from the right in the Y direction. As described above, a data line group consisting of three consecutive data lines for red, green, and blue is associated with one primary pixel column, and this primary pixel column is controlled by a pixel circuit column pair consisting of two adjacent pixel circuit columns. In this example, one data line group consists of the leftmost data line for red, the rightmost data line for blue, and the data line for green in between.

[0143] Each data line for green is connected to a pixel circuit for green in an associated pixel circuit column pair via a lead portion. For example, the data line for green, XGt, is connected to a pixel circuit for green in a pixel circuit column pair associated with the primary pixel column 461t. The same applies to the other data lines, XGt+1 to XGt+3.

[0144] Each data line for red transmits a data signal to a pixel circuit for red in an associated pixel circuit column pair and a pixel circuit for red in an adjacent pixel circuit column pair. Figure 12 In the configuration example, each data line for red is connected via a lead portion to a pixel circuit for red in the left pixel circuit column of its associated pixel circuit column pair and a pixel circuit for red in the right pixel circuit column of the pixel circuit column pair adjacent to the associated pixel circuit column pair on the left. For example, the data line for red, XRt+1, transmits a data signal to the right pixel circuit column of the pixel circuit column pair for the primary pixel column 461t and to the left pixel circuit column of the pixel circuit column pair for the primary pixel column 461t+1. The same applies to the other data lines for red.

[0145] Each data line for blue transmits a data signal to a pixel circuit for blue in an associated pixel circuit column pair and a pixel circuit for blue in an adjacent pixel circuit column pair. Figure 12In the configuration example, each data line for blue is connected via a lead portion to a pixel circuit for blue in the right pixel circuit column of the associated pixel circuit column pair and to a pixel circuit for blue in the left pixel circuit column of the pixel circuit column pair adjacent to the associated pixel circuit column pair on the right. For example, the data line for blue, XBt+1, transmits a data signal to the right pixel circuit column of the pixel circuit column pair for the primary pixel column 461t+1 and to the left pixel circuit column of the pixel circuit column pair for the primary pixel column 461t+2. The same applies to the other data lines for blue.

[0146] With reference Figure 8 Similar to the additional data line described for red, the circuit layout in this example includes an additional data line for blue outside the display area 125. Assume Figure 12 The main pixel column 461t in the display area 125 is the leftmost main pixel column, and the data line XBt-1 is an additional data line for blue outside the display area 125.

[0147] The additional data line XBt-1 for blue is arranged across the display area 125, opposite the data line for red. The additional data line XBt-1 for blue does not belong to any data line group in the display area and is arranged outside the plurality of data line groups. The pixel circuit for blue in the leftmost pixel circuit column in the display area 125 is supplied with a data signal from the additional data line XBt-1 for blue.

[0148] With reference Figure 8 Similar to the additional data line described for red, the additional data line XBt-1 for blue can be connected to a dummy pixel circuit. Figure 8 The description provided regarding the virtual circuit applies to the virtual circuit connected to the additional data line for blue. The same applies to the description regarding the demultiplexer.

[0149] As described above, the pixel circuit for blue or red is supplied with a data signal from the data line for blue or red in the associated data line group and the data line for blue or red (including additional data lines) that is not included in the associated data line group. The pixel circuit for green is supplied with a data signal from the data line for green in the associated data line group. Therefore, each pixel circuit is supplied with a data signal from the closest data line of the same color as the pixel circuit. Therefore, the area occupied by the lead portion including the switching TFT can be minimized, thereby easily realizing a pixel with higher resolution. In addition, the crosstalk caused by the capacitive coupling between the data line including the lead portion and the storage capacitor in the pixel circuit can be minimized.

[0150] As described above, each pixel circuit in display area 125 is connected to one of the data lines and the additional data line in display area 125 through a lead portion. The pixel circuits are associated with the lead portions in a one-to-one correspondence.

[0151] Figure 13 Shown is the Figure 12 1:2 demultiplexer circuit 136 configuration example of the data line output data signal. In this configuration example, each output terminal of the driver IC 134 sequentially outputs the data signal for the pixel circuit of the same color. This configuration achieves high display quality.

[0152] The demultiplexer circuit 136 includes a plurality of switching TFTs 621 to 636. Switching TFTs 621 and 622 are connected to the data line XBt-1. Switching TFTs 623 and 624 are connected to the data line XRt. Switching TFTs 625 and 626 are connected to the data line XGt. Switching TFTs 627 and 628 are connected to the data line XBt.

[0153] Switching TFTs 629 and 630 are connected to the data line XRt+1. Switching TFTs 631 and 632 are connected to the data line XGt+1. Switching TFTs 633 and 634 are connected to the data line XBt+1. Switching TFTs 635 and 636 are connected to the data line XRt+2.

[0154] The on / off states of the switching TFTs 621, 624, 625, 627, and 636 are controlled by a selection signal from a control terminal MUX1. The on / off states of the switching TFTs 622, 629, 631, and 634 are controlled by a selection signal from a control terminal MUX2. The on / off states of the switching TFTs 626, 630, and 633 are controlled by a selection signal from a control terminal MUX3. The on / off states of the switching TFTs 623, 628, 632, and 635 are controlled by a selection signal from a control terminal MUX4.

[0155] The control terminals MUX1 to MUX4 cyclically and repeatedly output on-pulses. The control terminals MUX1 and MUX2 sequentially output on-pulses in one horizontal period, and the control terminals MUX3 and MUX4 sequentially output on-pulses in the next horizontal period.

[0156] The demultiplexer circuit 136 includes a plurality of demultiplexers. Each demultiplexer sequentially receives a data signal from one output terminal of the driver IC 134 and outputs the data signal to a data line selected in turn. Each demultiplexer is connected to a different output terminal of the driver IC 134 and outputs the received data signal to a plurality of data lines for the same color. Figure 13, a demultiplexer for receiving a data signal from an output terminal OUT1n of the driver IC 134 is surrounded by a dotted line and is provided with a reference numeral 611.

[0157] The output terminal OUT1n alternately outputs the data signal of the pixel circuit for red in the main pixel column 461t and the data signal of the pixel circuit for red in the main pixel column 461t+1. The demultiplexer 611 for the output terminal OUT1n includes switching TFTs 624, 629, 630, and 635. The demultiplexer 611 outputs the data signal from the output terminal OUT1n to a data line selected in turn from the data lines XRt, XRt+1, and XRt+2 for red.

[0158] The output terminal OUT2n alternately outputs the data signal of the pixel circuit for green in the main pixel column 461t and the data signal of the pixel circuit for green in the main pixel column 461t+1. The demultiplexer for the output terminal OUT2n includes switching TFTs 625, 626, 631, and 632. The demultiplexer outputs the data signal from the output terminal OUT2n to a data line alternately selected from the data lines XGt and XGt+1 for green.

[0159] The output terminal OUT3n alternately outputs the data signal of the pixel circuit for blue in the main pixel column 461t and the data signal of the pixel circuit for blue in the main pixel column 461t+1. The demultiplexer for the output terminal OUT3n includes switching TFTs 622, 627, 628, and 633. The demultiplexer outputs the data signal from the output terminal OUT3n to a data line selected in turn from the data lines XBt-1, XBt, and XBt+1 for blue.

[0160] The output terminal OUT1n-1 alternately outputs the data signal for the red pixel circuit in the main pixel column 461t-2 and the data signal for the red pixel circuit in the main pixel column 461t-1. The output terminal OUT3n-1 alternately outputs the data signal for the blue pixel circuit in the main pixel column 461t-2 and the data signal for the blue pixel circuit in the main pixel column 461t-1. The output terminal OUT1n+1 alternately outputs the data signal for the red pixel circuit in the main pixel column 461t+2 and the data signal for the red pixel circuit in the main pixel column 461t+3. The output terminal OUT3n+1 alternately outputs the data signal for the blue pixel circuit in the main pixel column 461t+2 and the data signal for the blue pixel circuit in the main pixel column 461t+3.

[0161] The switching TFT 621 activates / disables conduction between the output terminal OUT3n-1 and the data line XBt-1. The switching TFT 623 activates / disables conduction between the output terminal OUT1n-1 and the data line XRt. The switching TFT 634 activates / disables conduction between the output terminal OUT3n+1 and the data line XBt+1. The switching TFT 636 activates / disables conduction between the output terminal OUT1n+1 and the data line XRt+2.

[0162] Each data line for green is connected to only one demultiplexer and, through the demultiplexer, is connected to only one output terminal of the driver IC 134. For example, the data lines XGt and XGt+1 transmit data signals only from the output terminal OUT2n.

[0163] The data lines for red include data lines connected to only one demultiplexer and data lines connected to different demultiplexers. For example, the data line XRt+1 is connected only to the demultiplexer 611 and transmits a data signal only from the output terminal OUT1n.

[0164] However, data lines XRt and XRt+2 are each connected to two demultiplexers and transmit data signals from two output terminals of the driver IC 134. Data line XRt transmits data signals from output terminals OUTn-1 and OUT1n. Data line XRt+2 transmits data signals from output terminals OUT1n and OUT1n+1.

[0165] The data lines for blue include data lines connected to only one demultiplexer and data lines connected to different demultiplexers. For example, the data line XBt is connected to only one demultiplexer and transmits a data signal only from the output terminal OUT3n.

[0166] However, data lines XBt-1 and XBt+1 are each connected to two demultiplexers and transmit data signals from two output terminals of the driver IC 134. Data line XBt-1 transmits data signals from output terminals OUT3n-1 and OUT3n. Data line XBt+1 transmits data signals from output terminals OUT3n and OUT3n+1.

[0167] Among the data lines for red connected to the same demultiplexer, a data line connected to another demultiplexer is located at the end of these data lines for red. Figure 13 In the example shown in FIG1 , the data lines for red connected to the demultiplexer for the output terminal OUT1n are data lines XRt, XRt+1, and XRt+2. Of these data lines, the data line XRt at one end is also connected to the demultiplexer for the output terminal OUT1n-1, and the data line XRt+2 at the other end is also connected to the demultiplexer for the output terminal OUT1n+1.

[0168] Similarly, among the data lines for blue connected to the same demultiplexer, the data line connected to another demultiplexer is located at the end of these data lines for blue. Figure 13 In the example shown in FIG3 , the data lines for blue connected to the demultiplexer for the output terminal OUT3n are data lines XBt-1, XBt, and XBt+1. Of these data lines, the data line XBt-1 at one end is also connected to the demultiplexer for the output terminal OUT3n-1, and the data line XBt+1 at the other end is also connected to the demultiplexer for the output terminal OUT3n+1.

[0169] As described above, the embodiments of the present invention have been described; however, the present invention is not limited to the above-described embodiments. Those skilled in the art can easily modify, add, or convert the various elements in the above-described embodiments within the scope of the present invention. A portion of the configuration of one embodiment may be replaced by the configuration of another embodiment, or the configuration of one embodiment may be incorporated into the configuration of another embodiment.

Claims

1. A display panel, wherein pixels of a first color, a second color, and a third color are arranged in a pattern of Δ- The layout is arranged in the display panel, and the display panel includes: a plurality of pixel circuit columns; as well as Multiple data lines, wherein the plurality of pixel circuit columns extend in a first direction and are arranged side by side in a second direction perpendicular to the first direction, Each of the plurality of pixel circuit columns is composed of pixel circuits for three colors that are arranged cyclically. wherein each of the pixel circuits for the three colors is configured to control the light intensity of pixels of the same color assigned to the pixel circuit, The plurality of pixel circuit columns constitute a plurality of pixel circuit column pairs, each pixel circuit column pair consisting of two adjacent pixel circuit columns. wherein the plurality of data lines extend in the first direction and are arranged side by side in the second direction, wherein the plurality of data lines are data lines for the three colors arranged in a cycle, wherein each of the plurality of data lines is configured to transmit a data signal to a pixel circuit for the same color assigned to the data line, wherein the plurality of data lines comprises a plurality of data line groups, and each data line group consists of the following three data lines arranged consecutively: a data line for the first color, a data line for the second color, and a data line for the third color; wherein the plurality of data lines include an additional data line for the first color arranged outside the plurality of data line groups, Each of the plurality of pixel circuit column pairs is associated with a different data line group, and wherein each pixel circuit for the first color in each of the plurality of pixel circuit column pairs is supplied with a data signal from a data line for the first color that is closer to a pixel circuit between a data line for the first color in an associated data line group and a data line for the first color that is adjacent to a data line for the third color in the associated data line group outside the associated data line group.

2. The display panel according to claim 1, in, each pixel circuit for the second color in each of the plurality of pixel circuit column pairs is supplied with a data signal from a data line for the second color in the associated data line group, and Particularly, all or part of the pixel circuits for the third color in each of the plurality of pixel circuit column pairs are supplied with data signals from the data lines for the third color in the associated data line group.

3. The display panel according to claim 1, wherein: The area occupied by the pixel circuit for the color with the highest visibility among the three colors is larger than the area occupied by the pixel circuit for either of the other two colors.

4. The display panel according to claim 1, wherein: Each pixel circuit in the plurality of pixel circuit columns is supplied with a data signal from a nearest data line for the same color assigned to the pixel circuit.

5. The display panel according to claim 1, wherein: Additional data lines for the first color are connected to a plurality of dummy pixel circuits.

6. The display panel according to claim 1 , further comprising an additional data line for the third color, the additional data line for the third color being arranged opposite to the additional data line for the first color across the plurality of data line groups, in, each pixel circuit for the second color in each of the plurality of pixel circuit column pairs is supplied with a data signal from a data line for the second color in the associated data line group, and In which, each pixel circuit for the third color in each of the multiple pixel circuit column pairs is supplied with a data signal from the data line for the third color in the associated data line group and the data line for the third color that is closest to the data line for the third color that is not included in the associated data line group.

7. The display panel according to claim 6, wherein: Each of the additional data line for the first color and the additional information line for the third color is connected to a plurality of dummy pixel circuits.

8. The display panel according to claim 1 , further comprising a demultiplexer circuit comprising a plurality of demultiplexers, in, Each of the plurality of demultiplexers is configured to output each data signal received at one input terminal to a data line selected in turn from the connected plurality of data lines, and Wherein, all output terminals of each of the plurality of demultiplexers are connected to data lines for the same color.

9. The display panel according to claim 6, further comprising a demultiplexer circuit comprising a plurality of demultiplexers, in, Each of the plurality of demultiplexers is configured to output each data signal received at one input terminal to a data line selected in turn from the connected plurality of data lines, wherein all output terminals of each of the plurality of demultiplexers are connected to data lines for the same color, wherein the data lines for the first color include data lines connected to only one demultiplexer and data lines connected to different demultiplexers, wherein each data line for the second color is connected to only one demultiplexer, and The data lines for the third color include data lines connected to only one demultiplexer and data lines connected to different demultiplexers.

10. The display panel according to claim 9, in, In a first data line group consisting of data lines for the first color connected to one demultiplexer, a data line connected to any other demultiplexer is located at an end of the first data line group, and Wherein, in the second data line group consisting of the data lines for the third color connected to one demultiplexer, the data line connected to any other demultiplexer is located at an end of the second data line group.

11. A display device comprising: The display panel according to claim 1; as well as Driver circuit, Wherein, the display panel further includes a demultiplexer circuit including a plurality of demultiplexers, Each of the plurality of demultiplexers is configured as follows: receiving a data signal output from one output terminal of the driver circuit; and Each data signal is output to a data line selected in turn from among the connected plurality of data lines.

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