Chip testing method, related equipment and computer-readable storage medium

Abstract

The embodiment of the present application provides a chip testing method, related equipment and computer-readable storage medium, which relate to the field of chips. The method includes: obtaining the communication status between itself and the device to be tested through a chip testing device; wherein, the chip to be tested contained in the device to be tested operates in the target working environment data; when the communication status indication is normal, the adjustment step is determined according to the preset adjustment method, and the target working environment data is updated according to the adjustment step until the adjustment step reaches the preset threshold step and the communication status indication is abnormal; wherein, the previous working environment data when the communication status indication is abnormal is the working environment boundary value of the chip to be tested. The chip testing method, related equipment and computer-readable storage medium provided by the embodiment of the present application have the advantages of relatively accurately and conveniently testing the boundary value of the working environment data of the chip to be tested and obtaining the distribution range of the working environment data of the chip to be tested.

Description

Technical Field

[0001] The present invention relates to the field of chips, and in particular, embodiments of the present invention relate to a chip testing method, related equipment, and a computer-readable storage medium. Background Art

[0002] Currently, how to obtain driving working environment data for driving chips, related components on chips or certain electronic products (that is, signals that provide power or energy for related chips or products to make them work, for example, power signals or current signals that enable chips or components on chips to work) is becoming increasingly important.

[0003] For example, for the chip itself, the specific range of the chip's voltage, current and other working environment data is a key performance indicator. Therefore, the reference ideal working environment data range given by the chip design needs to be continuously revised through actual testing.

[0004] For example, there are many types of chip peripheral interface devices (eg, keyboard, mouse, printer, etc.), so providing a range of working environment data for on-chip interfaces is increasingly important for adapting to various devices.

[0005] Take the chip's working environment data as IO voltage (current) as an example, Figure 1 As shown, the prior art solution is to obtain Figure 1 The operating voltage or current of the IO circuit is generally measured directly. It is understandable that the results measured by direct measurement are the normal voltage fluctuation range under a certain usage environment. It is difficult to measure the actual boundary of the chip IO voltage (current), and it is inconvenient to limit specific test conditions. Summary of the Invention

[0006] The purpose of the embodiments of the present invention is to provide a chip testing method related device and a computer-readable storage medium. By using the embodiments of the present invention, the boundary values ​​of the working environment data of the chip to be tested can be tested relatively accurately and conveniently, and the distribution range of the working environment data of the chip to be tested can be obtained.

[0007] In the first aspect, an embodiment of the present invention provides a chip testing method, which is applied to a chip testing system, wherein the chip testing system includes a chip testing device and a device to be tested, the device to be tested is equipped with a chip to be tested, and the device to be tested is used to provide working environment data for the chip to be tested and establish communication with the chip testing device under the working environment data; the method includes: obtaining the communication status between itself and the device to be tested through the chip testing device; wherein the chip to be tested contained in the device to be tested operates in the target working environment data; when the communication status indicates normal, the adjustment step is determined according to a preset adjustment method, and the target working environment data is updated according to the adjustment step until the adjustment step reaches a preset threshold step and the communication status indicates abnormality; wherein the previous working environment data when the communication status indicates abnormality is the working environment boundary value of the chip to be tested.

[0008] In some embodiments, the chip testing device obtains the communication status between itself and the device under test, including: the chip testing device sends test data to the device under test; the chip testing device receives return data fed back by the device under test, and when the similarity between the test data and the return data is greater than a first threshold, determines that the communication status between the chip testing device and the device under test is normal; when the similarity between the test data and the return data is less than the first threshold, determines that the communication status between the chip testing device and the device under test is abnormal.

[0009] By providing test data to the device under test and checking the return data obtained by the test data fed back by the device under test, it is determined whether the data between the device under test and the chip test device can be transmitted normally, thereby more accurately inferring whether the function of the chip under test is normal. In addition, due to the existence of measurement errors, it is difficult for the test data and the return data to be completely identical. Therefore, after receiving the return data, the chip test device calculates the similarity between the return data and the test data. When the similarity between the return data and the test data is greater than a first threshold, it is also determined that the return data is the same as the test data, the communication status between the chip test device and the device under test is normal, and the working environment data of the chip under test currently working is the working environment data in which the chip under test can work normally; when the similarity between the return data and the test data is less than the first threshold, it is determined that the return data is different from the test data. At this time, it is believed that the chip under test has been unable to complete the forwarding of the test data normally, the chip under test is working abnormally, the communication status between the chip test device and the device under test is abnormal, and the working environment data of the chip under test currently working exceeds the working environment boundary value in which the chip under test can work normally, thereby reducing the impact of measurement errors on the measurement results.

[0010] In some embodiments, updating the target working environment data according to the adjustment step size includes: gradually reducing the target working environment data with the adjustment step size as the step size, and when the adjustment step size reaches a preset step size threshold and the communication status indicates an abnormality, determining that the target working environment data when the adjustment step size reaches the preset step size threshold and the communication status indicates an abnormality is the lower limit value that the chip under test can withstand; gradually increasing the target working environment data with the adjustment step size as the step size, and when the adjustment step size reaches the preset step size threshold and the communication status indicates an abnormality, determining that the working environment data when the adjustment step size reaches the preset step size threshold and the communication status indicates an abnormality is the upper limit value that the chip under test can withstand.

[0011] Setting a larger adjustment step can reduce the number of adjustments to the working environment data when the communication status indicates an abnormal situation; setting a smaller adjustment step can improve the accuracy of the upper and lower limits of the working environment data; adjusting the adjustment step in the process of determining the working environment boundary value of the chip to be tested can achieve the effect of both reducing the number of adjustments and improving the accuracy of the results.

[0012] In some embodiments, the method further includes: when the upper limit value that the chip under test can withstand is less than the value determined when the chip under test is in the thermal design power consumption TDP, determining that the chip under test is a normal chip; when the upper limit value that the chip under test can withstand is greater than or equal to the value determined when the chip under test is in the thermal design power consumption TDP, determining that the chip under test is an abnormal chip.

[0013] By comparing the measured upper limit value that the chip under test can withstand with the value determined when the chip under test is under the thermal design power consumption TDP, it is determined whether the chip under test is an abnormal chip, thereby further detecting whether the chip under test is an abnormal chip.

[0014] In some embodiments, the working environment data is the working voltage or working current of the chip under test.

[0015] In the second aspect, an embodiment of the present invention further provides a chip testing device for testing a chip to be tested, wherein the chip to be tested is mounted in the device to be tested, and the device to be tested provides working environment data for the chip to be tested, and the chip testing device comprises: a communication module, wherein the communication module is used to communicate with the device to be tested; a communication status acquisition module, wherein the communication status acquisition module is used to obtain the communication status between the chip testing device and the device to be tested when the chip to be tested works under the target working environment data; a processing module, wherein the processing module is used to determine the adjustment step according to a preset adjustment method when the communication status indication is normal, and update the target working environment data according to the adjustment step until the preset threshold step is reached and the communication status indication is abnormal; wherein, the previous working environment data when the communication status indication is abnormal is the working environment boundary value of the chip to be tested.

[0016] In some embodiments, the communication module includes a sending submodule and a receiving submodule; the sending submodule is used to send test data to the device under test, and the receiving submodule is used to receive return data fed back by the device under test; the communication status acquisition module is used to determine that the communication status between the device under test is normal when the similarity between the test data and the return data is greater than a first threshold, and to determine that the communication status between the device under test is abnormal when the similarity between the test data and the return data is less than the first threshold.

[0017] In some embodiments, the device also includes: a power consumption judgment module, which is used to determine that the chip under test is a normal chip when the upper limit value that the chip under test can withstand is less than the value determined when the chip under test is under the thermal design power consumption TDP, and to determine that the chip under test is an abnormal chip when the upper limit value that the chip under test can withstand is greater than or equal to the value determined when the chip under test is under the thermal design power consumption TDP.

[0018] By setting up a power consumption judgment module, the upper limit value that the chip under test can withstand is compared with the value determined when the chip under test is under the thermal design power consumption TDP, so as to determine whether the chip under test is an abnormal chip, thereby achieving further detection of whether the chip under test is an abnormal chip.

[0019] In a third aspect, an embodiment of the present invention further provides a chip testing system for testing a chip to be tested, the system comprising a chip testing device as described above and a device to be tested that is communicatively connected to the chip testing device; the chip to be tested is mounted in the device to be tested, and the device to be tested provides working environment data for the chip to be tested.

[0020] In a fourth aspect, an embodiment of the present invention further provides an electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the chip testing method as described above.

[0021] In a fifth aspect, an embodiment of the present invention further provides a computer storage medium on which a computer program is stored, characterized in that when the computer program is executed by a processor, it can implement the chip testing method as described above.

[0022] In the chip testing method-related devices and computer-readable storage media provided in some embodiments of the present invention, the chip testing device obtains the communication status between itself and the device under test. When the communication status indicates normal, it indicates that the working status of the chip under test is also normal. The adjustment step is determined according to a preset adjustment method, and the target working environment data of the chip under test is updated according to the adjustment step until the adjustment step reaches the preset threshold step and the communication status indicates abnormality. The abnormal communication status indicates that the working status of the chip under test is also abnormal, which means that the current working environment data exceeds the boundary value of the working environment data when the chip under test is working normally. The previous working environment data when the communication status indicates abnormality is the working environment boundary value of the chip under test. This achieves accurate measurement of the boundary value of the working environment data of the chip under test. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments of the present invention. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0024] Figure 1 A method for obtaining the voltage or current range of the IO circuit interface on the CPU chip provided in the related technology;

[0025] Figure 2 A schematic diagram of the process of a chip testing method provided in the first embodiment of the present invention;

[0026] Figure 3 A schematic diagram of the structure of a chip testing system used in the process of the chip testing method provided in the first embodiment of the present invention;

[0027] Figure 4 A schematic flow chart of a chip testing method according to a second embodiment of the present invention;

[0028] Figure 5 A schematic diagram of the structure of a chip testing device provided in the third embodiment of the present invention;

[0029] Figure 6 A schematic structural diagram of a chip testing device provided in another embodiment of the present invention;

[0030] Figure 7 A schematic structural diagram of a chip testing device provided in a fourth embodiment of the present invention;

[0031] Figure 8 A schematic diagram of the structure of a chip testing system provided in a fifth embodiment of the present invention;

[0032] Figure 9 This is a structural diagram of an electronic device provided in Example 6 of the present invention. DETAILED DESCRIPTION

[0033] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0034] It should be noted that similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and should not be understood as indicating or implying relative importance.

[0035] At least in order to solve the technical defects brought about by direct measurement in the background technology part, some embodiments of the present application automatically adjust the working environment data of the object under test (for example, the chip IO voltage (current)), and use the communication monitoring mechanism to determine whether the function of the object under test is abnormal, and finally gradually determine the specific range of the driving signal required by the object under test, for example, obtain the specific range of the chip IO voltage (current).

[0036] Please see Figure 1 As described in the background technology section, the direct measurement results are the normal voltage fluctuation range under a certain usage environment. It is difficult to measure the actual boundaries of working environment data such as chip IO voltage (current), and specific test conditions need to be limited, which is relatively inconvenient.

[0037] In response to the above technical problems, this application proposes the following chip testing method related equipment and computer readable storage medium. Figure 2 An exemplary chip testing method provided by an embodiment of the present application is described, which is applied to Figure 3The chip testing system shown in the figure includes a chip testing device 100 and a device under test 200. The device under test 200 is equipped with a chip under test 300. The device under test 200 is used to provide a working environment for the chip under test 300. The chip under test 300 works in the working environment provided by the device under test 200. The working environment data is the quantitative data of the working environment provided by the device under test 200 for the chip under test 300.

[0038] In some embodiments of the present application, the operating environment data is the operating voltage or operating current of the chip under test 300 when it is operating in the device under test 200. It will be understood that the aforementioned operating environment data, namely the operating voltage or operating current of the chip under test 300 when it is operating in the device under test 200, is merely an example in some embodiments of the present application. In other embodiments of the present application, the operating environment data may also be other types of data, such as the power of the chip under test 300, the bus frequency of the chip under test 300, etc., and may be flexibly used according to the type of operating environment data actually required to be measured by the chip under test 300.

[0039] The chip testing method is as follows Figure 2 As shown, it may include but is not limited to the following steps:

[0040] Step S101: The chip testing device obtains the communication status between itself and the device under test.

[0041] The implementation process of S101 is described below by way of example.

[0042] In some embodiments of the present application, in order to obtain the communication status between itself and the device under test, the chip testing device needs to first send test data to the device under test, then receive return data fed back by the device under test, and finally obtain the working status based on the test data and the return data. In some embodiments of the present application, after the test data is sent to the device under test, the chip under test running in the device under test will forward the test data. The test data forwarded by the chip under test and sent to the chip testing device is the return data. If the test data and the return data are the same, it means that the chip under test can achieve normal forwarding function. At this time, the working environment data of the chip under test is the working environment data that the chip under test can work normally.

[0043] In some embodiments of the present application, due to the existence of measurement errors, it is difficult to achieve complete identity between the test data and the return data. Therefore, in some embodiments of the present application, a first threshold is preset, and the first threshold is a preset constant value. After receiving the return data, the chip testing device calculates the similarity between the return data and the test data. When the similarity between the return data and the test data is greater than the first threshold, it is also determined that the return data is the same as the test data, and the communication status between the chip testing device and the device under test is normal. The current working environment data of the chip under test is the working environment data in which the chip under test can work normally; when the similarity between the return data and the test data is less than the first threshold, it is determined that the return data is different from the test data. At this time, it is considered that the chip under test has been unable to complete the forwarding of the test data normally, the chip under test is working abnormally, the communication status between the chip testing device and the device under test is abnormal, and the current working environment data of the chip under test exceeds the working environment boundary value in which the chip under test can work normally.

[0044] That is to say, in some embodiments of the present application, the chip testing device determines whether the data between the device under test and the chip testing device can be transmitted normally by providing test data to the device under test and checking the return data obtained from the test data fed back by the device under test, thereby more accurately inferring whether the function of the chip under test is normal.

[0045] It is understandable that in some embodiments of the present application, in addition to completing the process of forwarding the test data, the chip under test can also use a preset data processing algorithm to process the test data, such as taking the derivative of the test data, adding one to the value, reversing the test data, etc., and forwarding the data obtained after the data processing to the chip testing device as return data. The chip testing device performs the same processing on the test data to obtain test data that is finally compared with the return data, and then calculates the similarity between the return data and the test data at this time to determine whether the communication status between the device under test and the chip testing device is normal. Using the chip under test to process the test data and then forwarding it to the chip testing device can ensure that the return data is the data processed by the chip under test, avoid the test data sent by the chip testing device being incorrectly collected, which will affect the test results of the chip under test, and improve the accuracy of the test results of the chip under test.

[0046] Step S102: When the communication status indication is normal, determine the adjustment step according to the preset adjustment method, and update the target working environment data according to the adjustment step until the adjustment step reaches the preset threshold step and the communication status indication is abnormal.

[0047] The implementation process of S102 is described below by way of example.

[0048] When the chip to be tested is designed, there is an initialized working environment data. The chip to be tested is designed and produced based on this initialized working environment data. However, various errors may exist during the production process, resulting in a certain difference between the working environment data of the chip to be tested that can work normally and the initialized working environment data. What this application aims to achieve is to perform more accurate measurement of the working environment data that enables the chip to be tested to work normally.

[0049] In some embodiments of the present application, the working environment data initially provided by the device under test to the chip under test is the working environment data initialized when the chip under test is designed, that is, the target working environment data. In the process of adjusting the target working environment data, it is necessary to measure the upper limit and lower limit of the working environment data at which the chip under test can work normally. For the lower limit that the chip under test can withstand, the target working environment data provided by the device under test can be gradually reduced with the adjustment step length as the step length, until the communication state between the device under test and the chip testing device changes from normal to abnormal, stop reducing the target working environment data provided by the device under test, and at this time determine that the working environment data when the communication state finally remains normal is the lower limit that the chip under test can withstand, that is, determine that the previous working environment data when the communication state changes to abnormal is the lower limit that the chip under test can withstand.

[0050] The measurement process of the upper limit value that the chip under test can withstand is similar to the measurement process of the lower limit value that the chip under test can withstand, that is, the target working environment data provided by the device under test is gradually increased with the adjustment step size, until the communication status between the device under test and the chip testing device changes from normal to abnormal, and then the increase of the target working environment data provided by the device under test is stopped. At this time, the working environment data when the communication status last remained normal is determined to be the upper limit value that the chip under test can withstand, that is, the previous working environment data when the communication status changed to abnormal is determined to be the upper limit value that the chip under test can withstand.

[0051] In some embodiments of the present application, the adjustment step size can also be adjusted in the process of determining the working environment boundary value of the chip under test. When the device under test is connected to the chip testing device, the chip testing device first uses a larger step size to adjust the target working environment data (which can be called coarse adjustment). When the coarse adjustment is performed until the communication state between the device under test and the chip testing device becomes abnormal, the adjustment step size is reduced, and the target working environment data is adjusted to the working environment data at the last moment when the communication state between the device under test and the chip testing device remains normal. The target working environment data at this time is adjusted again using the reduced adjustment step size (which can be called fine adjustment) until the communication state between the device under test and the chip testing device becomes abnormal again. At this time, it is considered that the previous working environment data when the communication state indicates abnormality is the working environment boundary value of the chip under test.

[0052] In some embodiments of the present application, the process of adjusting the size of the adjustment step can be performed multiple times, that is, each time the communication status between the device under test and the chip testing device becomes abnormal, the size of the adjustment step is reduced until the adjustment step reaches a preset threshold step, and the communication status between the device under test and the chip testing device becomes abnormal again. At this time, the previous working environment data when the communication status indicates abnormality is considered to be the working environment boundary value of the chip under test.

[0053] Using a coarse adjustment method to confirm the working environment boundary value of the chip under test can effectively reduce the number of times the target working environment data is adjusted and improve test efficiency. Using a fine adjustment method to confirm the working environment boundary value of the chip under test on the basis of coarse adjustment can improve the measurement accuracy of the working environment boundary value of the chip under test while improving test efficiency.

[0054] In some embodiments of the present application, the chip testing device adjusts the target working environment data provided by the device under test by sending a driving signal to the device under test. Sending a driving signal to the device under test requires first generating a driving signal. For example, the chip testing device may include a driving signal generating device (for example, a power control IC and corresponding circuits), which generates or updates the corresponding driving signal.

[0055] Two examples of the drive signal generating device are exemplarily described below.

[0056] For example, in some embodiments of the present application, when the target operating environment data is the IO voltage (current) of the chip under test, the drive signal generating device includes a single-chip microcontroller dedicated to voltage and current regulation (this function can also be performed by a processor in the test equipment), with built-in programs for coarse adjustment, fine adjustment, and step size setting. In some embodiments of the present application, corresponding coarse adjustment and fine adjustment programs can also be set on the test equipment.

[0057] For example, in some embodiments of the present application, the driving signal generating device is a voltage and current adjustable circuit, which is mainly divided into two types, one is a digital power supply circuit (i.e., PWM CONTROLLER+POWER STAGE), and the second is a DC-DC circuit, in which the resistance values ​​of the current limiting resistor and the feedback resistor can be adjusted by a dedicated single-chip microcomputer (or system processor) to achieve voltage and current regulation.

[0058] Step S103: The last working environment data when the communication status indicates abnormality is used as the working environment boundary value of the chip under test.

[0059] The implementation process of S103 is described below by way of example.

[0060] In some embodiments of the present application, when the communication status between the chip testing device and the device under test changes from normal to abnormal, it indicates that the current working environment data of the chip under test has exceeded the working environment boundary value of the chip under test. Under the previous working environment data when the communication status indicates abnormality, the chip under test can still maintain normal operation. If this working environment data is exceeded, the chip under test can no longer maintain normal operation. Therefore, the previous working environment data when the communication status indicates abnormality is used as the working environment boundary value of the chip under test.

[0061] In the chip testing method provided in the first embodiment of the present application, the chip testing device obtains the communication status between itself and the device under test. When the communication status indication is normal, it indicates that the working status of the chip under test is also normal. The adjustment step is determined according to the preset adjustment method, and the target working environment data of the chip under test is updated according to the adjustment step until the adjustment step reaches the preset threshold step and the communication status indication is abnormal. The abnormal communication status indication indicates that the working status of the chip under test is also abnormal, which means that the current working environment data exceeds the boundary value of the working environment data when the chip under test is working normally. The previous working environment data when the communication status indication is abnormal is the working environment boundary value of the chip under test. This achieves accurate measurement of the boundary value of the working environment data of the chip under test.

[0062] The second embodiment of the present application provides a chip testing method, specifically as follows: Figure 4 As shown, the following steps are included:

[0063] Step S201: The chip testing device obtains the communication status between itself and the device under test.

[0064] Step S202: When the communication status indication is normal, determine the adjustment step according to the preset adjustment method, and update the target working environment data according to the adjustment step until the adjustment step reaches the preset threshold step and the communication status indication is abnormal.

[0065] Step S203: The last working environment data when the communication status indicates abnormality is used as the working environment boundary value of the chip under test.

[0066] It can be understood that steps S201 to S203 in the chip testing method provided in the second embodiment of the present application are roughly the same as steps S101 to S103 in the first embodiment. For details, please refer to the specific description of the aforementioned embodiment and will not be repeated here.

[0067] Step S204: Determine whether the upper limit value that the chip under test can withstand is less than the value determined when the chip under test is under the thermal design power consumption TDP. If so, execute step S205; if not, execute step S206.

[0068] The implementation process of S101 is described below by way of example.

[0069] Thermal Design Power (TDP) is used to indicate the maximum heat dissipation that a chip can achieve when operating at full load. When the chip under test is in the TDP state, it corresponds to a value of the working environment data. If the upper limit value that the chip under test can withstand, as tested in step S203, is greater than or equal to the value of the working environment data determined for the chip under test under TDP, it indicates that the chip under test can still operate normally when the target working environment data provided by the test device is higher than the value of the working environment data determined under TDP. However, under this working environment data, the power of the chip under test has exceeded the maximum thermal design power consumption that the chip under test can achieve, indicating that the chip under test is an abnormal chip, and step S206 is executed. Conversely, if the upper limit value that the chip under test can withstand is less than the value determined for the chip under test under the thermal design power consumption TDP, it indicates that the chip under test is a normal chip, and step S205 is executed.

[0070] Step S205: Determine whether the chip to be tested is a normal chip.

[0071] Step S206: Determine whether the chip to be tested is an abnormal chip.

[0072] Compared with the prior art, the chip testing method provided in Example 2 of the present application retains all the technical features of Example 1 and has the same technical effects as Example 1. In addition, in Example 2 of the present application, by comparing the upper limit value that the chip under test can withstand obtained by measurement with the value determined when the chip under test is under the thermal design power consumption TDP, it is determined whether the chip under test is an abnormal chip, thereby achieving further detection of whether the chip under test is an abnormal chip.

[0073] The third embodiment of the present application provides a chip testing device for testing a chip to be tested. When the chip testing device is testing the chip to be tested, the chip to be tested is mounted in the device to be tested, and the device to be tested provides working environment data for the chip to be tested. The chip testing device is specifically as follows: Figure 5 As shown, including:

[0074] Communication module 601, communication module 601 is used to communicate with the device under test, including sending test data to the device under test and receiving return data returned by the device under test; communication status acquisition module 602, communication status acquisition module 602 is used to obtain the communication status between the chip testing device and the device under test when the chip under test operates under the target working environment data, that is, the communication status acquisition module 602 is used to execute step S101 in the aforementioned embodiment one; processing module 603, processing module 603 is used to determine the adjustment step according to the preset adjustment method when the communication status indication is normal, and update the target working environment data according to the adjustment step until the preset threshold step is reached and the communication status indication is abnormal; wherein, the previous working environment data when the communication status indication is abnormal is the working environment boundary value of the chip under test, that is, the processing module 603 is used to execute steps S102 and S103 in the aforementioned embodiment one.

[0075] It is not difficult to find that the chip testing device provided in Example 3 of the present application is an embodiment of the device corresponding to the chip testing method provided in the aforementioned Example 1. The technical details in Example 3 of the present application can be applied in Example 1, and the technical details in Example 1 of the present application can also be applied in Example 3.

[0076] Compared with the prior art, in the chip testing device provided in the third embodiment of the present application, the chip testing device obtains the communication status between itself and the device under test through the communication module 601 and the communication status acquisition module 602. When the communication status indication is normal, it indicates that the working status of the chip under test is also normal. The processing module 603 determines the adjustment step according to the preset adjustment method, and updates the target working environment data of the chip under test according to the adjustment step until the adjustment step reaches the preset threshold step and the communication status indication is abnormal. The abnormal communication status indication indicates that the working status of the chip under test is also abnormal, that is, the current working environment data exceeds the boundary value of the working environment data when the chip under test is working normally. The previous working environment data when the communication status indication is abnormal is the working environment boundary value of the chip under test. This achieves accurate measurement of the boundary value of the working environment data of the chip under test.

[0077] Furthermore, in some other embodiments of the present application, such as Figure 6 As shown, the communication module 601 includes a sending submodule 6011 and a receiving submodule 6012; the sending submodule 6011 is used to send test data to the device under test, and the receiving submodule 6012 is used to receive return data fed back by the device under test; the communication status acquisition module 602 is used to determine that the communication status between the device under test is normal when the similarity between the test data and the return data is greater than a first threshold, and determine that the communication status between the device under test is abnormal when the similarity between the test data and the return data is less than the first threshold.

[0078] The fourth embodiment of the present application provides a chip testing device, such as Figure 7 As shown, it also includes: a communication module 601, a communication status acquisition module 602, and a processing module 603. In addition, in this embodiment, the chip testing device also includes a power consumption judgment module 604. The power consumption judgment module 604 is used to determine that the chip under test is a normal chip when the upper limit value that the chip under test can withstand is less than the value determined by the thermal design power consumption TDP of the chip under test, and to determine that the chip under test is an abnormal chip when the upper limit value that the chip under test can withstand is greater than or equal to the value determined by the thermal design power consumption TDP of the chip under test.

[0079] It is not difficult to find that the chip testing device provided in the fourth embodiment of the present application is an embodiment of the device corresponding to the chip testing method provided in the aforementioned second embodiment. The technical details in the fourth embodiment of the present application can be applied in the second embodiment, and the technical details in the second embodiment of the present application can also be applied in the fourth embodiment.

[0080] Compared with the prior art, in the chip testing device provided in the fourth embodiment of the present application, a power consumption judgment module 604 is set to compare the upper limit value that the chip under test can withstand with the value determined when the chip under test is under the thermal design power consumption TDP, to determine whether the chip under test is an abnormal chip, thereby realizing further detection of whether the chip under test is an abnormal chip.

[0081] The fifth embodiment of the present application provides a chip testing system for testing a chip to be tested, such as Figure 8 As shown, the chip testing system includes a chip testing device 901 as provided in the aforementioned embodiment and a device to be tested 902 connected to the chip testing device 901. The chip to be tested is mounted in the device to be tested 902. The device to be tested 902 provides working environment data for the chip to be tested. The chip testing device 901 executes the chip testing method provided in the aforementioned embodiment to test the chip to be tested.

[0082] Compared with the prior art, the chip testing system provided in the fifth embodiment of the present application includes the chip testing device provided in the aforementioned embodiment, and the aforementioned chip testing method is run in the chip testing device, so it has the same technical effect as the aforementioned embodiment. For details, please refer to the specific description of the aforementioned embodiment.

[0083] The sixth embodiment of the present application provides an electronic device, such as Figure 9As shown, it includes: at least one processor 1001; and a memory 1002 that is communicatively connected to the at least one processor 1001; wherein the memory 1002 stores instructions that can be executed by the at least one processor 1001, and the instructions are executed by the at least one processor 1001 to enable the at least one processor 1001 to execute the chip testing method as described above.

[0084] The memory 1002 may be a read-only memory 1002 (ROM), a random access memory 1002 (RAM), or other memory 1002. In the embodiment of the present application, the memory 1002 is used to store data and various algorithms and commands, such as the algorithm for determining the IO voltage (current) range in the embodiment of the present application, the entire process, and the final result.

[0085] In the embodiments of the present application, the memory 1002 may include a physical device for storing information, typically digitizing the information and then storing it in a medium utilizing electrical, magnetic, or optical methods. The memory 1002 of this embodiment may further include: a device that stores information using electrical energy, such as RAM, ROM, etc.; a device that stores information using magnetic energy, such as a hard disk, floppy disk, magnetic tape, magnetic core memory 1002, bubble memory 1002, or USB flash drive; and a device that stores information optically, such as a CD or DVD. Of course, there are other types of memory 1002, such as quantum memory 1002, graphene memory 1002, and so on.

[0086] The processor 1001 is configured to read a computer program from the memory 1002 and execute the computer program to implement the chip testing method provided in the aforementioned embodiment.

[0087] It should be noted that the processor 1001 can be a central processing unit (CPU), and the processor 1001 can also be other processors 1001, digital signal processors 1001 (DSP), application specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The processor 1001 can be a microprocessor 1001 or the processor 1001 can also be any conventional processor 1001, etc. The processor 1001 can also be an integrated circuit chip with signal processing capabilities. In the implementation process, the various steps of the IO voltage (current) test method of the present application can be completed by the hardware integrated logic circuit in the processor 1001 or the instructions in the form of software.

[0088] In some embodiments of the present application, a drive signal generating device 1003 is further included. The drive signal generating device 1003 is configured to receive a drive signal adjustment instruction sent by the processor 1001 to adjust the drive signal provided to the device under test. After receiving the drive signal, the device under test adjusts the working environment data provided to the chip under test according to the drive signal.

[0089] For example, in some embodiments of the present application, the working environment data is the IO voltage or IO current of the chip, and the drive signal generating device 1003 is an IO voltage (current) control module, which is mainly composed of a power control IC and corresponding circuits.

[0090] The working process of the IO voltage (current) control module is described below by way of example.

[0091] In some embodiments of the present application, after receiving the drive signal adjustment instruction from the processor 1001, the IO voltage (current) control module constructs a drive signal according to the drive signal adjustment instruction and sends the drive signal to the device under test to control the device under test to adjust the IO voltage (current) provided to the chip under test accordingly.

[0092] In some embodiments of the present application, the driving signal generating device 1003 may also automatically adjust according to the levels pre-divided by the processor 1001 and working environment data such as IO voltage (current) provided by the device under test to the chip under test.

[0093] like Figure 9As shown, in some embodiments of the present application, the electronic device further includes: a display module 1004, which is configured to display the driving signal boundary value and / or receive an input driving signal adjustment step value.

[0094] It should be noted that in some embodiments of the present application, the display module is also used to display the content of the entire process, including the communication status between the device under test and the chip testing device, the similarity value between the returned data and the test data, etc. The embodiments of the present application do not limit the specific content displayed by the display module.

[0095] Display module 1004: This module is not limited to various display modes, and can be, for example, a digital tube display or liquid crystal screen, LCD, OLED, etc. Connection methods are not limited, such as IIC, SPI, UART, MIPI, DP, eDP, and HDMI. This module is mainly used to visually display the entire test process and final results.

[0096] like Figure 9 As shown, in some embodiments of the present application, the electronic device further includes: a communication interface 1005. The communication interface 1005 uses a transceiver device such as, but not limited to, a transceiver to implement communication between the chip testing device and the device under test.

[0097] Embodiment 7 of the present application provides a computer storage medium having a computer program stored thereon. When the computer program is executed by a processor, the method of any embodiment included in the above-mentioned method for obtaining a driving signal can be implemented.

[0098] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions and operations of the devices, methods and computer program products according to the multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and the module, program segment or a part of the code contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or can be implemented using a combination of dedicated hardware and computer instructions.

[0099] In addition, the functional modules in each embodiment of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0100] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0101] The foregoing is merely an embodiment of the present application and is not intended to limit the scope of protection of the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included within the scope of protection of the present application. It should be noted that similar reference numerals and letters represent similar items in the following figures. Therefore, once an item is defined in one figure, it does not need to be further defined or explained in subsequent figures.

[0102] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

[0103] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

Claims

1. A chip testing method, characterized in that: Applied to a chip testing system, the chip testing system includes a chip testing device and a device under test, the device under test is equipped with a chip under test, the device under test is used to provide working environment data for the chip under test, and establish communication with the chip testing device under the working environment data; the method includes: The chip testing device acquires the communication status between itself and the device under test through the chip testing device; wherein the chip under test contained in the device under test operates in the target working environment data; When the communication status indication is normal, determining an adjustment step length according to a preset adjustment method, and updating the target working environment data according to the adjustment step length until the adjustment step length reaches a preset threshold step length and the communication status indication is abnormal; wherein the previous working environment data when the communication status indication is abnormal is the working environment boundary value of the chip under test; When the upper limit value that the chip under test can withstand is less than the value determined when the chip under test is in the thermal design power consumption TDP, the chip under test is determined to be a normal chip; and when the upper limit value that the chip under test can withstand is greater than or equal to the value determined when the chip under test is in the thermal design power consumption TDP, the chip under test is determined to be an abnormal chip.

2. The method according to claim 1, wherein The obtaining of the communication status between the chip testing device and the device under test by the chip testing device includes: The chip testing device sends test data to the device under test; The chip testing device receives return data fed back by the device under test, and determines that the communication status between the chip testing device and the device under test is normal when the similarity between the test data and the return data is greater than a first threshold; and determines that the communication status between the chip testing device and the device under test is abnormal when the similarity between the test data and the return data is less than the first threshold.

3. The method according to claim 1, wherein The updating of the target working environment data according to the adjustment step size includes: The target operating environment data is gradually reduced with the adjustment step length as the step length, and when the adjustment step length reaches a preset step length threshold and the communication status indicates an abnormality, determining the previous operating environment data when the adjustment step length reaches the preset step length threshold and the communication status indicates an abnormality as a lower limit value that the chip under test can withstand; Taking the adjustment step as the step, gradually increase the target working environment data. When the adjustment step reaches the preset step threshold and the communication status indicates an abnormality, determine that the previous working environment data when the adjustment step reaches the preset step threshold and the communication status indicates an abnormality is the upper limit value that the chip under test can withstand.

4. The method according to claim 1, wherein The working environment data is the working voltage or working current of the chip to be tested.

5. A chip testing device, characterized in that: Used to test a chip under test, the chip under test is mounted in a device under test, and the device under test provides working environment data for the chip under test. The chip testing device includes: a communication module, the communication module being used to communicate with the device under test; a communication status acquisition module, configured to acquire a communication status between the chip testing device and the device under test when the chip under test operates under target operating environment data; a processing module, the processing module being configured to determine an adjustment step size according to a preset adjustment method when the communication status indication is normal, and update the target working environment data according to the adjustment step size until a preset threshold step size is reached and the communication status indication is abnormal; wherein the previous working environment data when the communication status indication is abnormal is the working environment boundary value of the chip under test; A power consumption judgment module is used to determine that the chip under test is a normal chip when the upper limit value that the chip under test can withstand is less than the value determined under the thermal design power consumption TDP of the chip under test, and to determine that the chip under test is an abnormal chip when the upper limit value that the chip under test can withstand is greater than or equal to the value determined under the thermal design power consumption TDP of the chip under test.

6. The device according to claim 5, characterized in that The communication module includes a sending submodule and a receiving submodule; The sending submodule is used to send test data to the device under test, and the receiving submodule is used to receive return data fed back by the device under test; The communication status acquisition module is used to determine that the communication status between the device under test is normal when the similarity between the test data and the return data is greater than a first threshold; and to determine that the communication status between the device under test is abnormal when the similarity between the test data and the return data is less than the first threshold.

7. A chip testing system, characterized in that: Used to test a chip to be tested, the system comprising a chip testing device according to any one of claims 5 to 6 and a device to be tested communicatively connected to the chip testing device; The chip under test is mounted in a device under test, and the device under test provides working environment data for the chip under test.

8. An electronic device, characterized in that: include: at least one processor; and, a memory communicatively coupled to the at least one processor; The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can perform the chip testing method according to any one of claims 1 to 4.

9. A computer storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the chip testing method according to any one of claims 1 to 4 can be implemented.

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