A method for handling gate pulse train contention timing

Abstract

This invention provides a method for handling gate pulse train contention timing. The method, developed based on an FPGA, includes the following steps: S1: Delaying the pulse modulation signal, and using the rising and falling edges of the delayed pulse modulation signal to trigger the generation of a leading-edge trigger pulse train and a turning-off leading-edge pulse train, respectively; S2: Widening the pulse modulation signal, and using the rising and falling edges of the widened pulse modulation signal to trigger the generation of a turning-off trailing-edge pulse train and a trailing-edge trigger pulse train, respectively; S3: Using the leading-edge trigger pulse and the turning-off trailing-edge pulse train to generate the rising edge of the secondary-side pulse modulation signal; using the trailing-edge trigger pulse train and the turning-off leading-edge pulse train to generate the falling edge of the secondary-side pulse modulation signal. This method effectively avoids the problem of gate drive waveform distortion caused by contention between leading and trailing-edge pulse trains under low repetition rate and wide pulse conditions.

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