Reference voltage circuit for generating a reference voltage

Abstract

The present invention provides a reference voltage circuit, comprising: a first circuit including a first PN junction device and a first resistor connected in series between a power supply node and a first node, a second resistor connected between the first node and an intermediate node, and a third resistor connected between the intermediate node and a reference voltage output node; and a second circuit including a second PN junction device connected between the power supply node and a second node and a fourth resistor connected between the second node and the intermediate node. A feedback current causes the voltage across the first resistor to cancel out the voltage change across the first PN junction device. A correction current is applied to boost and / or draw current in a reference voltage generator to extend the operating temperature range.

Description

Technical Field

[0001] The technology of the present invention relates to a reference voltage generator that maintains a constant reference voltage within a temperature range with very little variation, and more particularly, to extending the operating temperature range of such a reference voltage generator. Background Art

[0002] Reference voltage generators are widely used in electronic circuits including integrated circuits. It is desired that such circuits generate a reference voltage that varies very little with temperature. A bandgap reference circuit based on the bandgap voltage characteristic of a PN junction in a PN junction device such as a diode and a transistor is a commonly used component in a circuit for generating a reference voltage. The bandgap reference circuit can maintain a reference voltage value variation of only a few mV within an operating temperature range of, for example, 0 °C to 70 °C. It is desired to provide a technology that can extend the operating temperature range of a reference voltage generator. Summary of the Invention

[0003] The technology described in the present invention can be applied to reduce the variation of the reference voltage generated within the operating temperature range in a reference voltage circuit including a bandgap reference circuit. Brief Description of the Drawings

[0004] Figure 1 It is a schematic diagram of a bandgap reference voltage generator.

[0005] Figures 2A to 2C Plots the curve of the reference voltage versus temperature when the saturation current conditions of transistor Q1 and transistor Q2 in the circuit such as Figure 1 are different.

[0006] Figure 3 It is a schematic diagram of a bandgap reference voltage generator including a boosting correction current source for extending the operating temperature range of the circuit.

[0007] Figure 4 It is a diagram of a synthetic correction current that can extend the operating temperature range to -40 °C.

[0008] Figure 5 Plots the correction current and the uncorrected current through resistor R0 in the circuit of Figure 3 .

[0009] Figure 6 Plots the corrected reference voltage and the uncorrected reference voltage when the correction current applied Figure 4 is applied.

[0010] Figure 7 It is a schematic diagram of a bandgap reference voltage generator including a drawing correction current source for correcting the imbalance of the generated reference voltage.

[0011] Figure 8 It can be used to Figure 2BGraph of the magnitude correction current for the shift of the reference voltage curve.

[0012] Figure 9 Schematic diagram of a current subtractor and a current attenuator that can be used to generate the correction current as described in the present invention.

[0013] Figure 10 It includes similar to Figure 9 Schematic diagram of a reference voltage generator of a current synthesizer that can correct the reference voltage in a lower temperature range.

[0014] Figure 11 It is the curve of the current of transistor N1 in the circuit of Figure 10 within the temperature range when RN2 is equal to zero.

[0015] Figure 12 It is the curve of the current of transistor N3 in the circuit of Figure 10 within the temperature range when RN2 is equal to zero.

[0016] Figure 13 It is based on Figure 10 the change in the value of resistor RN2 for Figure 10 the simulation of the change in the current of transistor N4.

[0017] Figure 14 It is based on Figure 10 the change in the ratio value of the sizes of transistor N4 and transistor N5 in the circuit to generate the simulated curve of the reference voltage.

[0018] Figure 15 Schematic diagram of a reference voltage generator that includes two current synthesizers that can correct the reference voltage in a lower temperature range and a higher temperature range.

[0019] Figure 16 It is Figure 15 the graph of the current in transistor N7 versus temperature.

[0020] Figure 17 It is Figure 15 the graph of the current in transistor N9 versus temperature.

[0021] Figure 18 It is at Figure 15 different resistance values of resistor RN9 for Figure 15 the graph of the current in transistor N10 versus temperature.

[0022] Figure 19 It is to show for Figure 15 different current attenuation conditions in the circuit, the graph of the reference voltage versus temperature in a higher temperature range.

[0023] Figure 20 is a graph of VREF of the circuit using Figure 15 and Figure 10 over an extended temperature range.

[0024] Figure 21 is a schematic diagram of a reference voltage generator including a current synthesizer for providing a cancellation correction current as described in reference Figure 7 .

[0025] Figure 22 is Figure 21 a graph of the current in transistor Q2 with and without a cancellation current in the circuit of

[0026] Figure 23 is Figure 21 a graph of the reference voltage with and without a cancellation current in the circuit of

[0027] Figure 24 is a schematic diagram of a reference voltage generator including two current synthesizers for correcting the reference voltage in a lower temperature range and a higher temperature range, and a current synthesizer for generating a cancellation correction current.

[0028] Figure 25 is a graph of the reference voltage of the circuit using Figure 24 , Figure 21 and Figure 15 over an extended temperature range.

[0029] Figure 26 is a graph of the boosting cancellation current for correcting the skew shown in Figure 2C .

[0030] Figure 27 is a schematic diagram of a reference voltage generator including a current synthesizer for providing a boosting cancellation current as described in reference Figure 26 .

[0031] Figure 28 is a graph of the reference voltage generated by the circuit of Figure 26 with and without the boosting cancellation current of Figure 27 .

[0032] Figure 29 is a schematic diagram of a reference voltage generator including two current synthesizers for correcting the reference voltage in a lower temperature range and a higher temperature range, and a current synthesizer for generating a boosting cancellation current as described in Figure 26 .

[0033] Figure 30 is a graph of the reference voltage of the circuit using Figure 27 , Figure 15 and Figure 10Graph of the reference voltage of the circuit within an extended temperature range.

[0034] Figure 31 Schematic diagram of a reference voltage generator with enhanced correction current according to another embodiment.

[0035] Figure 32 Is similar to Figure 31 Schematic diagram of a reference voltage generator with a drawn correction current in

[0036] Description of reference numerals

[0037] 10, 35, 35': Voltage output nodes

[0038] 30, 50, IB: Current sources

[0039] 90: Current subtractor

[0040] 91: Current attenuator

[0041] 94: First current source

[0042] 95: Second current source

[0043] 101: CTAT reference circuit

[0044] 110, 151, 152, 211, 241, 242, 243, 271, 291, 292, 293: Current synthesizers

[0045] 800, 801: Regions

[0046] A: Intermediate node

[0047] Cc: Capacitor

[0048] CO: PMOS transistor

[0049] GC, GP: Control voltages

[0050] I1, Icor: Correction currents

[0051] IC, Ic1, Ic2, Ic3, Ic4, IcA, IcB, IcC, IN1, IN2, IN3, IN7, IN8, IN9, IN13, IN14, IN19, IN20, IP, I Q1 , I Q2 , I Q2 ', I R0 , I R0 ': Currents

[0052] I S1 , I S2 : Saturation currents

[0053] N, P: Nodes

[0054] N0, N1, N2, N3, N4, N5, N6, N7, N8, N9, N10, N11, N12, N13, N14, N15, N16, N17, N18, N19, N20, N21, N22, N23, P0, P1, P2, P3, P4, P5, P6, P7, P8, Q1, Q2, Q3, Q4: Transistors

[0055] OP, OP1, OP2: Operational amplifiers

[0056] R0, r1, R1, r2, R2, r3, R3, R5, RN2, RN9, RN14, RN20: Resistors

[0057] VBE: Base - emitter voltage

[0058] VDD: Power supply potential

[0059] Vr3, VREF, VREF′: Voltages

[0060] ΔVBE: Voltage difference Detailed implementation manners

[0061] Reference Figures 1 to 32 Provide a detailed description of the embodiments of the present invention.

[0062] A developed bandgap reference circuit has two PN - junction devices, such as transistors or diodes, which are used to generate a junction voltage difference between both ends of a resistor (for example, the base - emitter voltage as a function of the bandgap voltage), and maintain the voltage drop across the resistor through feedback, and the voltage drop cancels the change of the junction voltage with temperature.

[0063] Figure 1 is a schematic diagram of a bandgap reference circuit based on PNP transistors. The circuit includes PNP transistor Q1 and PNP transistor Q2, whose bases and collectors are connected to ground, or other reference power supply nodes. Transistors Q1 and Q2 are of different sizes. As Figure 1As marked, for transistor Q2, M = n, and for transistor Q1, M = 1, where "n" can be a multiple of the size of transistor Q1. Transistor Q1 can be implemented by one transistor, and transistor Q2 can be implemented by "n" identical parallel transistors when, for example, "n" is an integer. For a given current value, the current density in transistors Q1 and Q2 varies in proportion to their sizes. Resistor r1 is connected between node N and the reference voltage output node 10 that generates the reference voltage VREF. Resistor r2 is connected between the emitter of transistor Q1 and the reference voltage output node 10 that generates the reference voltage VREF. In addition, the emitter of transistor Q1 is connected to node P at the "positive" input of operational amplifier OP1, such that the base-emitter voltage of transistor Q1 is applied at node P. Resistor r3 is connected between the emitter of transistor Q2 and node N that is connected to the "negative" input of operational amplifier OP1. The P-channel MOS transistor P0 is connected between the reference voltage output node 10 and a power potential such as VDD or other reference power supply node. The output of operational amplifier OP1 is connected in a feedback manner to the gate of the P-channel MOS transistor P0, such that a base-emitter voltage difference between transistors Q1 and Q2 is generated across resistor r3.

[0064] The base-emitter voltage VBE of a bipolar transistor similar to transistor Q1 and the voltage at node P have at least a negative temperature coefficient in at least a first-order approximation, and thus have a magnitude with a characteristic complementary to absolute temperature (CTAT). The base-emitter voltage difference ΔVBE, and the voltage Vr3 across resistor r3 in this configuration have at least a positive temperature coefficient in at least a first-order approximation, and thus have a magnitude with a characteristic proportional to absolute temperature (PTAT).

[0065] As used in the present invention, a CTAT current or CTAT voltage is a current or voltage having a magnitude with at least a negative temperature coefficient in at least a first-order approximation within the relevant operating temperature range. As used in the present invention, a PTAT current or PTAT voltage is a current or voltage having a magnitude with at least a positive temperature coefficient in at least a first-order approximation within the relevant operating temperature range.

[0066] Thus, as a result of the feedback, the operational amplifier OP1 maintains the voltage at node N (equal to the base-emitter voltage of Q1) at node P. The values of resistor r1 and resistor r2 are typically equal, such that the reference voltage output at node 10 is equal to the voltage between node N and node P. Thus, the voltage difference ΔVBE of the base-emitter voltage VBE between transistor Q1 and transistor Q2 is canceled out by the voltage across resistor r3, which is induced by the current through resistor r3. When the base-emitter voltage VBE of transistor Q1 changes in a way that is inversely proportional to the absolute temperature CTAT, the operational amplifier generates a control voltage GP to induce a current that is proportional to the absolute temperature PTAT, such that the voltage across resistor r3 is equal to the difference in the base-emitter voltages. Thus, as the temperature increases, the base-emitter voltage VBE of transistor Q1 decreases and the voltage difference ΔVBE increases. The feedback increases the current across resistor r3 to track the increase in the voltage difference ΔVBE. The increase in the current also increases the voltage across resistor r1 and resistor r2 to compensate for the decrease in the base-emitter voltage VBE of transistor Q1. The same balance of CTAT voltage and PTAT voltage applies for decreasing temperatures. Thus, the reference voltage VREF can be relatively constant over the operating temperature range.

[0067] Figures 2A to 2C is the saturation current I in transistor Q1 S1 and the saturation current I in transistor Q2 S2 for the ratio of, similar to Figure 1 the graph of the reference voltage VREF versus temperature for the simulation of the bandgap reference circuit. Table 1 shows the comparison of the graphs.

[0068] Table 1

[0069] VREF (V) Figure 2A Figure 2B Figure 2C 125℃ 1.235 1.207 1.260 70℃ 1.240 1.216 1.261 0℃ 1.240 1.221 1.257 -40℃ 1.237 1.221 1.251 Δ 5.8E-03 1.4E-02 9.8E-03

[0070] At Figure 2A the ratio I S1 / I S2 equals 1. In this well-balanced case, as shown in Table 1, the voltage at 0 °C and the voltage at 70 °C are equal at 1.240 V. However, when the temperature exceeds 70 °C to 125 °C, the voltage drops to approximately 1.235 V; and when the temperature drops below 0 °C to approximately -40 °C, the voltage drops to approximately 1.237 V. Thus, the variation within the range of -40 °C to 125 °C is approximately 5.8 mV.

[0071] Figure 2B shows the case where the saturation current I S1 slightly exceeds the saturation current I S2 At Figure 2B the ratio I S1 / I S2is 1.0006 / 0.9999. As can be seen, this shifts the peak of the voltage curve downward to a lower temperature and results in a larger change in the reference voltage VREF. As seen in Table 1, for Figure 2B conditions, the change in the range from -40°C to 125°C is approximately 14 mV. However, the curve is relatively symmetric around the peak at approximately 35°C.

[0072] Figure 2C shows the saturation current I S1 a small amount less than the saturation current I S2 cases. In Figure 2B the ratio I S1 / I S2 is 0.9996 / 1.0000. As can be seen, this shifts the peak of the voltage curve upward to a higher temperature and results in a larger change in the reference voltage VREF. As seen in Table 1, for Figure 2C conditions, the change in the range from -40°C to 125°C is approximately 9.8 mV.

[0073] It should be noted that at typical operating temperatures from 0°C to 70°C, the reference voltage VREF in all three figures changes by 5 mV or less. However, as the temperature range is extended to -40°C and +125°C, the voltage VREF substantially decreases.

[0074] Figure 3 is a schematic diagram of a reference voltage circuit with an extended operating temperature range. The reference voltage circuit adds a current source 30 that generates a correction current Icor to compensate for the reference voltage VREF in a manner similar to Figure 1The tendency of substantial decline within an extended temperature range in a bandgap reference voltage circuit. The reference voltage circuit includes a first circuit and a second circuit. The first circuit and the second circuit respectively include a PNP transistor Q1 and a PNP transistor Q2. The bases and collectors of the PNP transistor Q1 and the PNP transistor Q2 are connected to a power supply potential (e.g., VSS or ground). For a given current magnitude, the sizes of transistor Q1 and transistor Q2 are different (for transistor Q2, M = n, for transistor Q1, M = 1) such that the current density varies in proportion to their sizes. A resistor R3 is connected between the emitter of transistor Q2 and the node N of the "negative" input of the operational amplifier OP1. A resistor R2 is connected between node N and an intermediate node A. A resistor R0 is connected between the intermediate node A and the reference voltage output node 35 that generates the reference voltage VREF'. A resistor R1 is connected between the emitter of transistor Q1 and the intermediate node A. Additionally, the emitter of transistor Q1 is connected to node P at the "positive" input of the operational amplifier OP1, such that the base-emitter voltage of transistor Q1 is applied at node P. A P-channel MOS transistor P0 is connected between the reference voltage output node 35 and a power supply potential (e.g., VDD or other power supply potential). The operational amplifier OP1 (which has PTAT characteristics) outputs a control voltage GP that is connected in a feedback manner to the gate of the P-channel MOS transistor P0, such that a base-emitter voltage difference between transistor Q1 and transistor Q2 is generated across resistor R3.

[0075] To extend the operating temperature range, a correction current Icor is applied from a current source 30 at the intermediate node A. The correction current Icor can increase the current passing through both ends of resistor R0 to extend the operating temperature range at both ends of the temperature threshold, such as below 0°C and above 70°C. Embodiments can be applied to extend the operating range to below 0°C. Embodiments can be applied to extend the operating range to above 70°C either alone or in combination with a correction for extending the operating range to below 0°C. Embodiments can also be applied either alone or in combination with other corrections for extending the temperature range to correct for Figures 2A to 2C the change in the ratio of the saturation current as described in the reference.

[0076] In Figure 3 the circuit, the current I in transistor Q2 Q2 depends only on the negative feedback circuit and does not depend on the current I passing through resistor R0 R0 .

[0077] Deriving the reference voltage VREF from the equations of the currents in the circuit is outlined in the following equations (1) to (3):

[0078] Through negative feedback, V N = V P or I Q2 ×R3 + VEB2 = V EB1 …(1)

[0079] Except for ΔV(A, V P ) = ΔV(A, V N ) or V R1 = V R2 otherwise, if R1 = R2, then I R1 = I R2 .

[0080] Since I R2 = I R3 = I Q2 and I R1 = I Q1 , therefore I R1 = I Q1 = I Q2 = I R3 .

[0081] And I R0 = I R1 + I R2 = 2I R1 = 2I Q2 …(2)

[0082] VREF = V EB1 + V R1 + V R0 = V EB1 + I R1 × R1 + I R0 × R0 = V EB1 + I R1 × R1 + 2I R1 × R0 = V EB1 + I R1 × (R1 + 2 × R0) = V EB1 + I Q2 × (R1 + 2 × R0)…(3)

[0083] By the superposition principle, I R0 ' = I R0 + Icor and V R0 ' = I R0 ' × R0 = V R0 + Icor × R0

[0084] Since V EB1 , V R1 is independent of Icor

[0085] VREF' = V EB1 + V R1 + V R0 ' = V EB1B1 + V R1 + VR0 +Icor×R0 = VREF + Icor×R0…(4)

[0086] The only voltage change resulting from adding the correction current Icor at the intermediate node A appears in the voltage V across the resistor R0 R0 and in the reference voltage VREF′ at the output node 35, as derived in the above equation (4). The addition of the resistor R0 and the current source 30 can be used to reduce Figure 2A the variation of the reference voltage VREF shown in. For example, the operating temperature range can be extended to -40°C in some cases, to +125°C in some cases, and to the entire range from -40°C to +125°C.

[0087] Figures 4 to 6 is a plot of current or voltage versus temperature, showing the addition of the correction current Icor in the plot of Figure 2A to compensate for the effect of the reference voltage VREF dropping below 0°C. As shown in Figure 4 , the correction current Icor is applied to boost the current in the resistor R0 at operating temperatures on the first side of the threshold (i.e., below 0°C) and turn off at operating temperatures on the opposite second side of the threshold (i.e., above 0°C). In this example, the correction current Icor has a CTAT characteristic, and as the temperature increases in the range from approximately -40°C to approximately 0°C, the correction current Icor drops from approximately 16 nA to zero. At the threshold of 0°C, the correction current Icor turns off, at least to the extent that it has no significant effect on the output voltage VREF above 0°C.

[0088] Figure 5 shows the effect of the correction current Icor on the resistor R0 circuit through Figure 3 . Figure 5 The lower curve in shows the current I through the resistor R0 without adding the correction current Icor R0 . The current I R0 has a PTAT characteristic, and as the temperature drops from approximately 10°C to approximately -40°C, the current I R0 drops from approximately 825 nA to approximately 730 nA. Figure 5 The upper curve in shows the current I Figure 4 with the correction current shown in added R0 ′. As can be seen, when the temperature drops below the threshold of approximately 0°C, the correction current makes I R0 ′ slightly greater than the correction current I R0 , and the margin increases as the temperature decreases relative to I R0 .

[0089] Figure 6 shows the addition ofFigure 4 The result of the output reference voltage VREF′ of the calibration current Icor. Figure 6 The lower curve in shows the simulated reference voltage VREF without adding the calibration current Icor. As can be seen, as the temperature drops from about 0 °C to about -40 °C, it drops from a level higher than 1.24 V to a level of about 1.2374 V. With the calibration current Icor added, the reference voltage VREF′ in the upper curve Figure 6 remains within a narrow range, thus extending the effective operating temperature range of the reference voltage circuit to -40 °C or even more negative temperatures.

[0090] For example, referring to Figures 4 to 6 The operating principle described can also be used to increase the operating temperature range to above 70 °C. A calibration current Icor can be applied to increase the current in the resistor R0 at operating temperatures on the first side of the threshold (i.e., above 70 °C), and turn off at operating temperatures on the opposite second side of the threshold (i.e., below 0 °C). For example, a calibration current Icor with a PTAT characteristic having a threshold above 70 °C can be applied to compensate for the tendency of the reference voltage VREF to drop rapidly above 70 °C. In addition, as described in the present invention, the calibration current can be a combination of currents designed to compensate for the temperature variation of the reference voltage in the higher and lower extensions of the operating temperature range.

[0091] It is also desirable to compensate for S1 the ratio of the saturation current I S2 is not equal to one, the shift of the reference voltage VREF shown in Figure 2B and Figure 2C relative to temperature. Under the conditions of Figure 2C , the saturation current I Sl the ratio of the saturation current I S2 is less than 1. As seen in Figure 2C , the peak of the reference voltage shifts to a higher operating temperature, resulting in asymmetry in the figure, such that the reference voltage VREF drops within the range of 0 °C to 70 °C. Compensation for this condition requires adding a CTAT calibration current within the operating range, which can raise the reference voltage VREF in the lower part of the temperature range. This can be achieved by using a current source 30 to add a CTAT calibration current across the resistor R0 to the intermediate node A, as discussed in more detail below.

[0092] Figure 7 is a schematic diagram of a reference voltage circuit with a current source 50 added, and the current source 50 generates a calibration current I1 to compensate for Figure 2B the conditions where S1 the ratio of the saturation current I S2 is greater than 1. As seen in Figure 2BAs can be seen, the peak of the reference voltage shifts to a lower operating temperature, resulting in asymmetry in the figure, such that the reference voltage VREF increases in the range of 0°C to 70°C. Compensation for this condition requires drawing a CTAT correction current, which reduces the current I in transistor Q1 Q1 . Figure 7 The circuit for implementing this compensation is shown in

[0093] Figure 7 . The circuit in includes a first circuit and a second circuit that respectively include a PNP transistor Q1 and a PNP transistor Q2. The bases and collectors of the PNP transistor Q1 and the PNP transistor Q2 are connected to a power supply potential (e.g., VSS or ground). For a given current magnitude, the sizes of transistor Q1 and transistor Q2 are different (M = n for transistor Q2, M = 1 for transistor Q1) such that the current density varies in proportion to their sizes. A resistor R3 is connected between the emitter of transistor Q2 and the node N at the "negative" input of operational amplifier OP1. A resistor R2 is connected between node N and an intermediate node A. A resistor R0 is connected between the intermediate node A and the reference voltage output node 35 that generates the reference voltage VREF'. A resistor R1 is connected between the emitter of transistor Q1 and the intermediate node A. In addition, the emitter of transistor Q1 is connected to node P at the "positive" input of operational amplifier OP1, such that the base-emitter voltage of transistor Q1 is applied at node P. A P-channel MOS transistor P0 is connected between the reference voltage output node 35 and the power supply potential (e.g., VDD). The output of operational amplifier OP1 is connected in a feedback manner to the gate of P-channel MOS transistor P0, such that a base-emitter voltage difference between transistor Q1 and transistor Q2 is generated across resistor R3

[0094] In this embodiment, a current source 50 is added to draw a correction current I1 from node P, which reduces the current in transistor Q1. This reduced current lowers the resulting reference voltage VREF. As shown by the following equation, the current source 50 that draws the correction current I1 from node P does not affect the feedback operation of operational amplifier OP1. As can be seen in equation (5), the current I Q2 depends on the ratio I Q1 / I Q2 . Therefore, when the correction current I1 is non-zero, the current I Q1 becomes smaller than the current I Q2 , and the second term in equation (5) becomes a negative constant. Therefore, drawing the correction current I1 from node P makes the current I Q2 smaller relative to the case where I1 = 0

[0095] Given V EB1 +V T ln(I Q1 / Is1 )V EB2 =V T ln(I Q2 / nI S2 )

[0096] The foregoing equation (1) can be rewritten as:

[0097] I Q2 ×R3 + V T ln(I Q2 / nI S2 ) = V T ln(I Q1 / I s1 )

[0098] I Q2 ×R3 = V T [ln(I Q1 / I s1 ) - ln(I Q2 / nI s2 )] = V T {ln[(nI s2 / I s1 )×(I Q1 / I Q2 )]} = V T [ln(nI s2 / I s1 ) + ln(I Q1 / I Q2 )]

[0099] I Q2 =(V T / R3)×[ln(nI S2 / I s1 ) + ln(I Q1 / I Q2 )]--(5)

[0100] Since V R1 =V R2 and R1 = R2, then I R1 =I R2 or I1 + I o1 =I Q2

[0101] If I1 = 0: I Q1 =I Q2 or ln(I Q1 / I Q2 ) = 0

[0102] If I1 > 0: I Q1 <I Q2 or ln(I Q1 / IQ2 ) < 0

[0103] Therefore,

[0104] If I1 = 0: I Q2 = (V T / R3) × [ln(nI S2 / I S1 )]

[0105] If I1 > 0: I Q2 = (V T / R3) × [ln(nI s2 / I S1 ) - constant]

[0106] Figure 8 is a graph of the current of the example correction current I1 with respect to temperature. In this example, the correction current I1 has CTAT characteristics in region 800 below a threshold of about 70 °C, the region 800 having a temperature range from about -40 °C to +70 °C, and turns off on the other side of the threshold in region 801 above 70 °C.

[0107] Figure 9 is a schematic diagram of a current source that can be used to provide a correction current Icor having the characteristics described above. In this embodiment, the current source includes a current synthesizer that includes a current subtractor 90 followed by a current attenuator 91. The current subtractor 90 includes NMOS transistors N0 to N3. Transistors N0 and N2 are connected in series between ground and a first current source 94 that applies a current IP. The gate of transistor N2 is connected to the drain of transistor N0. Transistors N1 and N3 are connected in series between ground and a second current source 95 that applies a current IC. The gate of transistor N1 is connected to its drain. Due to the current mirror effect of transistors N2 and N3, the difference between the current IP and the current IC is applied to the drain of NMOS transistor N4 of the current attenuator 91. The current attenuator 91 includes a second NMOS transistor N5, and transistor N5 and transistor N4 are configured in a current mirror relationship. The correction current Icor is generated at the drain 98 of transistor N5. By setting the ratio of the size of transistor N5 to that of transistor N4 to an expected value less than 1, the magnitude of the correction current Icor can be determined as needed. In addition, in this circuit, when the current through transistor N3 (IC in this example) drops below the current in transistor N2 (IP in this example) in magnitude, transistor N4 turns off, and thus the correction current Icor also turns off, or substantially so.

[0108] The correction current Icor or the correction current I1 as described above can be implemented such that it has CTAT characteristics or PTAT characteristics within the relevant operating range. For use inFigure 9 The technique for generating the CTAT characteristic current in the circuit in [reference] is to apply a current IC with CTAT characteristics and a current IP with PTAT characteristics, where the current IC has a larger magnitude across the relevant operating range, and the magnitude crosses the temperature threshold. Similarly, for generating the PTAT characteristic current in the Figure 9 circuit in [reference] is to apply a current IC with CTAT characteristics and a current IP with PTAT characteristics, where the current IP has a larger magnitude across the relevant operating range, and the magnitude crosses the temperature threshold.

[0109] Figure 10 An embodiment of a reference voltage generator that uses a current synthesizer 110 as a current source to generate a correction current Icor is shown. The current synthesizer 110 has a configuration similar to Figure 9 [reference]. The current subtractor includes NMOS transistors N0 to N3 and a resistor RN2. The transistors N0 and N2 and the resistor RN2 are connected in series between ground and a first PMOS transistor P1, and the gate of the first PMOS transistor P1 is connected to a control voltage GP. The gate of the transistor N2 is connected to the drain of the transistor N0. The control voltage GP in this example is generated at the output of an operational amplifier OP1 in a bandgap reference voltage generator, and thus a current is generated in the transistor P1 with PTAT characteristics. The transistors N1 and N3 are connected in series between ground and the PMOS transistor P1, and the gate of the PMOS transistor P2 is connected to a control voltage GC. The gate of the transistor N1 is connected to the gate of the transistor N0. In addition, the gate of the transistor N1 is connected to its drain. The control voltage GC in this example is generated by a CTAT reference circuit 101, which is used to generate a control voltage GC with CTAT characteristics. Therefore, the current in the transistor P2 has CTAT characteristics.

[0110] Due to the current mirror effect of the transistors N2 and N3, the difference between the current IN1 and the current IN2 is applied to the drain of the NMOS transistor N4 of the current attenuator. A second NMOS transistor N5 is configured in a current mirror relationship with the transistor N4. The correction current Icor is generated at the drain of the transistor N5 and applied to an intermediate node A of the reference voltage generator. By setting the ratio of the sizes of the transistor N5 and the transistor N4 to an expected value less than 1, the magnitude of the correction current Icor can be determined as needed.

[0111] The CTAT reference circuit 101 in this example includes a resistor R5 and a PMOS transistor C0 connected in series between ground and VDD (or other power supply potential). In addition, the second operational amplifier OP2 in the circuit 101 has a "positive" input connected to the emitter of the transistor Q2 and a "negative" input connected to the resistor R5. The operational amplifier OP generates an output voltage GC, and the output voltage GC maintains the current in the PMOS transistor C0 at a value that establishes a voltage across the resistor R5 that matches the base-emitter voltage VBE of the transistor Q2. The circuit 101 uses the first operational amplifier OP1 to operate without affecting the operation of the bandgap reference circuit feedback. Therefore, the transistor P2 in the current synthesizer 110 generates a current with CTAT characteristics.

[0112] In operation, Figure 10 the circuit in generates a CTAT current in the transistor N1 and PTAT currents in the transistors N0 and N2. The PTAT currents in the transistors N0 and N2 are achieved by the current mirror effect in the transistor P1 from the transistor P0, fed through the transistors N0 and N2 and mapped in the transistor N3, and the magnitude of the PTAT current carried is equal to one-third of the magnitude of the current across the resistor R0 (I R0 / 3). The resistor RN2 is tunable or set to modify the ratio of the currents IN3 / IN2 in the transistors N3 and N2.

[0113] Figure 11 and Figure 12 show the simulated current IN1 and the simulated current IN3 in the case where the resistor RN2 is 0Ω. As shown, the simulated current IN1 has a negative temperature coefficient (CTAT characteristic) that decreases from about 350 nA to about 265 nA in the range of about -40°C to about +10°C. On the other hand, the simulated current IN3 has a positive temperature coefficient (PTAT characteristic) that increases from about 240 nA to about 275 nA in the range of about -40°C to about +10°C.

[0114] In this simulation, the simulated current IN1 is approximately equal to the simulated current IN3 at 5°C, which is a temperature higher than the desired 0°C crossover point at which the correction current Icor needs to be turned off. However, increasing the size of the resistor RN2 increases the ratio of IN3 / IN2, thereby establishing a larger PTAT minuend in the current subtraction circuit. For example, in the circuit, increasing the resistor RN2 from about 0Ω to about 10 KΩ moves the zero crossover point to a lower temperature, as shown in Figure 13 . In this simulation, a resistor RN2 of 7.5 KΩ results in a zero crossover point at about 0°C. Using a resistor RN2 of 7.5 KΩ, the resulting subtracted current is attenuated by the ratio of the sizes of the transistors N5 and N4.

[0115] In Figure 14 it, the simulation results of the size ratio N5 / N4 of the plotted transistor N5 to the transistor N4 being 3 / 13, 3 / 15, 3 / 17, and 3 / 19 are shown. According to this simulation, for the resistor RN2 equal to 7.5 KΩ and the ratio N5 / N4 being 3 / 15, the variation of the output reference voltage VREF′ is less than 0.1 mV in the temperature range from -40°C to 0°C (varying between approximately 1.24014 V and approximately 1.2404 V).

[0116] In a given embodiment using the techniques described in the present invention, these current synthesis techniques can be used to tune the slope and crossover point of the correction current Icor. Other embodiments may employ other types of current synthesis circuits to generate the desired correction current Icor and the characteristics of the correction current I1.

[0117] Reference Figure 10 The described embodiments provide a correction current Icor that extends the operating temperature range downward towards -40°C or beyond -40°C. In Figure 15 it, examples of extending the operating range downward towards -40°C and beyond -40°C, and upward towards 125°C and beyond 125°C are described. In Figure 15 the example, the correction current Icor is the sum of the current IcA and the current IcB generated by the current synthesizer 151 and the current synthesizer 152, respectively. Figure 15 The current synthesizer 152 of Figure 10 is implemented as described above with reference to

[0118] Figure 15The current synthesizer 152 generates a CTAT correction current IcB having a selected cut-off temperature and includes a current subtractor and a current attenuator of the type used in the synthesizer 151. The current subtractor includes NMOS transistors N0 to N3 and a resistor RN2. The transistors N0 and N2 and the resistor RN2 are connected in series between ground and a first PMOS transistor P1, and the gate of the first PMOS transistor P1 is connected to a control voltage GP. The gate of the transistor N2 is connected to the drain of the transistor N0. The control voltage GP in this example is generated at the output of the operational amplifier OP1 in the bandgap reference voltage generator and thus generates a current in the transistor P1 having PTAT characteristics. The transistors N1 and N3 are connected in series between ground and a PMOS transistor P2, and the gate of the PMOS transistor P2 is connected to a control voltage GC. The gate of the transistor N1 is connected to the gate of the transistor N0. In addition, the gate of the transistor N1 is connected to its drain. The control voltage GC in this example is generated by the CTAT reference circuit 101, and the CTAT reference circuit 101 has a voltage GC with CTAT characteristics. Therefore, the current in the transistor P2 has CTAT characteristics.

[0119] Due to the current mirror effect of the transistors N2 and N3, the difference between the current IN1 and the current IN2 is applied to the drain of the NMOS transistor N4 of the current attenuator. A second NMOS transistor N5 is configured in a current mirror relationship with the transistor N4. A correction current Icor is generated at the drain of the transistor N5 and is applied to an intermediate node A of the reference voltage generator. By setting the ratio of the sizes of the transistors N5 and N4 to a desired value less than 1 and by selecting the resistance of the resistor RN2, the magnitude and cut-off threshold of the CTAT correction current IcB can be determined as needed.

[0120] Figure 15The current synthesizer 151 generates a PTAT correction current IcA having a selected cutoff temperature, and includes a current subtractor and a current attenuator. The current subtractor includes NMOS transistors N6 to N9 and a resistor RN9. The transistors N6 and N8 are connected in series between ground and a third PMOS transistor P3, and the gate of the third PMOS transistor P3 is connected to a control voltage GC. The gate of the transistor N8 is connected to the drain of the transistor N6. The control voltage GC in this example is generated by the CTAT reference circuit 101, and thus a current is generated in the transistor P3 having CTAT characteristics. The transistors N7 and N9 and the resistor RN9 are connected in series between ground and a fourth PMOS transistor P4, and the gate of the fourth PMOS transistor P4 is connected to a control voltage GP, which is generated at the output of an operational amplifier OP1 in a bandgap reference voltage generator. The gate of the transistor N7 is connected to the gate of the transistor N6. Further, the gate of the transistor N7 is connected to its drain. The current in the transistor P4 has PTAT characteristics in response to the control voltage GP.

[0121] Due to the current mirror effect of the transistors N9 and N8, the difference between the current IN7 and the current IN8 is applied to the drain of the NMOS transistor N10 of the current attenuator. A second NMOS transistor N11 is configured in a current mirror relationship with the transistor N10. A correction current Icor is generated at the drain of the transistor N11 and applied to an intermediate node A of the reference voltage generator. By setting the ratio of the sizes of the transistors N10 and N11 to an expected value less than 1, and by selecting the resistance of the resistor RN9, the magnitude and cutoff threshold of the PTAT correction current IcA can be determined as needed.

[0122] Figure 16 and Figure 17 show the simulated current IN7 and the simulated current IN9 in the case where the resistor RN9 is 0 Ω. As shown, the simulated current IN7 has a positive temperature coefficient (PTAT characteristic) that increases from about 301 nA to about 330 nA in the range of about +60 °C to about +125 °C. On the other hand, the simulated current IN9 has a negative temperature coefficient (CTAT characteristic) that decreases from about 341 nA to about 195 nA in the range of about +60 °C to about +125 °C.

[0123] In this simulation, the simulated current IN7 is approximately equal to the simulated current IN9 (308 nA) at 74°C, which is a temperature higher than the desired 70°C crossover point below which the correction current IcA needs to be turned off. However, increasing the size of resistor RN9 reduces the ratio of IN9 / IN8, thereby establishing a smaller CTAT minuend in the current subtraction circuit. For example, in the circuit, increasing resistor RN9 causes the crossover point with zero to shift to a lower temperature, as shown in Figure 18 . In this simulation, a resistor RN9 of 7.5 kΩ results in a zero crossover point at approximately 70°C. Using a resistor RN9 of 7.5 kΩ, the resulting subtracted current is attenuated by the ratio N5 / N4 of the sizes of transistor N5 and transistor N4.

[0124] In Figure 19 , the simulation results of the ratios N11 / N10 of the sizes of transistor N11 and transistor N10 being 4 / 25, 4 / 27, and 4 / 29 are plotted. According to this simulation, for a resistor RN9 equal to 7.5 kΩ and a ratio N11 / N10 of 4 / 27, the variation of the output reference voltage VREF′ is less than 0.2 mV (varying between approximately 1.24015 V and approximately 1.24035 V) in the temperature range from +70°C to approximately +125°C.

[0125] Figure 20 Shows the results of simulating a circuit similar to Figure 15 in the extended operating temperature range from -40°C to +125°C. In this range, the reference voltage VREF varies from a minimum value of approximately 1.24016 V at approximately 0°C to a maximum value of approximately 1.24098 at approximately 35°C. As a result of the techniques described in the present invention, the bandgap reference voltage has an extended operating temperature range within which the variation of the reference voltage VREF is approximately 1 mV or less.

[0126] As mentioned above with reference to Figure 7 and Figure 8 , for example due to manufacturing variations, the saturation current Is1 of transistor Q1 and the reference voltage generator may be mismatched with the saturation current I of transistor Q2. In such cases, the resulting reference voltage VREF may be skewed or shifted around the normal operating temperature, as shown in S2 . A technique for eliminating this skew or shift is described to improve the ability to extend the operating temperature range as discussed above using the correction current. For example, as in Figure 2B and Figure 2C shown. A technique for eliminating this skew or shift is described to improve the ability to extend the operating temperature range as discussed above using the correction current. For example, as in Figure 2BAs shown, the reference voltage at 70°C is approximately 1.216V, while the reference voltage at 0°C is approximately 1.221V. The reference voltage at 0°C should be reduced by approximately 5mV to compensate for the shift. As mentioned above, different from boosting the current through resistor R0 to boost the reference voltage VREF, reducing the reference voltage VREF requires reducing the PTAT currents I Q1 and PTAT current I Q2 . This can be achieved by drawing a correction current I1 at the emitter of transistor Q1, as Figure 7 and Figure 8 shown.

[0127] Figure 21 shows a reference voltage generator including a current synthesizer 211 for generating a correction current I1 similar to that Figure 8 shown in. Figure 21 The current synthesizer 211 generates a CTAT correction current I1 with a selected cut-off temperature of approximately 70°C and includes a current subtractor and a current attenuator. The current subtractor includes NMOS transistors N12 to N15 and resistor RN14. Transistors N12 and N14 and resistor RN14 are connected in series between ground and PMOS transistor P5, and the gate of PMOS transistor P5 is connected to the control voltage GP. The gate of transistor N14 is connected to the drain of transistor N12. The control voltage GP in this example is generated at the output of operational amplifier OP1 in the bandgap reference voltage generator, and thus a current is generated in PMOS transistor P5 with PTAT characteristics. Transistors N13 and N15 are connected in series between ground and PMOS transistor P6, and the gate of PMOS transistor P6 is connected to the control voltage GC, which in this example is generated by the CTAT reference circuit 101, and thus a current is generated in PMOS transistor P6 with CTAT characteristics. The gate of transistor N15 is connected to the gate of transistor N14. In addition, the gate of transistor N13 is connected to its drain.

[0128] Due to the current mirror effect of transistors N14 and N15, the difference between current IN13 and current IN14 is applied to the drain of NMOS transistor N16 of the current attenuator. The second NMOS transistor N17 is configured in a current mirror relationship with transistor N16. The correction current I1 is generated at the drain of transistor N17 and applied to node P of the reference voltage generator. By setting the ratio of the sizes of transistors N17 and N16 to an expected value less than 1 and by selecting the resistance of resistor RN14, the magnitude and cut-off threshold of the CTAT correction current I1 can be determined as needed, such as Figure 8 shown in.

[0129] Figure 22 is the current I in transistor Q2 without the correction current I1 Q2 and the current I in transistor Q2 with the sink correction current I1 Q2 ′, where the absorption correction current I1 is generated by synthesizing a current as shown in Figure 21 by simulating a circuit similar to the reference Figure 8 described.

[0130] Figure 23 is a curve of the reference voltage VREF without the sink correction current I1 and the reference voltage VREF′ with the sink correction current I1 having Figure 8 the characteristics.

[0131] As Figure 8 shown, the sink correction current I1 has a maximum value of about 18 nA at -40 °C and drops to about 0 nA at 70 °C, where it is turned off. According to the simulation, as Figure 22 seen, a sink correction current of about 11.3 nA at 0 °C can reduce I Q2 by about 3 nA. As the absorption current I1 increases towards the value at -40 °C, the reference voltage VREF′ continues to slightly decrease within the range, and improves the balance of the reference voltage VREF′ between 0 °C and 70 °C. This can result in Figure 23 the reference voltage VREF′ curve in Figure 2A being similar to the reference voltage VREF′ curve in Figure 2A , where the reference voltage VREF′ curve in

[0132] Figure 24 is a diagram of a reference voltage generator combining the techniques described in Figure 15 and Figure 21 . The circuit includes: a sink correction current synthesizer 243 similar to Figure 21 for generating the sink correction current I1 applied to node P; a boosting correction current synthesizer 242 similar to Figure 15 the synthesizer 151 for generating the boosting correction current IcA; and a boosting current synthesizer 241 similar to Figure 15 the synthesizer 152 for generating the boosting correction current IcB.

[0133] Figure 25 is a curve of the reference voltage VREF generated using a circuit similar to Figure 24 in the range of about -40 °C to about 125 °C, which varies by less than 1 mV from a peak of about 1.21671 at about 35 °C to a minimum of about 1.21604 at about 70 °C in the extended operating temperature range.

[0134] As shown Figure 2C in, when the saturation current ratio I S1 / I S2 is less than 1, the reference voltage VREF shifts or skews such that the voltage at 0 °C is approximately 4 mV lower than the voltage at approximately 70 °C. To eliminate this difference, a boosting correction current as shown Figure 26 in can be applied to the intermediate node A to raise the reference voltage generated at the lower temperature. Figure 26 The boosting correction current Icor of has a negative temperature coefficient (CTAT characteristic), where a maximum value of approximately 36 nA at -40 °C drops to approximately 0 nA at 70 °C and is turned off at the 70 °C.

[0135] Figure 27 shows a reference voltage generator including a correction current synthesizer for generating a boosting correction current as shown Figure 26 in. Figure 27 The current synthesizer 271 of generates a CTAT boosting correction current Icor having a selected cut-off temperature of approximately 70 °C and includes a current subtractor and a current attenuator. The current subtractor includes NMOS transistors N18 to NMOS transistor N21 and resistor RN20. Transistors N18 and transistor N20 and resistor RN20 are connected in series between ground and PMOS transistor P7, and the gate of the PMOS transistor P7 is connected to the control voltage GP. The gate of transistor N20 is connected to the drain of transistor N18. The control voltage GP in this example is generated at the output of the operational amplifier OP1 in the bandgap reference voltage generator and thus generates a current in the transistor P7 having a PTAT characteristic. Transistors N19 and transistor N21 are connected in series between ground and PMOS transistor P8, and the gate of the PMOS transistor P8 is connected to the control voltage GC, which in this example is generated by the CTAT reference circuit 101 and thus generates a current in the transistor P8 having a CTAT characteristic. The gate of transistor N21 is connected to the gate of transistor N20. The gate of transistor N19 is connected to the gate of transistor N18. In addition, the gate of transistor N19 is connected to its drain.

[0136] Due to the current mirror effect of transistors N21 and N20, the difference between current IN19 and current IN20 is applied to the drain of NMOS transistor N22 of the current attenuator. The second NMOS transistor N23 is configured in a current mirror relationship with transistor N22. A correction current Icor is generated at the drain of transistor N23 and applied to the intermediate node A of the reference voltage generator. By setting the ratio of the sizes of transistor N23 and transistor N22 to an expected value less than 1, and by selecting the resistance of resistor RN20, the magnitude and cut-off threshold of the CTAT correction current Icor can be determined as needed.

[0137] Figure 28 is a graph of the reference voltage VREF′ simulated using the boosted correction current from Figure 27 synthesizer 271 and the reference voltage VREF simulated without the boosted correction current. Thus, as a result of the correction current, the change in the reference voltage VREF′ is approximately -3 mV in the operating range of -40°C to +70°C, and approximately -1 mV in the range of approximately 125°C to 70°C. As a result of this correction for the shift caused by the imbalance of the saturation currents in transistors Q1 and Q2, the reference voltage generator can be more easily corrected using the techniques described above to extend the operating temperature range.

[0138] Figure 29 is a diagram of a reference voltage generator that combines the Figure 15 and Figure 27 described techniques. The circuit includes: a boosted correction current synthesizer 293 similar to synthesizer 271 of Figure 27 to generate a boosted correction current IcC applied to node A; a boosted correction current synthesizer 292 similar to synthesizer 151 of Figure 15 to generate a boosted correction current IcA; and a boosted current synthesizer 291 similar to synthesizer 152 of Figure 15 to generate a boosted correction current IcB.

[0139] Figure 30 is a graph of the reference voltage VREF generated using a circuit similar to Figure 29 synthesized in the range of approximately -40°C to approximately 125°C, which varies by less than 1 mV from a peak of approximately 1.21688 V at approximately 35°C to a minimum of approximately 1.21610 V at approximately 125°C in the extended operating temperature range.

[0140] Table 2 summarizes Figure 20 、 Figure 25 and Figure 30 VREF′ results.

[0141] Table 2

[0142] VREF′ (V) Figure 20 Figure 25 Figure 30 125℃ 1.24016 1.21601 1.26099 70℃ 1.24018 1.21604 1.26103 0℃ 1.24018 1.21604 1.26103 -40℃ 1.24016 1.21601 1.26099 Δ 8.1E-04 7.0E-04 9.0E-04

[0143] Thus, the techniques described in the present invention can be deployed in a variety of configurations to achieve an extended operating temperature range for a reference voltage generator.

[0144] A reference voltage generator using the examples described above can be implemented using other bandgap reference circuits. For example, Figure 31 and Figure 32 the circuits shown in illustrate alternative reference voltage generator circuits. Figure 31 and Figure 32 The reference voltage generator circuits of and include a first circuit and a second circuit that include a PNP transistor Q1 and a PNP transistor Q2, respectively, with the gates of the PNP transistor Q1 and the PNP transistor Q2 connected together. The emitter of transistor Q1 is connected to ground, and the emitter of transistor Q2 is connected to ground via a resistor R1. The base of transistor Q1 is connected to its drain, which conducts a current Ic1. In addition, the collector of transistor Q1 is connected to an intermediate node A via a resistor R2, at which a reference voltage VREF is generated. The collector of transistor Q2 is connected to intermediate node A via a resistor R3. Transistor Q4 is connected from node A to the power supply potential VDD and conducts a current Ic4. The base of transistor Q3 is connected to the collector of transistor Q2. Resistor R0 is connected from node A to the emitter of transistor Q4. The drain of transistor Q4 is connected to the power supply potential VDD and conducts a current Ic4. The base of transistor Q3 is connected to the collector of transistor Q2. The emitter of transistor Q3 is connected to ground. The collector of transistor Q3 is connected to ground across a capacitor Cc. In addition, the collector of transistor Q3 receives a reference current from a current source IB. The base of transistor Q4 is connected to the drain of transistor Q3.

[0145] Figure 31 and Figure 32 The circuits of and generate the reference voltage VREF by maintaining the following condition: the voltage difference ΔVBE generated by the current Ic2 in transistor Q2 multiplied by the resistance of R1, plus the base-emitter voltage VBE of transistor Q2, is equal to the base-emitter voltage of transistor Q1. Feedback is provided by a circuit including transistor Q3, which controls the charge on capacitor Cc to maintain the current Ic4 through transistor Q4 and resistor R1 at the level required to satisfy this condition. A boosting correction current Icor can be added at node A using the techniques described above. In addition, as shown in Figure 32 , the circuit of can be modified by adding a sinking correction current at the base of transistor Q1 using the techniques described above. In addition, a combination of the boosting correction current and the sinking correction current can be used for Figure 31 and Figure 31 and Figure 32in the reference generator.

[0146] In addition, for some embodiments of the technology, PN junction devices other than bipolar transistors (such as diodes or MOS transistors) can be used to implement the reference voltage generator.

[0147] In a given implementation using the technology described in the present invention, these current synthesis techniques can be used to tune the slope and crossover point of the boost correction current Icor and the draw correction current I1. Other embodiments may employ other types of current synthesis circuits to generate the desired correction current Icor and correction current I1 characteristics.

[0148] Embodiments of the technology described in the present invention use current subtraction and current attenuator techniques to implement the current synthesizer. In other embodiments, other types of current synthesizers can be used to generate the boost correction current and the draw correction current.

[0149] Although the present invention is disclosed with reference to the preferred embodiments and examples detailed above, it should be understood that these examples are intended in an illustrative rather than a limiting sense. Modifications and combinations that will readily occur to those skilled in the art are contemplated and will fall within the spirit of the present invention and the scope of the appended claims.

Claims

1. A reference voltage circuit for generating a reference voltage, characterized in that, Comprising: A first circuit including a first PN junction device, a first resistor, a second resistor, and a third resistor, wherein the first PN junction device and the first resistor are connected in series between a power supply node and a first node, the second resistor is connected between the first node and an intermediate node, and the third resistor is connected between the intermediate node and a reference voltage output node; A second circuit including a second PN junction device and a fourth resistor, wherein the second PN junction device is connected between the power supply node and a second node, and the fourth resistor is connected between the second node and the intermediate node; A feedback current source for supplying a feedback current to the reference voltage output node, the feedback current being distributed between the first circuit and the second circuit, and the feedback current having a magnitude controlled by a current control signal; A feedback circuit connected to one or both of the first node and the second node to generate the current control signal such that the voltage across the first resistor cancels out the change in the voltage across the first PN junction device; And A current source for supplying a correction current at the intermediate node to increase the current in the third resistor at an operating temperature on a first side of a threshold and to turn off at an operating temperature on a second side opposite to the threshold.

2. The reference voltage circuit for generating a reference voltage according to claim 1, characterized in that, Including a second current source for drawing a second correction current from the second node, the magnitude of the second correction current increasing with an increase in the operating temperature within a temperature range to cancel out the mismatch in the saturation currents of the first PN junction device and the second PN junction device.

3. The reference voltage circuit for generating a reference voltage according to claim 1, characterized in that, The current source includes a circuit for generating a correction current component, the magnitude of the correction current component decreasing with an increase in the operating temperature within a temperature range to cancel out the mismatch in the saturation currents of the first PN junction device and the second PN junction device.

4. The reference voltage circuit for generating a reference voltage according to claim 1, characterized in that, The correction current decreases as the temperature increases to the threshold and turns off when above the threshold.

5. The reference voltage circuit for generating a reference voltage according to claim 1, wherein The correction current decreases as the temperature decreases to the threshold and turns off when below the threshold.

6. The reference voltage circuit for generating a reference voltage according to claim 1, wherein The current source includes: A first circuit for generating a decreasing boost current component that decreases as the temperature increases to the threshold and turns off when above the threshold; And A second circuit for generating an increasing boost current component that increases as the temperature increases above a second threshold, where the second threshold is higher than the threshold, and the correction current is a combination of the increasing boost current component and the decreasing boost current component.

7. The reference voltage circuit for generating a reference voltage according to claim 1, characterized in that, The current source includes: A first circuit for generating a decreasing boost current component that decreases as the temperature increases to the threshold and turns off when above the threshold; A second circuit for generating an increasing boost current component that increases as the temperature increases above a second threshold, the second threshold being higher than the threshold; And A third circuit for generating a correction current component, the magnitude of the correction current component decreasing with an increase in the operating temperature within a temperature range to cancel the mismatch in the saturation currents of the first PN junction device and the second PN junction device; wherein the correction current is a combination of the increasing boost current component, the decreasing boost current component, and the correction current component.

8. The reference voltage circuit for generating a reference voltage according to claim 7, wherein, A second current source for drawing a second correction current from the second circuit, the magnitude of the second correction current increasing with an increase in the operating temperature within a temperature range to cancel the mismatch in the saturation currents of the first PN junction device and the second PN junction device.

9. The reference voltage circuit for generating a reference voltage according to claim 1, characterized in that, The current source includes a current subtractor circuit for generating the correction current in response to a difference between a PTAT current and a CTAT current.

10. The reference voltage circuit for generating a reference voltage according to claim 1, characterized in that, The current source includes: A circuit for generating a PTAT current in response to the feedback circuit; A circuit for generating a CTAT current in response to one of the first PN junction device and the second PN junction device; A current subtractor for generating a difference current; and A current attenuator for generating the correction current based on the difference current.

11. The reference voltage circuit for generating a reference voltage according to claim 1, wherein The correction current does not change the magnitude of the current in the first PN junction device and the second PN junction device.

12. The reference voltage circuit for generating a reference voltage according to claim 1, wherein, The PN junction device is a transistor.

13. A reference voltage circuit for generating a reference voltage, characterized in that, Comprising: A first circuit including a first transistor, a first resistor, a second resistor, and a third resistor, the first transistor and the first resistor being connected in series between a power supply node and a first node, the second resistor being connected between the first node and an intermediate node, and the third resistor being connected between the intermediate node and a reference voltage output node; A second circuit including a second transistor, a first terminal of the second transistor being connected to a first terminal of the first transistor, the second transistor being connected between the power supply node and a second node and a fourth resistor being connected between the second node and the intermediate node; A third transistor for supplying a feedback current to the reference voltage output node, the feedback current being distributed between the first circuit and the second circuit, the magnitude of the feedback current being controlled by a control signal; An operational amplifier having an input connected to the first node and the second node and an output connected to a control terminal of the third transistor, the operational amplifier for generating the control signal such that the voltage across the first resistor cancels the change in voltage across the PN junction of the first transistor; And A current source for supplying a correction current at the intermediate node to boost the current in the third resistor at operating temperatures on a first side of a threshold and to turn off at operating temperatures on a second, opposite side of the threshold.

14. The reference voltage circuit for generating a reference voltage according to claim 13, characterized in that, Comprising: A fifth resistor connected between a fourth node and a second terminal of the first transistor; A fourth transistor for supplying a current across the fifth resistor; And A second operational amplifier having a first input connected to the fourth node and a second input connected to the third terminal of the first transistor, the output of the second operational amplifier being connected to the control terminal of the fourth transistor, and wherein the current source responds to the output of the second operational amplifier and the output of the operational amplifier.

15. The reference voltage circuit for generating a reference voltage according to claim 14, characterized in that, A second current source for drawing a second correction current from the second node, the second correction current having a magnitude responsive to the output of the second operational amplifier and the output of the operational amplifier.

16. The reference voltage circuit for generating a reference voltage according to claim 14, wherein The current source includes: A circuit for generating a PTAT current responsive to the output of the operational amplifier; A circuit for generating a CTAT current responsive to the second operational amplifier; A current subtractor for generating a differential current between the PTAT current and the CTAT current; and A current attenuator for generating the correction current based on the differential current.

17. The reference voltage circuit for generating a reference voltage according to claim 13, characterized in that, The current source includes a circuit for generating a correction current component, the magnitude of the correction current component decreasing with an increase in the operating temperature within a temperature range to offset a mismatch in the saturation currents of the first transistor and the second transistor.

18. The reference voltage circuit for generating a reference voltage according to claim 13, wherein The current source includes: A circuit for generating a decreasing boost current component that decreases as the temperature increases to the threshold and turns off when above the threshold; and A circuit for generating an increasing boost current component that increases as the temperature increases above a second threshold, the second threshold being higher than the threshold, and the correction current being a combination of the increasing boost current component and the decreasing boost current component.

19. The reference voltage circuit for generating a reference voltage according to claim 13, characterized in that, The current source includes: A circuit for generating a decreasing boost current component that decreases as the temperature increases to the threshold and turns off when above the threshold; A circuit for generating an increasing boost current component that increases as the temperature increases above a second threshold, the second threshold being higher than the threshold; And A circuit for generating a correction current component, the magnitude of the correction current component decreasing with an increase in the operating temperature within a temperature range to offset a mismatch in the saturation currents of the first transistor and the second transistor; wherein the correction current is a combination of the increasing boost current component, the decreasing boost current component, and the correction current component.

20. The reference voltage circuit for generating a reference voltage according to claim 13, characterized in that, The reference voltage at the reference voltage output node varies by less than 1 mV within a temperature range of -40°C to +125°C.

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