A four-quadrant analog multiplier circuit

Abstract

This invention discloses a four-quadrant analog multiplier circuit, comprising: a Gilbert cell circuit, a first active attenuation circuit, and a second active attenuation circuit; the first input terminal of the Gilbert cell circuit is connected to the output terminal of the active attenuation circuit, and the second input terminal of the Gilbert cell circuit is connected to the output terminal of the second active attenuation circuit; a first signal is input to the first active attenuation circuit; a second signal is input to the second active attenuation circuit; the first and second active attenuation circuits attenuate the input signal and then perform level shifting, so that the Gilbert cell circuit operates in the saturation region. By reducing the number of transistors between the positive and negative power supplies, the minimum operating voltage is lowered, thereby reducing power consumption; furthermore, the simultaneous use of active attenuation circuits to process the input signal effectively expands the linear operating region.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit signal processing, and more particularly to a four-quadrant analog multiplier circuit. Background Technology

[0002] Analog multipliers are simple, highly practical unit circuits that occupy an important position in integrated circuits. They can perform not only simple analog signal operations, but also, when combined with operational amplifiers, filters, and other circuits, accomplish various complex signal processing functions. These functions are indispensable in signal processing and transmission systems; therefore, since their inception, analog multipliers have played a crucial role in the nonlinear domain. In recent years, the development of artificial neural networks and large-scale parallel systems has brought new impetus to the development of analog multipliers. Currently, analog multipliers are widely used in aerospace, automation, power industry, instrumentation, and wireless electronics, demonstrating that their applications cover almost every aspect of the electronics industry. Due to the continuous increase in circuit integration density, low-power design of integrated circuits has become a research focus and is gradually developing into an independent and systematic discipline. Analog multipliers were initially designed using bipolar technology. Bipolar analog multipliers have high accuracy and are relatively simple in structure and analysis, but they typically have high power supply voltage and high power consumption. To solve this problem, current technology mainly uses variable transconductance analog multipliers, including Gilbert cells, as the core unit. However, due to the limitations of the threshold voltage and saturation voltage drop of MOSFETs, it is difficult to further reduce the power supply voltage of general Gilbert cells. In addition, current technology uses a coupling method to apply the signal to the gate, thus having a small linear input range. Summary of the Invention

[0003] This invention provides a four-quadrant analog multiplier circuit to solve the technical problems of existing analog multipliers, such as the difficulty in further reducing the power supply voltage and the small linear input range.

[0004] To address the aforementioned technical problems, embodiments of the present invention provide a four-quadrant analog multiplier circuit, comprising: a Gilbert cell circuit, a first active attenuation circuit, and a second active attenuation circuit;

[0005] Wherein, the first input terminal of the Gilbert unit circuit is connected to the output terminal of the active attenuation circuit, and the second input terminal of the Gilbert unit circuit is connected to the output terminal of the second active attenuation circuit; the input terminal of the first active attenuation circuit is connected to a first signal; and the input terminal of the second active attenuation circuit is connected to a second signal.

[0006] The Gilbert unit circuit includes: a first MOSFET, a first differential input stage, a second differential input stage, a first active load, a second active load, a first current mirror, and a second current mirror;

[0007] The power supply is connected to the first active load, the first current mirror, and the second current mirror, respectively.

[0008] The first active load is connected to the first differential input stage, the first current mirror is connected to the first differential input stage and the second differential input stage, and the second current mirror is connected to the first differential input stage and the second differential input stage.

[0009] The first differential input stage is connected to the first input terminal of the Gilbert cell circuit and the drain of the first MOS transistor, and the second differential input stage is connected to the second input terminal of the Gilbert cell circuit and the second active load, respectively.

[0010] The gate of the first MOS transistor is connected to a bias voltage, the source of the first MOS transistor is connected to the circuit ground, and the second active load is connected to the circuit ground; wherein, the first MOS transistor is an NMOS transistor;

[0011] The second active load is used to convert the current difference of the included MOSFETs into an output voltage; wherein the current difference is expressed as a product function of the first signal and the second signal;

[0012] The first active attenuation circuit and the second active attenuation circuit are used to attenuate the input signal and then perform level shifting so that the Gilbert unit circuit operates in the saturation region.

[0013] In the Gilbert cell circuit of the present invention, the first active load, the first current mirror, and the second current mirror are connected to the operating power supply, and then connected to the first differential input stage and the second differential input stage; the second differential input stage and the second differential input stage are then connected to the circuit ground via the first MOSFET and the second active load, thus reducing at least one saturation voltage drop, thereby allowing operation at a lower operating voltage and lower power consumption; in addition, after the active attenuation circuit attenuates the input signal, it uses level shifting to make the Gilbert cell circuit operate in the saturation region, thereby improving the input linear range.

[0014] Furthermore, the first differential input stage includes a second MOSFET and a third MOSFET;

[0015] The second MOS transistor and the third MOS transistor are NMOS transistors with the same width-to-length ratio; the first input terminal includes a first positive input terminal and a first negative input terminal;

[0016] The drain of the second MOSFET is connected to the first active load;

[0017] The gate of the second MOS transistor is connected to the positive terminal of the first input.

[0018] The drain of the second MOS transistor is connected to the drain of the third MOS transistor and the drain of the first MOS transistor;

[0019] The source of the third MOS transistor is connected to the first active load and the first current mirror.

[0020] The gate of the third MOS transistor is connected to the negative input terminal of the first MOS transistor.

[0021] Furthermore, the first active load includes a fourth MOSFET and a fifth MOSFET; the first current mirror includes a fifth MOSFET and a sixth MOSFET; and the second current mirror includes a fourth MOSFET and a seventh MOSFET.

[0022] Among them, the fourth MOS transistor, the fifth MOS transistor, the sixth MOS transistor, and the seventh MOS transistor are PMOS transistors;

[0023] The drain of the fourth MOS transistor is connected to the source of the fifth MOS transistor, the drain of the sixth MOS transistor, the drain of the seventh MOS transistor, and the operating power supply.

[0024] The gate of the fourth MOS transistor is connected to the source of the fourth MOS transistor, the gate of the seventh MOS transistor, and the first differential input stage;

[0025] The gate of the fifth MOS transistor is connected to the drain of the fifth MOS transistor, the gate of the sixth MOS transistor, and the first differential input stage;

[0026] The source of the sixth MOS transistor is connected to the second differential input stage;

[0027] The source of the seventh MOS transistor is connected to the second differential input stage.

[0028] By connecting the first active load, the first current mirror, and the second current mirror, this invention enables this part of the circuit to have only the saturation voltage drop of a single field-effect transistor in the entire Gilbert unit circuit, which helps to further reduce the power supply voltage and thus reduce energy consumption.

[0029] Furthermore, the second differential input stage includes: an eighth MOSFET, a ninth MOSFET, a tenth MOSFET, and an eleventh MOSFET;

[0030] The eighth, ninth, tenth, and eleventh MOS transistors are PMOS transistors and have the same width-to-length ratio; the second input terminal includes a second positive input terminal and a second negative input terminal.

[0031] The drain of the eighth MOS transistor is connected to the source of the ninth MOS transistor and the first current mirror.

[0032] The source of the eighth MOS transistor is connected to the source of the tenth MOS transistor and the second active load.

[0033] The gate of the eighth MOS transistor is connected to the gate of the eleventh MOS transistor and the second positive input terminal;

[0034] The gate of the ninth MOS transistor is connected to the gate of the tenth MOS transistor and the second negative input terminal;

[0035] The drain of the ninth MOS transistor is connected to the drain of the eleventh MOS transistor and the second active load.

[0036] The drain of the tenth MOS transistor is connected to the source of the eleventh MOS transistor and the second current mirror.

[0037] Furthermore, the second active load includes: a twelfth MOSFET and a thirteenth MOSFET;

[0038] Among them, the twelfth MOS transistor and the thirteenth MOS transistor are NMOS transistors;

[0039] The drain of the twelfth MOS transistor is connected to the gate of the twelfth MOS transistor and the second differential input stage;

[0040] The source of the twelfth MOS transistor is connected to the drain of the thirteenth MOS transistor and the circuit ground;

[0041] The drain of the thirteenth MOS transistor is connected to the gate of the thirteenth MOS transistor and the second differential input stage.

[0042] The second active load in this invention is connected to the second differential input stage, which allows the saturation voltage drop and threshold voltage of the twelfth MOSFET to be used in the Gilbert cell circuit, which helps to further reduce the power supply voltage and thus reduce energy consumption.

[0043] Furthermore, the current difference is expressed as a product function of the first signal and the second signal, specifically:

[0044] The current difference between the twelfth and thirteenth MOS transistors is a product function of the first and second signals.

[0045] Furthermore, the first active attenuation circuit and the second active attenuation circuit have the same structure, both including: an attenuation circuit and a level shifting circuit;

[0046] The attenuation circuit is used to attenuate the input signal; the input signal includes either a first signal or a second signal.

[0047] The level shifting circuit is used to perform level conversion on the attenuated input signal so that the Gilbert unit circuit operates in the saturation region.

[0048] Furthermore, the attenuation circuit includes: the fourteenth MOS transistor, the fifteenth MOS transistor, the sixteenth MOS transistor, and the seventeenth MOS transistor; the level shifting circuit includes: the eighteenth MOS transistor, the nineteenth MOS transistor, the twentieth MOS transistor, and the twenty-first MOS transistor;

[0049] Among them, the fourteenth MOS transistor, the fifteenth MOS transistor, the sixteenth MOS transistor, and the seventeenth MOS transistor are PMOS transistors;

[0050] The gate of the fourteenth MOS transistor and the gate of the fifteenth MOS transistor are connected to the positive terminal of the first signal or the positive terminal of the second signal.

[0051] The drain of the fourteenth MOS transistor is connected to the operating power supply;

[0052] The source of the fourteenth MOS transistor is connected to the drain of the fifteenth MOS transistor and the level shifting circuit;

[0053] The source of the fifteenth MOS transistor is connected to the circuit ground;

[0054] The gate of the sixteenth MOS transistor and the gate of the seventeenth MOS transistor are connected to the negative terminal of the first signal or the negative terminal of the second signal.

[0055] The source of the sixteenth MOS transistor is connected to the operating power supply;

[0056] The drain of the sixteenth MOS transistor is connected to the source of the seventeenth MOS transistor and the level shifting circuit;

[0057] The drain of the seventeenth MOS transistor is connected to the circuit ground;

[0058] The eighteenth MOS transistor, the nineteenth MOS transistor, the twentieth MOS transistor, and the twenty-first MOS transistor are NMOS transistors;

[0059] The gate of the eighteenth MOS transistor is connected to the attenuation circuit;

[0060] The drain of the eighteenth MOS transistor is connected to the source of the nineteenth MOS transistor and the operating power supply.

[0061] The source of the eighteenth MOS transistor is connected to the source of the twentieth MOS transistor and the positive output terminal of the active attenuation circuit.

[0062] The gate of the nineteenth MOS transistor is connected to the attenuation circuit;

[0063] The drain of the nineteenth MOS transistor is connected to the drain of the twenty-first MOS transistor and the negative output terminal of the active attenuation circuit.

[0064] The gate of the twentieth MOS transistor is connected to the gate of the twentieth MOS transistor and the gate of the first MOS transistor;

[0065] The drain of the twentieth MOS transistor is connected to the source of the twentieth MOS transistor and the circuit ground.

[0066] The attenuation circuit of this invention preprocesses the input signal, and the level shifting circuit solves the problem of small amplitude of the preprocessed input signal, so that the Gilbert unit circuit works in the saturation region, thereby ensuring a large linear input range while ensuring a low power supply voltage.

[0067] Furthermore, the four-quadrant analog multiplier circuit also includes a bias circuit;

[0068] The bias circuit is connected to the first MOSFET and is used to provide operating current to the first MOSFET.

[0069] The bias circuit of the present invention provides operating current to the first MOSFET, so that the first MOSFET is in normal working state and the stability of circuit operation is guaranteed.

[0070] Furthermore, the bias circuit includes: a twenty-second MOSFET, a twenty-third MOSFET, and a twenty-fourth MOSFET;

[0071] Among them, the twentieth MOS transistor, the twentieth MOS transistor, and the twentieth MOS transistor are NMOS transistors;

[0072] The source of the twelfth MOS transistor is connected to the gate of the twelfth MOS transistor and the operating power supply;

[0073] The drain of the 22nd MOS transistor is connected to the source and gate of the 23rd MOS transistor.

[0074] The drain of the 23rd MOS transistor is connected to the source of the 24th MOS transistor, the gate of the 24th MOS transistor, and the gate of the first MOS transistor;

[0075] The drain of the 24th MOSFET is connected to the circuit ground. Attached Figure Description

[0076] Figure 1 This is a schematic diagram of the connection relationship of an existing Gilbert cell circuit provided by the present invention;

[0077] Figure 2 A schematic diagram of the connection relationship of one embodiment of the four-quadrant analog multiplier circuit provided by the present invention;

[0078] Figure 3 A schematic diagram showing the connection relationship of one embodiment of the Gilbert unit circuit provided by the present invention;

[0079] Figure 4 This is a schematic diagram showing the connection relationship of one embodiment of the active attenuation circuit provided by the present invention. Detailed Implementation

[0080] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0081] Analog multipliers were initially designed using bipolar technology. Bipolar analog multipliers offer high accuracy and are relatively simple in structure and analysis, but they typically require high power supply voltages and consume a lot of power. Analog multipliers designed using CMOS technology, on the other hand, have extremely low leakage current, which is beneficial for low-power design. The main structures of analog multipliers include: logarithmic-antilogarithmic analog multipliers, pulse high / wide pulse multipliers, 1 / 4 square difference multipliers, and variable transconductance multipliers. Among these, variable transconductance multipliers use differential circuits as their basic circuitry. The Gilbert cell is the most typical variable transconductance analog multiplier because it has advantages such as low AC feedthrough, good stability, high accuracy and speed, low cost, and easy integration. Currently, most integrated analog multiplier circuits use variable transconductance analog multipliers as their core unit.

[0082] In current analog multiplier design, Gilbert cell-based analog multipliers remain the mainstream approach. To further improve multiplier performance and reduce power consumption, new technologies are constantly being integrated into analog multiplier design. Particularly in the area of ​​low power consumption, novel design methods such as floating-gate MOS technology and Class AB current mirror technology are emerging in large numbers.

[0083] For example, the floating-gate device in a floating-gate multiplier can perform weighted squaring of multiple inputs, and the threshold voltage can be reduced by adjusting the fixed terminal voltage. Therefore, floating-gate technology is considered the most ideal design scheme for multiplier design. It can significantly reduce the layout area, but because the signal is applied to the gate through coupling, its linear input range is small and its accuracy is relatively low. AB-class current mirror multipliers: AB-class current mirrors are a commonly used current-mode analog multiplier design method. They are highly flexible and can perform multiplication of voltage and current signals separately. However, their linear input range is narrow, making them unsuitable for circuits with high input swing. All the multipliers mentioned above suffer from poor linearity.

[0084] Please refer to Figure 1 This is a schematic diagram of the connection relationship of the existing Gilbert unit circuit provided by the present invention. The circuit uses dual differential transistors as the core unit. Transistor M1 acts as an NMOS transistor, with its gate connected to the bias voltage, generating a tail current. M2 and M3 are NMOS transistors, with their gates connected to the positive and negative terminals of an input signal Vx, respectively. M4 and M7 are NMOS transistors, with their gates connected to the positive terminal of another input signal Vy. M5 and M6 are NMOS transistors, with the gates of two field-effect transistors connected to the negative terminal of Vy. M8 and M9 are PMOS transistors, connected as an active load to convert the output current into an output voltage. In this circuit, the current difference between M8 and M9 can be expressed as:

[0085] ;

[0086] Cox is the gate oxide capacitance per unit area of ​​the MOSFET. V represents the electron carrier mobility of the PMOS transistor, W / L is the width-to-length ratio of the transistor, and V is the voltage. x V y There are two input signals. Because V x V y The values ​​of are not restricted by sign, therefore this circuit can perform four-quadrant operations. The minimum supply voltage required by this circuit can be expressed as:

[0087] ;

[0088] in, This is the gate-source voltage difference of the MOSFET. This is the threshold voltage of the MOSFET. This is the saturation voltage drop of the MOSFET. Under current mature process conditions, the saturation voltage drop is approximately 0.3V, and the threshold voltage is approximately 0.7V. Therefore, the minimum supply voltage for this circuit is approximately 2V.

[0089] Example 1

[0090] Please refer to Figure 2 The diagram shows the connection relationship of an embodiment of the four-quadrant analog multiplier circuit provided by the present invention, which mainly includes: a Gilbert unit circuit, a first active attenuation circuit, and a second active attenuation circuit.

[0091] Wherein, the first input terminal of the Gilbert unit circuit is connected to the output terminal of the active attenuation circuit, and the second input terminal of the Gilbert unit circuit is connected to the output terminal of the second active attenuation circuit; the input terminal of the first active attenuation circuit is connected to a first signal; and the input terminal of the second active attenuation circuit is connected to a second signal.

[0092] The Gilbert cell circuit includes: a first MOSFET M1, a first differential input stage, a second differential input stage, a first active load, a second active load, a first current mirror, and a second current mirror;

[0093] The power supply is connected to the first active load, the first current mirror, and the second current mirror, respectively.

[0094] The first active load is connected to the first differential input stage, the first current mirror is connected to the first differential input stage and the second differential input stage, and the second current mirror is connected to the first differential input stage and the second differential input stage.

[0095] The first differential input stage is connected to the first input terminal of the Gilbert cell circuit and the drain of the first MOS transistor, and the second differential input stage is connected to the second input terminal of the Gilbert cell circuit and the second active load, respectively.

[0096] The gate of the first MOS transistor M1 is connected to a bias voltage, the source of the first MOS transistor M1 is connected to the circuit ground, and the second active load is connected to the circuit ground; wherein, the first MOS transistor M1 is an NMOS transistor;

[0097] The second active load is used to convert the current difference of the included MOSFETs into an output voltage; wherein the current difference is expressed as a product function of the first signal and the second signal;

[0098] The first active attenuation circuit and the second active attenuation circuit are used to attenuate the input signal and then perform level shifting so that the Gilbert unit circuit operates in the saturation region.

[0099] In this embodiment, the Gilbert cell circuit is used for multiplication. The first active load, the first current mirror, and the second current mirror, through connection to the operating power supply and the two differential input stages, can have only one saturation voltage drop; while the two differential input stages have the saturation voltage drop of a field-effect transistor; the second active load occupies one saturation voltage drop and one threshold voltage in the operating voltage, thus the entire circuit... Figure 1 Compared to the Gilbert cell circuit in the original design, structurally reducing the number of transistors between the positive and negative power supplies reduces the required operating voltage by at least one saturation voltage drop, resulting in lower energy consumption.

[0100] In addition, in order to expand the linear input range, an active attenuation circuit is used to attenuate the input signal, and then the attenuated input signal is level-shifted.

[0101] Please refer to Figure 3 This is a schematic diagram of the connection relationship of an embodiment of the Gilbert cell circuit provided by the present invention, wherein the first differential input stage includes: a second MOS transistor M2 and a third MOS transistor M3;

[0102] Wherein, the second MOS transistor M2 and the third MOS transistor M3 are NMOS transistors with the same width-to-length ratio; the first input terminal includes a first positive input terminal and a first negative input terminal;

[0103] The drain of the second MOSFET M2 is connected to the first active load;

[0104] The gate of the second MOS transistor M2 is connected to the positive terminal of the first input.

[0105] The drain of the second MOS transistor M2 is connected to the drain of the third MOS transistor M3 and the drain of the first MOS transistor M1;

[0106] The source of the third MOS transistor M3 is connected to the first active load and the first current mirror.

[0107] The gate of the third MOS transistor M3 is connected to the negative input terminal of the first input.

[0108] In this embodiment, the currents of the second NMOS transistor and the third MOS transistor M3 can be obtained according to the saturation region current formula of the MOS transistor:

[0109] ;

[0110] ;

[0111] ;

[0112] in, and The currents of the second and third NMOS transistors are... This represents the width-to-length ratio of the second and third NMOS transistors. The electron carrier mobility of the NMOS transistor; V TN The voltage threshold of the NMOS transistor;

[0113] Furthermore, the first active load includes: a fourth MOSFET M4 and a fifth MOSFET M5; the first current mirror includes: a fifth MOSFET M5 and a sixth MOSFET M6; the second current mirror includes: a fourth MOSFET M4 and a seventh MOSFET M7;

[0114] Among them, the fourth MOS transistor M4, the fifth MOS transistor M5, the sixth MOS transistor M6, and the seventh MOS transistor M7 are PMOS transistors;

[0115] The drain of the fourth MOS transistor M4 is connected to the source of the fifth MOS transistor M5, the drain of the sixth MOS transistor M6, the drain of the seventh MOS transistor M7, and the operating power supply.

[0116] The gate of the fourth MOS transistor M4 is connected to the source of the fourth MOS transistor M4, the gate of the seventh MOS transistor M7, and the first differential input stage.

[0117] The gate of the fifth MOS transistor M5 is connected to the drain of the fifth MOS transistor M5, the gate of the sixth MOS transistor M6, and the first differential input stage;

[0118] The source of the sixth MOS transistor M6 is connected to the second differential input stage;

[0119] The source of the seventh MOS transistor M7 is connected to the second differential input stage.

[0120] By connecting the first active load, the first current mirror, and the second current mirror, this invention enables this part of the circuit to have only the saturation voltage drop of a single field-effect transistor in the entire Gilbert unit circuit, which helps to further reduce the power supply voltage and thus reduce energy consumption.

[0121] Furthermore, the second differential input stage includes: an eighth MOSFET M8, a ninth MOSFET M9, a tenth MOSFET M10, and an eleventh MOSFET M11;

[0122] Among them, the eighth MOS transistor M8, the ninth MOS transistor M9, the tenth MOS transistor M10, and the eleventh MOS transistor M11 are PMOS transistors and have the same width-to-length ratio; the second input terminal includes: a second positive input terminal and a second negative input terminal;

[0123] The drain of the eighth MOS transistor M8 is connected to the source of the ninth MOS transistor M9 and the first current mirror.

[0124] The source of the eighth MOS transistor M8 is connected to the source of the tenth MOS transistor M10 and the second active load.

[0125] The gate of the eighth MOS transistor M8 is connected to the gate of the eleventh MOS transistor M11 and the second positive input terminal;

[0126] The gate of the ninth MOS transistor M9 is connected to the gate of the tenth MOS transistor M10 and the second negative input terminal;

[0127] The drain of the ninth MOS transistor M9 is connected to the drain of the eleventh MOS transistor M11 and the second active load.

[0128] The drain of the tenth MOS transistor M10 is connected to the source of the eleventh MOS transistor M11 and the second current mirror.

[0129] In this embodiment, the width-to-length ratio of the eighth MOSFET M8, the ninth MOSFET M9, the tenth MOSFET M10, and the eleventh MOSFET M11 is set to... Then we have:

[0130] ;

[0131] Among them, according to Substituting into the above formula, we get:

[0132]

[0133] ;

[0134] The current difference between the eighth MOSFET M8 and the ninth MOSFET M9 can then be obtained:

[0135] ;

[0136] in, The electron carrier mobility of the PMOS transistor. V SG This is the voltage difference between the source and gate of the PMOS transistor; The voltage threshold of the PMOS transistor;

[0137] In this embodiment, based on the symmetry of the circuit, the current difference between the eleventh MOSFET M11 and the tenth MOSFET M10 can be obtained as follows:

[0138] ;

[0139] in, The electron carrier mobility of the PMOS transistor;

[0140] Furthermore, the second active load includes: a twelfth MOSFET M12 and a thirteenth MOSFET M13;

[0141] Among them, the twelfth MOS transistor M12 and the thirteenth MOS transistor M13 are NMOS transistors;

[0142] The drain of the twelfth MOS transistor M12 is connected to the gate of the twelfth MOS transistor M12 and the second differential input stage;

[0143] The source of the twelfth MOS transistor M12 is connected to the drain of the thirteenth MOS transistor M13 and the circuit ground;

[0144] The drain of the thirteenth MOS transistor M13 is connected to the gate of the thirteenth MOS transistor M13 and the second differential input stage.

[0145] In this embodiment, the current difference is represented as the product function of the first signal and the second signal. Specifically, the current difference between the twelfth MOSFET M12 and the thirteenth MOSFET M13 is the product function of the first signal and the second signal. Wherein, the current difference between the twelfth MOSFET M12 and the thirteenth MOSFET M13 is:

[0146] ;

[0147] in, The electron carrier mobility of the PMOS transistor;

[0148] The second active load in this invention is connected to the second differential input stage, which allows the saturation voltage drop and threshold voltage of the twelfth MOSFET to be used in the Gilbert cell circuit, which helps to further reduce the power supply voltage and thus reduce energy consumption.

[0149] Please refer to Figure 4 This is a schematic diagram of the connection relationship of an embodiment of the active attenuation circuit provided by the present invention, wherein the first active attenuation circuit and the second active attenuation circuit have the same structure, both including: an attenuation circuit and a level shifting circuit;

[0150] The attenuation circuit is used to attenuate the input signal; the input signal includes either a first signal or a second signal.

[0151] The level shifting circuit is used to perform level conversion on the attenuated input signal so that the Gilbert unit circuit operates in the saturation region.

[0152] In this embodiment, although the Gilbert cell circuit can have a smaller operating voltage, its linear input range is very narrow, mainly because the following approximate relationship needs to be satisfied to achieve multiplication:

[0153] ,and .

[0154] in, denoted as , where is the electron carrier mobility of the PMOS transistor.

[0155] Therefore, in this embodiment of the invention, a first active attenuation circuit and a second active attenuation circuit are respectively placed between the two input signals and the first differential input stage and the second differential input stage. The output voltage of the active attenuator is typically only a few millivolts, thus greatly expanding the linear input range. To ensure that the input signal can guarantee that the low-voltage analog multiplication circuit operates in the saturation region, the attenuated signal also needs to be level-shifted; therefore, both active attenuation circuits include level-shifting circuits.

[0156] Furthermore, the attenuation circuit includes: the fourteenth MOSFET M14, the fifteenth MOSFET M18, the sixteenth MOSFET M15, and the seventeenth MOSFET M19; the level shifting circuit includes: the eighteenth MOSFET M22, the nineteenth MOSFET M23, the twentieth MOSFET M29, and the twenty-first MOSFET M30;

[0157] Among them, the fourteenth MOS transistor M14, the fifteenth MOS transistor M18, the sixteenth MOS transistor M15, and the seventeenth MOS transistor M19 are PMOS transistors;

[0158] The gate of the fourteenth MOS transistor M14 and the gate of the fifteenth MOS transistor M18 are connected to the positive terminal of the first signal or the positive terminal of the second signal.

[0159] The drain of the fourteenth MOS transistor M14 is connected to the operating power supply;

[0160] The source of the fourteenth MOS transistor M14 is connected to the drain of the fifteenth MOS transistor M18 and the level shifting circuit.

[0161] The source of the fifteenth MOS transistor M18 is connected to the circuit ground;

[0162] The gate of the sixteenth MOS transistor M15 and the gate of the seventeenth MOS transistor M19 are connected to the negative terminal of the first signal or the negative terminal of the second signal.

[0163] The source of the sixteenth MOS transistor M15 is connected to the operating power supply;

[0164] The drain of the sixteenth MOS transistor M15 is connected to the source of the seventeenth MOS transistor M19 and the level shifting circuit.

[0165] The drain of the seventeenth MOS transistor M19 is connected to the circuit ground;

[0166] The eighteenth MOS transistor M22, the nineteenth MOS transistor M23, the twentieth MOS transistor M29, and the twenty-first MOS transistor M30 are NMOS transistors;

[0167] The gate of the eighteenth MOS transistor M22 is connected to the attenuation circuit;

[0168] The drain of the eighteenth MOS transistor M22 is connected to the source of the nineteenth MOS transistor M23 and the operating power supply.

[0169] The source of the eighteenth MOS transistor M22 is connected to the source of the twentieth MOS transistor M29 and the positive output terminal of the active attenuation circuit.

[0170] The gate of the nineteenth MOS transistor M23 is connected to the attenuation circuit;

[0171] The drain of the nineteenth MOS transistor M23 is connected to the drain of the twenty-first MOS transistor M30 and the negative output terminal of the active attenuation circuit.

[0172] The gate of the twentieth MOSFET M29 is connected to the gate of the twentieth MOSFET M30 and the gate of the first MOSFET M1;

[0173] The drain of the twentieth MOSFET M29 is connected to the source of the eleventh MOSFET M30 and the circuit ground.

[0174] The attenuation circuit of this invention preprocesses the input signal, and the level shifting circuit solves the problem of small amplitude of the preprocessed input signal, so that the Gilbert unit circuit works in the saturation region, thereby ensuring a large linear input range while ensuring a low power supply voltage.

[0175] In this embodiment, it is assumed that the threshold voltages of the fourteenth MOSFET M14 and the fifteenth MOSFET M18 are the same, that is... Then we have:

[0176] ;

[0177] ;

[0178] in, The electron carrier mobility of the NMOS transistor. This is the minimum supply voltage of the circuit. Voltage threshold;

[0179] In this embodiment, when the current flowing through the fourteenth MOSFET M14 and the current flowing through the fifteenth MOSFET M18D are equal, that is... At that time, the output voltage of the active attenuator is:

[0180] ;

[0181] in, This is the minimum supply voltage of the circuit. Voltage threshold;

[0182] Then according to The output of the level shifting circuit can be obtained as follows:

[0183] .

[0184] Furthermore, the four-quadrant analog multiplier circuit also includes a bias circuit;

[0185] The bias circuit is connected to the first MOS transistor M1 and is used to provide operating current to the first MOS transistor M1.

[0186] The bias circuit of the present invention provides operating current to the first MOS transistor M1, so that the first MOS transistor M1 is in normal working state and the stability of circuit operation is guaranteed.

[0187] Furthermore, the bias circuit includes: a 22nd MOSFET M26, a 23rd MOSFET M27, and a 24th MOSFET M28;

[0188] Among them, the twentieth MOS transistor M26, the twentieth MOS transistor M27, and the twentieth MOS transistor M28 are NMOS transistors;

[0189] The source of the twelfth MOS transistor M26 is connected to the gate of the twelfth MOS transistor M26 and the operating power supply.

[0190] The drain of the twelfth MOS transistor M26 is connected to the source and gate of the twelfth MOS transistor M27.

[0191] The drain of the 23rd MOSFET M27 is connected to the source of the 24th MOSFET M28, the gate of the 24th MOSFET M28, and the gate of the first MOSFET M1.

[0192] The drain of the 24th MOSFET M28 is connected to the circuit ground.

[0193] In the Gilbert cell circuit of the present invention, the first active load, the first current mirror, and the second current mirror are connected to the operating power supply, and then connected to the first differential input stage and the second differential input stage; the second differential input stage and the second differential input stage are then connected to the circuit ground via the first MOSFET M1 and the second active load, thus reducing at least one saturation voltage drop, and thus operating at a lower operating voltage with lower power consumption; in addition, after the active attenuation circuit attenuates the input signal, it makes the Gilbert cell circuit operate in the saturation region through level shifting, thereby improving the input linear range.

[0194] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention for those skilled in the art.

Claims

1. A four-quadrant analog multiplier circuit, characterized by include: Gilbert unit circuit and first active attenuation circuit, second active attenuation circuit; Wherein, the first input terminal of the Gilbert unit circuit is connected to the output terminal of the first active attenuation circuit, and the second input terminal of the Gilbert unit circuit is connected to the output terminal of the second active attenuation circuit; the input terminal of the first active attenuation circuit is connected to a first signal; and the input terminal of the second active attenuation circuit is connected to a second signal. The Gilbert unit circuit includes: a first MOSFET, a first differential input stage, a second differential input stage, a first active load, a second active load, a first current mirror, and a second current mirror; The power supply is connected to the first active load, the first current mirror, and the second current mirror, respectively. The first active load is connected to the first differential input stage, the first current mirror is connected to the first differential input stage and the second differential input stage, and the second current mirror is connected to the first differential input stage and the second differential input stage. The first differential input stage is connected to the first input terminal of the Gilbert cell circuit and the drain of the first MOS transistor, and the second differential input stage is connected to the second input terminal of the Gilbert cell circuit and the second active load, respectively. The gate of the first MOS transistor is connected to a bias voltage, the source of the first MOS transistor is connected to the circuit ground, and the second active load is connected to the circuit ground; wherein, the first MOS transistor is an NMOS transistor; The second active load is used to convert the current difference of the included MOSFETs into an output voltage; wherein the current difference is expressed as a product function of the first signal and the second signal; The first active attenuation circuit and the second active attenuation circuit are used to attenuate the input signal and then perform level shifting so that the Gilbert unit circuit operates in the saturation region.

2. The four-quadrant analog multiplier circuit of claim 1, wherein, The first differential input stage includes: a second MOSFET and a third MOSFET; The second MOS transistor and the third MOS transistor are NMOS transistors with the same width-to-length ratio; the first input terminal includes a first positive input terminal and a first negative input terminal; The drain of the second MOSFET is connected to the first active load; The gate of the second MOS transistor is connected to the positive terminal of the first input. The drain of the second MOS transistor is connected to the drain of the third MOS transistor and the drain of the first MOS transistor; The source of the third MOS transistor is connected to the first active load and the first current mirror. The gate of the third MOS transistor is connected to the negative input terminal of the first MOS transistor.

3. The four-quadrant analog multiplier circuit of claim 1, wherein, The first active load includes a fourth MOSFET and a fifth MOSFET; the first current mirror includes a fifth MOSFET and a sixth MOSFET; the second current mirror includes a fourth MOSFET and a seventh MOSFET. Among them, the fourth MOS transistor, the fifth MOS transistor, the sixth MOS transistor, and the seventh MOS transistor are PMOS transistors; The drain of the fourth MOS transistor is connected to the source of the fifth MOS transistor, the drain of the sixth MOS transistor, the drain of the seventh MOS transistor, and the operating power supply. The gate of the fourth MOS transistor is connected to the source of the fourth MOS transistor, the gate of the seventh MOS transistor, and the first differential input stage; The gate of the fifth MOS transistor is connected to the drain of the fifth MOS transistor, the gate of the sixth MOS transistor, and the first differential input stage; The source of the sixth MOS transistor is connected to the second differential input stage; The source of the seventh MOS transistor is connected to the second differential input stage.

4. The four-quadrant analog multiplier circuit of claim 1, wherein, The second differential input stage includes: an eighth MOSFET, a ninth MOSFET, a tenth MOSFET, and an eleventh MOSFET; The eighth, ninth, tenth, and eleventh MOS transistors are PMOS transistors and have the same width-to-length ratio; the second input terminal includes a second positive input terminal and a second negative input terminal. The drain of the eighth MOS transistor is connected to the source of the ninth MOS transistor and the first current mirror. The source of the eighth MOS transistor is connected to the source of the tenth MOS transistor and the second active load. The gate of the eighth MOS transistor is connected to the gate of the eleventh MOS transistor and the second positive input terminal; The gate of the ninth MOS transistor is connected to the gate of the tenth MOS transistor and the second negative input terminal; The drain of the ninth MOS transistor is connected to the drain of the eleventh MOS transistor and the second active load. The drain of the tenth MOS transistor is connected to the source of the eleventh MOS transistor and the second current mirror.

5. The four-quadrant analog multiplier circuit as described in claim 1, characterized in that, The second active load includes: the twelfth MOSFET and the thirteenth MOSFET; Among them, the twelfth MOS transistor and the thirteenth MOS transistor are NMOS transistors; The drain of the twelfth MOS transistor is connected to the gate of the twelfth MOS transistor and the second differential input stage; The source of the twelfth MOS transistor is connected to the drain of the thirteenth MOS transistor and the circuit ground; The drain of the thirteenth MOS transistor is connected to the gate of the thirteenth MOS transistor and the second differential input stage.

6. The four-quadrant analog multiplier circuit of claim 5, wherein, The current difference is expressed as a product function of the first signal and the second signal, specifically: The current difference between the twelfth and thirteenth MOS transistors is a product function of the first and second signals.

7. The four-quadrant analog multiplier circuit of claim 1, wherein, The first active attenuation circuit and the second active attenuation circuit have the same structure, both including: an attenuation circuit and a level shifting circuit; The attenuation circuit is used to attenuate the input signal; the input signal includes either a first signal or a second signal. The level shifting circuit is used to perform level conversion on the attenuated input signal so that the Gilbert unit circuit operates in the saturation region.

8. The four-quadrant analog multiplier circuit of claim 7, wherein, The attenuation circuit includes: the fourteenth MOSFET, the fifteenth MOSFET, the sixteenth MOSFET, and the seventeenth MOSFET; the level shifting circuit includes: the eighteenth MOSFET, the nineteenth MOSFET, the twentieth MOSFET, and the twenty-first MOSFET; Among them, the fourteenth MOS transistor, the fifteenth MOS transistor, the sixteenth MOS transistor, and the seventeenth MOS transistor are PMOS transistors; The gate of the fourteenth MOS transistor and the gate of the fifteenth MOS transistor are connected to the positive terminal of the first signal or the positive terminal of the second signal. The drain of the fourteenth MOS transistor is connected to the operating power supply; The source of the fourteenth MOS transistor is connected to the drain of the fifteenth MOS transistor and the level shifting circuit; The source of the fifteenth MOS transistor is connected to the circuit ground; The gate of the sixteenth MOS transistor and the gate of the seventeenth MOS transistor are connected to the negative terminal of the first signal or the negative terminal of the second signal. The source of the sixteenth MOS transistor is connected to the operating power supply; The drain of the sixteenth MOS transistor is connected to the source of the seventeenth MOS transistor and the level shifting circuit; The drain of the seventeenth MOS transistor is connected to the circuit ground; The eighteenth MOS transistor, the nineteenth MOS transistor, the twentieth MOS transistor, and the twenty-first MOS transistor are NMOS transistors; The gate of the eighteenth MOS transistor is connected to the attenuation circuit; The drain of the eighteenth MOS transistor is connected to the source of the nineteenth MOS transistor and the operating power supply. The source of the eighteenth MOS transistor is connected to the source of the twentieth MOS transistor and the positive output terminal of the first active attenuation circuit. The gate of the nineteenth MOS transistor is connected to the attenuation circuit; The drain of the nineteenth MOS transistor is connected to the drain of the twenty-first MOS transistor and the negative output terminal of the first active attenuation circuit. The gate of the twentieth MOS transistor is connected to the gate of the twentieth MOS transistor and the gate of the first MOS transistor; The drain of the twentieth MOS transistor is connected to the source of the twentieth MOS transistor and the circuit ground.

9. The four-quadrant analog multiplier circuit of any of claims 1-8, wherein, It also includes a bias circuit; The bias circuit is connected to the first MOSFET and is used to provide operating current to the first MOSFET.

10. The four-quadrant analog multiplier circuit of claim 9, wherein, The bias circuit includes: a 22nd MOSFET, a 23rd MOSFET, and a 24th MOSFET; Among them, the twentieth MOS transistor, the twentieth MOS transistor, and the twentieth MOS transistor are NMOS transistors; The source of the twelfth MOS transistor is connected to the gate of the twelfth MOS transistor and the operating power supply; The drain of the 22nd MOS transistor is connected to the source and gate of the 23rd MOS transistor. The drain of the 23rd MOS transistor is connected to the source of the 24th MOS transistor, the gate of the 24th MOS transistor, and the gate of the first MOS transistor; The drain of the 24th MOSFET is connected to the circuit ground.

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