Memory interleaving matching method and device, readable storage medium and electronic equipment

Abstract

This invention provides a memory interleaving matching method, comprising: before at least one core of a chipset executes a service, acquiring multiple first latencies when the core accesses memory at multiple locations; acquiring multiple second latencies under multiple predetermined memory interleaving types based on the multiple first latencies and the proportion of memory accesses to multiple locations under multiple predetermined memory interleaving types; determining multiple reference values ​​for memory interleaving matching of a target service based on the multiple second latencies; acquiring the number of times the core accesses memory at each location within a predetermined time period when at least one core of the chipset executes the target service; acquiring the expected third latency of the target service based on the multiple first latencies and the number of accesses; and determining the memory interleaving type of the target service based on the multiple reference values ​​and the third latency. The memory interleaving matching method and apparatus provided by this invention can track the optimal memory interleaving type corresponding to the current execution scenario in real time.

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