Chip power consumption management controller automatic generation method, device and equipment
By automatically generating hardware design code and test models for chip power management controllers using the Perl language, the problems of low efficiency and high error rate of traditional manual coding are solved, and efficient and flexible chip power management is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HUNAN GREAT WALL GALAXY TECH CO LTD
- Filing Date
- 2025-03-07
- Publication Date
- 2026-06-19
AI Technical Summary
Traditional methods of manually writing hardware design code and test models for chip power management controllers are time-consuming, labor-intensive, prone to errors, and have high design complexity, making it difficult to adapt to changes in chip design.
The chip power management controller is automatically generated using Perl language based on parameter passing. Hardware design code and test models are generated through bus interface configuration, address decoding, power module configuration, clock module configuration, and test stimuli.
It improves the efficiency of custom design of power management controllers, reduces the time spent on manual code writing and testing models, and enhances the flexibility and maintainability of the design.
Smart Images
Figure CN120163122B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of chip testing technology and relates to a method, apparatus and device for automatically generating chip power management controllers. Background Technology
[0002] With the rapid development of chip technology, chip integration is constantly increasing, and chip scale is becoming larger and larger. As chip scale grows, power consumption becomes a key factor restricting chip performance and applications. To address this issue, power management controllers (PSCs) have emerged. PSCs effectively reduce overall energy consumption by implementing power or clock control on different modules within the chip, without affecting normal system operation. This is crucial for the stable operation and performance optimization of large-scale chips. Due to the diversity of chip development, different chips have different modules, requiring customized power management controllers for each chip. However, traditionally, manually writing hardware design code and test models for power management controllers is not only time-consuming and labor-intensive but also prone to errors. Therefore, developing an efficient and accurate technology for automatically generating power management controllers and their test models is of significant practical importance. Summary of the Invention
[0003] To address the problems existing in the above-mentioned traditional technologies, this invention proposes an automatic generation method for chip power management controllers, an automatic generation device for chip power management controllers, and a computer device, which can efficiently and accurately generate power management controllers and their test models automatically.
[0004] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions:
[0005] On the one hand, a method for automatically generating a chip power management controller is provided, including the following steps:
[0006] This code, written in Perl, uses parameter passing to customize the network transmission protocol configuration and completes the bus interface configuration between the power management controller and the chip system.
[0007] The Perl language is used to write the address decoding logic for each module of the chip during the module address decoding process;
[0008] Using the Perl language, the power modules of the chip are treated as a specific array by using array members, and the power module shutdown process is matched by regular expressions to generate the hardware design code of the power module.
[0009] Based on the Perl language, a special character matching pattern is used to determine the network status and network request initiation method of the module requiring low power control in the system, and a clear network request signal corresponding to the network request initiation method is generated; the network status includes network host or network slave, and the network request initiation method includes active or passive.
[0010] By using wildcard matching to match the control logic of the clock module, scripts are generated for the clock logic, reset logic, and isolation control logic of modules in the chip that require low-power control.
[0011] After quickly building a test model suitable for chip design by adjusting array members using the Perl language, the test stimulus assertion syntax is scripted by setting variables, and the chip power management controller is automatically generated.
[0012] On the other hand, an automatic generation device for chip power management controllers is also provided, comprising:
[0013] The bus configuration module is used to customize the network transmission protocol code based on the Perl language using parameter passing, and to complete the bus interface configuration between the power management controller and the chip system.
[0014] The address decoding module is used to write address decoding logic for each module of the chip in the module address decoding process using the Perl language;
[0015] The power configuration module is used to generate the hardware design code of the power module by using array members in Perl language to treat the chip's power modules as a specific array and matching the power module's shutdown process using regular expressions.
[0016] The network request module is used to determine the network status and network request initiation method of the module requiring low-power control in the system based on special character matching patterns using the Perl language, and to generate a clear network request signal corresponding to the network request initiation method; the network status includes network host or network slave, and the network request initiation method includes active or passive.
[0017] The clock configuration module is used to match the control logic of the clock module using wildcards and generate scripts for the clock logic, reset logic, and isolation control logic of modules in the chip that require low-power control.
[0018] The test stimulus module is used to quickly build a test model suitable for chip design by adjusting array members using the Perl language, and then script the assertion syntax of test stimuli by setting variables to automatically generate the chip power management controller.
[0019] In another aspect, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the above-mentioned chip power management controller automatic generation method.
[0020] One of the above technical solutions has the following advantages and beneficial effects:
[0021] The aforementioned chip power management controller automatic generation method, apparatus, and device achieve precise control of the communication network transmission process between the power management controller and the chip system by customizing the network transmission protocol code through parameter passing. Then, the power module is processed as a specific array through array members, and the power module's shutdown process is matched by regular expressions to automatically generate the power module's hardware design code. Finally, by flexibly adjusting array members and variable settings, a test model suitable for a specific chip design is quickly built, and the hardware design code of the power management controller is interconnected with the test environment of the test model to transmit test information.
[0022] Compared to traditional technologies, the above-mentioned parameter-based automatic generation method only requires confirming the low-power control method of the chip module and passing it to the script as parameters to quickly generate the corresponding hardware design code and module-level test environment and stimulus. This significantly improves the efficiency of custom design of power management controllers and reduces the time and workload of manually writing code and test models. Because of the script-based generation method, if modules need to be added or deleted during the chip design process, only the passed parameters need to be modified to quickly change the hardware design code, improving the flexibility and maintainability of the design. Attached Figure Description
[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0024] Figure 1 This is a schematic diagram of the main structure of the power management controller;
[0025] Figure 2 This is a flowchart illustrating an automatic generation method for a chip power management controller in one embodiment;
[0026] Figure 3 This is a schematic diagram of the process structure for automatic parameter generation in one embodiment;
[0027] Figure 4This is a schematic diagram of the processing flow generated by the hardware design in one embodiment.
[0028] Figure 5 This is a schematic diagram of parameter passing and test set structure in one embodiment;
[0029] Figure 6 This is a block diagram of an automatic generation device for a chip power management controller in one embodiment. Detailed Implementation
[0030] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention.
[0031] It should be noted that, in this document, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will understand that the embodiments described herein can be combined with other embodiments. The term "and / or" as used in the specification and appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.
[0032] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
[0033] With the evolution of chip technology, the number of transistors integrated into chips has increased exponentially. This has led to a dramatic increase in chip power consumption. Excessive power consumption not only causes severe overheating, affecting chip performance and reliability, but also increases system energy consumption. Power management controllers can intelligently control the power supply and clock of various modules within a chip based on its operating status. For example, when a module is idle, the power management controller can promptly shut down its power supply or clock, thereby significantly reducing the overall power consumption of the chip. Moreover, with the wide variety of chip types and the increasing integration and technological advancements, the complexity of power management is growing, making the need for highly efficient power management controllers even more urgent.
[0034] Currently, when customizing power management controllers for each chip, the hardware design code and test models are typically written manually. This approach has several drawbacks. First, writing the hardware design code for the power management controller requires a deep understanding of each module of the chip and familiarity with hardware description languages, a process that consumes a significant amount of time and effort. Second, writing the test models for the power management controller is equally complex, requiring consideration of various boundary conditions and abnormal situations to ensure the correctness and reliability of the controller. Furthermore, during the manual writing of the hardware design code, errors are easily introduced due to the writer's negligence and fatigue. These errors are often difficult to detect and fix during later debugging and verification, leading to extended chip design cycles and increased costs. In addition, when the chip design changes (such as adding or removing modules), the hardware design code for the power management controller also needs to be modified accordingly, further increasing design complexity.
[0035] The main structure of the power management controller is as follows: Figure 1 As shown, its main structure includes a bus interface module, a clock and power control module, a state transition control module, and a state transition monitoring module. Among them, the bus interface module plays a crucial role, mainly used to realize bidirectional data interaction between the chip system network and the controller, complete read and write access operations to the controller, and process configuration request access, ensuring the efficient transmission of system information flow.
[0036] The clock and power control module, under the strict control of the state transition control module, smoothly enters the configuration phase according to the specific requirements of the configuration request. This process is the core hub of the controller: the clock and power control module first performs a network clearing operation to ensure a clean network request environment for low-power modules, while maintaining network isolation, laying a solid foundation for the safe and stable operation of the system; subsequently, the clock and power control module precisely regulates and outputs a series of key control signals such as power supply, clock, and reset, providing stable operating conditions for the normal operation of all parts of the system. The state transition monitoring module plays a safeguard role at all times, monitoring every state transition of the system to ensure the accuracy and integrity of state transitions, and ensuring the stability and reliability of system operation.
[0037] This invention proposes a parameter-driven method for automatically generating chip power management controllers using the Perl language. This method generates hardware design code and test models for power management controllers. It not only enables customized design based on the needs of different chip modules, but also greatly improves development efficiency and accuracy.
[0038] In one embodiment, such as Figure 2As shown, a method for automatically generating a chip power management controller is provided, which may include the following steps S10 to S20:
[0039] S10 uses Perl language to customize the network transmission protocol through parameter passing, and completes the bus interface configuration between the power management controller and the chip system.
[0040] S12 uses Perl language to write address decoding logic for each module of the chip during the module address decoding process;
[0041] S14: Based on the Perl language, the power modules of the chip are used as a specific array by using array members, and the power module shutdown process is matched by regular expressions to generate the hardware design code of the power module.
[0042] S16, using Perl language and special character matching patterns, determine the network status and network request initiation method of the module requiring low power control in the system, and generate a clear network request signal corresponding to the network request initiation method; the network status includes network host or network slave, and the network request initiation method includes active or passive.
[0043] S18 uses wildcard matching to match the control logic of the clock module and generates scripts for the clock logic, reset logic, and isolation control logic of the modules in the chip that require low-power control.
[0044] S20, based on the Perl language, quickly builds a test model suitable for chip design by adjusting array members, and then scripts the assertion syntax of test stimuli through variable settings to automatically generate the chip power management controller.
[0045] As can be understood, this embodiment is implemented using the Perl language. It customizes the module names that the power management controller needs to control (both the power supply and the clock) by passing parameters, automatically generating the corresponding hardware design code and test model for the power management controller. This method can be divided into five key parts, such as... Figure 3 As shown, the steps in the hardware design code are as follows: bus interface configuration, module address decoding, power module configuration, clock module configuration, and generation of test environment and test stimuli.
[0046] The power management controller is a crucial module for reducing power consumption within the chip. Communication between the power management controller and the chip system relies on network protocol interaction. Since different network protocols have their own unique handshake methods, this embodiment uses parameter passing for bus interface configuration, customizing the network transmission protocol code to achieve precise control over the transmission process of the communication network between the power management controller and the chip system.
[0047] In the power management controller, the number of clock power control modules comes from the number of modules in the input parameters. During the module address decoding process, address decoding logic is written for each module, enabling the chip to access the power management controller through the bus interface and accurately identify the addresses of different modules, thus providing a foundation for subsequent power and clock control of each module.
[0048] During system operation, the PSC needs to control the power switches of modules that require power-off. In this solution, the power module configuration uses array members to process the power modules as a specific array. Regular expressions are used to match the power module shutdown process, automatically generating the hardware design code for the power modules.
[0049] In power management systems, a key strategy for reducing power consumption is to disable the clocks of all modules within a chip that require power management control. When implementing this strategy during clock module configuration, a special character matching pattern is first used to accurately determine whether the module requiring low-power control is a network host or a network slave in the system. Simultaneously, based on whether the module's network request initiation method is active or passive, a clear network request signal corresponding to the network request initiation method is generated. The core of this step lies in multi-dimensional filtering from array members to accurately locate and extract the network request signals unique to each module requiring low-power control. After completing the above steps, wildcard matching is cleverly used to match the control logic of the clock module, generating scripts for the clock, reset, and isolation control logic of the modules requiring low-power control.
[0050] The test environment section allows for the rapid construction of a test framework (model) suitable for specific chip designs by flexibly adjusting array members and variable settings, supporting various test scenarios from simple to complex. Through variable settings, the assertion syntax of test stimuli is scripted, ultimately enabling the generation of module-level test stimuli including address testing, single-module power control flow, and concurrent power control flow, providing strong assurance for the correctness and reliability of the power management controller. The design challenge in this test environment and test stimulus generation process is that different chip test scenarios require matching different output variables, and it is essential to ensure that the hardware design code of the power management controller remains consistent with the control results of the test model.
[0051] The aforementioned method for automatically generating chip power management controllers achieves precise control over the communication network transmission process between the power management controller and the chip system by customizing the network transmission protocol code through parameter passing. Then, the power module is processed as a specific array through array members, and the power module's shutdown process is matched using regular expressions to automatically generate the power module's hardware design code. Finally, by flexibly adjusting array members and variable settings, a test model suitable for a specific chip design is quickly built, interconnecting the power management controller's hardware design code with the test environment of the test model and transmitting test information.
[0052] Compared to traditional technologies, the above-mentioned parameter-based automatic generation method only requires confirming the low-power control method of the chip module and passing it to the script as parameters to quickly generate the corresponding hardware design code and module-level test environment and stimulus. This significantly improves the efficiency of custom design of power management controllers and reduces the time and workload of manually writing code and test models. Because of the script-based generation method, if modules need to be added or deleted during the chip design process, only the passed parameters need to be modified to quickly change the hardware design code, improving the flexibility and maintainability of the design.
[0053] In one embodiment, during the module address decoding process, the module name of the module to be controlled is stored in an array as a member of the array.
[0054] It is understandable that the processing flow generated by the hardware design is as follows: Figure 4 As shown, regarding module address decoding, the input parameter method involves using different modules as members of an array, and the script for module address decoding is based on this. For example, assuming the input modules to be controlled include chip modules A, B, and C, these module names are stored in an array, such as array @modules = ("moduleA", "moduleB", "moduleC"). The core of this specific implementation is: by matching each member of the array with data (this data is the address information of the modules in the older version of the chip, used to ensure that users do not need to reconfigure the address information of the unchanged modules in the driver for the modified chip), the address is calculated accurately, thereby completing the address decoding of the corresponding module, laying the foundation for stable system operation and efficient control.
[0055] In one embodiment, the process of generating the hardware design code for the power module by matching the power module's shutdown procedure using regular expressions may specifically include:
[0056] After filtering out the control signals related to the power module by matching special characters, a list of power control signals is generated.
[0057] The power module control script is automatically generated based on the matching results.
[0058] Regarding the specific implementation of power module configuration, for example, if the power module's control flow follows a specific naming convention, such as "power_down_moduleX" for power-down of module X, a crucial step is accurately distinguishing the different power domains within the power module. Power module configuration can filter relevant control signals by matching special characters, thereby generating a detailed list of power control signals for module X, such as... Figure 4 For example, for the power control domain, the power control domain can be matched by matching special characters such as domain a and domain b; then, based on the matching results, the power module control script for module X is automatically generated, ensuring that when the system needs to shut down the power of module X, the operation can be executed accurately to shut down the power of module X, ensuring stable and low-power operation of the system.
[0059] In one embodiment, regarding the clock module configuration process, specifically for example: when processing clock signals, wildcards can be used to match the clock signal names of all modules requiring low-power control, such as using clock signal names in the form of "clk_*", comprehensively covering various clock signals. Subsequently, corresponding clock control logic scripts are written for these matched clock signal names to achieve reliable clock shutdown operations for the corresponding modules. During this process, related logic such as reset and isolation control is simultaneously considered, such as... Figure 4 As shown, this ensures that the system remains stable and reliable even when the clock is off, avoiding various potential problems caused by clock shutdown.
[0060] In one embodiment, it can be understood that the process of generating the aforementioned test environment and test stimuli specifically involves the test environment portion rapidly building a test model suitable for a specific chip design by flexibly adjusting array members and variable settings, supporting various test scenarios from simple to complex. The hardware design code of the power management controller is interconnected with the test environment, and test information is transmitted, such as... Figure 5As shown, firstly, the address information of the modules to be tested is stored in an array, such as the test address array @test_addresses = ("address1", "address2",...). Then, based on this address information, the power management control process is initiated. By setting variables, the assertion syntax of the test stimuli is scripted. For example, the variable $expected_result is defined to represent the expected test result. The Perl assertion statement if ($actual_result == $expected_result) { print "Test Passed";} else { print "Test Failed";} is used to verify whether the power management control process is correct. Ultimately, a module-level test stimulus including address testing, single-module power control flow, and concurrent power control flow is implemented, providing strong assurance for the correctness and reliability verification of the power management controller.
[0061] It should be understood that, although the above process Figure 2 The steps in the diagram are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order in which these steps are executed; they can be performed in other orders. Furthermore, the above process... Figure 2 At least some of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.
[0062] In one embodiment, such as Figure 6As shown, an automatic generation device 100 for a chip power management controller is provided, including a bus configuration module 11, an address decoding module 13, a power configuration module 15, a network request module 17, a clock configuration module 19, and a test stimulus module 21. The bus configuration module 11 is used to customize the network transmission protocol code based on Perl language using parameter passing, completing the bus interface configuration between the power management controller and the chip system. The address decoding module 13 is used to write address decoding logic for each module of the chip using Perl language during the module address decoding process. The power configuration module 15 is used to generate the hardware design code for the power modules by using array members as a specific array and matching the power module shutdown process using regular expressions, based on Perl language. The network request module 17 is used to determine the network status and network request initiation method of the module requiring low-power control in the system using special character matching patterns, based on Perl language, and generates a clear network request signal corresponding to the network request initiation method; the network status includes network host or network slave, and the network request initiation method includes active or passive. The clock configuration module 19 is used to match the control logic of the clock module using wildcards, generating scripts for the clock logic, reset logic, and isolation control logic of modules in the chip that require low-power control. The test stimulus module 21 is used to quickly build a test model suitable for chip design by adjusting array members based on Perl language, and then script the assertion syntax of test stimuli through variable settings, thereby automatically generating the chip power management controller.
[0063] The aforementioned chip power management controller automatic generation device 100 achieves precise control over the communication network transmission process between the power management controller and the chip system by customizing the network transmission protocol code through parameter passing. Then, it processes the power module as a specific array member and uses regular expressions to match the power module's shutdown process to automatically generate the power module's hardware design code. Finally, by flexibly adjusting array members and variable settings, it quickly builds a test model suitable for a specific chip design, interconnecting the power management controller's hardware design code with the test model's test environment and transmitting test information. This reduces the time and workload of manually writing code and test models, allows for rapid changes to the hardware design code, and improves design flexibility and maintainability.
[0064] In one embodiment, during the module address decoding process, the module name of the module to be controlled is stored in an array as a member of the array.
[0065] In one embodiment, the process of generating the hardware design code of the power module by matching the power module's shutdown process using regular expressions may include: generating a power control signal list after filtering out the control signals related to the power module by matching special characters; and automatically generating the power module control script of the module based on the matching results.
[0066] For specific limitations of the aforementioned chip power management controller automatic generation device 100, please refer to the corresponding limitations of the chip power management controller automatic generation method mentioned above, which will not be repeated here.
[0067] In one embodiment, a computer device is provided, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the following processing steps: Customizing network transmission protocol code using Perl language with parameter passing to complete the bus interface configuration between the power management controller and the chip system; writing address decoding logic for each module of the chip using Perl language during module address decoding; using Perl language to treat the chip's power modules as a specific array and matching the power module shutdown process using regular expressions to generate hardware design code for the power modules; using Perl language to determine the network status and network request initiation method of the modules requiring low-power control in the system using special character matching patterns, and generating a clear network request signal corresponding to the network request initiation method; the network status includes network host or network slave, and the network request initiation method includes active or passive; using wildcard matching to match the control logic of the clock module, generating scripts for the clock logic, reset logic, and isolation control logic of the modules in the chip requiring low-power control; and using Perl language to quickly build a test model suitable for chip design by adjusting array members, and then scripting the test stimulus assertion syntax through variable settings to automatically generate the chip power management controller.
[0068] In one embodiment, when the processor executes a computer program, it may also implement the steps or sub-steps added to the various embodiments of the above-described automatic generation method for power management controllers.
[0069] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided by this invention can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), memory bus DRAM (RDRAM), and interface DRAM (DRDRAM), etc.
[0070] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0071] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of protection of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and all such modifications and improvements fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.
Claims
1. A method for automatically generating a chip power management controller, characterized in that, Including the following steps: This code, written in Perl, uses parameter passing to customize the network transmission protocol configuration and completes the bus interface configuration between the power management controller and the chip system. The Perl language is used to write the address decoding logic for each module of the chip during the module address decoding process; Using the Perl language, the power modules of the chip are treated as a specific array by using array members, and the power module shutdown process is matched by regular expressions to generate the hardware design code of the power module. Based on the Perl language, a special character matching pattern is used to determine the network status and network request initiation method of the module requiring low power control in the system, and a clear network request signal corresponding to the network request initiation method is generated; the network status includes network host or network slave, and the network request initiation method includes active or passive. By using wildcard matching to match the control logic of the clock module, scripts are generated for the clock logic, reset logic, and isolation control logic of modules in the chip that require low-power control. After quickly building a test model suitable for chip design by adjusting array members using the Perl language, the test stimulus assertion syntax is scripted by setting variables, and the chip power management controller is automatically generated.
2. The method for automatically generating a chip power management controller according to claim 1, characterized in that, During the module address decoding process, the module names of the modules that need to be controlled are stored in an array as array members.
3. The chip power management controller automatic generation method according to claim 1 or 2, characterized in that, The process of generating the hardware design code for the power module by matching the power module's shutdown process using regular expressions includes: After filtering out the control signals related to the power module by matching special characters, a list of power control signals is generated. The power module control script is automatically generated based on the matching results.
4. A chip power management controller automatic generation apparatus, characterized by, include: The bus configuration module is used to customize the network transmission protocol code based on the Perl language using parameter passing, and to complete the bus interface configuration between the power management controller and the chip system. The address decoding module is used to write address decoding logic for each module of the chip in the module address decoding process using the Perl language; The power configuration module is used to generate the hardware design code of the power module by using array members in Perl language to treat the chip's power modules as a specific array and matching the power module's shutdown process using regular expressions. The network request module is used to determine the network status and network request initiation method of the module requiring low-power control in the system based on special character matching patterns using the Perl language, and to generate a clear network request signal corresponding to the network request initiation method; the network status includes network host or network slave, and the network request initiation method includes active or passive. The clock configuration module is used to match the control logic of the clock module using wildcards and generate scripts for the clock logic, reset logic, and isolation control logic of modules in the chip that require low-power control. The test stimulus module is used to quickly build a test model suitable for chip design by adjusting array members using the Perl language, and then script the assertion syntax of test stimuli by setting variables to automatically generate the chip power management controller.
5. The chip power management controller automatic generation apparatus of claim 4, wherein, During the module address decoding process, the module names of the modules that need to be controlled are stored in an array as array members.
6. The automatic generation device for chip power management controller according to claim 4 or 5, characterized in that, The process of generating the hardware design code for the power module by matching the power module's shutdown process using regular expressions includes: After filtering out the control signals related to the power module by matching special characters, a list of power control signals is generated. The power module control script is automatically generated based on the matching results. 7.A computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the computer device is configured to perform the method according to any one of claims 1-6 when the computer program is executed by the processor. When the processor executes the computer program, it implements the steps of the automatic generation method for chip power management controller according to any one of claims 1 to 3.