Interrupt verification method and device, computer device, chip and chip module

Abstract

The application relates to an interrupt verification method and device, computer equipment, a chip and a chip module, which can be used in the technical field of processors. The method comprises the following steps: performing comparison processing on first log information and second log information; in the process of comparison processing, if an interrupt occurrence identifier is detected from the first log information, the comparison processing is paused, and interrupt processing information executed by a processor to be verified is checked; if an interrupt processing information checking result is obtained, the comparison processing is resumed according to interrupt breakpoint information corresponding to the interrupt occurrence identifier; and an interrupt verification result of the processor to be verified is determined according to a comparison result of the comparison processing and the interrupt processing information checking result. The method can improve the accuracy of interrupt verification.

Description

Technical Field

[0001] This application relates to the field of processor technology, and in particular to an interrupt verification method, apparatus, computer equipment, chip, and chip module. Background Technology

[0002] As processor design complexity continues to increase, the interrupt mechanism, as one of the core functions of a processor, becomes particularly important for verification during the research and development process. Interrupt verification needs to ensure that the processor can correctly respond to and handle various interrupt events during instruction execution, thus guaranteeing the reliability and stability of the system.

[0003] In related technologies, interrupt verification schemes often face verification difficulties due to the randomness of interrupt timing and the complexity of interrupt handling procedures, resulting in low accuracy of interrupt verification. Summary of the Invention

[0004] Therefore, it is necessary to provide an interrupt verification method, apparatus, computer equipment, chip, chip module, computer-readable storage medium, and computer program product that can improve the accuracy of interrupt verification in response to the above-mentioned technical problems.

[0005] Firstly, this application provides an interruption verification method. The method includes:

[0006] The first log information and the second log information are compared; the first log information is used to characterize the log information generated after executing the instruction stream through the processor to be verified; the second log information is used to characterize the log information generated after executing the instruction stream through the preset reference model corresponding to the processor to be verified.

[0007] During the comparison process, if an interruption flag is detected from the first log information, the comparison process is paused, and the interrupt handling information executed by the processor to be verified is verified.

[0008] If the interrupt handling information verification result is obtained, the comparison process is resumed according to the interrupt breakpoint information corresponding to the interruption occurrence identifier.

[0009] Based on the comparison results of the comparison process and the interrupt processing information verification results, the interrupt verification result of the processor to be verified is determined.

[0010] In one embodiment, the step of resuming the comparison process based on the interrupt breakpoint information corresponding to the interruption occurrence identifier includes:

[0011] Based on the interruption point information, determine the alignment recovery position of the alignment process;

[0012] The comparison process is resumed based on the comparison recovery position.

[0013] In one embodiment, the verification process for the interrupt handling information executed by the processor to be verified includes:

[0014] The interrupt attribute information in the interrupt handling information is verified to obtain a first verification result;

[0015] Based on preset verification information, the interrupt handling information is self-verified to obtain a second verification result;

[0016] The interrupt handling information verification result is determined based on the first verification result and the second verification result.

[0017] In one embodiment, the interrupt attribute information includes interrupt identification information and interrupt priority information;

[0018] The step of verifying the interrupt attribute information in the interrupt handling information to obtain a first verification result includes:

[0019] The interrupt identifier information is verified to obtain the verification result of the interrupt identifier information;

[0020] The interrupt priority information is verified to obtain the verification result of the interrupt priority information;

[0021] The first verification result is determined based on the verification results of the interrupt identifier information and the interrupt priority information.

[0022] In one embodiment, before comparing the first log information and the second log information, the method further includes:

[0023] Obtain the instruction stream generated by the instruction generator;

[0024] The instruction stream is compiled to obtain the executable file;

[0025] The processor to be verified executes the executable file to generate the first log information, and the preset reference model executes the executable file to generate the second log information.

[0026] In one embodiment, the comparison process between the first log information and the second log information includes:

[0027] Obtain the instruction execution order;

[0028] According to the execution order of the instructions, the first log information and the second log information are compared instruction by instruction.

[0029] Secondly, this application also provides an interruption verification device. The device includes:

[0030] The information comparison module is used to compare and process the first log information and the second log information; the first log information is used to characterize the log information generated after executing the instruction stream through the processor to be verified; the second log information is used to characterize the log information generated after executing the instruction stream through the preset reference model corresponding to the processor to be verified.

[0031] The information verification module is used to pause the comparison process and verify the interrupt handling information executed by the processor to be verified when an interruption identifier is detected from the first log information during the comparison process.

[0032] The processing recovery module is used to recover the comparison process based on the interrupt breakpoint information corresponding to the interruption occurrence identifier after obtaining the interrupt processing information verification result;

[0033] The result determination module is used to determine the interrupt verification result of the processor to be verified based on the comparison result of the comparison process and the interrupt processing information verification result.

[0034] Thirdly, this application also provides a computer device. The computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to perform the following steps:

[0035] The first log information and the second log information are compared; the first log information is used to characterize the log information generated after executing the instruction stream through the processor to be verified; the second log information is used to characterize the log information generated after executing the instruction stream through the preset reference model corresponding to the processor to be verified.

[0036] During the comparison process, if an interruption flag is detected from the first log information, the comparison process is paused, and the interrupt handling information executed by the processor to be verified is verified.

[0037] If the interrupt handling information verification result is obtained, the comparison process is resumed according to the interrupt breakpoint information corresponding to the interruption occurrence identifier.

[0038] Based on the comparison results of the comparison process and the interrupt processing information verification results, the interrupt verification result of the processor to be verified is determined.

[0039] Fourthly, this application also provides a chip, including a processor and a communication interface, wherein the processor is configured to cause the chip to perform:

[0040] The first log information and the second log information are compared; the first log information is used to characterize the log information generated after executing the instruction stream through the processor to be verified; the second log information is used to characterize the log information generated after executing the instruction stream through the preset reference model corresponding to the processor to be verified.

[0041] During the comparison process, if an interruption flag is detected from the first log information, the comparison process is paused, and the interrupt handling information executed by the processor to be verified is verified.

[0042] If the interrupt handling information verification result is obtained, the comparison process is resumed according to the interrupt breakpoint information corresponding to the interruption occurrence identifier.

[0043] Based on the comparison results of the comparison process and the interrupt processing information verification results, the interrupt verification result of the processor to be verified is determined.

[0044] Fifthly, this application also provides a chip module, including a communication module, a power module, a storage module, and a chip, wherein:

[0045] The power module is used to provide power to the chip module;

[0046] The storage module is used to store data and instructions;

[0047] The communication module is used for internal communication within the chip module, or for communication between the chip module and external devices.

[0048] The chip is used to perform the steps of the method provided in the first aspect above.

[0049] Sixthly, this application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program thereon, which, when executed by a processor, performs the following steps:

[0050] The first log information and the second log information are compared; the first log information is used to characterize the log information generated after executing the instruction stream through the processor to be verified; the second log information is used to characterize the log information generated after executing the instruction stream through the preset reference model corresponding to the processor to be verified.

[0051] During the comparison process, if an interruption flag is detected from the first log information, the comparison process is paused, and the interrupt handling information executed by the processor to be verified is verified.

[0052] If the interrupt handling information verification result is obtained, the comparison process is resumed according to the interrupt breakpoint information corresponding to the interruption occurrence identifier.

[0053] Based on the comparison results of the comparison process and the interrupt processing information verification results, the interrupt verification result of the processor to be verified is determined.

[0054] Seventhly, this application also provides a computer program product. The computer program product includes a computer program that, when executed by a processor, performs the following steps:

[0055] The first log information and the second log information are compared; the first log information is used to characterize the log information generated after executing the instruction stream through the processor to be verified; the second log information is used to characterize the log information generated after executing the instruction stream through the preset reference model corresponding to the processor to be verified.

[0056] During the comparison process, if an interruption flag is detected from the first log information, the comparison process is paused, and the interrupt handling information executed by the processor to be verified is verified.

[0057] If the interrupt handling information verification result is obtained, the comparison process is resumed according to the interrupt breakpoint information corresponding to the interruption occurrence identifier.

[0058] Based on the comparison results of the comparison process and the interrupt processing information verification results, the interrupt verification result of the processor to be verified is determined.

[0059] The aforementioned interrupt verification methods, devices, computer equipment, chips, chip modules, computer-readable storage media, and computer program products, by comparing the first log information and the second log information, can verify the correctness of the instruction stream executed by the processor under test during the non-interrupt phase, which is beneficial for discovering execution differences between the processor under test and the preset reference model. By pausing the comparison process when an interruption flag is detected and performing independent verification processing on the interrupt handling information executed by the processor under test, it is beneficial for avoiding comparison errors caused by the preset reference model's inability to perceive the interruption occurrence time. By resuming the comparison process based on the interrupt breakpoint information, it is beneficial for accurately continuing the comparison from the breakpoint position after the interrupt handling is completed, thereby ensuring the continuity and integrity of the comparison process. By comprehensively comparing the comparison results and the interrupt handling information verification results to determine the interrupt verification result, it is beneficial for comprehensively covering the verification requirements of each stage before the interrupt occurs, during the interrupt handling process, and after the interrupt return, thereby improving the accuracy of interrupt verification. Attached Figure Description

[0060] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0061] Figure 1 This is a flowchart illustrating the interrupt verification method in one embodiment;

[0062] Figure 2 This is a schematic diagram of the architecture of an interrupt verification system in one embodiment;

[0063] Figure 3 This is a flowchart illustrating the interrupt verification method in another embodiment;

[0064] Figure 4 This is a structural block diagram of an interrupt verification device in one embodiment;

[0065] Figure 5 This is an internal structural diagram of a computer device in one embodiment;

[0066] Figure 6 This is an internal structure diagram of a chip module in one embodiment. Detailed Implementation

[0067] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0068] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0069] In one exemplary embodiment, such as Figure 1As shown, an interrupt verification method is provided. This embodiment illustrates the application of this method to a chip. It is understood that this method can also be applied to a terminal or server, and further to a system including both a terminal and a server, implemented through interaction between the terminal and the server. The terminal can be, but is not limited to, various personal computers, laptops, smartphones, tablets, etc.; the server can be a standalone physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing cloud computing services. In this embodiment, the method includes the following steps:

[0070] Step S101: Compare the first log information and the second log information; the first log information is used to characterize the log information generated after executing the instruction stream through the processor to be verified; the second log information is used to characterize the log information generated after executing the instruction stream through the preset reference model corresponding to the processor to be verified.

[0071] Step S102: During the comparison process, if an interruption flag is detected from the first log information, the comparison process is paused, and the interrupt handling information executed by the processor to be verified is verified.

[0072] Step S103: After obtaining the interrupt handling information verification result, resume the comparison process according to the interrupt breakpoint information corresponding to the interrupt occurrence identifier.

[0073] Step S104: Determine the interrupt verification result of the processor to be verified based on the comparison result of the comparison process and the interrupt processing information verification result.

[0074] The first log information may be a runtime trajectory log generated after the instruction stream is executed by the processor to be verified. The first log information may include information such as program counter value, opcode, and register value during instruction execution.

[0075] The second log information can be a simulation log generated after executing the same instruction stream through a preset reference model. This second log information is used as a comparison benchmark to verify whether the execution result of the processor to be verified is correct.

[0076] The comparison process can involve comparing and analyzing the first log information and the second log information instruction by instruction to determine whether the result of each instruction executed by the processor to be verified is consistent with the execution result of the preset reference model.

[0077] The processor to be verified can be a processor that requires interrupt functionality verification and has a scalable microarchitecture design.

[0078] The instruction stream can be a test program generated by a random instruction generator, which is compiled and loaded into the processor to be verified for execution.

[0079] The preset reference model can be a software simulation model used to generate standard execution results. This preset reference model executes the same instruction flow as the processor to be verified and generates second log information for comparison.

[0080] The interruption identifier can be a marker in the first log information used to indicate the occurrence of an interruption event. This interruption identifier is used to trigger a pause operation in the comparison process.

[0081] The pause comparison process can be implemented by stopping the comparison of each instruction in the first and second log information after an interruption flag is detected, in order to avoid inconsistencies caused by the interruption process.

[0082] The interrupt handling information can be related information generated by the processor to be verified during the execution of the interrupt service routine. This interrupt handling information includes interrupt number, interrupt priority, and other information.

[0083] The verification process can be an operation that verifies the correctness of the interrupt handling information executed by the processor to be verified. This verification process ensures the correctness of the interrupt service routine execution through a pre-set self-verification program.

[0084] The interrupt handling information verification result can be a verification conclusion obtained after verifying the interrupt handling information. This interrupt handling information verification result is used to indicate whether the interrupt service routine is executed correctly.

[0085] The interrupt breakpoint information can be the breakpoint location information recorded when the interrupt occurs. This interrupt breakpoint information includes the program counter value when the interrupt occurs, which is used to restore the starting position of the comparison process after the interrupt handling is completed.

[0086] The recovery comparison process can be performed after the interruption process is completed and the verification is passed, by restarting the comparison of each instruction in the first log information and the second log information according to the interruption breakpoint information.

[0087] The comparison result can be a comparison conclusion obtained after comparing the first log information and the second log information. The comparison result is used to indicate whether the processor to be verified executes correctly in the non-interrupt phase.

[0088] The interrupt verification result can be the final verification conclusion determined by combining the comparison results and the interrupt handling information verification results. This interrupt verification result is used to indicate whether the interrupt function of the processor to be verified is correctly implemented.

[0089] Optionally, the chip compares the first log information and the second log information. The first log information is generated after the instruction stream is executed by the processor to be verified, and the second log information is generated after the instruction stream is executed by the preset reference model corresponding to the processor to be verified. During the comparison process, the instruction execution results in the first log information and the second log information are compared line by line. If an interruption flag is detected in the first log information, the comparison process is paused, and the interrupt breakpoint information corresponding to the interruption flag is obtained. The interrupt handling information executed by the processor to be verified is verified, and the interrupt handling information includes the interrupt number and interrupt priority. If the interrupt handling information verification result is obtained, the position for resuming the comparison is determined according to the interrupt breakpoint information, and the comparison process is resumed. Based on the comparison result and the interrupt handling information verification result, the interrupt verification result of the processor to be verified is determined. If both the comparison result and the interrupt handling information verification result are passed, the interrupt verification result is determined to be verified successfully.

[0090] For example, the chip compares the first log information obtained after executing the instruction stream generated by the random instruction generator through the processor under test with the second log information obtained after executing the same instruction stream through a preset reference model, instruction by instruction. During the comparison process, it monitors whether there is an interrupt occurrence flag in the first log information. If an interrupt occurrence flag is detected, it captures the interrupt breakpoint information corresponding to the interrupt occurrence flag. The interrupt breakpoint information includes the program counter value and the interrupt cause register value at the time of the interrupt. The comparison process is paused, and the interrupt handling information executed by the processor under test is verified. The verification of the interrupt handling information includes verification of the interrupt number and the interrupt priority. The correctness of the interrupt service routine execution is also verified by executing a pre-set self-verification program. After obtaining the interrupt handling information verification result, the position for resuming the comparison process after the interrupt return is determined according to the program counter value in the interrupt breakpoint information. After the processor to be verified executes the interrupt return instruction, the comparison process of the first log information and the second log information is resumed at the position corresponding to the program counter value. Based on the comparison result of the comparison process and the interrupt handling information verification result, the interrupt verification result of the processor to be verified is determined. If the comparison result indicates that all instructions in the non-interrupt phase are executed correctly, and the interrupt handling information verification result indicates that the interrupt service routine is executed correctly, the interrupt verification result is determined to be verified as passed.

[0091] In the above-described interrupt verification method, by comparing the first log information and the second log information, the correctness of the instruction flow executed by the processor under test during the non-interrupt phase can be verified, which is beneficial for discovering the execution differences between the processor under test and the preset reference model. By pausing the comparison process when an interruption flag is detected and performing independent verification processing on the interrupt handling information executed by the processor under test, it is beneficial to avoid comparison errors caused by the preset reference model's inability to perceive the interruption occurrence time. By resuming the comparison process based on the interrupt breakpoint information, it is beneficial to accurately continue the comparison from the breakpoint position after the interrupt handling is completed, thereby ensuring the continuity and integrity of the comparison process. By comprehensively comparing the comparison results and the interrupt handling information verification results to determine the interrupt verification result, it is beneficial to comprehensively cover the verification requirements of each stage before the interrupt occurs, during the interrupt handling process, and after the interrupt return, thereby improving the accuracy of interrupt verification.

[0092] In an exemplary embodiment, the comparison process is resumed based on the interruption breakpoint information corresponding to the interruption occurrence identifier, including: determining the comparison recovery position of the comparison process based on the interruption breakpoint information; and resuming the comparison process based on the comparison recovery position.

[0093] The comparison recovery position can be the instruction position used to resume the comparison process, which is determined based on the interrupt breakpoint information. This comparison recovery position corresponds to the instruction address pointed to by the program counter value when the interrupt occurred.

[0094] Optionally, after obtaining the interrupt handling information verification result, the chip determines the comparison recovery position of the comparison processing based on the interrupt breakpoint information. The interrupt breakpoint information includes the program counter value saved when the interrupt occurred. The chip reads the program counter value in the interrupt breakpoint information, determines the instruction address corresponding to the program counter value as the comparison recovery position, and after the processor to be verified executes the interrupt return instruction, the chip resumes the comparison processing of the first log information and the second log information at the instruction corresponding to the comparison recovery position.

[0095] For example, the chip obtains the program counter value stored in the interrupt breakpoint information. This program counter value indicates the address of the instruction being executed by the processor to be verified when the interrupt occurred. The program counter value is converted into a comparison recovery position. After the processor to be verified completes the execution of the interrupt service routine and executes the interrupt return instruction, the chip locates the instruction entry corresponding to the comparison recovery position in the first log information and locates the instruction entry corresponding to the same instruction address in the second log information. Starting from the comparison recovery position, the chip continues to compare the first log information and the second log information instruction by instruction until the instruction stream is completed or the interruption flag is detected again.

[0096] The technical solution provided in this embodiment determines the comparison recovery position of the comparison process based on the interruption breakpoint information, which helps to accurately locate the instruction position for continuing the comparison. By resuming the comparison process based on the comparison recovery position, it helps to ensure the continuity and integrity of the comparison process, thereby improving the accuracy of interrupted verification.

[0097] In an exemplary embodiment, the interrupt handling information executed by the processor to be verified is verified, including: verifying the interrupt attribute information in the interrupt handling information to obtain a first verification result; performing self-verification on the interrupt handling information based on preset verification information to obtain a second verification result; and determining the interrupt handling information verification result based on the first verification result and the second verification result.

[0098] Interrupt attribute information can be attribute data that describes the characteristics of an interrupt event, including interrupt identification information and interrupt priority information.

[0099] The first verification result can be a verification conclusion obtained after verifying the interrupt attribute information in the interrupt handling information. The first verification result is used to indicate whether the interrupt attribute information meets the expected configuration.

[0100] The preset verification information can be pre-set verification data used to verify the correctness of the interrupt service routine execution. This preset verification information can be generated by a matrix unique solution program.

[0101] The self-verification process can be a process of independently verifying interrupt handling information based on preset verification information. This self-verification process is used to ensure the correctness of the interrupt service routine execution.

[0102] The second verification result can be a verification conclusion obtained after performing self-verification on the interrupt handling information. This second verification result is used to indicate whether the interrupt service routine is executed correctly.

[0103] The interrupt handling information verification result can be the final verification conclusion determined by combining the first verification result and the second verification result.

[0104] Optionally, after pausing the comparison process, the chip performs verification processing on the interrupt handling information executed by the processor to be verified, verifies the interrupt attribute information in the interrupt handling information, verifies whether the interrupt attribute information meets the expected configuration, and obtains a first verification result; based on preset verification information, the chip performs self-verification processing on the interrupt handling information, which can be generated by a pre-set program with a unique solution, and verifies the correctness of the interrupt service routine execution by executing the self-verification program, and obtains a second verification result; based on the first verification result and the second verification result, the chip determines the interrupt handling information verification result, and if both the first verification result and the second verification result are passed, the chip determines that the interrupt handling information verification result is passed.

[0105] The technical solution provided in this embodiment obtains a first verification result by verifying the interrupt attribute information, which is beneficial for verifying the correctness of the interrupt configuration. It obtains a second verification result by performing self-verification based on preset verification information, which is beneficial for verifying the correctness of the interrupt service routine execution. By combining the first and second verification results, the interrupt processing information verification result is determined, thereby improving the accuracy of interrupt verification.

[0106] In an exemplary embodiment, the interrupt attribute information includes interrupt identification information and interrupt priority information; the interrupt attribute information in the interrupt handling information is verified to obtain a first verification result, including: verifying the interrupt identification information to obtain a verification result of the interrupt identification information; verifying the interrupt priority information to obtain a verification result of the interrupt priority information; and determining the first verification result based on the verification results of the interrupt identification information and the interrupt priority information.

[0107] The interrupt identification information can be information used to uniquely identify an interrupt event. This interrupt identification information includes an interrupt number, which is stored in the interrupt cause register.

[0108] Interrupt priority information can be used to characterize the priority order of interrupt event processing, and different interrupt sources have different interrupt priority information.

[0109] The verification result of the interruption identification information can be a verification conclusion obtained after verifying the interruption identification information. The verification result of the interruption identification information is used to indicate whether the interruption identification information is consistent with the expected interruption number.

[0110] The verification result of the interrupt priority information can be a verification conclusion obtained after verifying the interrupt priority information. The verification result of the interrupt priority information is used to indicate whether the interrupt priority information is consistent with the expected priority configuration.

[0111] Optionally, the chip extracts interrupt attribute information from the interrupt handling information. The interrupt attribute information includes interrupt identifier information and interrupt priority information. The interrupt identifier information is verified by comparing the interrupt number in the interrupt identifier information with the expected configured interrupt number to obtain the verification result of the interrupt identifier information. The interrupt priority information is also verified by comparing the priority value in the interrupt priority information with the expected configured priority value to obtain the verification result of the interrupt priority information. Based on the verification results of the interrupt identifier information and the interrupt priority information, a first verification result is determined. If both the verification results of the interrupt identifier information and the interrupt priority information are passed, the first verification result is determined to be passed.

[0112] For example, the chip reads the interrupt identifier information from the interrupt cause register. The interrupt identifier information is the interrupt number. The read interrupt number is compared with the expected interrupt number to be triggered in the interrupt configuration. If they match, the interrupt identifier information verification result is determined to be passed; if they do not match, the interrupt identifier information verification result is determined to be failed. The chip then obtains the interrupt priority information and compares it with the priority threshold and priority order set in the interrupt configuration to verify whether the currently responding interrupt is a pending interrupt of the preset priority. If the verification passes, the interrupt priority information verification result is determined to be passed; if the verification fails, the interrupt priority information verification result is determined to be failed. The chip then determines whether the interrupt identifier information verification result is passed and whether the interrupt priority information verification result is passed. If both verification results are passed, the first verification result is determined to be passed; if either verification result fails, the first verification result is determined to be failed.

[0113] The technical solution provided in this embodiment obtains the verification result of the interrupt identifier information by performing verification processing on the interrupt identifier information, which is beneficial to verifying the correctness of the interrupt identifier information. It also obtains the verification result of the interrupt priority information by performing verification processing on the interrupt priority information, which is beneficial to verifying the correctness of the interrupt priority. By combining the verification results of the interrupt identifier information and the verification results of the interrupt priority information, the first verification result is determined, thereby improving the accuracy of interrupt attribute verification.

[0114] In an exemplary embodiment, before comparing the first log information and the second log information, the method further includes: obtaining an instruction stream generated by an instruction generator; compiling the instruction stream to obtain an executable file; executing the executable file through a processor to be verified to generate the first log information; and executing the executable file through a preset reference model to generate the second log information.

[0115] The instruction generator can be a tool for randomly generating test instruction streams. This instruction generator can generate assemblers containing various instruction types and combinations.

[0116] The compilation process can be the process of converting an instruction stream into an executable file format, and the compilation process can convert an assembly program into an executable linker file.

[0117] The executable file to be executed can be an executable file obtained after compilation, which can be loaded into the processor to be verified and the preset reference model for execution.

[0118] Optionally, before comparing the first log information and the second log information, the chip obtains an instruction stream generated by an instruction generator, wherein the instruction generator randomly generates an assembly program containing various instruction types as the instruction stream; the instruction stream is compiled to convert the instruction stream from assembly format to executable link format to obtain an executable file; the executable file is executed by the processor to be verified, and during the execution of the executable file by the processor to be verified, information such as the program counter value, opcode, and register value after each instruction is executed is recorded to generate the first log information; the executable file is executed by a preset reference model, and during the execution of the executable file by the preset reference model, the corresponding instruction execution information is recorded to generate the second log information.

[0119] The technical solution provided in this embodiment obtains the instruction stream generated by the instruction generator, compiles and processes the instruction stream to obtain the executable file, which is beneficial to obtaining a unified format file that can be executed by both the processor to be verified and the preset reference model. By executing the executable file respectively, first log information and second log information are generated, which is beneficial to provide a data foundation for subsequent comparison processing.

[0120] In an exemplary embodiment, the comparison processing of the first log information and the second log information includes: obtaining the instruction execution order; and performing instruction-by-instruction comparison processing on the first log information and the second log information according to the instruction execution order.

[0121] The instruction execution order can be the order in which each instruction in the instruction stream is executed.

[0122] The instruction-by-instruction comparison process can be a method that compares the corresponding instruction entries in the first log information and the second log information one by one according to the order of instruction execution.

[0123] Optionally, when the chip compares the first log information and the second log information, it first obtains the instruction execution order, which is determined based on the sequence of changes in the program counter value recorded in the first log information and the second log information. According to the instruction execution order, the chip performs instruction-by-instruction comparison processing on the first log information and the second log information. For each instruction, the chip compares whether the program counter value, opcode, and register value corresponding to the instruction in the first log information are consistent with the information corresponding to the same instruction in the second log information.

[0124] The technical solution provided in this embodiment compares the first log information and the second log information instruction by instruction according to the instruction execution order, which helps to accurately locate the execution differences between the processor to be verified and the preset reference model, thereby improving the accuracy of interrupt verification and the efficiency of problem location.

[0125] The following example illustrates the interrupt verification method provided in this application. This example demonstrates the application of this method to a chip.

[0126] This embodiment can be applied to the interrupt verification method of processors based on the RISC-V (Reduced Instruction Set Computer - Fifth Generation) architecture, and can efficiently achieve the convergence of interrupt verification.

[0127] The technical problem this embodiment aims to solve is that interrupt verification in RISC-V architecture often faces challenges due to the customizability and modular extensibility of the RISC-V microarchitecture. Existing open-source or commercial reference models often fail to meet the requirements, necessitating significant time for verification personnel to adapt the reference model. This allows for instruction-by-instruction verification, but due to the uncertainty of interrupt events, the model is unaware of which instruction caused the interruption, making comparison with the model impossible after an interruption occurs. Unless a mechanism is developed that enables the model to detect the instruction at which the interruption occurred, comparison with the model is impossible after an interruption. This interrupt verification method employs a technique that allows interrupt verification and comparison with the model without requiring model adaptation, achieving faster interrupt verification convergence.

[0128] This embodiment includes: a verification scheme for dynamic switch checking (verification) before and after an interrupt; when checking with the model while it is off, that is, when entering the interrupt handler, a self-check is performed to finally achieve the dynamic switch checking scheme; and the correct dynamic switch timing is obtained.

[0129] Existing and traditional interrupt verification schemes mainly involve modifying the reference model to adapt to the microarchitecture. When an interrupt occurs, both the reference model and the DUT (processor under test) are aware of the interrupt, thus enabling instruction-by-instruction verification even before and after the interrupt occurs.

[0130] Figure 2 The diagram illustrates the overall architecture of the interrupt verification system, including the following components and processes: The ISG (Instruction Sequence Generator) generates an assembler; this is compiled into an ELF (Executable Linkable Format) file by gcc (the compiler); the VIP (Verification Interface Protocol Component) embeds a memory model; the DUT (Processor Under Test) executes the instructions; the Interrupt_cfg (Interrupt Configuration) component performs Backdoor_operate (backdoor operation / backdoor configuration operation), and the Interrupt_cfg information includes the Random_type_int generator, which is applied to the DUT via a force method; the Sva (System Assertion) component monitors signals; the Int_deal check (Interrupt Handling Check) module interacts with the interrupt handler and sv check (Supervisory Check) under a custom protocol; and the RTL trace log (Register Transfer Level Trace Log) and the Iss sim log (Instruction Set Simulator Simulation Log) undergo dynamic comparison, followed by comparative analysis via a post-processing script.

[0131] Figure 2Detailed Explanation: First, the ISG (random instruction generator) generates assembly program test interrupts; second, after being compiled into an ELF (executable linker format) file by gcc (compiler), the file is loaded into the VIP (verification interface protocol component), which embeds a MEM model (memory model); third, through UVM (unified verification methodology), an interrupt UVM_Agent (unified verification methodology agent component) is built, which can randomly generate interrupt stimuli and apply them to the DUT (processor under test) through a force method. Based on the custom and microarchitecture implementation of the RISC-V architecture, it can randomly generate various interrupt source combinations, interrupt priorities, interrupt thresholds, edge responses, level responses, and other random configurations. Due to the limitations of model and microarchitecture adaptation, functions not implemented in the model are implemented directly on the DUT (processor under test) through a force method instead of through assembly instructions; fourth, upon completion of each instruction, an RTL trace log (register transfer level trace log) is exported. The model reads the ELF (executable linker format) file generated by the ISG (random instruction generator) and converts it into a more easily processed ISS SIM through a script. Fifth, compare the RTL trace log (instruction set simulator simulation log) and the ISS sim log (instruction set simulator simulation log) instruction by instruction. If there are any inconsistencies, the simulation will report an error. Sixth, there is also a check in the UVM (Unified Verification Methodology) environment that performs interrupt handling. This check is performed by interrupt handling assembly and SV check (supervisory check) under a custom protocol to satisfy the handshake relationship and thus ensure that the check passes.

[0132] Figure 3The detailed process of interrupt verification is illustrated in the diagram, which includes the following steps and content: The Isg random instruction stream is executed in the DUT, and each instruction is compared with the model; when an interrupt occurs, information such as PC (Program Counter), Opcode, and Reg=value is displayed. The PC includes addresses such as 0x80000000, 0x80000004, and 0x80000008; the Opcode includes contents such as 00004281, 7a029073, and 7a0023f3; and the register information includes X5=00000000, X7=00000000; when an interrupt occurs, "Happened a" is displayed. interrupt: mepc=0x80000008 (Interrupt occurred: exception program counter equals 0x80000008); The interrupt handling process includes disabling interrupts, saving breakpoints, addressing interrupt service routines, saving the context, executing interrupt service routines, restoring the context, and returning to mepc (exception program counter); During interrupt handling, the interrupt number and interrupt priority are compared, and the interrupt service routine's self_check is performed using a unique solution; The entire process includes comparing the instruction by (to) the instruction with the model, interrupt generation, interrupt handling, and interrupt return, and disabling the comparison with the model when the interrupt occurs.

[0133] Figure 3 Detailed explanation: First, the execution of the random instruction stream from the Isg (random instruction generator) in the RTL (Register Transfer Level) and the execution in the model are compared. When an interrupt occurs, the RTL trace log monitor monitors the RTL information, obtains the keyword "happen a interrupt," and prints the MEPC (Exception Program Counter) and Mcause (Interrupt Cause Register) at the time of the interrupt. Second, when the script performs the comparison, if it recognizes the keyword "happen a interrupt," captures the MEPC and Mcause, it closes the script comparison at this moment. After the interrupt handling returns, the comparison is performed again at the position of the MEPC. Third, during the period when the script closes the comparison, a pre-defined matrix unique solution program is used to ensure the correctness of the interrupt service routine execution. The interrupt service routine will also compare the interrupt number and interrupt priority.

[0134] The technical solution provided in this embodiment, from a chip perspective, is applied to interrupt verification of the RISC-V processor architecture, and can efficiently perform interrupt verification convergence and verification completeness.

[0135] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0136] Based on the same inventive concept, this application also provides an interrupt verification device for implementing the interrupt verification method described above. This device can be applied to or integrated into a chip or chip module, for example. The solution provided by this device is similar to the implementation scheme described in the above method; therefore, the specific limitations in one or more interrupt verification device embodiments provided below can be found in the limitations of the interrupt verification method above, and will not be repeated here.

[0137] In one exemplary embodiment, such as Figure 4 As shown, an interrupt verification device 400 is provided, which may include:

[0138] The information comparison module 401 is used to compare the first log information and the second log information; the first log information is used to characterize the log information generated after executing the instruction stream through the processor to be verified; the second log information is used to characterize the log information generated after executing the instruction stream through the preset reference model corresponding to the processor to be verified.

[0139] The information verification module 402 is used to pause the comparison process and verify the interrupt handling information executed by the processor to be verified when an interruption flag is detected from the first log information during the comparison process.

[0140] The processing recovery module 403 is used to recover the comparison processing based on the interrupt breakpoint information corresponding to the interruption occurrence identifier after obtaining the interrupt processing information verification result.

[0141] The result determination module 404 is used to determine the interrupt verification result of the processor to be verified based on the comparison result of the comparison process and the verification result of the interrupt processing information.

[0142] In an exemplary embodiment, the processing recovery module 403 is further configured to determine the comparison recovery position of the comparison processing based on the interruption breakpoint information; and to resume the comparison processing based on the comparison recovery position.

[0143] In an exemplary embodiment, the information verification module 402 is further configured to perform verification processing on the interrupt attribute information in the interrupt processing information to obtain a first verification result; perform self-verification processing on the interrupt processing information based on preset verification information to obtain a second verification result; and determine the interrupt processing information verification result based on the first verification result and the second verification result.

[0144] In an exemplary embodiment, the interrupt attribute information includes interrupt identification information and interrupt priority information; the information verification module 402 is further configured to perform verification processing on the interrupt identification information to obtain the verification result of the interrupt identification information; perform verification processing on the interrupt priority information to obtain the verification result of the interrupt priority information; and determine the first verification result based on the verification result of the interrupt identification information and the verification result of the interrupt priority information.

[0145] In an exemplary embodiment, the device 400 further includes: an information generation module, configured to acquire an instruction stream generated by an instruction generator; compile the instruction stream to obtain an executable file; execute the executable file through a processor to be verified to generate first log information; and execute the executable file through a preset reference model to generate second log information.

[0146] In an exemplary embodiment, the information comparison module 401 is further configured to obtain the instruction execution order; and to perform instruction-by-instruction comparison processing on the first log information and the second log information according to the instruction execution order.

[0147] Each module in the aforementioned interrupt verification device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the operations corresponding to each module.

[0148] Regarding the modules / units included in the various devices and products described in the above embodiments, they can be software modules / units, hardware modules / units, or a combination of both. For example, for various devices and products applied to or integrated into a chip, all of their modules / units can be implemented using hardware methods such as circuits, or at least some modules / units can be implemented using software programs that run on a processor integrated within the chip, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits; for various devices and products applied to or integrated into a chip module, all of their modules / units can be implemented using hardware methods such as circuits, and different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components of the chip module, or at least some modules / units can be implemented using hardware methods such as circuits. The components can be implemented using software programs that run on the processor integrated within the chip module. The remaining (if any) modules / units can be implemented using hardware methods such as circuits. For various devices and products applied to or integrated into the terminal, each of its components / units can be implemented using hardware methods such as circuits. Different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or in different components within the terminal. Alternatively, at least some modules / units can be implemented using software programs that run on the processor integrated within the terminal, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits.

[0149] In one exemplary embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 5As shown, the computer device includes a processor, memory, input / output interfaces, a communication interface, a display unit, and an input device. The processor, memory, and input / output interfaces are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interfaces. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The input / output interfaces are used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, NFC (Near Field Communication), or other technologies. When the computer program is executed by the processor, it implements an interrupt verification method. The display unit is used to form a visually visible image and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the computer device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the computer device, or external keyboards, touchpads, or mice, etc.

[0150] Those skilled in the art will understand that Figure 5 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0151] In one exemplary embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above-described method embodiments.

[0152] In one exemplary embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above-described method embodiments.

[0153] In one exemplary embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above-described method embodiments.

[0154] Based on the same inventive concept, this application also provides a chip, including a processor coupled to a memory, for executing a computer program or instructions stored in the memory, and implementing the steps in the above method embodiments when the processor executes the computer program or instructions.

[0155] It is understood that the chip involved in the embodiments of this application may be a field-programmable gate array (FPGA), may be an application-specific integrated circuit (ASIC), may be a system on chip (SoC), may be a central processor unit (CPU), may be a network processor (NP), may be a digital signal processor (DSP), may be a microcontroller unit (MCU), may be a programmable logic device (PLD) or other integrated chips, etc.

[0156] Based on the same inventive concept, this application also provides a chip module, such as... Figure 6 As shown, the chip module includes a communication module, a power module, a storage module, and a chip. Among them:

[0157] The power module is used to provide power to the chip module; the storage module is used to store data and instructions; the communication module is used for internal communication within the chip module, or for communication between the chip module and external devices; this chip corresponds to the chip in the above chip embodiment.

[0158] The implementation method of this chip module can be found in the relevant content of the above chip embodiment, and will not be repeated here.

[0159] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0160] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0161] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. An interruption verification method, characterized in that, The method includes: The first log information and the second log information are compared; the first log information is used to characterize the log information generated after executing the instruction stream through the processor to be verified; the second log information is used to characterize the log information generated after executing the instruction stream through the preset reference model corresponding to the processor to be verified. During the comparison process, if an interruption flag is detected from the first log information, the comparison process is paused, and the interrupt handling information executed by the processor to be verified is verified. If the interrupt handling information verification result is obtained, the comparison process is resumed according to the interrupt breakpoint information corresponding to the interruption occurrence identifier. Based on the comparison results of the comparison process and the interrupt processing information verification results, the interrupt verification result of the processor to be verified is determined.

2. The method according to claim 1, characterized in that, The step of resuming the comparison process based on the interrupt breakpoint information corresponding to the interruption occurrence identifier includes: Based on the interruption point information, determine the alignment recovery position of the alignment process; The comparison process is resumed based on the comparison recovery position.

3. The method according to claim 1, characterized in that, The verification process for the interrupt handling information executed by the processor to be verified includes: The interrupt attribute information in the interrupt handling information is verified to obtain a first verification result; Based on preset verification information, the interrupt handling information is self-verified to obtain a second verification result; The interrupt handling information verification result is determined based on the first verification result and the second verification result.

4. The method according to claim 3, characterized in that, The interrupt attribute information includes interrupt identification information and interrupt priority information; The step of verifying the interrupt attribute information in the interrupt handling information to obtain a first verification result includes: The interrupt identifier information is verified to obtain the verification result of the interrupt identifier information; The interrupt priority information is verified to obtain the verification result of the interrupt priority information; The first verification result is determined based on the verification results of the interrupt identifier information and the interrupt priority information.

5. The method according to claim 1, characterized in that, Before comparing the first and second log information, the process also includes: Obtain the instruction stream generated by the instruction generator; The instruction stream is compiled to obtain the executable file; The processor to be verified executes the executable file to generate the first log information, and the preset reference model executes the executable file to generate the second log information.

6. The method according to any one of claims 1 to 5, characterized in that, The comparison process between the first log information and the second log information includes: Obtain the instruction execution order; According to the execution order of the instructions, the first log information and the second log information are compared instruction by instruction.

7. An interrupt verification device, characterized in that, The device includes: The information comparison module is used to compare and process the first log information and the second log information; the first log information is used to characterize the log information generated after executing the instruction stream through the processor to be verified; the second log information is used to characterize the log information generated after executing the instruction stream through the preset reference model corresponding to the processor to be verified. The information verification module is used to pause the comparison process and verify the interrupt handling information executed by the processor to be verified when an interruption identifier is detected from the first log information during the comparison process. The processing recovery module is used to recover the comparison process based on the interrupt breakpoint information corresponding to the interruption occurrence identifier after obtaining the interrupt processing information verification result; The result determination module is used to determine the interrupt verification result of the processor to be verified based on the comparison result of the comparison process and the interrupt processing information verification result.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 6.

9. A chip, characterized in that, The device includes a processor and a communication interface, wherein the processor is configured to cause the chip to perform the steps of the method described in any one of claims 1 to 6.

10. A chip module, characterized in that, This includes communication modules, power modules, storage modules, and chips, among which: The power module is used to provide power to the chip module; The storage module is used to store data and instructions; The communication module is used for internal communication within the chip module, or for communication between the chip module and external devices. The chip is used to perform the steps of the method according to any one of claims 1 to 6.

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