Testing device, testing method, and program

Abstract

Provided is a test device comprising: a reception unit that receives a reception signal sequence including a pseudo-random signal sequence of a T value (where T is an integer of 2 or more) output by a device under test; a decoding unit that decodes the pseudo-random signal sequence of the T value in the reception signal sequence into a decoded signal sequence of a C value (where C is an integer of 2 or more and is different from T); and a detection unit that detects that a pseudo-random signal generator that has generated the pseudo-random signal sequence of the T value in the reception signal sequence is in a prohibited state, in accordance with a proportion of a predetermined signal value in the decoded signal sequence being outside a reference range.

Description

Test Device, Test Method, and Program

[0001] The present invention relates to a test device, a test method, and a program.

[0002] In the test of a device under test, the quality of the device under test may be determined according to whether the pseudo-random signal sequence output from the device under test matches an expected value signal sequence. [Prior Art Documents] [Patent Documents] [Patent Document 1] International Publication No. 2004 / 081786 General Disclosure

[0003] In a first aspect of the present invention, a receiving unit that receives a received signal sequence including a pseudo-random signal sequence of T values (where T is an integer of 2 or more) output by a device under test, a decoding unit that decodes the pseudo-random signal sequence of T values in the received signal sequence into a decoded signal sequence of C values (where C is an integer of 2 or more and different from T), and a detection unit that detects that the pseudo-random signal generator that generated the pseudo-random signal sequence of T values in the received signal sequence was in a prohibited state when a ratio of predetermined signal values in the decoded signal sequence was outside a reference range are provided.

[0004] In the above test device, T may be an integer of 3 or more, and C may be an integer of 2 or more and less than T.

[0005] In the above test device, the decoding unit may decode each signal value of the T value of the pseudo-random signal sequence of T values into signal values of 2 or more C values.

[0006] In any of the above test devices, C may be 2, and T may be a power of 2.

[0007] In any of the above test devices, the decoding unit may decode each signal value of the T value of the pseudo-random signal sequence of T values into signal values of 2 or more C values that are Gray-coded.

[0008] In any of the above test apparatuses, the device under test generates a pseudo-random signal sequence of C values ​​and encodes it into T values ​​to generate a pseudo-random signal sequence of T values, and the test apparatus may include an expected value generation unit that generates an expected value signal sequence that includes a pseudo-random signal sequence of C values ​​identical to the pseudo-random signal sequence of C values ​​generated by the device under test.

[0009] In any of the above-described test devices, the detection unit may determine that the predetermined ratio of signal values ​​in the decoded signal sequence is outside the reference range if the ratio of predetermined signal values ​​in the pseudo-random signal sequence of C values ​​included in the expected value signal sequence is outside the reference range.

[0010] Any of the above test devices may include a comparison unit that compares a decoded signal sequence with a pseudo-random signal sequence of C values ​​within the expected value signal sequence.

[0011] Any of the above-described test devices may include a result determination unit that determines the test result based on the comparison result from the comparison unit and the detection result from the detection unit.

[0012] Any of the above test devices may include a setting unit that uses a portion of the decoded signal sequence to set a random seed for the pseudo-random signal sequence of C values ​​in the expected value signal sequence generated by the expected value generation unit.

[0013] In any of the above test apparatuses, the device under test generates a pseudo-random signal sequence of C values ​​and decodes it into T values ​​to generate a pseudo-random signal sequence of T values, and the detection unit may change the reference range according to the number of digits in the shift register of the pseudo-random signal generator that generated the pseudo-random signal sequence of C values.

[0014] A second aspect of the present invention provides a test method comprising: receiving a received signal sequence containing a pseudo-random signal sequence of T values ​​(where T is an integer of 3 or more) output by a device under test; decoding the pseudo-random signal sequence of T values ​​in the received signal sequence into a decoded signal sequence of C values ​​(where C is an integer of 2 or more and less than T); and detecting that the pseudo-random signal generator that generated the pseudo-random signal sequence of T values ​​in the received signal sequence was in a prohibited state when the ratio of predetermined signal values ​​in the decoded signal sequence falls outside a reference range.

[0015] In a third aspect of the present invention, a program is provided which is executed by a computer and causes the computer to function as a receiving unit that receives a received signal sequence including a pseudo-random signal sequence of T values ​​(where T is an integer of 3 or more) output by the device under test; a decoding unit that decodes the pseudo-random signal sequence of T values ​​in the received signal sequence into a decoded signal sequence of C values ​​(where C is an integer of 2 or more and less than T); and a detection unit that detects that the pseudo-random signal generator that generated the pseudo-random signal sequence of T values ​​in the received signal sequence was in a prohibited state when the ratio of predetermined signal values ​​in the decoded signal sequence falls outside a reference range.

[0016] It should be noted that the above summary of the invention does not enumerate all of its features. Furthermore, subcombinations of these features may also constitute an invention.

[0017] The configuration of the test apparatus 100 according to this embodiment is shown together with the DUT 10. An example of the configuration of the setting unit 120 and the expected value generation unit 130 according to this embodiment is shown. An example of the configuration of the encoding unit 35 according to this embodiment is shown. An example of the configuration of the decoding unit 115 according to this embodiment is shown. An example of the configuration of the detection unit 150 according to this embodiment is shown. An example of the reference range according to this embodiment is shown. A test flow using the test apparatus 100 according to this embodiment is shown. An example of a computer 2200 in which multiple embodiments of the present invention may be embodied whole or in part is shown.

[0018] The present invention will be described below through embodiments, but these embodiments are not intended to limit the scope of the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0019] Figure 1 shows the configuration of the test apparatus 100 according to this embodiment, together with the DUT 10 (Device Under Test 10, also referred to as "device under test 10"). The DUT 10 includes a transmitter 20. The transmitter 20 outputs a signal generated inside the DUT 10 to another device, etc., via wired or wireless connection. In this embodiment, the transmitter 20 outputs a signal having multiple signal values ​​to the outside of the DUT 10 in each cycle. In this disclosure, the transmitter 20 is described as outputting a signal having a signal value of T (where T is an integer of 3 or more). The transmitting unit 20 may output a multi-level signal using pulse amplitude modulation (PAM), pulse width modulation (PWM), phase shift keying (PSK), frequency shift keying (FSK), amplitude shift keying (Amplitude Shift Keying), quadrature phase amplitude modulation (QAM), OFDM (Orthogonal Frequency Division Multiplexing), or any other arbitrary encoding or modulation scheme.

[0020] The DUT 10 may include a pseudo-random signal generator 30 and an encoding unit 35. The pseudo-random signal generator 30 may generate a pseudo-random signal sequence of C value (where C is an integer between 2 and N) used to generate a pseudo-random signal sequence of T value to be included in the signal that the transmitting unit 20 outputs to the outside of the DUT 10 during testing of the DUT 10. For example, the pseudo-random signal generator 30 may be a PRBS generator that generates a pseudo-random signal sequence such as PRBS (Pseudo Random Binary Sequence), and supplies the generated pseudo-random signal sequence to the encoding unit 35.

[0021] The encoding unit 35 is connected to the pseudo-random signal generator 30. The encoding unit 35 generates a pseudo-random signal sequence of T values ​​by encoding the pseudo-random signal sequence of C values ​​generated by the pseudo-random signal generator 30 into T values. In this embodiment, the case where T=4 and C=2 is described as an example. Alternatively, the DUT 10 and the test device 100 may use any integer of 3 or more as T, and any integer of 2 or more and less than T as C.

[0022] In addition to the transmitting unit 20, the pseudo-random signal generator 30, and the encoding unit 35, the DUT 10 may also include a receiving unit for receiving signals from an external source, a processing unit for performing calculations or signal processing according to the received signals and the internal state of the DUT 10, or various other circuits. In this specification, we focus on a configuration in which the DUT 10 is tested by the test device 100 inspecting the signals output by the DUT 10, so the components other than the transmitting unit 20, the pseudo-random signal generator 30, and the encoding unit 35 are not shown or described.

[0023] Depending on the test content or the type of DUT 10, the pseudo-random signal generator 30 may be located outside the DUT 10. In this case, the encoding unit 35 inside the DUT 10 converts the pseudo-random signal sequence with C values ​​input from the pseudo-random signal generator 30 outside the DUT 10 into a pseudo-random signal sequence with T values ​​and supplies it to the transmitting unit 20. In addition to the pseudo-random signal generator 30, the encoding unit 35 may also be located outside the DUT 10. In this case, the transmitting unit 20 inside the DUT 10 receives the pseudo-random signal sequence with T values ​​input from the encoding unit 35 outside the DUT 10 and transmits it outside the DUT 10.

[0024] The test device 100 is connected to the DUT 10 and tests the DUT 10. The test device 100 includes a receiving unit 110, a decoding unit 115, a setting unit 120, an expected value generation unit 130, a comparison unit 140, a detection unit 150, a result determination unit 160, and a control unit 170.

[0025] The receiving unit 110 is connected to the DUT 10 so as to be able to receive signals transmitted from the transmitting unit 20. The receiving unit 110 receives a received signal sequence that includes a pseudo-random signal sequence of T values ​​output by the DUT 10. Here, "signal sequence" means a sequence of signal values ​​for multiple cycles, with one signal value for each cycle (or signal period). "T-value signal sequence" means a sequence of signal values ​​for multiple cycles, with one T-value signal value (i.e., one T-value symbol) for each cycle (or signal period). "T-value signal value" means a signal value that takes one of T types of values ​​(i.e., 0, 1, ..., T-1), or in other words, a signal value that corresponds to one digit of a base T number. For example, a four-value signal value takes one of the values ​​0, 1, 2, or 3. In this disclosure, in order to indicate that a signal value is a T-value (or base T number), the common notation "1 ４ Sometimes, a subscript indicating the base number of the signal value is added after the signal value, such as "(Signal value 1 in a 4-level signal)".

[0026] The DUT 10 may output a pseudo-random signal sequence of T values ​​directly from its terminal (antenna in the case of a wireless connection). In this case, the receiving unit 110 receives the pseudo-random signal sequence of T values ​​output by the DUT 10 as the received signal sequence. Alternatively, the DUT 10 may output a signal sequence such as a packet containing a pseudo-random signal sequence of T values ​​in a specific field, such as the data portion, from its terminal or the like. In this case, the receiving unit 110 receives a signal sequence such as a packet containing a pseudo-random signal sequence of T values ​​output by the DUT 10 in a specific field as the received signal sequence.

[0027] The decoding unit 115 is connected to the receiving unit 110. The decoding unit 115 converts (decodes) the pseudo-random signal sequence of T values ​​in the received signal sequence into a decoded signal sequence of C values ​​(where C is an integer greater than or equal to 2 and less than T). As a result, the decoding unit 115 can supply the pseudo-random signal sequence of C values ​​output by the pseudo-random signal generator 30, before encoding by the encoding unit 35, to the setting unit 120, the comparison unit 140, and the detection unit 150 as a decoded signal sequence.

[0028] The setting unit 120 is connected to the decoding unit 115. The setting unit 120 sets a random seed for the pseudo-random signal sequence of C values ​​for the expected value generation unit 130, which is capable of generating an expected value signal sequence that includes the same pseudo-random signal sequence of C values ​​as the pseudo-random signal sequence of C values ​​used to generate the pseudo-random signal sequence of T values ​​included in the received signal sequence. The setting unit 120 may use a portion of the decoded signal sequence decoded by the decoding unit 115 to set a random seed for the pseudo-random signal sequence of C values ​​in the expected value signal sequence generated by the expected value generation unit 130.

[0029] The expected value generation unit 130 is connected to the setting unit 120. The expected value generation unit 130 uses a random seed of the pseudo-random signal sequence of C values ​​set by the setting unit 120 to generate an expected value signal sequence that includes the same pseudo-random signal sequence of C values ​​as the pseudo-random signal sequence of T values ​​that the DUT 10 should output. If the signal sequence output by the DUT 10 is a packet or the like that includes fields other than the pseudo-random signal sequence of T values, the expected value generation unit 130 may generate the expected value signal sequence by adding fields such as a packet header to the pseudo-random signal sequence of C values, depending on the format of the signal sequence output by the transmission unit 20.

[0030] The comparison unit 140 is connected to the decoding unit 115 and the expected value generation unit 130. The comparison unit 140 compares the received signal sequence and the expected value signal sequence. The comparison unit 140 may compare the decoded signal sequence of C values ​​obtained by decoding the pseudo-random signal sequence of T values ​​in the received signal sequence with the pseudo-random signal sequence of C values ​​in the expected value signal sequence.

[0031] The detection unit 150 is connected to the decoding unit 115. It detects whether the pseudo-random signal generator 30, which was used to generate a pseudo-random signal sequence of T values ​​in the received signal sequence, was in a prohibited state. Here, a pseudo-random signal generator like the pseudo-random signal generator 30 normally outputs a pseudo-random signal sequence in which the signal value changes randomly (or changes in a way that can be considered random) each cycle. However, if the internal state of the pseudo-random signal generator becomes a special state, it will always output the same value and will not be able to output a pseudo-random signal sequence. This state in which the pseudo-random signal generator is unable to output a pseudo-random signal sequence is referred to as a "prohibited state". In this embodiment, the detection unit 150 detects whether the pseudo-random signal generator 30 was in a prohibited state using the decoded signal sequence of C values ​​decoded by the decoding unit 115.

[0032] The result determination unit 160 is connected to the comparison unit 140 and the detection unit 150. The result determination unit 160 determines the test result based on the comparison result from the comparison unit 140 and the detection result from the detection unit 150.

[0033] The control unit 170 is connected to various parts of the test apparatus 100. The control unit 170 may be a computer such as a PC (personal computer), workstation, server computer, or general-purpose computer, or it may be a computer system in which multiple computers are connected. Such a computer system is also a computer in a broad sense. The control unit 170 may also be implemented by a virtual computer environment that can run one or more times within the computer. Alternatively, the control unit 170 may be a dedicated computer designed for the test apparatus 100, or it may be dedicated hardware realized by dedicated circuits.

[0034] The control unit 170 controls the DUT 10 test by controlling each part of the test apparatus 100 (receiving unit 110, ..., result determination unit 160, etc.). The control unit 170 may execute a test program created by an engineer for testing the DUT 10 and control each part of the DUT 10 according to the contents described in the test program, thereby controlling the DUT 10 test in accordance with the contents described in the test program.

[0035] According to the test apparatus 100 of this embodiment, the internal circuits of the DUT 10, including the transmitter 20, can be tested by comparing the output signal sequence, which includes a pseudo-random signal sequence of T values ​​output from the DUT 10, with the expected value signal sequence. The test apparatus 100 decodes the pseudo-random signal sequence of T values ​​included in the output signal sequence into a decoded signal sequence of C values ​​and compares it with the pseudo-random signal sequence of C values ​​included in the expected value signal sequence. Here, since the expected value generation unit 130 is set with a random number seed using the decoded C value sequence obtained by decoding the pseudo-random signal sequence of T values ​​included in the received signal sequence, if the pseudo-random signal generator 30 is disabled, the pseudo-random signal generator in the expected value generation unit 130 will also be disabled. In this case, both the decoded C value sequence obtained by decoding the pseudo-random signal sequence of T values ​​included in the received signal and the pseudo-random signal sequence of C values ​​included in the expected value signal sequence will always be the same fixed value, and it will be judged that the received signal sequence and the expected value signal sequence match.

[0036] According to the test apparatus 100 of this embodiment, by detecting whether or not the pseudo-random signal generator 30 was in a disabled state using the detection unit 150, even if the comparison unit 140 determines that the received signal sequence and the expected value signal sequence match, it is possible to determine whether there is an abnormality in the DUT 10 itself, an abnormality in the connection between the DUT 10 and the test apparatus 100, or an abnormality in other tests, depending on whether the pseudo-random signal generator 30 was in a disabled state.

[0037] Figure 2 shows an example of the configuration of the setting unit 120 and the expected value generation unit 130 according to this embodiment. The expected value generation unit 130 has a pseudo-random signal generator that includes a shift register composed of a plurality of flip-flops (D-FFs, etc.) or latches connected in cascades, and a circuit that includes one or more exclusive OR (XOR) elements and calculates the outputs of two or more D-FFs and feeds them back to the first stage D-FF of the shift register. The expected value generation unit 130 in this figure has an N-bit shift register, and the N stages of flip-flops included in the shift register take values ​​from B[N-1] to B[0] (also indicated as B[N-1:0]) in order from downstream. The downstream flip-flop of the shift register outputs the signal value B[N-1] as the next signal value in the pseudo-random signal sequence for each clock cycle.

[0038] A feedback circuit containing multiple exclusive OR (XOR) operators calculates the next value to input to the shift register based on the value B[N-1:0] output by two or more D-FFs. The calculation formula of the feedback circuit is predetermined so that the signal sequence output by the expected value generation unit 130 can be considered as a pseudo-random number.

[0039] Such a pseudo-random signal generator outputs the signal values ​​stored in multiple D-FFs of the shift register sequentially from downstream for each clock cycle, while simultaneously replenishing the first-stage D-FF with the next signal value generated by the feedback circuit. If the received signal sequence includes fields other than the pseudo-random signal sequence, the pseudo-random signal generator 30 and the pseudo-random signal generator in the expected value generation unit 130 may stop the clock input and stop generating pseudo-random numbers during the transmission period of such fields, or they may continue the clock input during the transmission period of such fields and advance the generation of pseudo-random numbers for the same clock cycle.

[0040] If the received signal sequence may include fields other than the pseudo-random signal sequence, the expectation value generation unit 130 may further have other expectation value generation circuits that output the expected values ​​of the signal values ​​that should be included in such fields. The expectation value generation unit 130 may generate an expectation value signal sequence from a pseudo-random signal generator for fields in the received signal sequence that include the pseudo-random signal sequence, and generate an expectation value signal sequence from other expectation value generation circuits for other fields in the received signal sequence.

[0041] Furthermore, the pseudo-random signal generator in the expected value generation unit 130 and the pseudo-random signal generator 30 may be designed or configured to use the same number of stages and the same feedback circuit. The test apparatus 100 may be made capable of changing or switching the number of stages of the pseudo-random signal generator and the configuration of the feedback circuit provided in the expected value generation unit 130 in order to be able to test various types of DUT 10.

[0042] The pseudo-random signal generator illustrated in Figure 2 outputs a pseudo-random signal sequence, i.e., a pseudo-random binary signal sequence (PRBS), where each signal value is either 0 or 1 (binary, C=2). Alternatively, the DUT 10 and the test apparatus 100 may use a pseudo-random signal generator that outputs a pseudo-random signal sequence where each signal value is multi-level (C>2). The multi-level pseudo-random signal generator may output the binary signal values ​​output by the binary pseudo-random signal generator as a set of multiple cycles, representing one digit of the multi-level signal value. Alternatively, the multi-level pseudo-random signal generator may have a shift register with memory elements for storing multi-level one-digit signal values ​​connected in cascades, and a circuit that calculates at least two-digit signal values ​​and feeds them back as the signal value of the first stage of the shift register, outputting a multi-level one-digit signal value from the downstream side of the shift register for each cycle.

[0043] The setting unit 120 has a selector 210 that switches whether to supply the output of the feedback circuit of the pseudo-random signal generator or the decoded signal decoded by the decoding unit 115 to the first stage D-FF of the pseudo-random signal generator in the expected value generation unit 130. In this embodiment, the setting unit 120 switches whether to supply the output of the feedback circuit or the decoded signal to the first stage D-FF according to the setting instruction signal from the control unit 170. The setting unit 120 can set a random number seed for the pseudo-random signal sequence of C values ​​in the pseudo-random signal generator in the expected value generation unit 130 by supplying the decoded signal sequence for the number of stages of the D-FF. Subsequently, the setting unit 120 can output a pseudo-random signal sequence of C values ​​using the set random number seed as the initial value by supplying the output of the feedback circuit of the expected value generation unit 130 to the first stage D-FF.

[0044] According to the expected value generation unit 130 described above, the feedback circuit generates a pseudo-random value as the next 1-bit signal value from the signal values ​​of the most recent N bits stored in the shift register in the pseudo-random signal sequence of C values, and feeds it back to the first-stage D-FF. Here, if the feedback circuit is implemented by combining exclusive OR (XOR) as illustrated in this figure, then 0 XOR 0 = 0, so if all of B[N-1:0] are 0, the signal value 0 will be fed back to the first-stage D-FF, and the pseudo-random signal generator will always output 0. Therefore, such a pseudo-random signal generator is in a prohibited state where it does not generate a random signal sequence when all bits in the shift register are "0". Note that depending on the configuration of the feedback circuit in the expected value generation unit 130, the prohibited state may also be when all bits in the shift register are "1".

[0045] Figure 3 shows an example of the configuration of the encoding unit 35 according to this embodiment. The encoding unit 35 encodes a pseudo-random signal sequence of C values ​​generated by the pseudo-random signal generator 30 into a pseudo-random signal sequence of T values. The encoding unit 35 may convert a pseudo-random signal sequence of C values ​​into a pseudo-random signal sequence of T values ​​by encoding m C value signal values ​​into n T value signal values. Here, m and n are positive integers, and n may be 1 or 2 or greater. Since C < T, m > n may be the case.

[0046] The encoding unit 35 may convert two or more C-value signal values ​​into a single T-value signal value. When a PRBS generator is used as the pseudo-random signal generator 30, the encoding unit 35 may group the m binary signal values ​​generated by the PRBS generator together into two ｍ The values ​​may be converted into signal values. In the example shown in this figure, the encoding unit 35 converts the two binary signal values ​​into one 4 (=2 ２ The signal is converted to a quadrivalent value. As shown in the example in this figure, a pseudo-random signal sequence obtained by converting two consecutive binary signal values ​​in the PRBS output by a PRBS generator into a single quadrivalent signal value is known as QPRBS-CEI.

[0047] The encoding unit 35 according to this embodiment includes an FF310, a conversion circuit 320, a plurality of FFs 330a to d (also referred to as "FF330"), and a plurality of switches 340a to d (also referred to as "switch 340"). The FF310 is a storage element such as a flip-flop or a latch. The FF310 captures the signal value of the pseudo-random signal sequence of the C (= 2 in this figure, the same hereinafter) value output by the pseudo-random signal generator 30 input to the input terminal (D terminal) at the timing of clock 1 (for example, the rising timing), and outputs it from the output terminal (Q terminal). Here, clock 1 may be the same as the clock in FIG. 2. The FF310 functions as a delay element that delays the signal value of the binary pseudo-random signal sequence from the pseudo-random signal generator 30 by one cycle. Thereby, the pair of the current signal value Bb supplied from the pseudo-random signal generator 30 and the signal value Ba one cycle before latched by the FF310 becomes a pair of consecutive m (= 2) C (= 2) value signal values in the pseudo-random signal sequence of the C (= 2) value from the pseudo-random signal generator 30.

[0048] The conversion circuit 320 is connected to the pseudo-random signal generator 30 and the FF310. The conversion circuit 320 inputs a set of m (= 2) C (= 2) value signal values, and converts the input set of m C value signal values into n (= 1) T (= 4) value signal values and outputs them. The conversion circuit 320 shown in this figure regards a set of two 2-value signal values (Ba, Bb) as a 2-digit 2-value signal value, and converts it into a 4-value signal value. Specifically, the conversion circuit 320 converts (Ba, Bb) = (0 ２ , 0 ２ ) to 0 ４ , (0 ２ , 1 ２ ) to 1 ４ , (1 ２ , 0 ２ ) to 2 ４ , (1 ２ , 1 ２ ) to 3 ４ .

[0049] The conversion circuit 320 may perform the conversion between a set of C-value signal values ​​and a T-value signal value using other coding methods. For example, the conversion circuit 320 may perform the conversion between a set of C-value signal values ​​and a T-value signal value using Gray coding. When Gray coding is used in the conversion circuit 320, (0 ２ ,0 ２ ) to 0 ４ (0 ２ ,1 ２ ) to 1 ４ (1 ２ ,1 ２ ) to 2 ４ (1 ２ ,0 ２ ) to 3 ４ You may convert it to this.

[0050] The conversion circuit 320 shown in this figure outputs the signal value of T (=4) in a representation format using outputs Z0 to Z3. The conversion circuit 320 outputs the signal value 0 ４ (Z0, Z1, Z2, Z3) = (1, 0, 0, 0), signal value 1 ４ (Z0, Z1, Z2, Z3) = (0, 1, 0, 0), signal value 2 ４ (Z0, Z1, Z2, Z3) = (0, 0, 1, 0), signal value 3 ４ Output the result in the format (Z0, Z1, Z2, Z3) = (0, 0, 0, 1).

[0051] Multiple FF330a to d are memory elements such as flip-flops or latches, and are connected to the conversion circuit 320. Multiple FF330a to d are provided corresponding to the outputs Z0 to Z3 of the conversion circuit 320. Each of the multiple FF330a to d takes each of the multiple outputs Z0 to Z3 of the conversion circuit 320, which are input to the input terminal (D terminal), at the timing of clock 2 (for example, the rising edge timing), and outputs it from the output terminal (Q terminal). Here, clock 2 is a clock obtained by dividing clock 1 by m (=2). As a result, the encoding unit 35 can sequentially extract m consecutive C value signal values ​​from the pseudo-random signal sequence of C values ​​from the pseudo-random signal generator 30 and convert them into T value signal values.

[0052] Each of the multiple switches 340a to 340d is connected between each of the voltages V0 to V3 and the output terminal of the encoding unit 35. The multiple switches 340a to 340d are provided in correspondence with the multiple FF 330a to 330d. Each of the multiple switches 340a to 340d turns on when the output Zx (x = 0, 1, 2, or 3) from the corresponding FF 330 is 1, and supplies the corresponding voltage Vx to the output terminal of the encoding unit 35. Here, each of the multiple voltages V0 to V3 is a 4-value PAM signal (PAM-4 signal) with a signal value of 0 ４ , 1 ４ , 2 ４ , 3 ４ These are the voltage values ​​that should be present in each of them. As a result, the encoding unit 35 determines that the signal value of T (=4) is 0 ４ In this case, the voltage V0, 1 ４ In this case, voltage V1, 2 ４ In this case, voltage V2, 3 ４ In this case, voltage V3 can be output. For example, voltages V0 to V3 may have the relationship V3 > V2 > V1 > V0.

[0053] In this embodiment, the encoding unit 35 includes an FF 310, a conversion circuit 320, and a plurality of FF 330a to d that convert a pseudo-random signal sequence of C values ​​into a pseudo-random signal sequence of T values ​​represented by a logical representation using Z0 to Z3, and a plurality of switches 340a to d that convert a pseudo-random signal sequence of T values ​​represented by a logical representation into a pseudo-random signal sequence of T values ​​in an output signal format (PAM-4 signal format in this figure) that the DUT 10 outputs to the outside. Alternatively, the function of converting a pseudo-random signal sequence of T values ​​represented by a logical representation into an output signal format may be provided in the transmitting unit 20.

[0054] Figure 4 shows an example of the configuration of the decoding unit 115 according to this embodiment. The decoding unit 115 decodes the pseudo-random signal sequence of T values ​​in the received signal sequence received by the receiving unit 110 into a decoded signal sequence of C values. The conversion from the T-value signal sequence to the C-value signal sequence by the decoding unit 115 may correspond to the inverse conversion of the conversion from the C-value signal sequence to the T-value signal sequence by the encoding unit 35. The decoding unit 115 may convert the pseudo-random signal sequence of T values ​​into a pseudo-random signal sequence of C values ​​(decoded signal sequence) by decoding n T-value signal values ​​into m C-value signal values. Here, m and n are positive integers, and n may be 1 or 2 or greater. Since C < T, m > n may be the case.

[0055] The decoding unit 115 may decode each T-value signal of the pseudo-random signal sequence of T-values ​​into a C-value signal of 2 or more. In this embodiment, C is 2 and T is a power of 2. When a PRBS generator is used as the pseudo-random signal generator 30, the decoding unit 115 encodes the m 2 (=C)-value signal values ​​generated by the PRBS generator to obtain the 2 ｍ The receiving unit 110 receives a (=T) value signal and the PRBS generator may decode it into m 2 (=C) value signal values. In the example shown in the figure, the decoding unit 115 decodes the two binary signal values ​​into one 4 (=2 ２ In order to perform the inverse conversion of the encoding unit 35 that converts the signal value into a quaternary value, one quaternary signal value is converted into two binary signal values.

[0056] The decoding unit 115 according to this embodiment includes a plurality of comparators 410a to c (also referred to as "comparator 410"), a plurality of FFs 420a to c (also referred to as "FF420"), a conversion circuit 430, an FF 440, a NOT element 450, and a selector 460. Each of the plurality of comparators 410a to c has a positive terminal (+) connected to the receiving unit 110 and a negative terminal (-) connected to a plurality of threshold voltages VT1 to 3. The plurality of comparators 410 compare each signal value (signal voltage) of the pseudo-random signal sequence of T values ​​in the received signal sequence, which is input to the positive terminal, with the plurality of threshold voltages VT1 to 3. That is, comparator 410a compares the signal value of the pseudo-random signal sequence with the threshold voltage VT1 and outputs a logical value of 1 if the signal value is greater than or equal to the threshold voltage VT1, and a logical value of 0 if the signal value is less than the threshold voltage VT1 as the comparison result ZT1. Similarly, comparator 410b compares the signal value of the pseudo-random signal sequence with the threshold voltage VT2 and outputs a logical value of 1 if the signal value is greater than or equal to the threshold voltage VT2, and a logical value of 0 if the signal value is less than the threshold voltage VT2 as the comparison result ZT2. Comparator 410c compares the signal value of the pseudo-random signal sequence with the threshold voltage VT3 and outputs a logical value of 1 if the signal value is greater than or equal to the threshold voltage VT3, and a logical value of 0 if the signal value is less than the threshold voltage VT3 as the comparison result ZT3. Here, VT1 < VT2 < VT3, and the threshold voltage VT1 corresponds to a signal value of 0 ４ and 1 ４ The threshold voltage VT2, which is the voltage at the boundary, is the signal value 1 ４ and 2 ４ The threshold voltage VT3, which is the boundary voltage, is the signal value 2 ４ and 3 ４ This is the voltage that marks the boundary.

[0057] Multiple FF420a to c are memory elements such as flip-flops or latches. Multiple FF420a to c are provided in correspondence with multiple comparators 410a to c. Each of the multiple FF420a to c is connected to the corresponding comparator 410 among the multiple comparators 410a to c. Each of the multiple FF420a to c is input to the input terminal (D terminal), and the corresponding comparison result from the multiple comparison results ZT1 to ZT3 is acquired at the timing of clock 2, and is output from the output terminal (Q terminal) as each of the multiple comparison results ZD1 to ZT3. Here, clock 2 may be a sampling clock that samples the output signal from DUT 10, and is a clock with the same period as clock 2 in Figure 3.

[0058] The conversion circuit 430 is connected to multiple FF420a to c. The conversion circuit 430 takes n (=1) sets of T (=4) signal values ​​as input and converts the input n sets of T signal values ​​into m (=2) C (=2) signal values ​​and outputs them. The conversion circuit 430 shown in this figure uses (ZD3, ZD2, ZD1) = (0,0,0) as the T (=4) signal value. ４ , represented by (ZD3, ZD2, ZD1) = (0, 0, 1) ４ , represented by (ZD3, ZD2, ZD1) = (0, 1, 1) ４ , represented by (ZD3, ZD2, ZD1) = (1,1,1) ４ The input is used to decode m (=2) pairs of C (=2) signal values ​​(Ba, Bb) = (0 ２ ,0 ２ ), (0 ２ ,1 ２ ), (1 ２ ,0 ２ ), or (1 ２ ,1 ２ Output as ).

[0059] The decoding unit 115 may decode each T-value signal of the pseudo-random signal sequence of T-values ​​into two or more Gray-coded C-value signal values. When Gray coding is used, the conversion circuit 430 is 0 ４ to (0 ２ ,0 ２ ) to, 1４ to (0 ２ ,1 ２ ) to, 2 ４ (1 ２ ,1 ２ ) to, 3 ４ (1 ２ ,0 ２ You may convert it to ).

[0060] The FF440 and NOT element 450 invert the selection signal output to the selector 460 at each timing of clock 1. In the example shown in this figure, the NOT element 450 inverts the Q output of the FF440 and supplies it to the D input of the FF440. As a result, the FF440 latches the inverted value of the Q output at the timing of clock 1 and uses it as the Q output for the next cycle. Consequently, the FF440 outputs a selection signal to the selector 460 that changes from a logical value of 0, 1, 0, 1, ... at each timing of clock 1. Here, clock 1 may be a clock having twice the frequency of clock 2, and is a clock with the same period as clock 1 in Figure 3.

[0061] The selector 460 is connected to the conversion circuit 430 and the FF 440. The selector 460 switches which of the m C-value signal values ​​output by the conversion circuit 430 is output as the decoded signal, according to the selection signal input from the FF 440. In the example shown in this figure, the selector 460 outputs the signal value Ba as the decoded signal when the selection signal is a logical value of 0, and outputs the signal value Bb as the decoded signal when the selection signal is a logical value of 1. As a result, the decoding unit 115 can sequentially output each of the m C-value signal values ​​decoded from the T-value signal value in each cycle of clock 1.

[0062] Figure 5 shows an example of the configuration of the detection unit 150 according to this embodiment. The detection unit 150 detects whether or not the pseudo-random signal generator 30, which was used to generate a pseudo-random signal sequence of T values ​​in the received signal sequence, was in a prohibited state. In this embodiment, the detection unit 150 detects the prohibited state when the ratio of predetermined signal values ​​in the pseudo-random signal sequence of C values ​​(decoded signal sequence) obtained by decoding the pseudo-random signal sequence of T values ​​in the received signal sequence falls outside the reference range.

[0063] In this embodiment, the pseudo-random signal generator 30 and the pseudo-random signal generator within the expected value generation unit 130 are configured such that the bit values ​​of all bits included in the shift register (i.e., all bit values ​​from B[N-1] to B[0]) are 0. ２ In this case, the system enters a forbidden state and outputs a signal sequence with a signal value of always 0. Conversely, if the decoded signal sequence of the C value obtained by decoding the pseudo-random signal sequence of the T value in the received signal sequence is a suitable signal sequence, then the signal value 1, which is a signal value that does not occur in the forbidden state, is output. ２ The ratio is approximately 50%. Therefore, the detection unit 150 detects the signal value 1 in the pseudo-random signal sequence within the received signal sequence. ２ For example, if the ratio falls below 40% (i.e., it does not meet the standard range of 40% or more), or if the signal value is 0, which is a signal value that is always generated in a prohibited state. ２ The prohibition state may be detected when the ratio exceeds, for example, 60% (i.e., it does not meet the standard range of 60% or less).

[0064] The detection unit 150 according to this embodiment includes a counter 510, a counter 520, and a forbidden state determination unit 530. The counter 510 is connected to the decode unit 115. The counter 510 receives a decoded signal obtained by decoding the received signal and a clock signal with a cycle corresponding to each signal value of the decoded signal, and counts the number of predetermined signal values ​​(for example, "1") included in the decoded signal sequence. Here, the clock signal used by the detection unit 150 may have the same frequency as clock 1 in Figure 4, or may be identical to clock 1 in Figure 4.

[0065] Counter 520 receives a clock signal and counts the number of clock cycles. Counters 510 and 520 may receive a measurement enable signal from the control unit 170 or other trigger circuit, etc., instructing them to enable measurement during a period in which at least a portion of the pseudo-random signal sequence of T values ​​is included in the received signal sequence (also referred to as the "measurement period"), and may perform counting operations during the measurement period. In addition, counters 510 and 520 may be initialized to a count value of 0 or the like before the start of measurement.

[0066] The prohibited state determination unit 530 is connected to counters 510 and 520. The prohibited state determination unit 530 calculates the ratio of predetermined signal values ​​in the decoded signal sequence based on the number of predetermined signal values ​​included in the decoded signal sequence during the measurement period, which is counted by counter 510, and the total number of cycles (total number of clocks) during the measurement period, which is counted by counter 520. In the example shown in the figure, the prohibited state determination unit 530 calculates the ratio of predetermined signal values ​​(e.g., 1) by calculating the count of counter 510 / the count of counter 520. The prohibited state determination unit 530 determines whether the calculated ratio is outside the reference range (e.g., less than 40%). The prohibited state determination unit 530 then outputs a detection result indicating that the system is in a prohibited state, depending on whether the calculated ratio is outside the reference range.

[0067] As described above, the detection unit 150 can detect whether or not the pseudo-random signal generator 30, which was used to generate the pseudo-random signal sequence of T values ​​in the received signal sequence, was in a prohibited state, using the received signal sequence. The pseudo-random signal generator in the expected value generation unit 130 has the same circuit configuration as the pseudo-random signal generator 30, and generates the same pseudo-random signal sequence as the pseudo-random signal generator 30 by receiving a random number seed setting from at least a part of the pseudo-random signal sequence of C values ​​obtained by decoding the pseudo-random signal sequence of T values ​​included in the received signal sequence. Therefore, instead of directly detecting whether or not the pseudo-random signal generator 30 that generated the pseudo-random signal sequence of C values ​​used to generate the pseudo-random signal sequence of T values ​​included in the received signal sequence was in a prohibited state, or in addition to that, the detection unit 150 may determine that the ratio of predetermined signal values ​​in the decoded signal sequence is outside the reference range when the ratio of predetermined signal values ​​in the pseudo-random signal sequence of C values ​​included in the expected value signal sequence is outside the reference range, and detect that the pseudo-random signal generator 30 was in a prohibited state. In this embodiment, instead of counting the number of times the decoded signal sequence was a predetermined signal value, the counter 510 in the detection unit 150 may count the number of times the expected value signal of the C value output by the expected value generation unit 130 was a predetermined signal value.

[0068] The detection unit 150 may be implemented as a hardware circuit, or it may be implemented by executing a program on various types of computers. The detection unit 150 can be implemented in a wide variety of ways other than the configuration shown in this figure.

[0069] For example, instead of counting a signal value that does not occur in the prohibited state (e.g., signal value 1) as a predetermined signal value, the counter 510 may count a signal value that always occurs in the prohibited state (e.g., signal value 0). The detection unit 150 may have a counter that counts signal value 1 that does not occur in the prohibited state and a counter that counts signal value 0 that always occurs in the prohibited state. The detection unit 150 does not need to have a counter 520 if the number of cycles of the measurement period is known in advance.

[0070] Furthermore, the test device 100 may capture the received signal sequence or decoded signal sequence using a capture circuit and store it in a capture memory or the like provided inside the test device 100 or outside the main body of the test device 100. If the received signal sequence is stored in the capture memory or the like, the decoding unit 115 may read the received signal sequence stored in the capture memory or the like through computer program processing and convert it into a decoded signal sequence. The detection unit 150 may input the decoded signal sequence stored in the capture memory or the decoded signal sequence output by the decoding unit 115 through computer program processing and calculate a predetermined ratio of signal values.

[0071] The detection unit 150 may also be implemented as a forbidden state determination circuit added to the pseudo-random signal generator in the expected value generation unit 130. Such a forbidden state determination circuit may detect a forbidden state when all bits of the shift register included in the pseudo-random signal generator in the expected value generation unit 130 are 0.

[0072] In the case where C > 2, the detection unit 150 may calculate the ratio of two or more or all of the C-type signal values ​​that the decoded signal can take. In this case, the detection unit 150 may output a detection result indicating a prohibited state if at least one of the ratios calculated for two or more signal values ​​falls outside the reference range.

[0073] Figure 6 shows an example of the reference range according to this embodiment. In a C (=2) value pseudo-random signal generator in which the state where all bits of the shift register are 0 is a forbidden state, the ratio of signal values ​​1 can change depending on the number of digits or bits of the shift register. For example, if the shift register is 2 bits, there can be four possible values ​​for the shift register B[1:0]: 0b00, 0b01, 0b10, and 0b11. Note that "0b" indicates that the following number is represented in binary. Here, B[1:0] = 0b00 is a forbidden state, so a 2-bit pseudo-random signal generator will go through three states (0b01, 0b10, and 0b11) during one cycle of internal states. ２ For each of the states (-1), a random signal value is generated. The number of times such a signal value is 1 (a signal value that is not generated in the forbidden state) is 2 ２ / 2 = 2 times. Therefore, the ratio of signal 1 generated by the 2-bit pseudo-random signal generator is 66.7%.

[0074] In the case of an N-bit pseudo-random signal generator, excluding the forbidden state (2 Ｎ For each of the states in -1), random signal values ​​are generated, and of these, the number of times the signal value is 1 is 2. Ｎ / 2 times. Therefore, the ratio of signal values ​​1 in the pseudorandom signal sequence generated by an N-bit pseudorandom signal generator is (2 Ｎ / 2) / (2 Ｎ -1)

[0075] If the pseudo-random signal generator 30 is an N-bit pseudo-random signal generator, the pseudo-random signal sequence is 2 Ｎ -1 bit completes one cycle, and thereafter the same 2 Ｎ-1 bit is repeated as a sequence. The expected value generation unit 130 uses the first or middle N bits of the pseudo-random signal sequence of the C value, which is decoded from the received pseudo-random signal sequence of the T value, as a random seed to generate the expected value of the pseudo-random signal of the C value that is decoded from the pseudo-random signal of the T value that is received thereafter. In this case, the pseudo-random signal sequence of the C value converted from the received signal sequence and the pseudo-random signal sequence of the C value included in the expected value signal sequence may be longer than N bits.

[0076] Furthermore, the pseudo-random signal sequence of C values ​​does not necessarily have to be the number of bits required for the internal state of the pseudo-random signal generator 30 to complete one cycle (i.e., (2 Ｎ -1) The length does not have to be greater than or equal to 1 bit. In this case, the detection unit 150 receives a portion of the pseudo-random signal sequence for one cycle as a decoded signal sequence and detects whether the pseudo-random signal generator 30 was in a disabled state. Here, the ratio of signal values ​​1 within a portion of the pseudo-random signal sequence for one cycle may differ to some extent from the ratio of signal values ​​1 in the entire pseudo-random signal sequence for one cycle. Also, depending on the structure of the test apparatus 100, it may not be possible to accurately trigger the start and end of the measurement period of the detection unit 150 for periods in which the received signal sequence contains pseudo-random signal sequences with T values. In this case, the detection unit 150 may receive signal values ​​obtained by converting the signal values ​​of fields other than the pseudo-random signal sequences with T values ​​in the received signal sequence to C values ​​at the beginning or end of the measurement period.

[0077] Therefore, the detection unit 150 may determine that the pseudo-random signal generator for C values ​​is in a prohibited state if, within the measurement period of the pseudo-random signal sequence of C values ​​(=2) generated by the N-bit pseudo-random signal generator, the ratio of predetermined signal values ​​(e.g., signal value 1) falls outside a reference range that has a margin of ±10% or so relative to the ratio of predetermined signal values ​​(e.g., signal value 1) included in one cycle of the pseudo-random signal sequence of C values. When the state where all bits of the shift register are 0 is considered the prohibited state, the lower limit of the reference range that the ratio of signal value 1 must satisfy may be a value greater than 0%, (1 / (2 Ｎ-1)) may be a value greater than or equal to this. This allows the detection unit 150 to appropriately detect whether the pseudo-random signal generator was in a disabled state, even when the received signal sequence includes a pseudo-random signal sequence with a T value having a length of less than one cycle, and even when the measurement period of the detection unit 150 is slightly off.

[0078] Since the ratio of signal values ​​1 changes when the number of bits in the pseudo-random signal generator changes, the detection unit 150 may change the reference range according to the number of digits or bits in the shift register of the pseudo-random signal generator 30 that generated the pseudo-random signal sequence of C values ​​used to generate the pseudo-random signal sequence of T values ​​in the received signal sequence. For example, before the test is performed, the control unit 170 may set the number of digits or bits in the shift register of the expected value generation unit 130 to match the number of digits or bits in the pseudo-random signal generator 30 in the DUT 10 under test, and set the reference range in the detection unit 150 according to the number of digits or bits in the pseudo-random signal generator 30. As an example, the detection unit 150 may use a reference range that adds a positive or negative margin (for example, a ±10% margin) to the ratio of predetermined signal values ​​included in the pseudo-random signal sequence of C values ​​for one cycle, as shown in the figure. That is, for example, in the example shown in the figure, when an N-bit pseudo-random signal generator is used, the detection unit 150 may set (2 Ｎ / 2) / (2 Ｎ -1) A reference range of ±10% may be used.

[0079] Furthermore, an N-bit pseudo-random signal generator has a maximum length of 2 depending on the configuration of the feedback circuit. Ｎ - It is possible to generate a pseudo-random signal sequence with a C value that completes one cycle with fewer than -1 bits. However, the feedback circuit of a pseudo-random signal generator is usually determined so that the pseudo-random signal sequence completes one cycle with its maximum length. Therefore, the example in this figure shows the case in which the pseudo-random signal generator 30 generates a pseudo-random signal sequence with a C value that completes one cycle with its maximum length. Note that the feedback circuit of the pseudo-random signal generator 30 is 2 ＮIf it is possible to select a circuit that generates a pseudo-random signal sequence of C values ​​that cycles with fewer than -1 bits, the reference range shown in Figure 6 may be determined based on the ratio of signal values ​​1 in such a pseudo-random signal sequence of C values.

[0080] When the detection unit 150 counts signal values ​​that are always generated in the prohibited state (for example, signal value 0), the upper limit of the reference range may be a value less than 100%. For example, when using a 4-bit pseudo-random signal generator, the detection unit 150 may determine that the value is within the reference range when the ratio of signal values ​​0 is 56.7% (100% - 43.3%) or less.

[0081] The detection unit 150 may change the reference range according to the number of digits or bits of the shift register if it is below a threshold, and may fix the reference range if it exceeds the threshold. For example, if the number of digits or bits of the shift register is 4 or less, the detection unit 150 may set the reference range according to the number of digits or bits as shown in this figure, and if the number of digits or bits of the shift register exceeds 4, the reference range may be set to a fixed range such as 40% to 60%.

[0082] When the state in which all bits of the shift register are 0 is prohibited, the detection unit 150 does not need to limit the upper limit of the reference range in which the ratio of signal values ​​1 should be included. For example, if the shift register has 4 bits, the detection unit 150 may set the reference range in which the ratio of signal values ​​1 should be included to 43.3% or more (100% or less). Similarly, when the state in which all bits of the shift register are 1 is prohibited, the detection unit 150 does not need to limit the upper limit of the reference range in which the ratio of signal values ​​0 should be included.

[0083] The number of possible values ​​for the C value signal is smaller than the number of possible values ​​for the T value signal. The detection unit 150 can narrow down the population of signal values ​​to be inspected by detecting the prohibited state of the pseudo-random signal generator using the decoded C value signal sequence obtained by decoding the pseudo-random T value signal sequence in the received signal sequence. For example, when T=16 and C=4, there are 16 possible T value signal values, while there are 4 possible C value signal values. Therefore, the detection unit 150 can narrow down the population of signal values ​​to be inspected (i.e., the number of possible values ​​for the signal values ​​to be inspected) from 16 to 4 by inspecting the C value signal sequence obtained by decoding the T value signal.

[0084] When using a decoding unit 115 that performs the inverse conversion from the C-value signal value to the T-value signal value conversion by the encoding unit 35, the detection unit 150 can use a ratio determined according to the characteristics of the pseudo-random signal generator 30 as a reference range. The test device 100 or the user of the test device 100 may determine a reference range for the ratio of predetermined signal values ​​used by the detection unit 150 based on the ratio at which predetermined signal values ​​appear when the pseudo-random signal sequence generated by the pseudo-random signal generator 30 completes one cycle.

[0085] When C is 2, the pseudo-random signal generator 30 and the pseudo-random signal generator in the expected value generation unit 130 become PRBS generators. Therefore, the detection unit 150 can measure the ratio of both signal values ​​0 and 1 by counting either signal value 0 or 1. When C is 2, the ratio of signal values ​​0 and 1 generated by the PRBS generator can be theoretically calculated as shown in Figure 6, so the test apparatus 100 may determine the reference range using the method described in relation to this figure.

[0086] Figure 7 shows the test flow using the test apparatus 100 according to this embodiment. Prior to executing this test flow, the test apparatus 100 connects the DUT 10 to be tested and controls the DUT 10 to output an output signal sequence that includes a pseudo-random signal sequence of T values.

[0087] In step S700, the receiving unit 110 begins receiving a pseudo-random signal sequence of T values ​​included in the received signal sequence. In S705, the decoding unit 115 converts (decodes) the pseudo-random signal sequence of T values ​​in the received signal sequence into a decoded signal sequence of C values.

[0088] In S710, the setting unit 120 uses a portion of the decoded signal sequence (the leading portion or a portion near the leading portion, etc.) to set the random seed of the pseudo-random signal sequence of C values ​​in the pseudo-random signal generator in the expected value generation unit 130. As a result, the expected value generation unit 130 begins outputting an expected value signal sequence that includes the pseudo-random signal sequence of C values. In S720, the counters 510 and 520 in the detection unit 150 begin counting predetermined signal values ​​in the decoded signal sequence and counting the number of clock cycles in the measurement period.

[0089] In S730, the comparison unit 140 compares the received signal sequence and the expected value signal sequence. In this comparison, the comparison unit 140 compares the decoded signal sequence of C values ​​obtained by decoding the pseudo-random signal sequence of T values ​​in the received signal sequence with the pseudo-random signal sequence of C values ​​in the expected value signal sequence. If the received signal sequence and the expected value signal sequence do not match as a result of the comparison (YES in S740), the result determination unit 160 determines in S780 that the test was abnormal. Depending on the specifications of the test, the result determination unit 160 may use conditions for determining abnormality such as the received signal sequence and the expected value signal sequence not being a perfect match, or the number or ratio of mismatched signal values ​​between the received signal sequence and the expected value signal sequence exceeding a threshold. Such test abnormalities can occur due to a faulty DUT 10, a poor connection between the DUT 10 and the test device 100, a failure of the test device 100, etc. If the test apparatus 100 is functioning normally and the connection between the DUT 10 and the test apparatus 100 is deemed normal, the result determination unit 160 may determine that the DUT 10 is abnormal.

[0090] In S750, the detection unit 150 detects whether the pseudo-random signal generator 30, which was used to generate the pseudo-random signal sequence of T values ​​in the received signal sequence, was in a prohibited state. In this embodiment, the detection unit 150 detects a prohibited state (S760: YES) when the ratio of predetermined signal values ​​in the decoded signal sequence of C values ​​obtained by decoding the pseudo-random signal sequence of T values ​​in the received signal sequence falls outside the reference range, and proceeds to S780. As shown in relation to Figure 5, the detection unit 150 may also determine that the ratio of predetermined signal values ​​in the decoded signal sequence is outside the reference range when the ratio of predetermined signal values ​​in the pseudo-random signal sequence of C values ​​included in the expected value signal sequence falls outside the reference range. In S780, the result determination unit 160 determines that the test was abnormal as described above.

[0091] If the received signal sequence and the expected signal sequence match, and the pseudo-random signal generator 30 is not in a disabled state (i.e., the ratio of predetermined signal values ​​in the decoded signal sequence of the C value is within the reference range), the result determination unit 160 determines in S770 that the test was successful. In this case, the result determination unit 160 determines that the test result DUT 10 was successful.

[0092] According to the test apparatus 100 described above, the detection unit 150 can detect whether the pseudo-random signal generator 30 or the pseudo-random signal generator in the expected value generation unit 130 was in a disabled state. As a result, even if the comparison unit 140 determines that the received signal sequence and the expected value signal sequence match, the test apparatus 100 can determine whether there is an abnormality in the DUT 10 itself, an abnormality in the connection between the DUT 10 and the test apparatus 100, or an abnormality in the test, depending on whether the disabled state of the pseudo-random signal generator has been detected.

[0093] Furthermore, the detection unit 150 according to this embodiment can determine the prohibited state of the pseudo-random signal generator by inputting a decoded signal sequence of C values ​​or an expected value signal sequence obtained by decoding the pseudo-random signal sequence of T values ​​in the received signal sequence. Therefore, the detection unit 150 can be realized by inputting a decoded signal sequence of C values ​​obtained by decoding the pseudo-random signal sequence of T values ​​in the received signal sequence or an expected value signal sequence to a circuit provided separately from the IC, LSI, or FPGA including the expected value generation unit 130. Also, if the test device 100 is equipped with a capture circuit that captures a decoded signal sequence of C values ​​obtained by decoding the pseudo-random signal sequence of T values ​​in the received signal sequence, the detection unit 150 can analyze the captured decoded signal sequence after the test operation between the DUT 10 and the test device 100 has been completed and detect whether or not the pseudo-random signal generator was in a prohibited state. Such a detection unit 150 can also be implemented by a computer or the like, separate from the main body of the test apparatus 100, which is equipped with a receiving unit 110, a decoding unit 115, a setting unit 120, an expected value generation unit 130, and a comparison unit 140. A test system including a main body of the test apparatus equipped with a receiving unit 110, a decoding unit 115, a setting unit 120, an expected value generation unit 130, and a comparison unit 140, and a detection unit 150 (and a result determination unit 160 if necessary) implemented by a computer or the like connected to such a main body of the test apparatus via a network, can be considered as a single test apparatus.

[0094] Furthermore, in the test apparatus 100 according to another embodiment, the comparison unit 140 may adopt a configuration in which it compares each signal value of the T value in the pseudo-random signal sequence of T values ​​in the received signal sequence with each signal value of the T value in the pseudo-random signal sequence of T values ​​included in the expected value signal sequence. In such an embodiment, the expected value generation unit 130 generates an expected value signal sequence that includes a pseudo-random signal sequence of T values ​​by converting a pseudo-random signal sequence of C values ​​into a pseudo-random signal sequence of T values ​​using an encoding unit similar to the encoding unit 35. The comparison unit 140 receives the received signal sequence from the receiving unit 110 without going through the decoding unit 115 and compares the received signal sequence with the expected value signal sequence.

[0095] In other embodiments of the DUT 10 and test apparatus 100, the pseudo-random signal generator 30 and the expected value generation unit 130 may be configured to include two or more C-value pseudo-random signal generators internally. In this case, the encoding unit 35 in the DUT 10 may encode two or more C-value signal values ​​generated by the two or more pseudo-random signal generators into at least one T-value signal value. As an example, the DUT 10 may include two pseudo-random signal generators that generate binary pseudo-random signal sequences, and the binary signal value generated by one pseudo-random signal generator may be used as input Ba to the conversion circuit 320 shown in Figure 3, while the binary signal value generated by the other pseudo-random signal generator at the same timing or in the same cycle may be used as input Bb to the conversion circuit 320, thereby converting to a four-value signal value. The DUT 10 and test apparatus 100 may include m C-value pseudo-random signal generators. The encoding unit 35 may encode the m C-value signal values ​​generated by the m pseudo-random signal generators into n T-value signal values.

[0096] In this case, the detection unit 150 may detect that at least one of two or more (or m) pseudo-random signal generators was in a disabled state in response to the ratio of predetermined signal values ​​in the decoded signal sequence falling outside the reference range. The detection unit 150 may also determine whether the ratio of predetermined signal values ​​in the sequence of signal values ​​corresponding to each pseudo-random signal generator in the decoded signal sequence fell outside the reference range.

[0097] In the embodiments described above, T is an integer of 3 or more, and C is an integer of 2 or more and less than T. In other embodiments, T may be an integer of 2 or more, and C may be an integer of 2 or more and different from T. For example, T may be an integer of 2 or more, and C may be an integer greater than T. In this case, the pseudo-random signal generator 30 of the DUT 10 generates m signal values ​​of C, and the encoding unit 35 converts the m signal values ​​of C into n (n > m) signal values ​​of T. In such other embodiments as well, the decoding unit 115 in the test device 100 decodes the n signal values ​​of T into m signal values ​​of C, and the detection unit 150 can detect the prohibited state of the pseudo-random signal generator using the signal values ​​of C generated by the pseudo-random signal generator 30 in the DUT 10 or the pseudo-random signal generator in the expected value generation unit 130.

[0098] Various embodiments of the present invention may be described with reference to flowcharts and block diagrams, where a block may represent (1) a stage in a process in which an operation is performed, or (2) a section of a device having the role of performing the operation. Specific stages and sections may be implemented by dedicated circuits, programmable circuits supplied with computer-readable instructions stored on a computer-readable medium, and / or processors supplied with computer-readable instructions stored on a computer-readable medium. Dedicated circuits may include digital and / or analog hardware circuits, and may include integrated circuits (ICs) and / or discrete circuits. Programmable circuits may include reconfigurable hardware circuits, including logic AND, logic OR, logic XOR, logic NAND, logic NOR, and other logic operations, memory elements such as flip-flops, registers, field-programmable gate arrays (FPGAs), programmable logic arrays (PLAs), etc.

[0099] Computer-readable media may include any tangible device capable of storing instructions to be executed by a suitable device, and as a result, computer-readable media having instructions stored therein will comprise a product containing instructions that can be executed to create means for performing operations specified in a flowchart or block diagram. Examples of computer-readable media may include electronic storage media, magnetic storage media, optical storage media, electromagnetic storage media, semiconductor storage media, etc. More specific examples of computer-readable media may include floppy disks (registered trademark), diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), electrically erasable programmable read-only memory (EEPROM), static random access memory (SRAM), compact disk read-only memory (CD-ROM), digital versatile disk (DVD), Blu-ray (registered trademark) disk, memory stick, integrated circuit card, etc.

[0100] Computer-readable instructions may include assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk®, Java®, C++, and conventional procedural programming languages ​​such as the C programming language or similar programming languages.

[0101] Computer-readable instructions may be provided locally or via a wide area network (WAN) such as a local area network (LAN) or the Internet to the processor or programmable circuit of a programmable data processing device such as a general-purpose computer, a special-purpose computer, or another computer, and the computer-readable instructions may be executed to create means for performing operations specified in a flowchart or block diagram. Examples of processors include computer processors, processing units, microprocessors, digital signal processors, controllers, microcontrollers, etc.

[0102] Figure 8 shows an example of a computer 2200 in which multiple aspects of the present invention may be embodied in whole or in part. A program installed on the computer 2200 can cause the computer 2200 to function as an operation or one or more sections of an apparatus according to an embodiment of the present invention, or to execute such operation or one or more sections, and / or to cause the computer 2200 to execute a process or a stage of such process according to an embodiment of the present invention. Such a program may be executed by the CPU 2212 to cause the computer 2200 to perform a particular operation associated with some or all of the blocks in the flowcharts and block diagrams described herein.

[0103] The computer 2200 according to this embodiment includes a CPU 2212, RAM 2214, a graphics controller 2216, and a display device 2218, which are interconnected by a host controller 2210. The computer 2200 also includes input / output units such as a communication interface 2222, a hard disk drive 2224, a DVD-ROM drive 2226, and an IC card drive, which are connected to the host controller 2210 via an input / output controller 2220. The computer also includes legacy input / output units such as a ROM 2230 and a keyboard 2242, which are connected to the input / output controller 2220 via an input / output chip 2240.

[0104] The CPU 2212 operates according to programs stored in the ROM 2230 and RAM 2214, thereby controlling each unit. The graphics controller 2216 acquires image data generated by the CPU 2212 from a frame buffer provided in RAM 2214 or from itself, and displays the image data on the display device 2218.

[0105] The communication interface 2222 communicates with other electronic devices via a network. The hard disk drive 2224 stores programs and data used by the CPU 2212 in the computer 2200. The DVD-ROM drive 2226 reads programs or data from the DVD-ROM 2201 and provides them to the hard disk drive 2224 via the RAM 2214. The IC card drive reads programs and data from the IC card and / or writes programs and data to the IC card.

[0106] The ROM 2230 stores boot programs and / or programs that depend on the computer 2200's hardware, which are executed by the computer 2200 when activated. The input / output chip 2240 may also connect various input / output units to the input / output controller 2220 via parallel ports, serial ports, keyboard ports, mouse ports, etc.

[0107] The program is provided on a computer-readable medium such as a DVD-ROM 2201 or an IC card. The program is read from the computer-readable medium and installed on a hard disk drive 2224, RAM 2214, or ROM 2230, which are examples of computer-readable mediums, and executed by the CPU 2212. The information processing described within these programs is read by the computer 2200, resulting in coordination between the program and the various types of hardware resources described above. The apparatus or method may be configured to realize the manipulation or processing of information in accordance with the use of the computer 2200.

[0108] For example, when communication is performed between a computer 2200 and an external device, the CPU 2212 may execute a communication program loaded into the RAM 2214 and, based on the processing described in the communication program, instruct the communication interface 2222 to perform communication processing. Under the control of the CPU 2212, the communication interface 2222 reads transmission data stored in a transmission buffer processing area provided in a recording medium such as the RAM 2214, hard disk drive 2224, DVD-ROM 2201, or IC card, transmits the read transmission data to the network, or writes received data received from the network to a reception buffer processing area provided on the recording medium.

[0109] Furthermore, the CPU 2212 may read all or necessary parts of a file or database stored on an external recording medium such as a hard disk drive 2224, a DVD-ROM drive 2226 (DVD-ROM 2201), or an IC card into the RAM 2214, and perform various types of processing on the data in the RAM 2214. The CPU 2212 then writes the processed data back to the external recording medium.

[0110] Various types of information, such as various types of programs, data, tables, and databases, may be stored on the recording medium and subjected to information processing. The CPU 2212 may perform various types of processing on the data read from the RAM 2214, including various types of operations, information processing, conditional judgments, conditional branching, unconditional branching, information retrieval / replacement, etc., as described throughout this disclosure and specified by the program instruction sequence, and write the results back to the RAM 2214. The CPU 2212 may also retrieve information in files, databases, etc., within the recording medium. For example, if a plurality of entries having attribute values ​​of a first attribute, each associated with an attribute value of a second attribute, are stored in the recording medium, the CPU 2212 may search among the plurality of entries for an entry that matches the condition for which the attribute value of the first attribute is specified, read the attribute value of the second attribute stored in that entry, and thereby obtain the attribute value of the second attribute associated with the first attribute that satisfies a predetermined condition.

[0111] The program or software module described above may be stored on or near computer 2200 on a computer-readable medium. Alternatively, a recording medium such as a hard disk or RAM provided within a server system connected to a dedicated communication network or the Internet can be used as a computer-readable medium, thereby providing the program to computer 2200 via the network.

[0112] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention.

[0113] It should be noted that the execution order of operations, procedures, steps, and stages in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before," "prior to," etc., and that these can be performed in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc. for convenience, it does not mean that it is essential to perform the operations in that order.

[0114] 10 DUT, 20 Transmitter, 30 Pseudo-random signal generator, 35 Encoder, 100 Test device, 110 Receiver, 115 Decoder, 120 Setting unit, 130 Expected value generation unit, 140 Comparison unit, 150 Detection unit, 160 Result determination unit, 170 Control unit, 210 Selector, 310 FF, 320 Conversion circuit, 330a-d FF, 340a-d Switch, 410a-c Comparator, 420a-c FF, 430 Conversion circuit, 440 FF, 450 NOT element, 460 Selector, 510 Counter, 520 Counter, 530 Forbidden state determination unit, 2200 Computer, 2201 DVD-ROM, 2210 Host controller, 2212 CPU, 2214 RAM, 2216; Graphics controller, 2218; Display device, 2220; Input / output controller, 2222; Communication interface, 2224; Hard disk drive, 2226; DVD-ROM drive, 2230; ROM, 2240; Input / output chip, 2242; Keyboard

Claims

1. A test apparatus comprising: a receiving unit that receives a received signal sequence containing a pseudo-random signal sequence of T values ​​(where T is an integer of 2 or more) output by the device under test; a decoding unit that decodes the pseudo-random signal sequence of T values ​​in the received signal sequence into a decoded signal sequence of C values ​​(where C is an integer of 2 or more and different from T); and a detection unit that detects that the pseudo-random signal generator that generated the pseudo-random signal sequence of T values ​​in the received signal sequence was in a prohibited state when the ratio of predetermined signal values ​​in the decoded signal sequence falls outside a reference range.

2. The test apparatus according to claim 1, wherein T is an integer of 3 or more, and C is an integer of 2 or more and less than T.

3. The test apparatus according to claim 2, wherein the decoding unit decodes each signal value of the T value in the pseudo-random signal sequence of the T value into two or more signal values ​​of the C value.

4. The test apparatus according to claim 3, wherein C is 2 and T is a power of 2.

5. The test apparatus according to claim 4, wherein the decoding unit decodes each signal value of the T value in the pseudo-random signal sequence of T values ​​into two or more Gray-coded signal values ​​of the C values.

6. The test apparatus according to claim 1, wherein the device under test generates a pseudo-random signal sequence of C values ​​and encodes it into T values ​​to generate a pseudo-random signal sequence of T values, and the test apparatus comprises an expected value generation unit that generates an expected value signal sequence including the same pseudo-random signal sequence of C values ​​as the pseudo-random signal sequence of C values ​​generated by the device under test.

7. The test apparatus according to claim 6, wherein the detection unit determines that the ratio of predetermined signal values ​​in the decoded signal sequence is outside the reference range when the ratio of predetermined signal values ​​in the pseudo-random signal sequence of C values ​​included in the expected value signal sequence is outside the reference range.

8. The test apparatus according to claim 6, further comprising a comparison unit for comparing the decoded signal sequence with the pseudo-random signal sequence of the C value in the expected value signal sequence.

9. The test apparatus according to claim 8, further comprising a result determination unit that determines the test result based on the comparison result from the comparison unit and the detection result from the detection unit.

10. The test apparatus according to claim 6, further comprising a setting unit that sets a random number seed for the pseudo-random signal sequence of the C value in the expected value signal sequence generated by the expected value generation unit using a portion of the decoded signal sequence.

11. The test apparatus according to claim 1, wherein the device under test generates a pseudo-random signal sequence of C values ​​and decodes it into T values ​​to generate a pseudo-random signal sequence of T values, and the detection unit changes the reference range according to the number of digits in the shift register of the pseudo-random signal generator that generated the pseudo-random signal sequence of C values.

12. A test method comprising: receiving a received signal sequence containing a pseudo-random signal sequence of T values ​​(where T is an integer of 2 or more) output by a device under test; decoding the pseudo-random signal sequence of T values ​​in the received signal sequence into a decoded signal sequence of C values ​​(where C is an integer of 2 or more and different from T); and detecting that the pseudo-random signal generator that generated the pseudo-random signal sequence of T values ​​in the received signal sequence was in a prohibited state when the ratio of predetermined signal values ​​in the decoded signal sequence falls outside a reference range.

13. A program executed by a computer, which causes the computer to function as a receiving unit that receives a received signal sequence containing a pseudo-random signal sequence of T values ​​(where T is an integer of 2 or more) output by the device under test; a decoding unit that decodes the pseudo-random signal sequence of T values ​​in the received signal sequence into a decoded signal sequence of C values ​​(where C is an integer of 2 or more and different from T); and a detection unit that detects that the pseudo-random signal generator that generated the pseudo-random signal sequence of T values ​​in the received signal sequence was in a prohibited state when the ratio of predetermined signal values ​​in the decoded signal sequence falls outside a reference range.

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