Signal transmission method, apparatus and electronic device

Abstract

The present disclosure relates to a signal transmission method, device and electronic equipment. The signal transmission method is used for a plurality of electronic devices in cascade, each of the plurality of electronic devices has a corresponding order number in the cascade, each of the plurality of electronic devices communicates with a controller to receive a data stream and a clock signal from the controller, the data stream includes a plurality of parts corresponding to the plurality of electronic devices, and the method comprises: causing each of the plurality of electronic devices to count based on the clock signal to obtain a current count value of itself; and causing each of the plurality of electronic devices to receive a part corresponding to itself from the data stream in response to the current count value of itself matching the order number of itself. The method is advantageous to improve the frequency of signal transmission.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to a signal transmission method, apparatus and electronic device. BACKGROUND

[0002] With the development of integrated circuits and electronic technology, multiple electronic devices are often cascaded to transmit signals. For example, in the field of liquid crystal display panels or organic light emitting diode (OLED) display panels, multiple source driving chips are cascaded to provide image data of a row of pixel units to the row of pixel units, so as to form a gray voltage required by each gray scale of a display image in each row of pixel units in a row-by-row scanning manner, and then display a frame of image. SUMMARY

[0003] At least one embodiment of the present disclosure provides a signal transmission method for multiple electronic devices cascaded, each of the multiple electronic devices having a corresponding order number in the cascade, each of the multiple electronic devices being in communication with a controller to receive a data stream and a clock signal from the controller, the data stream including multiple parts corresponding to the multiple electronic devices, the method comprising: causing each of the multiple electronic devices to count based on the clock signal to obtain a current count value of itself; and causing each of the multiple electronic devices to receive a part corresponding to itself from the data stream in response to the current count value of itself matching the order number of itself.

[0004] For example, in the signal transmission method provided by an embodiment of the present disclosure, the method further comprises: causing each of the multiple electronic devices to obtain an order indication signal; and causing each electronic device to determine the order number of itself according to the order indication signal of itself.

[0005] For example, in the signal transmission method provided by an embodiment of the present disclosure, the multiple electronic devices include a master device arranged at a first position in the cascade and at least one slave device arranged at a subsequent position of the master device in the cascade in sequence, and causing each of the multiple electronic devices to obtain an order indication signal comprises: causing each of the at least one slave device to obtain the order indication signal for each slave device from a previous device.

[0006] For example, in the signal transmission method provided by an embodiment of the present disclosure, the method further comprises: causing each electronic device of a current stage to update the order indication signal for the electronic device of the current stage obtained from a previous device; and providing the updated order indication signal for a next-stage electronic device in the cascade to the next-stage electronic device.

[0007] For example, in the signal transmission method provided by an embodiment of the present disclosure, the order indication signal includes at least one pulse signal.

[0008] For example, in the signal transmission method provided by an embodiment of the present disclosure, each electronic device determines its own sequence number according to the sequence indication signal of itself, which includes: each electronic device determines its own sequence number according to the number of the at least one pulse signal received.

[0009] For example, in the signal transmission method provided by an embodiment of the present disclosure, the electronic device of each current stage updates the sequence indication signal of the electronic device of the current stage obtained from the electronic device of the previous stage, which includes: the electronic device of each current stage increments the number of the at least one pulse signal received from the electronic device of the previous stage.

[0010] For example, in the signal transmission method provided by an embodiment of the present disclosure, each of the plurality of electronic devices receives the part corresponding to itself from the data stream in response to the current count value of itself matching the sequence number of itself, which includes: obtaining the expected count value of the clock signal corresponding to each electronic device according to the sequence number of each electronic device itself; and causing each of the plurality of electronic devices to receive the part corresponding to itself from the data stream in response to the current count value of itself being consistent with the expected count value of itself.

[0011] For example, in the signal transmission method provided by an embodiment of the present disclosure, each electronic device is connected to the controller through a pair of low-voltage differential signal lines, and the expected count value of the clock signal corresponding to each electronic device is obtained according to the sequence number of each electronic device itself, which includes: obtaining the number of data channels of the electronic device, the number of pairs of low-voltage differential signal lines, and the number of data input ports of the electronic device; and calculating the expected count value of the clock signal corresponding to each electronic device based on the sequence number, the number of data channels, the number of pairs of low-voltage differential signal lines, and the number of data input ports.

[0012] For example, in the signal transmission method provided by an embodiment of the present disclosure, the calculation formula of the expected count value is as follows: CV = (CN / IDP) × SSN / (P / NB), where CV represents the expected count value, CN represents the number of data channels, IDP represents the number of periodic processing data channels, SSN represents the sequence number, P represents the number of pairs of low-voltage differential signal lines, and NB represents the number of input ports of the electronic device.

[0013] For example, in the signal transmission method provided by an embodiment of the present disclosure, the plurality of electronic devices includes a plurality of source driving chips, the controller includes a timing controller, and the data stream includes image data.

[0014] For example, in the signal transmission method provided by an embodiment of the present disclosure, the ordering number of each source drive chip is acquired during vertical blanking of scanning controlled by the timing controller.

[0015] For example, in the signal transmission method provided by an embodiment of the present disclosure, the timing controller provides display signals through a low voltage differential signal interface in at least two modes, the display signals including a plurality of display sub-signals, the at least two modes respectively providing display sub-signals, the at least two modes including a row configuration mode and a frame configuration mode, the image data being provided in the row configuration mode during image display, and frame configuration data being provided in at least the frame configuration mode during the vertical blanking.

[0016] For example, in the signal transmission method provided by an embodiment of the present disclosure, a master source drive chip in the plurality of source drive chips provides the ordering indication signal to a slave source drive chip that is subsequent to the master source drive chip in the cascade and adjacent to the master source drive chip in response to receiving the frame configuration data, the master source drive being a source drive chip that is first in the cascade.

[0017] An embodiment of the present disclosure provides a signal transmission apparatus, including a plurality of electronic devices in a cascade, each of the plurality of electronic devices having a corresponding ordering number in the cascade, each of the plurality of electronic devices being in communication with a controller to receive a data stream and a clock signal from the controller, the data stream including a plurality of portions corresponding to the plurality of electronic devices, the apparatus including: a counting unit configured to cause each of the plurality of electronic devices to count based on the clock signal; and a receiving unit configured to cause each of the plurality of electronic devices to receive a portion corresponding to itself from the data stream in response to a current count value of itself matching the ordering number of itself.

[0018] An embodiment of the present disclosure provides an electronic device, including a controller, and a signal transmission apparatus including a plurality of electronic devices in a cascade, each of the plurality of electronic devices having a corresponding ordering number in the cascade, each of the plurality of electronic devices being in communication with the controller to receive a data stream and a clock signal from the controller, the data stream including a plurality of portions corresponding to the plurality of electronic devices, the signal transmission apparatus including: a counting unit configured to cause each of the plurality of electronic devices to count based on the clock signal; and a receiving unit configured to cause each of the plurality of electronic devices to receive a portion corresponding to itself from the data stream in response to a current count value of itself matching the ordering number of itself. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure and not limit the present disclosure.

[0020] Figure 1 A schematic diagram of a signal transmission method applied to a source driver is shown;

[0021] Figure 2 A flow chart of a signal transmission method provided by at least one embodiment of the present disclosure is shown;

[0022] Figure 3 A flow chart of another signal transmission method provided by at least one embodiment of the present disclosure is shown;

[0023] Figure 4 A schematic diagram of each slave device obtaining a sequencing indication signal from a previous stage device provided by at least one embodiment of the present disclosure is shown;

[0024] Figure 5 A flow chart of another signal transmission method provided by at least one embodiment of the present disclosure is shown;

[0025] Figure 6 A schematic diagram of a display signal provided by a controller to a source driver provided by at least one embodiment of the present disclosure is shown; Figure 2 A method flow chart of step S20 is shown;

[0026] Figure 7A And 7B A signal format schematic diagram of a display signal provided by a controller to a source driver provided by at least one embodiment of the present disclosure is shown;

[0027] Figure 7C A schematic diagram of a signal transmission method applied to a source driver is shown;

[0028] Figure 8 A schematic block diagram of a signal transmission device 800 provided by at least one embodiment of the present disclosure is shown; and

[0029] Figure 9 A schematic block diagram of an electronic device 900 provided by at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0030] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the following will be combined with the drawings of the embodiments of the present disclosure to make a clear and complete description of the technical solutions of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without any inventive effort fall within the protection scope of the present disclosure.

[0031] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning understood by a person of ordinary skill in the art to which the present disclosure pertains. The terms "first", "second" and similar terms used in the present disclosure do not denote any order, quantity or importance, but are used to distinguish different components. Similarly, the terms "one", "a" or "the" and similar terms do not denote quantity limitation, but mean that there is at least one. The terms "include", "contain" and similar terms mean that the components or objects before the terms encompass the components or objects listed after the terms and their equivalents, without excluding other components or objects. The terms "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right" and the like are only used to represent relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships can also be changed accordingly.

[0032] Figure 1 A schematic diagram of a signal transmission method applied to a source driver is shown.

[0033] As shown in Figure 1 The source driver 101 includes a plurality of source drive chips in cascade, for example, the plurality of source drive chips include a master device SIC1 arranged in the first position in the cascade and a slave device SIC2, a slave device SIC3 and the like arranged in the subsequent positions of the master device SIC1 in sequence.

[0034] Each source drive chip is connected with the controller 102 to receive a data stream and a clock signal CLK from the controller. For example, the controller can be a timing controller, and the data stream, for example, includes image data for the pixel units to display images. The plurality of source drive chips are respectively connected with a plurality of columns of pixel units in the pixel array. For example, the master device SIC1, the slave device SIC2 and the slave device SIC3 are respectively connected with the plurality of columns of pixel units 103, the plurality of columns of pixel units 104 and the plurality of columns of pixel units 105 to respectively provide image data to the plurality of columns of pixel units 103, the plurality of columns of pixel units 104 and the plurality of columns of pixel units 105.

[0035] Figure 1The source driver, the controller and the pixel array as shown are applied to a display panel, for example. Various driving circuits for a display panel usually include a source driver and a controller, in addition to a scan driving integrated circuit (also referred to as a gate driver or G-IC), etc. The controller is mainly used to convert a data signal, a control signal, a clock signal, etc. received from an external source (such as a storage device, a network modem, etc.) into a data signal, a gate signal, a control signal, a clock signal, etc. suitable for the source driver and the gate driver, for implementing image display driving of the display panel. The controller can be a timing controller (TCON), for example. The source driver is mainly used to receive a digital signal (a display signal or an image signal) and a control signal, etc. provided by the aforementioned controller, convert the digital signal into a corresponding analog gray scale voltage signal through analog-digital conversion, and input the analog gray scale voltage signal into each column of pixel units of the pixel array of the display panel. The gate driver is mainly used to implement opening of each row of pixel units of the pixel array, for example, row by row (or interlaced), and under the action of a control signal, cooperate with the source driver to input a required data signal into a corresponding pixel unit for the opened row of pixel units, so that the pixel unit can display according to the data signal.

[0036] In the process of providing the data stream to each source driving chip by the controller 102, the source driver determines whether to receive the data stream from the controller 102 according to the start indication signal EIO to obtain the part data signal corresponding to itself in the data stream.

[0037] For example, each source driving chip receives the part data signal from the controller 102 according to the clock signal in response to receiving the start indication signal EIO.

[0038] In some embodiments, for example, each source driving chip sends the start indication signal to the next level source driving chip of itself, and the next level source driving chip receives the part data signal according to the frequency of the clock signal in response to the start indication signal. As Figure 1 As shown, each source driving chip includes an indication signal input port EIO1 and an indication signal output port EIO2. The indication signal input port EIO1 is used to receive the start indication signal, and the indication signal output port EIO2 is used to provide the start indication signal for the next level source driving chip to the next level source driving chip.

[0039] As Figure 1 As shown, for example, the data stream provided by the controller 102 includes a reset signal, image data (such as RGB data) applied to each source driving chip, and invalid data.

[0040] For example, after each source driver chip receives the reset signal, the master device acquires the start indication signal in response to its indication signal input port EIO1, and acquires the RGB data of the master device from the controller 102. For example, the master device SIC1 provides the start indication signal EIO2_1 for the first slave device SIC2 through its indication signal output port EIO2 in response to receiving the RGB data of the master device, and the first slave device SIC2 acquires the RGB data of the first slave device provided by the controller 102 in response to the start indication signal EIO2_1. After the first slave device SIC2 acquires the RGB data of the first slave device, the master device SIC1 provides the start indication signal EIO2_2 for the second slave device SIC3 through its indication signal output port EIO2 in response to receiving the RGB data of the master device, and the second slave device SIC3 acquires the RGB data of the second slave device provided by the controller 102 in response to the start indication signal EIO2_2.

[0041] The indication signal input port EIO1 of the master device SIC1 can be connected to the controller or other devices, for example, to start receiving the partial data stream provided by the controller 102 in response to the control of the controller or other devices, and to provide the start indication signal EIO2_1 for the first slave device SIC2 to the first slave device SIC2.

[0042] With the increase of the frequency of signal transmission between the controller and the source driver, the delay of the start indication signal EIO in the process of transmitting the data stream from the master device to the plurality of slave devices in turn becomes crucial. If the start indication signal EIO is delayed too much, the source driver chip cannot receive complete or correct image data. Therefore, the delay of the start indication signal EIO seriously affects the frequency of signal transmission between the controller and the source driver.

[0043] In order to alleviate the influence of the delay of the start indication signal EIO on the frequency of signal transmission, the present disclosure proposes a signal transmission method. The signal transmission method assigns a ranking number to each electronic device in the cascade, and makes each electronic device count its current count value based on a clock signal; and makes each of the plurality of electronic devices acquire a part corresponding to itself from the data stream in response to its current count value matching its ranking number. The signal transmission method makes the transmission of the data stream independent of the start indication signal, thereby avoiding the influence of the delay of the start indication signal in the transmission process, and thereby facilitating the improvement of the frequency of signal transmission.

[0044] It should be noted that although the signal transmission method of the present disclosure is exemplified by the source driver in the present disclosure, the present disclosure is not limited thereto, i.e., the signal transmission method provided by the present disclosure is not only applied to the source driver but also applicable to any scenario of signal transmission by cascading. For example, it is applied to the typical serial peripheral interface (SPI) daisy chain signal transmission.

[0045] Figure 2 A flowchart of a signal transmission method provided by at least one embodiment of the present disclosure is shown.

[0046] As shown in Figure 2 , the signal transmission method comprises steps S10 and S20. The signal transmission method is applied to a plurality of electronic devices cascaded, each of the plurality of electronic devices having a corresponding order number in the cascade, each of the plurality of electronic devices being in communication with a controller to receive a data stream and a clock signal from the controller, the data stream comprising a plurality of portions corresponding to the plurality of electronic devices.

[0047] Step S10: causing each of the plurality of electronic devices to count based on the clock signal to obtain a current count value of itself.

[0048] Step S20: causing each of the plurality of electronic devices to receive a portion corresponding to itself from the data stream in response to the current count value of itself matching the order number of itself.

[0049] For example, Figure 2 , the signal transmission method can be applied to Figure 1 the controller 102 and the source driver 101. For example, in the source driver 101, each source driver chip has a corresponding order number. In some embodiments of the present disclosure, for example, the order number is written to each electronic device, so that each electronic device pre-stores the order number of itself. In other embodiments of the present disclosure, the order number can be determined by each electronic device according to the obtained order indication signal, please refer to the following Figure 3 .

[0050] For example, the order number of the master device SIC1 is 0 by default, the order number of the first slave device SIC2 is 1, and the order number of the second slave device SIC3 is 2.

[0051] The master device SIC1, the first slave device SIC2, and the second slave device SIC3 receive the clock signal and the respective image data from the controller 102. For example, the data stream comprises image data, and the master device SIC1, the first slave device SIC2, and the second slave device SIC3 receive the RGB data of the master device, the RGB data of the first slave device, and the RGB data of the second slave device from the controller 102, respectively.

[0052] The RGB data of the master device is used for display of the pixel units 103, the RGB data of the first slave device is used for display of the pixel units 104, and the RGB data of the second slave device is used for display of the pixel units 105.

[0053] In some embodiments of the present disclosure, the controller transmits data according to a clock signal, and each electronic device receives a data stream according to the clock signal. For example, the controller transmits 6 bits of image data in each clock cycle, and each electronic device receives a partial data stream at the rising edge of the clock signal.

[0054] For step S10, for example, each electronic device includes a counter for counting the periods of the clock signal to obtain a current count value. For example, the counter starts counting the periods of the clock signal in response to a counting instruction. The counting instruction is triggered, for example, when the controller starts providing the data stream to the source driver.

[0055] For example, the current count value represents the length of time or the number of clock cycles during which the controller provides the data stream to the source driver.

[0056] For step S20, for example, the current count value is consistent with the ranking number of the electronic device itself, and the electronic device receives the partial data stream corresponding to the electronic device itself from the data stream.

[0057] In other embodiments of the present disclosure, for example, each ranking number corresponds to an expected count value, and when the current count value of each electronic device is consistent with the expected count value corresponding to the ranking number of the electronic device, each electronic device receives the partial data stream corresponding to the electronic device itself from the data stream.

[0058] For example, the ranking number of a certain slave device SICi is i-1, the expected count value corresponding to the ranking number i-1 is P, and when the current count value of the counter of the slave device SICi is P, the partial data stream provided by the controller is received, i is an integer greater than 1, and P is an integer greater than 1.

[0059] The signal transmission method no longer uses a start indication signal to prompt the electronic device to receive the partial data stream, but instead assigns a ranking number to each electronic device in advance and counts the clock signal, and starts receiving the data stream when the current count value matches the ranking number. The signal transmission method makes the transmission of the data stream independent of the start indication signal, thereby avoiding the impact of the delay of the start indication signal in the transmission process, thereby facilitating an increase in the frequency of signal transmission.

[0060] Figure 3 A flowchart of another signal transmission method provided by at least one embodiment of the present disclosure is shown.

[0061] As Figure 3As shown, in addition to steps S10 and S20, the signal transmission method further includes steps S30 and S40.

[0062] Step S30: Each of the multiple electronic devices acquires a sorting instruction signal.

[0063] Step S40: Each electronic device determines its own sorting number according to its own sorting indication signal.

[0064] This method provides each electronic device with its own sorting number through a sorting instruction signal, so that the sorting number of each electronic device can be flexibly adjusted and set.

[0065] For step S30, the sorting indication signal is used to indicate the sorting sequence number of each electronic device in the cascade.

[0066] In some embodiments of this disclosure, the sorting indication signal includes at least one pulse signal. For example, the number of pulse signals represents the sorting sequence number. For instance, 5 pulse signals represent a sorting sequence number of 5.

[0067] In other embodiments of this disclosure, the sorting indication signal may include, for example, a voltage signal. For instance, different voltage values ​​of the voltage signal represent different sorting indication signals. For example, a voltage value of 1V represents a sorting sequence number of 1V.

[0068] In some embodiments of this disclosure, for example, each electronic device is directly connected to an interface for providing a sorting indication signal, so as to obtain the sorting indication signal directly from the interface.

[0069] In other embodiments of this disclosure, for example, multiple electronic devices include a master device that is first in the cascade and at least one slave device that is sequentially arranged after the master device in the cascade, and step S30 includes: each of the at least one slave device obtaining a sorting indication signal for the slave device from the previous level device.

[0070] Figure 4 A schematic diagram is shown illustrating how each slave device obtains a sorting indication signal from its parent device, according to at least one embodiment of this disclosure.

[0071] like Figure 4 As shown, the method provided in this embodiment is applied to Figure 1 The source driver 101 is shown.

[0072] For example, the master device SIC1 provides a sequencing indication signal PL1 to the first slave device SIC2 through its own start signal output port, and the first slave device SIC2 receives the sequencing indication signal PL1 provided by the master device SIC1 through its own start signal input port. Then, the second slave device SIC3 acquires the sequencing indication signal PL2 for the second slave device SIC3 from the first slave device SIC2, and so on, each slave device receives the sequencing indication signal from the previous level device.

[0073] It should be noted that the sequencing indication signals for each slave device are different, for example, the sequencing indication signal PL1 for the first slave device SIC2 and the sequencing indication signal PL2 for the second slave device SIC3 are different.

[0074] The method can utilize Figure 1 The start signal input port and the start signal output port of the source driving chip shown in the figure transmit the sequencing indication signal in multiple source driving chips, without the need to modify the hardware of the source driving chip, good compatibility, and easy to implement.

[0075] For step S40, for example, the sequencing indication signal is at least one pulse signal, and each electronic device can determine its own sequencing order number according to the number of received at least one pulse signal. For another example, the sequencing indication signal is a voltage signal, and each electronic device can determine its own sequencing order number according to the voltage value of the received voltage signal.

[0076] Figure 5 A flowchart of another signal transmission method provided by at least one embodiment of the present disclosure is shown.

[0077] As Figure 5 As shown in the figure, the signal transmission method further includes steps S50 and S60 in addition to steps S10-S40.

[0078] Step S50: updating, by each electronic device of the current level, the sequencing indication signal for the electronic device of the current level acquired from the previous level device.

[0079] Step S60: providing the updated sequencing indication signal for the next level electronic device to the next level electronic device in the cascade.

[0080] For step S50, the electronic device of the current level is the electronic device to which the sequencing indication signal is passed. For example, in Figure 4For example, the ranking indication signal PL1 is transmitted from the master device SIC1 to the first slave device SIC2, i.e. the first slave device SIC2 receives the ranking indication signal PL1, while the slave devices behind the first slave device SIC2 have not received the ranking indication signal, at this time the electronic device of the current stage is the first slave device SIC2. For another example, the ranking indication signal is transmitted from the first slave device SIC2 to the second slave device SIC3, i.e. the second slave device SIC3 receives the ranking indication signal PL2 provided by the first slave device SIC2, while the slave devices behind the second slave device SIC3 have not received the ranking indication signal, at this time the electronic device of the current stage is the second slave device SIC3.

[0081] For example, the electronic device of the current stage is the first slave device SIC2, after the first slave device SIC2 receives the ranking indication signal PL1 from the master device SIC1, the first slave device SIC2 updates the ranking indication signal PL1. For example, the first slave device SIC2 updates the ranking indication signal PL1 to the ranking indication signal PL2.

[0082] In some embodiments of the present disclosure, the ranking indication signal is, for example, at least one pulse signal, and the step S50 comprises incrementing, by each electronic device of the current stage, the number of at least one pulse signal received from the device of the previous stage.

[0083] For example, each electronic device of the current stage increments the number of at least one pulse signal received from the device of the previous stage by a step. The step can be, for example, 1, and the number of pulse signals output by each electronic device of the current stage to the device of the next stage is the number of pulse signals received by the electronic device of the current stage plus 1.

[0084] For example, in the example of Figure 4 For example, the electronic device of the current stage is the first slave device SIC2, the ranking indication signal PL1 received by the first slave device SIC2 from the master device SIC1 is 1 pulse signal, and the first slave device SIC2 increases the number of pulse signals by 1, i.e. 2, and thus the ranking indication signal PL2 provided by the first slave device SIC2 to the second slave device SIC3 is 2 pulse signals.

[0085] The present disclosure does not limit the value of the step, and the step is 1 only as an example, and those skilled in the art can set the step according to needs.

[0086] If the ranking indication signal is a voltage signal, each electronic device of the current stage can increment the voltage value of the voltage signal received from the device of the previous stage.

[0087] For step S60, for example, the electronic device of the current stage is the first slave device SIC2, after the first slave device SIC2 updates the order indication signal PL1 to the order indication signal PL2, the order indication signal PL2 is provided to the electronic device of the next stage, the second slave device SIC3, which is located after the first slave device SIC2.

[0088] Figure 6 It is shown that the at least one embodiment provided by the present disclosure Figure 2 The method flowchart of step S20.

[0089] As Figure 6 It is shown that step S20 includes step S21 and step S22.

[0090] Step S21: According to the order sequence number of each electronic device itself, the expected count value of the clock signal corresponding to each electronic device is calculated.

[0091] Step S22: Each of the plurality of electronic devices receives the part corresponding to itself from the data stream in response to the consistency of the current count value of itself and the expected count value of itself.

[0092] The mapping relationship between the order sequence number and the expected count value can be flexibly set as needed, so that the applicability is stronger and easy to implement.

[0093] For step S21, for example, the mapping relationship between the order sequence number and the expected count value can be set by the person skilled in the art according to the actual situation. For example, the mapping relationship is represented by a correspondence table, and the expected count value of the clock signal corresponding to each electronic device is determined by looking up the correspondence table. For another example, the mapping relationship is represented in the form of a formula, and the expected count value of the clock signal corresponding to each electronic device is calculated by substituting the order sequence number into the formula.

[0094] In some embodiments of the present disclosure, for example, for a source driver, step S21 includes obtaining the number of data channels of each electronic device, the number of low-voltage differential signal line pairs, and the number of data input ports of the electronic device; and based on the order sequence number, the number of data channels, the number of low-voltage differential signal line pairs, and the number of data input ports, the expected count value of the clock signal corresponding to each electronic device is calculated.

[0095] For example, the number of data channels of each electronic device is how many data channels through which the electronic device provides data to other devices. For example, the electronic device is a source drive chip, the source drive chip provides image data to 960 column pixel units, and the source drive chip can include 960 data channels, each of which provides image data to a column of pixel units.

[0096] For example, each source drive chip and the controller low voltage differential signal interface are connected, and the low voltage differential signal interface of the source drive chip and the low voltage differential signal interface of the controller are connected through 3 low voltage differential signal line pairs or 6 low voltage differential signal line pairs. Each low voltage differential signal line pair includes two low voltage differential signal lines for transmitting two complementary low voltage differential signals, and the image data is transmitted through the two complementary differential signals. For example, the low voltage differential signal interface can be an LVDS (Low-Voltage Differential Signaling) interface or a mini-LVDS interface, etc.

[0097] The number of data channels of each electronic device, the number of low voltage differential signal line pairs, and the number of data input ports of the electronic device are, for example, inherent parameters of the electronic device itself.

[0098] For example, the calculation formula of the expected count value is as follows:

[0099] CV = (CN / IDP) × SSN / (P / NB),

[0100] CV represents the expected count value, CN represents the number of data channels, IDP represents the number of periodically processed data channels, SSN represents the sorting sequence number, P represents the number of low voltage differential signal line pairs, and NB represents the number of data input ports of the electronic device.

[0101] For example, IDP represents that data is periodically processed in several data channels. For example, in the internal definition of the electronic device, data is processed in 6 data channels, and 6 data channels are processed in 1 clock cycle, that is, 6 data channels are used to process data in each clock cycle.

[0102] For example, the electronic device is a source driver, and the source driver includes 6 data input ports connected with the timing controller to receive image data from the timing controller.

[0103] For example, in the example of Figure 4 In the example of

[0104] Step S22: For example, each of the plurality of electronic devices receives the part corresponding to itself from the data stream in response to the current count value of itself being consistent with the expected count value of itself.

[0105] The current count value is, for example, a count of clock cycles of the clock signal provided by the controller to the source driver chip. For each electronic device, in response to the current count value matching the expected count value, it begins to receive a portion of the data stream provided by the controller.

[0106] In some embodiments of this disclosure, the sorting number of each source driver chip is acquired during the vertical blanking of a scan controlled by a timing controller.

[0107] During display panel operation, video and animation are composed of numerous frames displayed sequentially in chronological order (e.g., frame rate of 60Hz or 120Hz). Each frame is a complete image displayed on the display panel. During the display of a frame, the gate driver sequentially activates each row of pixel units in the pixel array from the first row to the last row for scanning. During this scanning process, the source driver inputs the necessary data signals for each row of pixel units into the activated pixel units, thus completing the scanning and display of one frame. For example, due to the manufacturing process of the display panel's pixel units, the display needs to be continuously refreshed to achieve a clear, complete, and high-quality display. Each refresh requires displaying one frame, and multiple consecutively displayed frames visually constitute a static or dynamic image. After the gate driver completes scanning one frame, it needs to return to the first row to begin scanning a new frame. The time period from the end of the gate driver's scan of the last row to returning to the first row is called the Vertical Blanking Period (VBP). A single frame display cycle may include, for example, an image display period (Active Frame) and a vertical blanking period. During the image display period, image data is displayed line by line in a pixel array, for example. During the vertical blanking period, preparation is made for the display of the next frame of image data, and no image data is displayed.

[0108] During vertical blanking, the acquisition of sorting numbers by each source driver chip does not affect the acquisition of image data during image display, thus not affecting image display, and is robust to electrostatic discharge noise.

[0109] In some embodiments of this disclosure, the timing controller provides display signals through a low-voltage differential signal interface in at least two modes. The display signals include multiple display sub-signals, and the display sub-signals are provided in at least two modes respectively. The at least two modes include a line configuration mode and a frame configuration mode. Image data is provided in the line configuration mode during image display, and frame configuration data is provided in at least the frame configuration mode during vertical blanking.

[0110] For example, the display signal can include image data and configuration data. The configuration data includes, for example, row configuration data and frame configuration data. The row configuration data is used to configure the source driver (i.e., each source drive chip) so that the source driver outputs the row image data and timing control signals, etc. to the row of pixels in response to the row configuration data. The row configuration data includes, for example, a data polarity inversion control signal, a start signal of the image data, etc. The frame configuration data is used to configure the source driver (i.e., each source drive chip) so that the source driver outputs control signals for the frame image. The frame configuration data can include, for example, a gamma (Gamma) setting signal, an amplification (AMP) offset control signal, a shift direction selection signal, etc.

[0111] In some embodiments of the present disclosure, the row configuration data and the frame configuration data of each source drive chip are the same. Therefore, the timing controller can provide the row configuration data and the frame configuration data to each source drive chip at the same time so that each source drive chip is configured. Hereinafter, each source drive chip is referred to as a source driver.

[0112] Figure 7A and 7B A signal format diagram of a display signal provided by the controller to the source driver according to at least one embodiment of the present disclosure is shown.

[0113] As Figure 7A shown, in a frame display period (including an image display period and a vertical blanking period), the display signal includes a plurality of display sub-signals 701 provided in a row configuration mode, a display sub-signal 702 provided in a frame configuration mode, and a display sub-signal 703 provided in a correction configuration mode.

[0114] For example, the plurality of display sub-signals 701 are provided in the row configuration mode during the image display period, the display sub-signal 702 is provided in the frame configuration mode during the vertical blanking period, and the display sub-signal 703 is provided in the correction configuration mode.

[0115] As Figure 7A shown, the display signal provided to the source driver by the low-voltage differential signal interface in at least two modes within a frame display period includes: the display signal provided to the source driver by the low-voltage differential signal interface in at least two modes sequentially within a frame display period, and for each mode, one or more display sub-signals provided to the source driver by the low-voltage differential signal interface sequentially.

[0116] For example, in Figure 7AIn the example, multiple display sub-signals 701 are first provided to the source driver in row configuration mode using a low-voltage differential signal interface, then display sub-signals 702 are provided to the source driver in frame configuration mode, and finally display sub-signals 703 are provided to the source driver in calibration configuration mode. For example, in the row configuration mode including multiple display sub-signals 701, multiple display sub-signals 701 are provided to the source driver sequentially using a low-voltage differential signal interface. That is, in Figure 7A In the example, multiple display sub-signals 701 are first provided to the source driver using the low-voltage differential signal interface, then display sub-signals 702 are provided to the source driver using the low-voltage differential signal interface, and then display sub-signals 703 are provided to the source driver using the low-voltage differential signal interface.

[0117] like Figure 7A As shown, each display sub-signal 701 provided in row configuration mode includes row data (LPC) and image data (e.g., RGB data). Figure 7B As shown, the row data LPC includes a pattern recognition signal A and row configuration data. For example, the pattern recognition signal A includes a reset signal RESET and a row mode start signal LPC Start. For example, the row mode start signal can be a logic invalid level, such as "000 000". Please refer to the description above for the pattern recognition signal and row configuration data of the row configuration mode.

[0118] like Figure 7A As shown, each display sub-signal 702 provided in frame configuration mode includes frame data FPC and invalid data IDLE0 and invalid data IDLE1. The display sub-signals provided in frame configuration mode include data signals 712 provided in power control sub-mode. (As shown...) Figure 7B As shown, the Frame Data Programming (FPC) includes a pattern recognition signal B and frame configuration data. For example, the pattern recognition signal B of the Frame Data Programming (FPC) is a reset signal RESET and a frame mode start signal FPC Start. For example, the frame mode start signal differs from the line mode start signal to distinguish between frame configuration mode and line configuration mode; the frame mode start signal can be, for example, a logic active level such as "111 111". Please refer to the description above for the pattern recognition signal and frame configuration data for the frame configuration mode.

[0119] like Figure 7A As shown, each display sub-signal 703 provided in the calibration configuration mode includes calibration data ASC. (As...) Figure 7B As shown, the correction data ASC includes a pattern recognition signal C and a correction signal. The pattern recognition signal C can be, for example, a logic invalid level. Please refer to the description above for information about the correction signal.

[0120] like Figure 7AAs shown in FIG. 1, after the display signal in a frame display period is transmitted to the source driver, the display signal in the next frame display period is continuously transmitted to the source driver.

[0121] As shown in FIG. 1, before each display sub-signal is provided to the source driver, a trigger signal PSI is provided to the source driver, and the trigger signal PSI is used to inform the source driver to perform the transmission operation in at least two modes. Figure 7A

[0122] In some embodiments of the present disclosure, in addition to transmitting the display signal to the source driver in at least two modes, the controller can also transmit the display signal to the source driver in a single mode.

[0123] In this embodiment, the transmission operation in at least two modes performed by the source driver informed by the trigger signal PSI facilitates the compatibility of the source driver and the controller to other transmission operations in addition to the transmission operation in at least two modes, and provides compatibility. For example, in addition to the transmission operation in at least two modes, the transmission operation in a single mode can also be compatibly performed between the controller and the source driver. For example, the display signal transmitted in at least two modes conforms to a first signal transmission protocol, and the display signal transmitted to the source driver in a single mode conforms to a second signal transmission protocol. If the controller and the source driver perform the transmission operation in at least two modes, the controller first provides the trigger signal PSI to the source driver as an indication signal of the transmission operation in at least two modes; if the controller and the source driver perform the transmission operation in a single mode, the controller provides a single mode indication signal different from the trigger signal PSI to the source driver. The second signal transmission protocol can be some protocol different from the first signal transmission protocol, such as some transmission protocol in the related art. By setting the trigger signal, signal line multiplexing can be achieved, the chip has multiple functions, and thus the difficulty of popularizing the first signal transmission protocol is also reduced.

[0124] In some embodiments of the present disclosure, a master source driving chip in a plurality of source driving chips provides a sequencing indication signal to a slave source driver that is located in a subsequent position and adjacent to the master source driving chip in the cascade in response to receiving frame configuration data. The master source driving chip is a source driving chip located in a first position in the cascade.

[0125] Figure 7C A schematic diagram of transmitting a sequencing indication signal between a plurality of electronic devices provided by at least one embodiment of the present disclosure is shown.

[0126] As shown in FIG. 1, a plurality of electronic devices, for example, are Figure 7C Figure 4 a plurality of cascaded master devices SIC1, a first slave device SIC2, and a second slave device SIC3, etc.

[0127] ​​Electronic components such as the master device SIC1, the first slave device SIC2, and the second slave device SIC3 are, for example, source driver chips. For instance, each source driver chip and the timing controller are connected via a mini-LVDS interface.

[0128] In this example, the timing controller provides display signals via a low-voltage differential signal interface in at least two modes. These at least two modes include, for example, a line configuration mode and a frame configuration mode; image data is provided in line configuration mode during image display, and frame configuration data is provided in at least frame configuration mode during vertical blanking.

[0129] like Figure 7C As shown, in frame configuration mode, after the controller provides the trigger signal PSI to each source driver chip, the controller provides the frame configuration data FPC to each source driver chip.

[0130] exist Figure 7C In the example, the master device SIC1 is the first among the cascaded devices, and it is the main source driver chip. In response to receiving frame configuration data FPC, the master device SIC1 (the main source driver chip) transmits at least one pulse signal PL1 to the first slave device SIC2 via its start signal output port EIO2. For example, the at least one pulse signal PL1 contains one pulse. In response to receiving at least one pulse signal PL1, the first slave device SIC2 increments the number of at least one pulse signal PL1 by a step size and transmits the incremented at least one pulse signal PL2 to the second slave device SIC3 via its own start signal output port EIO2. Figure 7C As shown, in this example, the step size is 1, which facilitates calculation. The second slave device SIC3, in response to receiving at least one pulse signal PL2, increments the number of pulse signals PL2 according to the step size to obtain at least one pulse signal PL3, and provides at least one pulse signal PL3 to subsequent slave devices through its own start signal output port EIO2.

[0131] At least one electronic device that is sequentially located in the subsequent bits of the second slave device SIC3 performs operations similar to those of the first slave device SIC2 and the second slave device SIC3, which will not be described in detail here.

[0132] It should be noted that this disclosure does not limit the number of electronic devices. Although the number of electronic devices is shown as 3 in the above embodiments, in practice, the number of electronic devices can be more than, equal to or less than 3.

[0133] Figure 8A schematic block diagram of a signal transmission apparatus 800 is shown. The signal transmission apparatus 800 cascades a plurality of electronic devices, each of which has a corresponding order number in the cascade, and each of which communicates with a controller to receive a data stream and a clock signal from the controller, the data stream including a plurality of portions corresponding to the plurality of electronic devices.

[0134] For example, as shown in Figure 8 The signal transmission apparatus 800 includes a counting unit 810 and a receiving unit 820.

[0135] The counting unit 810 is configured to cause each of the plurality of electronic devices to count based on the clock signal.

[0136] The counting unit 810 may, for example, perform the step S10 described above. Figure 2

[0137] The receiving unit 820 is configured to cause each of the plurality of electronic devices to receive, from the data stream, a portion corresponding to itself in response to a current count value of itself matching the order number of itself.

[0138] The receiving unit 820 may, for example, perform the step S20 described above. Figure 2

[0139] The signal transmission method makes the transmission of the data stream independent of the start indication signal, thereby avoiding the influence of the delay of the start indication signal in the transmission process, and thus facilitating an increase in the frequency of signal transmission.

[0140] For example, the counting unit 810 and the receiving unit 820 can be hardware, software, firmware, or any feasible combination thereof. For example, the counting unit 810 and the receiving unit 820 can be a special-purpose or general-purpose circuit, chip, or apparatus, or a combination of a processor and a memory. The embodiments of the present disclosure do not limit the specific implementation forms of the above-mentioned units.

[0141] It should be noted that, in the embodiments of the present disclosure, the units of the signal transmission apparatus 800 correspond to the steps of the signal transmission method described above, and the specific functions of the signal transmission apparatus 800 can be referred to the related description of the signal transmission method, which will not be described here. Figure 8 The components and structures of the signal transmission apparatus 800 shown are only exemplary and are not limiting, and the signal transmission apparatus 800 can also include other components and structures as needed.

[0142] Figure 9 A schematic block diagram of an electronic device 900 is shown. As Figure 9 ​​As shown, the electronic device 900 includes a controller 910 and a signal transmission device 920.

[0143] The signal transmission device 920 is, for example, a source driver. The signal transmission device 920 includes a plurality of cascaded electronic devices, each having a corresponding sequence number in the cascade. Each of the plurality of electronic devices communicates with the controller to receive a data stream and a clock signal from the controller, the data stream including multiple portions corresponding to the plurality of electronic devices. The signal transmission device 920 includes: a counting unit configured to cause each of the plurality of electronic devices to count based on the clock signal; and a receiving unit configured to cause each of the plurality of electronic devices, in response to matching its current count value with its own sequence number, to receive the portion corresponding to itself from the data stream.

[0144] like Figure 9 As shown, the electronic device 900 may also include a display panel 930.

[0145] The signal transmission device 920, for example, performs the above... Figure 2 The described signal transmission method. The display panel 930 is, for example, a liquid crystal display panel, used to receive drive signals (i.e., grayscale voltage signals) provided by the source driver 920 and display images.

[0146] The electronic device 900 can be any electronic device with image display capabilities, including but not limited to smartphones, tablets, laptops, monitors, televisions, etc.

[0147] This electronic device enables data stream transmission to be independent of the start indication signal, thereby avoiding the impact of delays caused by the start indication signal during transmission and thus improving the frequency of signal transmission.

[0148] Although the above points have been made, the following points still need to be clarified:

[0149] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0150] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0151] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure should be determined by the scope of protection of the claims.

Claims

1. A signal transmission method for cascaded multiple electronic devices, wherein, Each of the plurality of electronic devices has a corresponding sequence number in the cascade, and each of the plurality of electronic devices communicates with the controller to receive data streams and clock signals from the controller, the data streams comprising multiple portions corresponding to the plurality of electronic devices. The method includes: Each of the plurality of electronic devices counts based on the clock signal to obtain its own current count value; Each of the plurality of electronic devices, in response to its current count value, matches it with its sorting number and receives the portion corresponding to itself from the data stream. Specifically, each of the plurality of electronic devices, in response to matching its current count value with its sorting number, receives the portion corresponding to itself from the data stream, including: Based on the sequence number of each electronic device, obtain the expected count value of the clock signal corresponding to each electronic device; and Each of the plurality of electronic devices, in response to its current count value aligning with its expected count value, receives its corresponding portion from the data stream. Each electronic device is connected to the controller via a low-voltage differential signal pair. Based on the sequence number of each electronic device, obtain the expected count value of the clock signal corresponding to each electronic device, including: Obtain the number of data channels for each electronic device, the number of low-voltage differential signal line pairs, and the number of data input ports for each electronic device; and Based on the sorting number, the number of data channels, the number of low-voltage differential signal pairs, and the number of data input ports, the expected count value of the clock signal corresponding to each electronic device is calculated.

2. The method according to claim 1, further comprising: Each of the plurality of electronic devices acquires a sorting instruction signal; as well as Each electronic device determines its own sequence number based on its own sequence indication signal.

3. The method according to claim 2, wherein, The plurality of electronic devices includes a master device that is first in the cascade and at least one slave device that is sequentially arranged in the cascade following the master device. Enabling each of the plurality of electronic devices to acquire a sorting indication signal includes: The at least one slave device obtains the sorting indication signal for each slave device from the parent device.

4. The method according to claim 3, further comprising: Each current-level electronic device updates its sorting indication signal obtained from the previous-level device, wherein the sorting indication signal includes at least one pulse signal, and the update includes incrementing the number of the at least one pulse signal received from the previous-level device; and Provide updated sorting indication signals for the next level of electronics in the cascade.

5. The method according to claim 4, wherein, Each electronic device determines its own sequence number based on its own sequence indication signal, including: Each electronic device determines its own sequence number based on the number of the at least one pulse signal received.

6. The method according to claim 1, wherein, The formula for calculating the expected count value is as follows: CV=(CN / IDP)×SSN / (P / NB) ， Wherein, CV represents the expected count value, CN represents the number of data channels, IDP represents the number of periodically processed data channels, SSN represents the sorting sequence number, P represents the number of low voltage differential signal line pairs, and NB represents the number of data input ports of the electronic device.

7. The method according to any one of claims 2 to 5, wherein, The plurality of electronic devices include a plurality of source driver chips, the controller includes a timing controller, and the data stream includes image data.

8. The method according to claim 7, wherein, The sorting number of each source driver chip is obtained during the vertical blanking of the scan controlled by the timing controller.

9. The method according to claim 8, wherein, The timing controller provides display signals via a low-voltage differential signal interface in at least two modes. The display signals include multiple display sub-signals, and the at least two modes each provide a separate display sub-signal. The at least two modes include line configuration mode and frame configuration mode. The image data is provided in the row configuration mode during image display. Frame configuration data is provided at least in the frame configuration mode during the vertical blanking process.

10. The method according to claim 9, wherein, In response to receiving the frame configuration data, the master source driver chip among the plurality of source driver chips provides the sorting indication signal to the slave source driver chip that is located in the subsequent position of the master source driver chip in the cascade and is adjacent to the master source driver chip. The main source driver chip is the first source driver chip in the cascade.

11. A signal transmission device comprising a plurality of cascaded electronic devices, wherein, Each of the plurality of electronic devices has a corresponding sequence number in the cascade, and each of the plurality of electronic devices communicates with the controller to receive data streams and clock signals from the controller, the data streams comprising multiple portions corresponding to the plurality of electronic devices. The device includes: A counting unit is configured to cause each of the plurality of electronic devices to count based on the clock signal; The receiving unit is configured such that each of the plurality of electronic devices, in response to matching its current count value with its own sequence number, receives the portion corresponding to itself from the data stream. The receiving unit is configured as follows: Based on the sequence number of each electronic device, obtain the expected count value of the clock signal corresponding to each electronic device; and Each of the plurality of electronic devices, in response to its current count value aligning with its expected count value, receives its corresponding portion from the data stream. Each electronic device is connected to the controller via a low-voltage differential signal pair. Specifically, based on the sequence number of each electronic device, the expected count value of the clock signal corresponding to each electronic device is obtained, including: Obtain the number of data channels for each electronic device, the number of low-voltage differential signal line pairs, and the number of data input ports for each electronic device; and Based on the sorting number, the number of data channels, the number of low-voltage differential signal pairs, and the number of data input ports, the expected count value of the clock signal corresponding to each electronic device is calculated.

12. An electronic device, comprising: Controller; as well as A signal transmission device includes a plurality of cascaded electronic devices, each of which has a corresponding sequence number in the cascade, and each of which communicates with a controller to receive a data stream and a clock signal from the controller, the data stream comprising multiple portions corresponding to the plurality of electronic devices. The signal transmission device includes: A counting unit is configured to cause each of the plurality of electronic devices to count based on the clock signal; The receiving unit is configured such that each of the plurality of electronic devices, in response to matching its current count value with its own sequence number, receives the portion corresponding to itself from the data stream. The receiving unit is configured as follows: Based on the sequence number of each electronic device, obtain the expected count value of the clock signal corresponding to each electronic device; and Each of the plurality of electronic devices, in response to its current count value aligning with its expected count value, receives its corresponding portion from the data stream. Each electronic device is connected to the controller via a low-voltage differential signal pair. Specifically, based on the sequence number of each electronic device, the expected count value of the clock signal corresponding to each electronic device is obtained, including: Obtain the number of data channels for each electronic device, the number of low-voltage differential signal line pairs, and the number of data input ports for each electronic device; and Based on the sorting number, the number of data channels, the number of low-voltage differential signal pairs, and the number of data input ports, the expected count value of the clock signal corresponding to each electronic device is calculated.

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