A fast recovery power device with an embedded tunnel diode structure and a method of producing the same

Abstract

The application discloses a fast recovery power device with embedded tunnel diode structure and a production method thereof, wherein the power device has a plurality of uniformly arrayed heavy doped regions with opposite doped types under a neutral body region, and the heavy doped regions form a tunnel PN junction structure with the doped regions with opposite doped types in the neutral body region; the tunnel PN junction structure can provide an additional minority carrier leakage conduction channel when the power MOSFET device is switched from a conducting state to a closed state, reduces the tail current when the device is closed, makes the power device quickly closed from an open state, and thus improves the working speed of the device and expands the frequency band range of the power device. The application realizes the fast recovery characteristic of the device through the process steps of adding the arrayed opposite heavy doped regions and rapid thermal annealing, makes the power device have the advantages of low cost and fast recovery, and breaks the barrier that the VDMOS power device can only be used in the medium and low frequency field applications.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor manufacturing technology, specifically to a fast recovery power device with an embedded tunnel diode structure and its manufacturing method. Background Technology

[0002] Over the past few decades, power devices have seen rapid development, especially power metal-oxide-semiconductor field-effect transistors (MOSFETs). Their high input impedance, low on-state power dissipation, and high current handling capability have greatly expanded their application areas. To meet low power consumption requirements, it is essential to effectively reduce the on-resistance of power MOSFETs, while maintaining a high breakdown voltage and a large on-current. Traditional vertical double-diffused metal-oxide-semiconductor field-effect transistors (VDMOS) are widely used. However, to maintain a high breakdown voltage, VDMOS retains a PIN-like diode structure with a thick, lightly doped intrinsic region. This results in a long "tail" current when the device switches from the on to the off state, making it difficult to turn off and limiting VDMOS applications to low-to-medium frequency fields.

[0003] To improve device operating speed, the "superjunction" concept was proposed in the early 1990s. This technology utilizes alternating P-pillars and N-pillars to replace the N-type drift region of traditional power devices, successfully breaking the "silicon limit." It can achieve both low on-state power consumption and high switching speed while maintaining breakdown voltage. However, compared to traditional MOSFETs, the superjunction structure has a significant drawback: high reverse recovery stiffness and long recovery time in the body diode. Due to the large PN junction area in the superjunction structure, the peak reverse recovery current is large, leading to significant reverse recovery losses. Furthermore, in low- and medium-voltage applications, shielded gate power MOSFETs designed using the superjunction principle also exhibit high peak reverse recovery currents. Traditional methods control minority carrier lifetime through electron irradiation or heavy metal doping to reduce reverse recovery charge and peak current. However, this increases manufacturing costs and leads to high leakage current, while also affecting the reliability and doping distribution of the gate oxide, causing changes in the device's conventional performance and further reducing long-term reliability. Summary of the Invention

[0004] To solve the above problems, the technical solution provided by the present invention is as follows:

[0005] A fast recovery power device with an embedded tunnel diode structure includes a first conductivity type substrate, a first conductivity type drift region on the first conductivity type substrate, a gate oxide layer on the first conductivity type drift region, a polysilicon layer on the gate oxide layer, a passivation layer on the polysilicon layer, and a source metal layer on the passivation layer and the first conductivity type drift region. A drain metal layer is formed at the bottom of the first conductivity type substrate. A neutral body region is provided above the first conductivity type drift region. A second conductivity type lightly doped region is provided above the neutral body region. A second conductivity type heavily doped body contact region is provided at the bottom of the second conductivity type lightly doped body contact region. A first conductivity type heavily doped ohmic contact region and a second conductivity type heavily doped ohmic contact region are provided above the second conductivity type lightly doped region. The second conductivity type heavily doped ohmic contact region penetrates the first conductivity type heavily doped ohmic contact region.

[0006] The present invention is further configured such that the first conductivity type heavily doped body contact region array is distributed at the bottom of the second conductivity type heavily doped body contact region, the first conductivity type heavily doped body contact region is located between the second conductivity type heavily doped body contact region and the neutral body region, and the first conductivity type heavily doped body contact region and the second conductivity type heavily doped body contact region constitute a tunnel PN junction.

[0007] The present invention is further configured such that the surfaces of the lightly doped region of the second conductivity type, the first heavily doped ohmic contact region of the first conductivity type, and the second heavily doped ohmic contact region of the second conductivity type are flush, and the source metal layer is in contact with the first heavily doped ohmic contact region of the first conductivity type and the second heavily doped ohmic contact region of the second conductivity type, respectively.

[0008] The present invention is further configured such that the ion concentration in the first conductivity type heavily doped contact region is higher than the ion concentration in the first conductivity type heavily doped ohmic contact region.

[0009] The present invention is further configured such that the ion concentration in the heavily doped ohmic contact region of the second conductivity type is higher than the ion concentration in the heavily doped body contact region of the second conductivity type.

[0010] The present invention is further configured such that the first conductivity type is N-type and the second conductivity type is P-type.

[0011] A method for manufacturing a fast recovery power device with an embedded tunnel diode structure, characterized in that the preparation of the power device includes:

[0012] An N-type substrate is provided, and a low-doped N-type drift region is formed on the N-type substrate using a solid-state epitaxy method;

[0013] An active region is defined by photolithography on the N-type substrate that forms the N-type drift region, JFET impurity implantation is performed and annealing is performed to push the junction, thereby forming a uniformly doped neutral body region in the N-type drift region.

[0014] A gate oxide layer is formed by growing gate oxide on the neutral body region; a polysilicon layer is formed by depositing polysilicon on the gate oxide layer; and the polysilicon layer is doped to form a polysilicon gate.

[0015] Photolithography is performed on the polysilicon gate to etch out the electrode window; low-concentration P-type ions are implanted into the electrode window and annealing is performed to push the junction to form a lightly doped P-type region;

[0016] A high concentration of P-type ions is implanted into the bottom of the lightly doped P-type region and then annealed to form a heavily doped P-type contact region.

[0017] A high concentration of N-type ions is implanted into the upper part of the lightly doped P-type region and then annealed to form a heavily doped N-type ohmic contact region.

[0018] An N+ region is defined by photolithography on the electrode window, a high concentration of N-type ions is implanted into the N+ region and annealed, and an N-type heavily doped contact region is formed at the bottom of the P-type heavily doped contact region.

[0019] An electrode region is defined by photolithography on the electrode window, a high concentration of P-type ions is implanted into the electrode region and annealed, and a P-type heavily doped ohmic contact region that penetrates the N-type heavily doped ohmic contact region is formed on the P-type lightly doped region.

[0020] A passivation layer is deposited on the polysilicon gate, and contact holes are photolithographically formed; metal is deposited on the passivation layer and the electrode region, and a source metal layer is formed by photolithography and etching.

[0021] The bottom of the N-type substrate is thinned and a drain metal layer is formed by metal sputtering.

[0022] The present invention is further configured such that the annealing time required for the formation of the P-type heavily doped contact region and the N-type heavily doped contact region is no more than 60s.

[0023] The present invention is further configured such that the concentration of N-type ions implanted to form the N-type heavily doped contact region is greater than the concentration of N-type ions implanted to form the N-type heavily doped ohmic contact region; and the concentration of P-type ions implanted to form the P-type heavily doped ohmic contact region is greater than the concentration of P-type ions implanted to form the P-type heavily doped contact region.

[0024] The present invention is further configured to grow a shielding oxide layer on the N-type drift region before performing JFET impurity implantation.

[0025] Compared with the prior art, the technical solution provided by this invention has the following advantages:

[0026] This technical solution presents a power device with several uniformly arrayed, heavily doped regions of opposite doping types below the neutral body region. These heavily doped regions, together with the doped regions of opposite doping types in the neutral body region, form a tunnel PN junction structure. These tunnel PN junction structures provide additional minority carrier leakage conduction channels when the power MOSFET device switches from the on-state to the off-state, reducing the tail current during device shutdown and enabling the power device to quickly turn off from the on-state. This improves the device's operating speed and expands its operating frequency range. By adding arrayed, heavily doped regions of opposite doping and employing rapid thermal annealing processes, this invention achieves rapid recovery characteristics, giving the power device the advantages of low cost and fast recovery, breaking the barrier that VDMOS power devices can only be used in low-to-medium frequency applications. Attached Figure Description

[0027] Figure 1 This is a cross-sectional schematic diagram of the fast recovery power device with an embedded tunnel diode structure according to an embodiment of the present invention.

[0028] Figure 2 This is a flowchart illustrating the fabrication process of a fast recovery power device with an embedded tunnel diode structure according to an embodiment of the present invention.

[0029] Figures 3a to 3k This is a detailed flowchart of the manufacturing method of a fast recovery power device with an embedded tunnel diode structure according to an embodiment of the present invention. Detailed Implementation

[0030] To further understand the content of this invention, a detailed description of the invention will be provided in conjunction with the accompanying drawings and embodiments.

[0031] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0032] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation", "connection", and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, an integral connection, or a detachable connection; they can refer to a mechanical connection or an electrical connection, or a connection within two components; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms according to the specific circumstances.

[0033] Example 1

[0034] Combined with appendix Figure 1The present invention provides a fast recovery power device with an embedded tunnel diode structure, comprising a first conductivity type substrate 110, a first conductivity type drift region 120 on the first conductivity type substrate 110, a gate oxide layer 130 on the first conductivity type drift region 120, a polysilicon layer 140 on the gate oxide layer 130, a passivation layer 150 on the polysilicon layer 140, and a source metal layer 160 on the passivation layer 150 and the first conductivity type drift region 120. A drain metal layer 170 is formed at the bottom of the first conductivity type substrate 110. The upper part of 20 is provided with a neutral body region 121, the upper part of the neutral body region 121 is provided with a lightly doped region 122 of the second conductivity type, the bottom of the lightly doped region 122 is provided with a heavily doped body contact region 123 of the second conductivity type, the bottom of the heavily doped body contact region 123 is provided with a first heavily doped body contact region 124 of the second conductivity type, the upper part of the lightly doped region 122 is provided with a first heavily doped ohmic contact region 125 of the second conductivity type and a second heavily doped ohmic contact region 126 of the second conductivity type, and the second heavily doped ohmic contact region 126 penetrates the first heavily doped ohmic contact region 125 of the first conductivity type.

[0035] In this embodiment, the first type of heavily doped contact region 124 is arrayed at the bottom of the second type of heavily doped contact region 123. The first type of heavily doped contact region 124 is located between the second type of heavily doped contact region 123 and the neutral body region 121. The first type of heavily doped contact region 124 and the second type of heavily doped contact region 123 constitute a tunnel PN junction.

[0036] In this embodiment, the surfaces of the second conductivity type lightly doped region 122, the first conductivity type heavily doped ohmic contact region 125, and the second conductivity type heavily doped ohmic contact region 126 are flush, and the source metal layer 160 is in contact with the first conductivity type heavily doped ohmic contact region 125 and the second conductivity type heavily doped ohmic contact region 126, respectively.

[0037] In this embodiment, the ion concentration of the first conductivity type heavily doped contact region 124 is higher than the ion concentration of the first conductivity type heavily doped ohmic contact region 125.

[0038] In this embodiment, the ion concentration of the second conductivity type heavily doped ohmic contact region 125 is higher than the ion concentration of the second conductivity type heavily doped body contact region 123.

[0039] In this embodiment, the first conductivity type is N-type and the second conductivity type is P-type.

[0040] The power device of this invention has several uniformly arrayed heavily doped regions of opposite doping type below the neutral body region. These heavily doped regions and the doped regions of opposite doping type in the neutral body region form a tunnel PN junction structure. These tunnel PN junction structures can provide additional minority carrier leakage conduction channels when the power MOSFET device switches from the on state to the off state, reducing the tail current when the device is turned off, enabling the power device to quickly turn off from the on state, thereby improving the operating speed of the device and expanding the operating frequency band of the power device.

[0041] Example 2

[0042] Combined with appendix Figure 2 and appendix Figure 3a ~Attached Figure 3k The present invention provides a method for manufacturing a fast recovery power device with an embedded tunnel diode structure, comprising the following steps:

[0043] An N-type substrate 301 is provided, and a low-doped N-type drift region 302 is formed on the N-type substrate 301 using a solid-state epitaxial method;

[0044] An active region is defined by photolithography on the N-type substrate on which the N-type drift region 302 is formed, JFET impurity implantation is performed and annealing is performed to push the junction, and a uniformly doped neutral body region 303 is formed in the N-type drift region.

[0045] A gate oxide layer 304 is formed by growing gate oxide on the neutral body region 303; a polysilicon layer 305 is formed by depositing polysilicon on the gate oxide layer 304; and the polysilicon layer 305 is doped to form a polysilicon gate.

[0046] Photolithography is performed on the polysilicon gate to etch out the electrode window 306; low concentration of P-type ions are implanted into the electrode window 306 and annealing is performed to push the junction to form a lightly doped P-type region 307.

[0047] High concentrations of P-type ions are implanted into the bottom of the lightly doped P-type region 307 and then annealed to form a heavily doped P-type contact region 308.

[0048] High-concentration N-type ions are implanted into the upper part of the lightly doped P-type region 307 and then annealed to form a heavily doped N-type ohmic contact region 309.

[0049] An N+ region is defined by photolithography on the electrode window 306, an array of photoresist 316 is arranged in the N+ region, a high concentration of N-type ions is implanted into the N+ region and annealed, and an N-type heavily doped contact region 310 is formed at the bottom of the P-type heavily doped contact region 308.

[0050] An electrode region is defined by photolithography on the electrode window 306, a high concentration of P-type ions is implanted into the electrode region and annealed, and a P-type heavily doped ohmic contact region 311 is formed on the P-type lightly doped region 307, penetrating the N-type heavily doped ohmic contact region 310;

[0051] A passivation layer 312 is deposited on the polysilicon gate, and contact holes are photolithographically formed; metal is deposited on the passivation layer 132 and the electrode region, and source metal layer 313 is formed by photolithography and etching.

[0052] The bottom of the N-type substrate 301 is thinned and a drain metal layer 314 is formed by metal sputtering.

[0053] In this embodiment, the annealing time required to form the P-type heavily doped contact region 308 and the N-type heavily doped contact region 310 is no more than 60 seconds.

[0054] In this embodiment, the N-type ion concentration implanted to form the N-type heavily doped contact region 310 is greater than the N-type ion concentration implanted to form the N-type heavily doped ohmic contact region 309; and the P-type ion concentration implanted to form the P-type heavily doped ohmic contact region 311 is greater than the P-type ion concentration implanted to form the P-type heavily doped contact region 308.

[0055] In this embodiment, a shielding oxide layer 315 is grown on the N-type drift region 302 before JFET impurity implantation.

[0056] In this embodiment, a corresponding mask is placed on the device during both photolithography and etching.

[0057] In this embodiment, the N-type ion is a pentavalent ion, such as P or As; the P-type ion is a trivalent ion, such as B or Ga.

[0058] In this embodiment, rapid thermal annealing and high-energy ion implantation are key to forming the N-type heavily doped contact region 310 and the P-type heavily doped contact region 308.

[0059] The technical solution of this invention adds array of opposite heavily doped regions and rapid thermal annealing to the power device, realizing the rapid recovery characteristics of the device and giving the power device the advantages of low cost and fast recovery; it solves the problem of long "tail" current when the device switches from the on to the off state, breaking the barrier that VDMOS power devices can only be used in the low and medium frequency fields.

[0060] To further illustrate the manufacturing method of the power device in this embodiment, the fabrication process of the VDMOS device with an embedded tunnel PN junction structure of the present invention is described using the fabrication of a fast N-type recovery vertical double-diffused power semiconductor device as an example, including the following steps:

[0061] Prepare a 6-inch N-type monocrystalline silicon wafer with a resistivity of 0.5 Ω·cm, and clean the wafer using the RCA standard cleaning process;

[0062] A single-crystal silicon epitaxial layer was grown on a silicon substrate in a silane atmosphere at 850°C for 30 min using chemical vapor deposition (CVD). The target single-crystal silicon thickness was 32 μm. In-situ doping resulted in a resistivity of approximately 10 Ω·cm corresponding to the doping concentration of the epitaxial layer. CVD growth of a high-resistivity single-crystal silicon layer can reduce the reaction temperature and enhance the reaction rate. The reaction gas was SiH4, the reaction temperature was between 600°C and 700°C, the reaction chamber pressure was between 11 and 14 Pa, the reaction time was between 10 and 20 min, and the silane flow rate was between 13.1 and 17.5 sccm.

[0063] Photolithography defines the active region. After removing the photoresist, a pre-implanted oxide layer is grown before JFET impurity implantation to obtain a target oxide layer with a thickness of 30nm.

[0064] JFET impurity implantation was performed, with phosphorus ions implanted at an energy of 100 keV and a dose of 1E12cm. -2 The tilt angle is 7°; then the junction push annealing of the JFET implantation is performed; the annealing process parameters are: 1050, ℃ for 120 min, N2 atmosphere;

[0065] The buffer oxide layer was etched away, and high-quality gate oxide was regrown with a target thickness of 50 nm. CVD polysilicon deposition was then performed, resulting in a polysilicon gate thickness of 500 nm. The polysilicon gate was then doped using phosphorus ion implantation at an implantation energy of 80 keV and a dose of 1E13 cm⁻¹. -2 Inclination angle 0°;

[0066] Photolithography defines the polysilicon gate region, with a gate coverage area width of 3µm, while P-type ion implantation is performed at an implantation dose of 1E13 cm⁻¹. -2 The energy was 90keV and the tilt angle was 0°. P-well advance annealing was carried out at a temperature of 1050°C for 60 minutes in an atmosphere of N2 to initially form the P-well and channel.

[0067] High-concentration P-type injection was performed at the bottom of the P-trap at an injection energy of 120 keV and a dose of 1E12cm. -2 The tilt angle is 0°. This step uses a rapid thermal annealing process to avoid the diffusion of doping elements and reduce the doping concentration. The annealing temperature is 1050°C and the time is 60s.

[0068] N+ ion implantation was performed to form the source region; the implantation energy was 120 keV, and the implantation dose was 6E14cm. -2 Annealing temperature 1150℃, annealing time 60min, atmosphere N2;

[0069] Photolithography defines the N+ region of the array, followed by arsenic ion implantation at a dose of 2E15cm. -2 The injection energy is 150keV. In order to better control the distribution of impurities, arsenic ions that are not easily diffused and a high-temperature rapid thermal annealing process are adopted. The annealing temperature is 1050℃ and the annealing time is 1min.

[0070] A silicon nitride buffer layer with a thickness of 1 μm was deposited by CVD. The neutral body electrode region was then lithographically and etched, followed by P+ ion doping at an implantation energy of 130 keV and an implantation dose of 4E15 cm⁻¹. -2 Next, borosilicate glass is deposited as a protective layer with a thickness of 10 μm; then, metal is deposited to form the source ohmic contact.

[0071] Backside ion implantation and sputtering of aluminum electrodes form a drain ohmic contact.

[0072] The present invention and its embodiments have been described above illustratively. This description is not restrictive, and the figures shown are only one embodiment of the present invention; the actual structure is not limited thereto. Therefore, if those skilled in the art are inspired by this description and design similar structures and embodiments without departing from the spirit of the present invention, such designs should fall within the protection scope of the present invention.

Claims

1. A fast recovery power device with an embedded tunnel diode structure, characterized in that, The system includes a first conductivity type substrate, a first conductivity type drift region on the first conductivity type substrate, a gate oxide layer on the first conductivity type drift region, a polysilicon layer on the gate oxide layer, a passivation layer on the polysilicon layer, and a source metal layer on the passivation layer and the first conductivity type drift region. A drain metal layer is formed at the bottom of the first conductivity type substrate. A neutral body region is provided above the first conductivity type drift region. A second conductivity type lightly doped region is provided above the neutral body region. A second conductivity type heavily doped body contact region is provided at the bottom of the second conductivity type lightly doped region. The first conductive type heavily doped body contact region is provided in the first conductive type, and the upper part of the second conductive type lightly doped body region is provided with the first conductive type heavily doped ohmic contact region and the second conductive type heavily doped ohmic contact region. The second conductive type heavily doped ohmic contact region penetrates the first conductive type heavily doped ohmic contact region. The first conductive type heavily doped body contact region is arrayed at the bottom of the second conductive type heavily doped body contact region. The first conductive type heavily doped body contact region is located between the second conductive type heavily doped body contact region and the neutral body region. The first conductive type heavily doped body contact region and the second conductive type heavily doped body contact region constitute a tunnel PN junction.

2. The fast recovery power device with an embedded tunnel diode structure according to claim 1, characterized in that, The surfaces of the lightly doped region of the second conductivity type, the heavily doped ohmic contact region of the first conductivity type, and the heavily doped ohmic contact region of the second conductivity type are flush, and the source metal layer is in contact with the first heavily doped ohmic contact region and the second heavily doped ohmic contact region, respectively.

3. The fast recovery power device with an embedded tunnel diode structure according to claim 1, characterized in that, The ion concentration in the first conductivity type heavily doped contact region is higher than the ion concentration in the first conductivity type heavily doped ohmic contact region.

4. The fast recovery power device with an embedded tunnel diode structure according to claim 1, characterized in that, The ion concentration in the heavily doped ohmic contact region of the second conductivity type is higher than the ion concentration in the heavily doped body contact region of the second conductivity type.

5. A fast recovery power device with an embedded tunnel diode structure according to claim 1, characterized in that, The first conductivity type is N-type, and the second conductivity type is P-type.

6. A method for manufacturing a fast recovery power device with an embedded tunnel diode structure, characterized in that, The preparation of the power device according to any one of claims 1 to 5 comprises: An N-type substrate is provided, and a low-doped N-type drift region is formed on the N-type substrate using a solid-state epitaxy method; An active region is defined by photolithography on the N-type substrate that forms the N-type drift region, JFET impurity implantation is performed and annealing is performed to push the junction, thereby forming a uniformly doped neutral body region in the N-type drift region. A gate oxide layer is formed by growing gate oxide on the neutral body region; a polysilicon layer is formed by depositing polysilicon on the gate oxide layer; and the polysilicon layer is doped to form a polysilicon gate. Photolithography is performed on the polysilicon gate to etch out the electrode window; low-concentration P-type ions are implanted into the electrode window and annealing is performed to push the junction to form a lightly doped P-type region; A high concentration of P-type ions is implanted into the bottom of the lightly doped P-type region and then annealed to form a heavily doped P-type contact region. A high concentration of N-type ions is implanted into the upper part of the lightly doped P-type region and then annealed to form a heavily doped N-type ohmic contact region. An N+ region is defined by photolithography on the electrode window, a high concentration of N-type ions is implanted into the N+ region and annealed, and an N-type heavily doped contact region is formed at the bottom of the P-type heavily doped contact region. The P-type heavily doped contact region is located between the N-type heavily doped contact region and the neutral body region. The P-type heavily doped contact region and the N-type heavily doped contact region constitute a tunnel PN junction. An electrode region is defined by photolithography on the electrode window, a high concentration of P-type ions is implanted into the electrode region and annealed, and a P-type heavily doped ohmic contact region that penetrates the N-type heavily doped ohmic contact region is formed on the P-type lightly doped region. A passivation layer is deposited on the polysilicon gate, and contact holes are photolithographically formed; metal is deposited on the passivation layer and the electrode region, and a source metal layer is formed by photolithography and etching. The bottom of the N-type substrate is thinned and a drain metal layer is formed by metal sputtering.

7. The method for manufacturing a fast recovery power device with an embedded tunnel diode structure according to claim 6, characterized in that, The annealing time required for the formation of the P-type heavily doped contact region and the N-type heavily doped contact region is no more than 60 seconds.

8. A method for manufacturing a fast recovery power device with an embedded tunnel diode structure according to claim 6, characterized in that, The concentration of N-type ions implanted to form the N-type heavily doped contact region is greater than the concentration of N-type ions implanted to form the N-type heavily doped ohmic contact region; the concentration of P-type ions implanted to form the P-type heavily doped ohmic contact region is greater than the concentration of P-type ions implanted to form the P-type heavily doped contact region.

9. A method for manufacturing a fast recovery power device with an embedded tunnel diode structure according to claim 6, characterized in that, A shielding oxide layer is grown on the N-type drift region before JFET impurity implantation.

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