Power mosfet and method of fabrication

Abstract

The application discloses a power MOSFET and a manufacturing method, which is suitable for different process treatments. The power MOSFET is manufactured by the following steps: exposing a plurality of grooves in a spaced manner by using a photoresist mask layer; and implanting P-type (or N-type) ions into implantation regions at different positions by using any one of ion implantation modes, such as inclined implantation, reverse doping implantation and channel implantation, so as to form a doping region; the dose of the doping region is used to control the threshold voltage of a second sub-transistor; P-type ions are implanted between the grooves to form a P-type well region, so as to control the threshold voltage of a first sub-transistor; and the different ion implantation modes are matched with the staggered arrangement element design method, so that the threshold voltage of the element can be controlled in different ranges under the premise of maintaining the element size, and a wider safe working area capability is realized.

Description

Technical Field

[0001] This invention relates to a power metal-oxide-semiconductor field-effect transistor, and more particularly to a power metal-oxide-semiconductor field-effect transistor and its fabrication method that uses ion implantation technology combined with component design techniques to extend the safe operating area (SOA). Background Technology

[0002] In recent years, the increasing demand for server performance in data centers, especially in applications requiring hot-swapping, has made the performance of power metal-oxide-semiconductor field-effect transistors (Power MOSFETs) a crucial factor in evaluating the reliability and safety of power protection components. The goal is to provide immediate protection when servers face abnormal conditions. Current practices primarily utilize planar MOSFETs for this purpose. However, servers typically operate continuously for extended periods, making power consumption a key design consideration. Therefore, to reduce overall power consumption, Power MOSFETs need to possess lower on-resistance (Ron) to effectively reduce conduction losses. Consequently, compared to planar MOSFETs, shielded-gate trench MOSFETs (SGTs) are a more suitable option. MOSFETs can achieve low on-resistance in a small area, but due to their inherent structural characteristics, heat sources tend to accumulate in the same area. Therefore, the thermal stability of MOSFETs mainly depends on their SOA (Self-Supporting Aspect Ratio) capability. To improve the above-mentioned and related problems, the following patents related to this technology exist: Chinese Patent Publication No. CN111599685B discloses a power semiconductor device and its fabrication method: The fabrication method of the power semiconductor device, by adding a first type of ion light doping process, can connect the first type of ion heavily doped region and the second type of ion heavily doped region, which is beneficial to deepen the depth of the first type of ion heavily doped region, thereby shifting the trench downward, avoiding the second type of ions transferred from the gate oxide thinning position from entering the first type of ion heavily doped region, reducing the impact on the trench, improving the uniformity of the threshold voltage of the SGT MOSFET, and thus improving the quality of the power semiconductor device; Taiwan Patent Publication No. TWM667641U, Driving Circuit and Voltage Converter; US Patent Publication No. US20170062407A1, POWER TRANSISTOR DEVICE AND PROTECTIONMETHOD THEREFOR.

[0003] The technologies disclosed in the above patents, such as improving the threshold voltage of SGT MOSFETs by changing the ion-doped region, focus on improving the quality of shielded gate trench transistors to increase manufacturing yield. Regarding the insufficient stability of SGT power devices under high voltage and high current conditions, existing methods mainly involve adjusting the component density or complicating the component's structural dimensions to distribute heat. However, this manufacturing approach often results in increased on-resistance and higher costs. Therefore, how to maintain low on-resistance without increasing component size, while simultaneously expanding the safe operating range of power MOSFETs to improve the withstand capability of power devices under high current and voltage conditions, is a problem that urgently needs to be solved. Summary of the Invention

[0004] In view of the above problems, based on years of experience in related industries, the inventors have made improvements to address the limitation of the safe operating range of existing power metal-oxide-semiconductor field-effect transistors. Therefore, the main objective of this invention is to provide a power metal-oxide-semiconductor field-effect transistor and its manufacturing method that can extend the safe operating range of the device by ion implantation in different regions of the device during the manufacturing process, thereby controlling the critical voltage of the transistor within different ranges.

[0005] To achieve the above objectives, the present invention provides a power metal-oxide-semiconductor field-effect transistor and its fabrication method. The method primarily involves first providing a substrate in the fabrication process. An epitaxial layer is formed on the substrate. Several trenches are formed on the epitaxial layer by etching. Each trench extends downwards from the epitaxial layer towards the substrate. Subsequently, an insulating layer between the shielded gate and the gate electrode, as well as a gate oxide layer and gate processing, are completed to form a shielded gate trench transistor structure. After the gate processing is completed in each trench, a gate is formed, and a shielding electrode is disposed below the gate. A P-type well region is then formed. The device is formed between trenches in the epitaxial layer; an N-type source region is formed on the surface above the P-type well region with a heavily doped N-type conductive dielectric; a dielectric layer is deposited above the N-type source region; a contact trench is formed by etching, extending downward from the surface of the dielectric layer through the N-type source region and the epitaxial layer; a metal layer is deposited on top of the dielectric layer for parallel coupling of the first and second sub-transistors; furthermore, this invention uses different ion implantation methods for each trench in a channel-separated manner to control the critical voltage of the device. In one main embodiment of the present invention, a trench inclined implantation is adopted to implant P-type ions or N-type ions into the implantation area to form a doped region. The implantation area is located on both sides of the trench above the trench. The dose of the formed doped region controls the second critical voltage of the second sub-transistor. In another embodiment of the present invention, anti-doping implantation is used, with the area below the N-type source region as the implantation region. First, P-type ions (acceptors) with a heavy doping dose are implanted, and then N-type ions (net acceptors) are implanted, so that the N-type ions cancel out the P-type ions. By anti-doping with N-type, the concentration of the net acceptor can be reduced to form a doped region. The concentration of the doped region is lower than that of the original P-type well region, and the dose of the doped region controls the second critical voltage of the second sub-transistor. In another embodiment of the present invention, channel implantation is employed to implant P-type or N-type ions into the implantation region to form a doped region. The implantation region is located in the channel region on both sides of the gate of the trench. The dose of the formed doped region controls the second critical voltage of the second sub-transistor.

[0006] The implantation conditions may include setting an implantation location, or setting a doping dose of the ion, an implantation energy, and a tilt angle.

[0007] The process for forming this power metal-oxide-semiconductor field-effect transistor can be either an SGT process to fabricate a shielded gate trench transistor or a trench process to fabricate a trench metal-oxide-semiconductor field-effect transistor.

[0008] The present invention provides a power metal-oxide-semiconductor field-effect transistor, comprising: One substrate; An epitaxial layer is formed on the substrate, and several trenches are formed by etching. The trenches are formed on the epitaxial layer and extend towards the substrate. A gate is formed inside each trench, and a shielding electrode is disposed below the gate. The trenches are arranged in a staggered manner to form a planting area. After the planting area is tilted, an ion is implanted into the planting area to form a doped region. The ion is a P-type ion or an N-type ion. A P-type well region is formed between the trenches in the epitaxial layer; An N-type source region is formed on the surface above the P-type well region using a heavily doped N-type conductive dielectric. A dielectric layer is deposited on top of the N-type source region; A contact trench, formed by etching, extends downwards from the surface of the dielectric layer through the N-type source region and the epitaxial layer, with the bottom of the contact trench extending into the P-type well region; and A metal layer is deposited on top of the dielectric layer, for a first sub-transistor and a second sub-transistor to be coupled in parallel and arranged in an alternating or proportional configuration.

[0009] The implantation area is located on both sides of the trench. After the ion is implanted into the implantation area by the inclined implantation, the dose of the doped area controls the second critical voltage of the second sub-transistor.

[0010] The tilted implantation can be replaced by an anti-doped implantation, and the implantation region is formed below the N-type source region. After the anti-doped implantation implants the ion into the implantation region, a doped region with a concentration lower than that of the P-type well region is formed, and the dose of the doped region controls a second critical voltage for the formation of the second sub-transistor.

[0011] The inclined implantation can be replaced by a channel implantation, so that the implantation region is formed in a channel region, and the ion is implanted into the channel region through the channel implantation. The dose of the doped region formed controls the second critical voltage of the second sub-transistor.

[0012] Another power metal-oxide-semiconductor field-effect transistor of the present invention includes: One substrate; An epitaxial layer is formed on the substrate, and several shallow trenches are formed by etching. These trenches are formed on the epitaxial layer extending towards the substrate, and a gate is formed inside each trench. The trenches are arranged in a staggered manner to form a planting area. After the planting area is tilted, an ion is implanted into the planting area to form a doped region. The ion is a P-type ion or an N-type ion. A P-type well region is formed between the trenches in the epitaxial layer; An N-type source region is formed on the surface above the P-type well region using a heavily doped N-type conductive dielectric. A dielectric layer is deposited on top of the N-type source region; A contact trench, formed by etching, extends downwards from the surface of the dielectric layer through the N-type source region and the epitaxial layer, with the bottom of the contact trench extending into the P-type well region; and A metal layer is deposited on top of the dielectric layer, for a first sub-transistor and a second sub-transistor to be coupled in parallel and arranged in an alternating or proportional configuration.

[0013] The implantation area is located on both sides of the trench. After the ion is implanted into the implantation area by the inclined implantation, the dose of the doped area controls the second critical voltage of the second sub-transistor.

[0014] The tilted implantation can be replaced by an anti-doped implantation, so that the implantation region is formed in the epitaxial layer. After the anti-doped implantation implants the ions into the implantation region, a doped region with a concentration lower than that of the P-type well region is formed, and the dose of the doped region controls a second critical voltage for the formation of the second sub-transistor.

[0015] The tilted implantation can be replaced by a threshold implantation (Threshold IMP), which extends the implantation region upward into the N-type source region. The implantation region is located in a channel region, and the ion is implanted into the channel region through the channel implantation. The dose of the doped region formed controls the second critical voltage of the second sub-transistor.

[0016] The beneficial effects of this invention are: In summary, by employing different ion implantation strategies in the MOS process, the power metal-oxide-semiconductor field-effect transistor of the present invention can, while maintaining the original component package volume, form at least two types of first and second sub-transistors with different critical voltages connected in parallel on the same substrate, and arranged in an alternating and proportional configuration, thereby expanding the safe operating area.

[0017] To enable your review committee to clearly understand the purpose, technical features, and effects of this invention, the following description is provided in conjunction with illustrations. Please refer to the accompanying figures. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the transistor circuit connection of the present invention; Figure 2 Here is a flowchart of the method of the present invention; Figure 3A This is a cross-sectional schematic diagram of the planting stage of the present invention; Figure 3B This is a schematic cross-sectional view of the structure of the present invention; Figure 4A This is a cross-sectional view of the planting stage in another embodiment (a) of the present invention; Figure 4B This is a cross-sectional view of another embodiment (a) of the present invention; Figure 5A This is a cross-sectional view of the planting stage in another embodiment (II) of the present invention; Figure 5B This is a cross-sectional view of another embodiment (ii) of the present invention; Figure 6A This is a cross-sectional view of the planting stage in another embodiment (iii) of the present invention; Figure 6B This is a cross-sectional view of another embodiment (iii) of the present invention; Figure 7A This is a cross-sectional view of the planting stage in another embodiment (iv) of the present invention; Figure 7B This is a cross-sectional view of another embodiment (four) of the present invention; Figure 8A This is a cross-sectional view of the planting stage in another embodiment (V) of the present invention; Figure 8B This is a cross-sectional view of another embodiment (v) of the present invention; Figure 9A The waveforms of the control group components under the same electrical test conditions are shown below. Figure 9B The waveform diagram is shown below, which is a waveform diagram of the present invention under the same electrical test conditions.

[0019] Explanation of reference numerals in the attached figures: 10-Power Metal-Oxide-Semiconductor Field-Effect Transistor 101 substrate 102 epitaxial layers 103 trench 104 P-type well area 1031 gate 1031' Shielding Electrode 105 N-type source region 106 dielectric layer 107 Contact groove 108 metal layer 201 substrate 202 epitaxial layer 203 Trench 204 P-type well area 2031 gate 205 N-type source region 206 dielectric layer 207 Contact Groove 208 metal layer M1 First Transistor M2 Second Transistor G acting as a gate G1 First Gate G2 Second Gate D action drain D1 First Drain D2 Second Drain S acting as a source S1 First Source S2 Second Source V DS Drain voltage I D Drain current T start Start time T end End time Planting areas A, B, and C Epitaxial layer grown on T1 substrate T2 forms a shielded gate structure T3 performs the first planting T4 is used for the second planting. T5 forms MOS structures with different critical voltages. Detailed Implementation

[0020] Please see Figure 1 The figure shows a schematic diagram of the transistor circuit connection of the present invention. The position and structural relationship of each region are designed during the photomask stage. The power metal-oxide-semiconductor field-effect transistor 10 of the present invention includes a first sub-transistor M1 and a second sub-transistor M2, which are connected in parallel. The first gate G1 of the first sub-transistor M1 and the second gate G2 of the second sub-transistor M2 are connected to serve as the gate G of the power metal-oxide-semiconductor field-effect transistor 10. The first drain D1 of the first sub-transistor M1 and the second drain D2 of the second sub-transistor M2 are connected to serve as the drain D of the power metal-oxide-semiconductor field-effect transistor 10. The first source S1 of the first sub-transistor M1 and the second source S2 of the second sub-transistor M2 are connected to serve as the source S of the power metal-oxide-semiconductor field-effect transistor 10.

[0021] Please see Figure 2 The figure shows a flowchart of the method of the present invention. The power metal-oxide-semiconductor field-effect transistor 10 of the present invention can be formed into a shielded gate trench MOSFET (SGT MOSFET) using shielded gate trench (SGT) technology. For a clearer explanation of the process, please refer to the following: Figures 3A to 3B The diagram shows a cross-sectional view of the implantation stage and a structural cross-sectional view of the present invention. The SGT process includes the following steps: Step T1 for growing an epitaxial layer on a substrate: First, an N-type substrate 101 is provided. The substrate 101 is made of Si (or SiC). A back metal layer is deposited at the bottom of the substrate 101. An N-type epitaxial layer 102 is formed on the substrate 101 by epitaxial growth. Next, a photoresist (PR) is used as an etching mask, and several trenches 103 are formed in the epitaxial layer 102 by etching. The number of trenches 103 after etching is not limited to a specific number. Each trench 103 is formed on the epitaxial layer 102 and extends downward toward the substrate 101. Next, each trench 103 is insulated and backfilled to fill the trench 103 with oxide or nitride material and fill in the shielding gate. Then, it is backfilled to a specific depth. The insulating layer between the shielding gate and the gate electrode, as well as the gate oxide layer and gate electrode process, are then completed to form a shielding gate trench transistor structure.

[0022] Step T2: Following the previous step, after completing the gate process inside each trench 103, a gate 1031 (shielded gate) is formed. By setting a polysilicon shielding electrode 1031' below the gate 1031, the on-resistance (RDS(on)) of the device can be reduced through the charge coupling effect.

[0023] The first implantation step T3 is performed as follows: In one embodiment of the invention, a pre-patterned photoresist mask layer is partially removed at intervals / alternates to expose odd-numbered trenches 103 (e.g., the first, third, fifth, etc. from left to right). Tilting implantation is then performed, and implantation conditions are set (including but not limited to setting the implantation position, or setting the ion type, doping dose, implantation energy, and tilt angle; the ion type can be P-type or N-type ions). The implantation conditions include implanting P-type or N-type ions into an implantation region A in each odd-numbered trench 103 to form a doped region. The implantation region A is located on both side walls above each trench 103. The threshold voltage (Threshold Voltage) for the subsequent formation of the second transistor M2 can be controlled according to the difference in the doping dose of the ions in the doped region. The range is defined as follows: (ge, Vth) ; Additionally, adjacent even-numbered trenches 103 (e.g., the second, fourth, sixth, etc. from left to right) are blocked by a photoresist masking layer; It should be noted that the distinction between "odd" and "even" numbers mentioned herein is merely illustrative to better understand how the present invention achieves spaced / interval planting of trenches 103 through ion implantation. Any other partitioning method that achieves the same technical effect as "spaced" or "interval" is included within the scope of the present invention and does not constitute a limitation; Furthermore, in addition to inclined implantation, the present invention can also employ different ion implantation methods: In one embodiment, counter doping is employed, with the area below an N-type source region 105 designated as a planting region B (see reference). Figures 5A to 5B The implantation conditions are set, including first implanting P-type ions (acceptors) with a heavy doping dose, followed by implanting N-type ions (net acceptors), so that the N-type ions cancel out the P-type ions. Through N-type dedoping, the net acceptor concentration can be reduced to form a doped region. The doping concentration is lower than that of a P-type well region 104, and the dose of the doped region controls the second critical voltage formed by the second sub-transistor M2. After implantation, rapid thermal annealing is performed to activate the dopant and control its diffusion to maintain the control effect of the critical voltage. The doping concentration and implantation order of the aforementioned "P-type ions" and "N-type ions" are not necessarily restricted, and the two can also be exchanged for dedoping. In one embodiment, Threshold IMP is employed and implantation conditions are set, including implanting P-type or N-type ions into an implantation region C (see reference). Figures 7A to 7B To form a doped region, the implanted region C is located in a channel region, and the dose of the formed doped region controls the second critical voltage formed by the second sub-transistor M2.

[0024] Step 1: Proceed to the second planting T4 step: Please refer to [link / reference needed] Figure 3B In conjunction with the implantation and structure formation methods described in steps T2 to T3, after controlling the second critical voltage of the second sub-transistor M2 using the ion implantation method disclosed above, P-type ions are further implanted in the gaps between adjacent trenches 103 in a channel / spaced manner to form a P-type well region 104, thereby forming the first critical voltage of the first sub-transistor M1.

[0025] Step T5, forming a MOS structure with different critical voltages: Following the subsequent processes, the aforementioned P-type well region 104 is formed between the trenches 103 in the epitaxial layer 102; the N-type source region 105 is formed on the surface above the P-type well region 104 using a heavily doped N-type conductive dielectric; a dielectric layer 106 is deposited above the N-type source region 105 using chemical vapor deposition (CVD) or similar methods, providing insulation and isolation; a contact trench 107 is etched from the surface of the dielectric layer 106 downwards through the N-type source region 105 and the epitaxial layer 102, with the bottom of the contact trench 107 extending into the P-type well region 104; a metal layer 108 is deposited... At the top of the dielectric layer 106, the first sub-transistor M1 and the second sub-transistor M2 are connected in parallel. In this invention, the number of the first sub-transistor M1 and the second sub-transistor M2 is not limited. They are arranged in an alternating manner or in proportion according to the device specifications and characteristics to ensure uniform heat distribution. In summary, by integrating different ion implantation strategies in a single MOS process (SGT process or trench process), the power metal-oxide-semiconductor field-effect transistor 10 of this invention can form at least two types of first sub-transistors M1 and second sub-transistors M2 with different critical voltages in parallel on the same substrate 101 while maintaining the original device package volume, thereby expanding the safe operating area.

[0026] Please see Figures 4A to 4B The figure shows a cross-sectional view and a structural cross-sectional view of the implantation stage in another embodiment (I) of the present invention. Similarly, it can be seen that the power metal-oxide-semiconductor field-effect transistor 10 in this embodiment can also be formed into a trench metal-oxide-semiconductor field-effect transistor (Trench MOSFET) using a trench process. The structure and process are the same as those of the present invention. Figure 2 The disclosed processes are largely the same, including a substrate 201, an epitaxial layer 202, a trench 203, a P-type well region 204, an N-type source region 205, a dielectric layer 206, a contact trench 207, and a metal layer 208 (corresponding to the aforementioned substrate 101 to metal layer 108 of the SGT MOS, respectively). The structural difference lies in the fact that the trench 203 formed by the trench process is different from the trench 103 formed by the SGT process (please refer back to the previous text). Figure 3B The trench 203 is shallower and does not extend excessively into the epitaxial layer 202. After the gate process, the trench 203 forms a gate 2031 (control gate). In addition, the ion implantation method can also be the same as the method disclosed in SGT MOS.

[0027] Please see Figures 5A to 5B This is a cross-sectional view and a structural cross-sectional view of the implantation stage in another embodiment (II) of the present invention. This embodiment discloses a power metal-oxide-semiconductor field-effect transistor 10 in the SGT MOS state, which has the same characteristics as... Figure 3B The same structure and component symbols are used, therefore repetitive descriptions are omitted; such as Figure 5A As shown, firstly, part of the photoresist masking layer is removed, exposing the area above the trenches 103 between two adjacent trenches. Then, after setting the planting conditions for the exposed part, vertical anti-doping is performed. First, heavily doped P-type ions are implanted into the planting area B, which is located between trenches 103 below the N-type source region 105. Then, N-type ions are implanted to counteract the previously implanted P-type ions through anti-doping characteristics, forming a doped region with a concentration lower than the original P-type well region 104, thereby controlling the critical voltage of the second sub-transistor M2 (which is relatively small). The doping concentration and implantation order of the aforementioned P-type and N-type ions can also be interchanged for anti-doping, without being limited to a specific form. The remaining unimplanted trenches 103 are then separated by P-type ions to form P-type well regions 104. The critical voltage of the P-type well region 104 is greater than the critical voltage of the aforementioned N-type anti-doped region, thereby expanding the range of the safe operating area.

[0028] Please see Figures 6A to 6B This is a cross-sectional view and a structural cross-sectional view of the planting stage in another embodiment (III) of the present invention. Figures 5A to 5B Similarly, as described above, the power metal-oxide-semiconductor field-effect transistor 1 in this embodiment can also be formed into a trench MOS using a trench process, possessing the same characteristics as... Figure 4B Since the same structure and symbols are used, repetitive descriptions are omitted. The ion implantation method can also be achieved by first removing part of the photoresist masking layer to expose the area above the trenches 203 of the two adjacent channels and setting the implantation conditions before performing anti-doping implantation. The implantation area B is located in the epitaxial layer 202. The anti-doping implantation is completed to form a doped region with a concentration lower than that of the original P-type well region 204. The dose of the doped region controls the critical voltage of the second sub-transistor M2. In this way, the critical voltage of the second sub-transistor M2 is lower than that of the first sub-transistor M1, so that the device has different ranges of critical voltage and achieves the purpose of expanding the safe operating area.

[0029] Please see Figures 7A to 7B This is a cross-sectional view and a structural cross-sectional view of the implantation stage in another embodiment (four) of the present invention. This embodiment discloses a power metal-oxide-semiconductor field-effect transistor 10 in the SGT MOS state, which has the same characteristics as... Figure 3BSince the same structure and component symbols are used, repetitive descriptions are omitted. Specifically, a portion of the photoresist masking layer is removed by means of spacing / channel separation to expose the odd-numbered trenches 103. After setting the placement conditions by channel placement, P-type or N-type ions are vertically implanted into the placement area C after setting the dosage to form a doped region, thereby adjusting the critical voltage of the second sub-transistor M2. The placement area C is located in the channel region on both sides of the trench 103 and the gate 1031. The dosage of the formed doped region controls the second critical voltage formed by the second sub-transistor M2.

[0030] Please see Figures 8A to 8B This is a cross-sectional view and a structural cross-sectional view of the planting stage in another embodiment (V) of the present invention. Figures 7A to 7B Similarly, it can be deduced that the power metal-oxide-semiconductor field-effect transistor 10 in this embodiment can also be formed into a trench MOS using a trench process, possessing the same characteristics as... Figure 4B Since the same structure and symbols are used, repetitive descriptions are omitted. In this process, a portion of the photoresist masking layer is removed in a spaced / interval manner to expose the odd-numbered trenches 203. After setting the implantation conditions with channel implantation, P-type or N-type ions are vertically implanted into a portion of the N-type source region 205 and the implantation region C after setting the dosage to form a doped region. The implantation region C extends upward into the N-type source region 205 and is located in the channel region. After the ions are implanted into the channel region through channel implantation, the dosage of the doped region formed controls the second critical voltage formed by the second sub-transistor M2.

[0031] Please see Figures 9A to 9B The waveforms of the control group device under the same electrical test conditions and the waveforms of the control group device under the same electrical test conditions are shown. During the test phase, high voltage and high current conditions are simultaneously applied to the power metal-oxide-semiconductor field-effect transistor 1 of the present invention to simulate its operation under high power operation or hot-swappable application environment, so as to test the device's tolerance and further confirm the safe operating area (hereinafter referred to as SOA) range. First, the existing shielded gate trench metal-oxide-semiconductor field-effect transistor (SGT MOSFET) is used as the control group, and a drain voltage V is set. DS 30 volts (V), one drain current I D The voltage was set to 10 amperes (A). The test was then conducted using this as the measurement condition, and the measured waveforms were captured. The lighter-colored waveform represents the drain voltage V. DS The dark waveform represents the drain current I. D And record a start time T respectively. start With an end time T end The start time T start To begin applying voltage and current (drain voltage V) DS With drain current I DThe time of the end, and the time of the end. end This represents the exact moment the component burns out. Using this method, it can be recorded that the existing SGT MOSFET only withstands 8 milliseconds (ms) before burning out. As shown in the waveform in the figure, since the drain and source terminals are short-circuited, the drain voltage V... DS =0V; Comparison Figure 9A It can be seen that the power metal-oxide-semiconductor field-effect transistor 1 of the present invention operates at the same drain voltage V as the control group. DS With drain current I D Under these conditions, the component can withstand burning out after 85ms, which is significantly shorter than the 8ms of the control group, demonstrating that the present invention can indeed significantly improve its SOA capability.

[0032] As described above, the power metal-oxide-semiconductor field-effect transistor and its fabrication method of the present invention mainly involve removing a portion of the photoresist masking layer at intervals during the process, exposing an odd number of trenches, and then implanting P-type or N-type ions into different implantation regions using any of the following methods: trench tilting implantation, anti-doping implantation, and channel implantation, to form doped regions. The dose of the doped regions controls the second critical voltage of the second sub-transistor. Simultaneously, P-type ions are implanted between trenches to form P-type well regions, thereby forming the first critical voltage of the first sub-transistor. The first and second sub-transistors are staggered according to the device specifications and characteristics. The arrangement or proportion configuration is set to ensure uniform heat distribution. By integrating different ion implantation strategies in a single MOS process, this invention can form at least two first and second sub-transistors with different critical voltages in parallel on the same substrate while maintaining the original component package volume, thereby expanding the safe operating area. After implementation, this invention can indeed achieve the purpose of providing a power metal-oxide-semiconductor field-effect transistor and its fabrication method that can control the critical voltage of the transistor within different ranges by ion implantation in different regions of the component, thereby expanding the safe operating area capability of the component.

[0033] However, the above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of the present invention; any equivalent changes and modifications made by those skilled in the art without departing from the spirit and scope of the present invention should be covered within the patent scope of the present invention.

Claims

1. A method for fabricating a power metal-oxide-semiconductor field-effect transistor, characterized in that, include: A substrate is provided, on which an epitaxial layer is formed. Several trenches are formed in the epitaxial layer by etching. The trenches are formed in the epitaxial layer and extend toward the substrate. The power metal-oxide-semiconductor field-effect transistor is formed by a process, which includes a first sub-transistor and a second sub-transistor connected in parallel in an alternating or proportional configuration. The trenches are obliquely implanted in a channel manner. The oblique implantation also includes setting an implantation condition and implanting an ion into a implantation area in the trenches to form a doped region. The ion can be a lightly doped or heavily doped P-type ion or an N-type ion. The implantation region is located on both sides of the trench above, and a second critical voltage for the formation of a second sub-transistor is controlled according to the dosage of the doped region; and After implanting the P-type ion below an N-type source region, a P-type well region is formed. The P-type well region is located between each trench or between adjacent trenches at intervals. The P-type well region forms a first critical voltage of a first sub-transistor.

2. The method for fabricating a power metal-oxide-semiconductor field-effect transistor as described in claim 1, characterized in that, The implantation conditions may include setting an implantation location, or setting a doping dose of the ion, an implantation energy, and a tilt angle.

3. The method for fabricating a power metal-oxide-semiconductor field-effect transistor as described in claim 1, characterized in that, The tilted implantation can be replaced by an anti-doped implantation. After setting the implantation conditions, the implantation region is located below the N-type source region or in the epitaxial layer. The implantation conditions also include first implanting the heavily doped P-type ions into the implantation region, and then implanting the N-type ions into the implantation region, so that the N-type ions cancel out the P-type ions to form the doped region. The dose of the doped region is lower than that of the P-type well region, which can control the second critical voltage formed by the second sub-transistor.

4. The method for fabricating a power metal-oxide-semiconductor field-effect transistor as described in claim 1, characterized in that, The tilted implantation can be replaced by a channel implantation, and after setting the implantation conditions, the implantation region is located in a channel region. The implantation conditions also include implanting the ion into the implantation region to form the doped region, and the dose of the doped region controls the second critical voltage formed by the second sub-transistor.

5. The method for fabricating a power metal-oxide-semiconductor field-effect transistor as described in claim 1, characterized in that, The process for forming this power metal-oxide-semiconductor field-effect transistor can be either an SGT process to fabricate a shielded gate trench transistor or a trench process to fabricate a trench metal-oxide-semiconductor field-effect transistor.

6. A power metal-oxide-semiconductor field-effect transistor, characterized in that, include: One substrate; An epitaxial layer is formed on the substrate, and several trenches are formed by etching. The trenches are formed on the epitaxial layer and extend towards the substrate. A gate is formed inside each trench, and a shielding electrode is disposed below the gate. The trenches are arranged in a staggered manner to form a planting area. After the planting area is tilted, an ion is implanted into the planting area to form a doped region. The ion is a P-type ion or an N-type ion. A P-type well region is formed between the trenches in the epitaxial layer; An N-type source region is formed on the surface above the P-type well region using a heavily doped N-type conductive dielectric. A dielectric layer is deposited on top of the N-type source region; A contact trench, formed by etching, extends downwards from the surface of the dielectric layer through the N-type source region and the epitaxial layer, with the bottom of the contact trench extending into the P-type well region; and A metal layer is deposited on top of the dielectric layer, for a first sub-transistor and a second sub-transistor to be coupled in parallel and arranged in an alternating or proportional configuration.

7. The power metal-oxide-semiconductor field-effect transistor as described in claim 6, characterized in that, The implantation area is located on both sides of the trench. After the ion is implanted into the implantation area by the inclined implantation, the dose of the doped area controls the second critical voltage of the second sub-transistor.

8. The power metal-oxide-semiconductor field-effect transistor as described in claim 6, characterized in that, The tilted implantation can be replaced by an anti-doped implantation, and the implantation region is formed below the N-type source region. After the ion is implanted into the implantation region by the anti-doped implantation, a doped region with a concentration lower than that of the P-type well region is formed, and the dose of the doped region controls a second critical voltage for the formation of the second sub-transistor.

9. The power metal-oxide-semiconductor field-effect transistor as described in claim 6, characterized in that, The tilted implantation can be replaced by a channel implantation, in which the implantation region is formed in a channel region, and after the ion is implanted into the channel region through the channel implantation, the dose of the doped region formed controls a second critical voltage of the second sub-transistor.

10. A power metal-oxide-semiconductor field-effect transistor, characterized in that, include: One substrate; An epitaxial layer is formed on the substrate, and several shallow trenches are formed by etching. These trenches are formed on the epitaxial layer extending towards the substrate, and a gate is formed inside each trench. The trenches are arranged in a staggered manner to form a planting area. After the planting area is tilted, an ion is implanted into the planting area to form a doped region. The ion is a P-type ion or an N-type ion. A P-type well region is formed between the trenches in the epitaxial layer; An N-type source region is formed on the surface above the P-type well region using a heavily doped N-type conductive dielectric. A dielectric layer is deposited on top of the N-type source region; A contact trench, formed by etching, extends downwards from the surface of the dielectric layer through the N-type source region and the epitaxial layer, with the bottom of the contact trench extending into the P-type well region; and A metal layer is deposited on top of the dielectric layer, for a first sub-transistor and a second sub-transistor to be coupled in parallel and arranged in an alternating or proportional configuration.

11. The power metal-oxide-semiconductor field-effect transistor as described in claim 10, characterized in that, The implantation area is located on both sides of the trench. After the ion is implanted into the implantation area by the inclined implantation, the dose of the doped area controls the second critical voltage of the second sub-transistor.

12. The power metal-oxide-semiconductor field-effect transistor as described in claim 10, characterized in that, The tilted implantation can be replaced by an anti-doped implantation, so that the implantation region is formed in the epitaxial layer, and after the anti-doped implantation implants the ions into the implantation region, a doped region with a concentration lower than that of the P-type well region is formed, and the dose of the doped region controls a second critical voltage for the formation of the second sub-transistor.

13. The power metal-oxide-semiconductor field-effect transistor as described in claim 10, characterized in that, The tilted implantation can be replaced by a channel implantation, in which the implantation region extends upward into the N-type source region, and the implantation region is located in a channel region. After the ion is implanted into the channel region through the channel implantation, the dose of the doped region formed controls the second critical voltage of the second sub-transistor.

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