A shield gate power mosfet layout for optimizing soa and a mosfet

Abstract

The application provides a shield gate power MOSFET layout for optimizing SOA and a MOSFET, wherein a second well region is arranged above part of the first well region. The two well regions are formed by ion implantation, so that two different threshold voltages exist, and current mainly flows out of the channel with a low threshold voltage. In the case that other processes remain unchanged, compared with other designs, the device is in a safe working area SOA, and the overcurrent capacity of the safe working area SOA is optimized.

Description

Technical Field

[0001] The embodiments of this application belong to the field of semiconductor technology, and in particular relate to a shielded gate power MOSFET layout and MOSFET for optimizing SOA. Background Technology

[0002] In the layout design of shielded gate power MOSFETs, the source polysilicon electrode, gate, and source need to be connected separately, and the source polysilicon electrode needs to be isolated from the gate. Before design optimization, such as Figure 1 As shown, under normal circumstances, the area between the trenches 2 of the chip is injected only once to form the well region 1, and then injection regions with different doping types are formed in the well region. This structure does not have strong overcurrent capability in the safe operating area (SOA). Summary of the Invention

[0003] To address or mitigate the problems in the prior art, in a first aspect, embodiments of this application provide a shielded gate power MOSFET layout for optimizing SOA, including: an active region;

[0004] The active region includes multiple trenches spaced apart;

[0005] A first well region is provided in the area between two adjacent trenches;

[0006] A second well region is disposed above a portion of the first well region.

[0007] In a preferred embodiment of this application, the cross-section of the region adjacent to the second well region is square.

[0008] In a preferred embodiment of this application, the cross-sections of adjacent second well regions are the same.

[0009] In a preferred embodiment of this application, the adjacent regions forming the second well region are spaced apart.

[0010] Secondly, embodiments of this application also provide a shielded gate power MOSFET for optimizing SOA, fabricated using the layout described in any of the first aspects.

[0011] Compared with existing technologies, this application provides a shielded gate power MOSFET layout and MOSFET for optimizing SOA, by correspondingly providing a second well region above a portion of the first well region. Two well regions are implanted through ion implantation, resulting in two different threshold voltages. Current mainly flows out from the channel with the lower threshold voltage. With other process parameters unchanged, this design allows the device to operate in the safe operating area (SOA), optimizing the SOA overcurrent capability. Attached Figure Description

[0012] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. Some specific embodiments of this application will be described in detail below with reference to the accompanying drawings in an exemplary and non-limiting manner. The same reference numerals in the drawings designate the same or similar parts or components. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings:

[0013] Figure 1 This is a shielded gate power MOSFET layout provided by existing technology for optimizing SOA;

[0014] Figure 2 This is a shielded gate power MOSFET layout for optimizing SOA provided in an embodiment of this application. Detailed Implementation

[0015] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some, not all, of the embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort should fall within the scope of protection of the present application.

[0016] like Figure 2 As shown, in a first aspect, embodiments of this application provide a shielded gate power MOSFET layout for optimizing SOA, including: an active region;

[0017] The active region includes multiple spaced trenches 2;

[0018] A first well region 1 is provided in the area between two adjacent trenches;

[0019] A second well region 3 is correspondingly provided above a portion of the first well region.

[0020] In a preferred embodiment of this application, the cross-section of the region formed by adjacent second well regions 3 is square. It should be noted that the first well corresponding to the first well region and the second well corresponding to the second well region have the same doping type.

[0021] In a preferred embodiment of this application, the cross-sections of adjacent second well regions 3 are the same.

[0022] In a preferred embodiment of this application, all adjacent second well regions 3 are arranged in a region-spaced configuration.

[0023] It should be noted that, in Figure 2In this case, no second well region 3 is provided on the first well region 4 between adjacent second well regions.

[0024] Secondly, embodiments of this application also provide a shielded gate power MOSFET for optimizing SOA, fabricated using the layout described in any of the first aspects.

[0025] Compared with the prior art, this application provides a shielded gate power MOSFET layout and MOSFET for optimizing SOA, by correspondingly providing a second well region 3 above a portion of the first well region 1. Two well region implantations are formed through ion implantation, resulting in two different threshold voltages. Current mainly flows out from the channel with the lower threshold voltage. With other process parameters unchanged, this design allows the device to operate in the safe operating area (SOA), optimizing the SOA overcurrent capability.

[0026] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A shielded gate power MOSFET layout for optimizing SOA, characterized in that, include: Active region; The active region includes multiple trenches spaced apart; A first well region is provided in the area between two adjacent trenches; A second well region is disposed above a portion of the first well region.

2. The shielded gate power MOSFET layout for optimizing SOA as described in claim 1, characterized in that, The cross-section of the region adjacent to the second well region is square.

3. A shielded gate power MOSFET layout for optimizing SOA as described in claim 2, characterized in that, The cross-sections of adjacent second well regions are the same.

4. A shielded gate power MOSFET layout for optimizing SOA as described in claim 2, characterized in that, The interval between adjacent regions forming the second well region is set.

5. A shielded gate power MOSFET for optimizing SOA, characterized in that, The layout is prepared according to any one of claims 1 to 4.

Images