An ultrafast response low on-state power MOS transistor

Abstract

This invention discloses an ultrafast response, low-conduction-loss power MOSFET, relating to the field of power semiconductor device technology. The ultrafast response, low-conduction-loss power MOSFET includes a housing, an auxiliary mounting plate fixed to the top of the housing, a heat sink fixed to the bottom, and source (S), drain (D), and gate (G) pins. Inside the housing are a source metal layer, a source region, a gradient-doped drift layer, and a drain metal layer. Gate trenches are formed on the source metal layer and the source region, with a high-k gate dielectric layer and a gate metal electrode fixed within the trenches. A dielectric trench-assisted depletion structure layer is formed on the gradient-doped drift layer. The high-k gate dielectric layer and gate trench optimize the switching response, while the gradient-doped drift layer and dielectric trench structure reduce conduction losses. With all components working collaboratively, this ultrafast response, low-conduction-loss power MOSFET breaks the trade-off between switching response and conduction losses, improves power conversion efficiency, balances voltage withstand and stability, and is easy to install, making it widely applicable in high-frequency power conversion scenarios.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor device technology, and in particular to an ultrafast response, low conduction loss power MOSFET. Background Technology

[0002] With the rapid development of new energy, artificial intelligence, industrial automation and other fields, power electronic systems are iterating and upgrading towards higher frequency, higher efficiency and smaller size, which puts forward increasingly stringent requirements on the performance of core power switching devices. As the core device for realizing power conversion and switching control in power electronic systems, the switching response speed and conduction loss of power MOSFETs directly determine the efficiency, size and reliability of the entire power conversion system. They are widely used in various power conversion equipment such as high frequency switching power supplies, photovoltaic inverters, power tools, and vehicle chargers, and are one of the key supporting devices for the development of modern power electronic technology. The gate structure of existing power MOSFETs mostly adopts traditional planar gate or conventional trench gate design, and the gate dielectric layer mostly uses ordinary dielectric materials, resulting in large gate drain capacitance (Cgd) and total gate charge (Qg). During high-frequency switching, the gate charging and discharging speed is slow, and the switching delay time, rise time and fall time are long. This not only increases switching losses, but also causes the device dynamic response to be slow, making it difficult to adapt to high-frequency power conversion scenarios above MHz. Summary of the Invention

[0003] The purpose of this invention is to at least solve one of the technical problems existing in the prior art, and to provide an ultra-fast response, low conduction loss power MOSFET that can solve the above-mentioned problems.

[0004] To achieve the above objectives, the present invention provides the following technical solution: an ultrafast response low conduction loss power MOSFET, comprising a housing, an auxiliary mounting plate fixedly connected to the top of the housing, a source S pin fixedly connected to one side of the bottom of the housing, a drain D pin disposed on one side of the source S pin, a gate G pin disposed on the other side of the drain D pin, both the drain D pin and the gate G pin being fixedly connected to the bottom of the housing, and a fast response component disposed on the housing, the fast response component comprising a source metal layer fixedly connected inside the housing.

[0005] Preferably, a heat sink is fixedly connected to the bottom of the housing.

[0006] Preferably, an active region is fixedly connected to the bottom of the source metal layer, and gate trenches are provided on the source metal layer and the source region.

[0007] Preferably, a high-k gate dielectric layer is fixedly connected in the gate trench, and a gate metal electrode is fixedly connected on the high-k gate dielectric layer, with the gate metal electrode disposed in the gate trench.

[0008] Preferably, a gradient-doped drift layer is fixedly connected to the bottom of the source region, and a drain metal layer is fixedly connected to the bottom of the gradient-doped drift layer.

[0009] Preferably, the drain metal layer, the gradient doped drift layer, and the source region are all disposed inside the housing.

[0010] Preferably, a dielectric trench-assisted depletion structure layer is provided on the gradient doped drift layer.

[0011] Preferably, the auxiliary mounting plate is provided with auxiliary mounting holes.

[0012] Compared with the prior art, the beneficial effects of the present invention are: 1. This ultra-fast response, low conduction loss power MOSFET significantly improves switching response speed, optimizes device dynamic performance, and adapts to the needs of high-frequency power conversion scenarios.

[0013] 2. This ultra-fast response, low conduction loss power MOSFET effectively reduces conduction loss, improves power conversion efficiency, and reduces heat generation during device operation.

[0014] 3. This ultra-fast response, low conduction loss power MOSFET balances the device's withstand voltage performance and operational stability, while optimizing installation convenience and heat dissipation, thereby improving the overall reliability and practicality of the device. Attached Figure Description

[0015] The present invention will be further described below with reference to the accompanying drawings and embodiments: Figure 1 This is a schematic diagram of an ultrafast response, low conduction loss power MOSFET according to the present invention; Figure 2 This is a schematic diagram of an ultrafast response, low conduction loss power MOSFET according to the present invention. Figure 3 This is a schematic cross-sectional view of an ultrafast response, low conduction loss power MOSFET according to the present invention. Figure 4 For the present invention Figure 3 Enlarged view of point A in the middle; Figure 5 For the present invention Figure 3 Enlarged view of point B in the middle; Figure 6 This is a schematic diagram of an ultrafast response, low conduction loss power MOS transistor according to the present invention.

[0016] Reference numerals: 1. Housing; 2. Auxiliary mounting plate; 3. Source S-pin; 4. Drain D-pin; 5. Gate G-pin; 6. Heat sink; 7. Drain metal layer; 8. Gradient doped drift layer; 9. Source metal layer; 10. Source region; 11. Gate trench; 12. High-K gate dielectric layer; 13. Gate metal electrode; 14. Dielectric trench auxiliary depletion structure layer. Detailed Implementation

[0017] This section will describe in detail specific embodiments of the present invention. Preferred embodiments of the present invention are shown in the accompanying drawings. The purpose of the drawings is to supplement the textual description with graphics, so that people can intuitively and vividly understand each technical feature and overall technical solution of the present invention, but they should not be construed as limiting the scope of protection of the present invention.

[0018] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0019] In the description of this invention, terms such as greater than, less than, and exceeding are understood to exclude the stated number, while terms such as above, below, and within are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0020] In the description of this invention, unless otherwise explicitly defined, terms such as "setting," "installing," and "connecting" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0021] Please see Figure 1-6 The present invention provides a technical solution: an ultrafast response low conduction loss power MOSFET, including a housing 1, an auxiliary mounting plate 2 fixedly connected to the top of the housing 1, a source S pin 3 fixedly connected to one side of the bottom of the housing 1, a drain D pin 4 disposed on one side of the source S pin 3, a gate G pin 5 disposed on the other side of the drain D pin 4, the drain D pin 4 and the gate G pin 5 are both fixedly connected to the bottom of the housing 1, and a fast response component is disposed on the housing 1, the fast response component including a source metal layer 9, the source metal layer 9 being fixedly connected inside the housing 1; The auxiliary mounting plate 2 is used to fix the entire device, and plays a role in positioning and fixing it, ensuring that the device is stable in position when it is working, and improving the ease of installation and assembly efficiency. A heat sink 6 is fixedly connected to the bottom of the housing 1; Heat sink 6 promptly conducts the heat generated during device operation, preventing heat buildup from affecting device performance, reducing device operating temperature, ensuring long-term stable operation of the device, and extending device lifespan. A source region 10 is fixedly connected to the bottom of the source metal layer 9, and a gate trench 11 is provided on the source metal layer 9 and the source region 10. The source metal layer 9 receives the current transmitted from the source region 10 and delivers it to the source S pin 3, reducing current transmission resistance loss and providing a mounting base for gate-related structures. Source region 10 provides a mounting carrier for gate trench 11, which, together with gate-related structures, forms a conductive channel to ensure normal switching of the device and stable current transmission. A high-K gate dielectric layer 12 is fixedly connected inside the gate trench 11, and a gate metal electrode 13 is fixedly connected on the high-K gate dielectric layer 12. The gate metal electrode 13 is disposed inside the gate trench 11. The gate trench 11 increases the contact area between the gate and the channel, shortens the charge transport path, accelerates the gate charging and discharging process, improves the switching response speed of the device, and provides stable mounting space for gate-related structures. The high-K gate dielectric layer 12 accumulates charge quickly, reduces gate-drain capacitance and total gate charge, improves device switching response speed, and also serves as an insulating layer to prevent short circuits between the gate and the source region and the source metal layer. The gate metal electrode 13 receives the drive signal transmitted from the gate G pin 5, generates an electric field and acts on the source region 10 and the source metal layer 9 to form a conductive channel, controls the device to turn on and off, and ensures the accuracy of the electric field. A gradient-doped drift layer 8 is fixedly connected to the bottom of the source region 10, and a drain metal layer 7 is fixedly connected to the bottom of the gradient-doped drift layer 8. The drain metal layer 7 receives the current flowing into the drain D pin 4 and transfers it to the gradient doped drift layer 8, reducing resistance loss during current transmission and helping to reduce conduction loss. The drain metal layer 7, the gradient doped drift layer 8, and the source region 10 are all disposed inside the housing 1; A dielectric trench-assisted depletion structure layer 14 is provided on the gradient doped drift layer 8; The gradient-doped drift layer 8, combined with the dielectric trench-assisted depletion structure layer 14, improves the current carrying capacity of the drift region, reduces the specific on-resistance, and optimizes the low-loss performance of the device while ensuring the device's breakdown voltage performance. The dielectric trench-assisted depletion structure layer 14 and the gradient-doped drift layer 8 achieve depletion, which further improves the current carrying capacity of the drift region, reduces the specific on-resistance, and optimizes the electric field distribution and operating stability of the device while ensuring the device's withstand voltage performance. The auxiliary mounting plate 2 is provided with auxiliary mounting holes.

[0022] Working principle: First, the device is fixedly installed through the auxiliary mounting holes on the auxiliary mounting plate 2. The auxiliary mounting plate 2 is fixed to the top of the housing 1, which plays a positioning and fixing role, ensuring that the device is stable in position during operation. The housing 1 serves as the outer shell of the entire device, enclosing all the core semiconductor structures inside. It plays a role in insulation, protecting the internal structure, and isolating external interference. The heat sink 6 is fixed to the bottom of the housing 1 to conduct heat generated during device operation in a timely manner, preventing heat accumulation from affecting device performance and ensuring long-term stable operation of the device. The switching control core of the device is completed by the gate-related structure (gate trench 11, high-K gate dielectric layer 12, gate metal electrode 13) and the gate G pin 5 in collaboration. This is also the key to achieving ultra-fast response. When the gate G pin 5 is connected to the positive drive voltage, the drive signal is transmitted to the gate metal electrode 13. Since the high-K gate dielectric layer 12 has excellent charge storage and isolation performance, it can quickly accumulate charge, reduce gate drain capacitance and total gate charge, and accelerate the gate charging and discharging process. At this time, the electric field generated by the gate metal electrode 13 acts on the source region 10 and the source metal layer 9 through the high-K gate dielectric layer 12, forming a conductive channel between the source region 10 and the gradient doped drift layer 8, realizing the rapid turn-on of the device, greatly shortening the turn-on delay time, and demonstrating ultra-fast response characteristics. When the positive drive voltage is stopped at the gate G pin 5, the charge on the gate metal electrode 13 is released quickly, the electric field disappears, the conductive channel is closed, and the device is turned off quickly, further ensuring the switching response speed. During this process, the high-K gate dielectric layer 12 always plays an insulating role to prevent the gate metal electrode 13 from short-circuiting with the source region 10 and the source metal layer 9, thus ensuring the stability of the switching control. When the device is turned on, current flows in from the drain D pin 4, passes through the drain metal layer 7, the gradient doped drift layer 8, the source region 10, and the source metal layer 9 in sequence, and finally flows out from the source S pin 3, completing the current transmission. The gradient doped drift layer 8 adopts a gradient doping design, with the doping concentration gradually increasing from the side near the drain metal layer 7 to the side near the source region 10. Combined with the dielectric trench auxiliary depletion structure layer 14 set on its surface, the current carrying capacity of the drift region is effectively improved and the specific on-resistance is reduced while ensuring the device's withstand voltage performance. The drain metal layer 7 and the source metal layer 9 are made of highly conductive materials, which reduces the resistance loss during the current transmission process, further reducing the conduction loss and achieving efficient power transmission. The source S pin 3, drain D pin 4, and gate G pin 5 are all fixed at the bottom of the housing 1. The three have a clear division of labor: the source S pin 3 is used for output current, the drain D pin 4 is used for input current, and the gate G pin 5 is used to connect drive signals and control the on and off of the device. The three work together to ensure the precise connection between the device and the external circuit.

[0023] Structural Description: Housing 1: As the outer shell of the entire device, it encloses all the core semiconductor structures inside, and plays the role of insulation, protection of the internal structure and isolation of external interference. It provides a stable mounting carrier for the internal components, ensures that the components are fixed in position and work together, and at the same time avoids damage to the internal semiconductor structure by the external environment, thus ensuring the overall structural integrity and operational stability of the device. Auxiliary mounting plate 2: It is fixedly connected to the top of the housing 1 and is provided with auxiliary mounting holes to realize the overall fixed installation of the device. It plays a role in positioning and fixing, ensuring that the device is stable in position during operation, avoiding device displacement and poor pin contact due to vibration and other factors, and improving the ease of device installation and assembly efficiency. Source S pin 3: It is fixedly connected to one side of the bottom of the housing 1 and is used to output current. It serves as the current output interface between the device and the external circuit. Its position is reasonably arranged with the drain D pin 4 and the gate G pin 5, with clear division of labor, to ensure precise connection with the external circuit, ensure stable current output, and help the power conversion process to be completed smoothly. Drain pin 4: Located on the side of source pin 3 and fixedly connected to the bottom of housing 1, it is used to input current and serves as the current input interface between the device and external circuits. It works in conjunction with source pin 3 and gate pin 5 to define the current transmission path and ensure that the current flows into the device in an orderly manner, providing a basis for power conversion. Gate G pin 5: Located on the other side of drain D pin 4, it is fixedly connected to the bottom of housing 1 and is used to receive drive signals to control the on and off of the device. Its position is close to the internal gate-related structure, which can shorten the drive signal transmission path, ensure the fast and stable transmission of drive signals, and ensure the timeliness and accuracy of device switching control. Heat sink 6: Fixedly connected to the bottom of housing 1, it is used to conduct heat generated during device operation in a timely manner, avoid heat accumulation affecting device performance, reduce device operating temperature through rapid heat dissipation, ensure long-term stable operation of device, extend device life, and at the same time reduce the design requirements of additional heat dissipation structures, thus improving device practicality. Drain metal layer 7: It is fixedly connected to the bottom of the gradient doped drift layer 8 and located inside the housing 1. As an intermediate carrier for current transmission, it receives the current flowing in from the drain D pin 4 and transmits it to the gradient doped drift layer 8. It is made of highly conductive material, which can reduce the resistance loss during current transmission, help reduce conduction loss, and achieve efficient power transmission. Gradient doped drift layer 8: It is fixedly connected to the bottom of the source region 10 and the top of the drain metal layer 7, and is located inside the housing 1. A dielectric trench-assisted depletion structure layer 14 is provided on it. The gradient doping design can effectively improve the current carrying capacity of the drift region and reduce the specific on-resistance while ensuring the device's voltage withstand performance. At the same time, in conjunction with the dielectric trench-assisted depletion structure layer 14, it further optimizes the device's voltage withstand and low-loss performance. Source metal layer 9: As a component of the fast response component, it is fixedly connected inside the housing 1, and the bottom is fixedly connected to the source region 10. It is used to receive the current transmitted from the source region 10 and deliver it to the source S pin 3. It is made of highly conductive material, which can reduce the resistance loss during current transmission and reduce the conduction loss. At the same time, it provides a mounting base for the gate-related structure and helps to realize the fast response characteristics of the device. Source region 10: It is fixedly connected to the bottom of the source metal layer 9 and the top of the gradient doped drift layer 8, and is located inside the housing 1. It works together with the source metal layer 9 and the gradient doped drift layer 8 to form a current transmission path, and at the same time provides a mounting carrier for the gate trench 11. It forms a conductive channel with the gate-related structure to ensure that the device can be turned on and off normally and to ensure stable current transmission. Gate trench 11: It is disposed on the source metal layer 9 and the source region 10, and a high-K gate dielectric layer 12 and a gate metal electrode 13 are fixedly connected inside. Its structural design can increase the contact area between the gate and the channel, shorten the charge transport path, accelerate the gate charging and discharging process, help improve the switching response speed of the device, and at the same time provide a stable mounting space for the gate-related structure to ensure the stable realization of the gate control function. High-K gate dielectric layer 12: It is fixedly connected in the gate trench 11 and the gate metal electrode 13 is fixedly connected on it. It has excellent charge storage and isolation performance, can quickly accumulate charge, reduce gate leakage capacitance and total gate charge, accelerate the gate charging and discharging process, improve the device switching response speed, and at the same time play an insulating role to prevent short circuit between the gate metal electrode 13 and the source region 10 and the source metal layer 9, and ensure the stability of switching control. Gate metal electrode 13: It is fixedly connected to the high-K gate dielectric layer 12 and disposed in the gate trench 11. It is used to receive the drive signal transmitted by the gate G pin 5, generate an electric field and act on the source region 10 and the source metal layer 9 through the high-K gate dielectric layer 12 to form a conductive channel, and control the turn-on and turn-off of the device. Its placement in the gate trench 11 can ensure the accuracy of the electric field action and further improve the switching response speed and control stability of the device. Dielectric trench assisted depletion structure layer 14: It is disposed on the gradient doped drift layer 8 and works in synergy with the gradient doped drift layer 8 to assist the gradient doped drift layer 8 in achieving depletion. While ensuring the device's withstand voltage performance, it further improves the current carrying capacity of the drift region, reduces the specific on-resistance, helps reduce the device's conduction loss, and optimizes the device's electric field distribution to improve the device's operating stability.

[0024] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.

Claims

1. An ultrafast response, low conduction loss power MOSFET, comprising a housing (1), characterized in that: An auxiliary mounting plate (2) is fixedly connected to the top of the housing (1). A source S pin (3) is fixedly connected to one side of the bottom of the housing (1). A drain D pin (4) is provided on one side of the source S pin (3). A gate G pin (5) is provided on the other side of the drain D pin (4). Both the drain D pin (4) and the gate G pin (5) are fixedly connected to the bottom of the housing (1). A fast response component is provided on the housing (1). The fast response component includes a source metal layer (9). The source metal layer (9) is fixedly connected inside the housing (1).

2. The ultrafast response low conduction loss power MOSFET according to claim 1, characterized in that: A heat sink (6) is fixedly connected to the bottom of the housing (1).

3. The ultrafast response low conduction loss power MOSFET according to claim 1, characterized in that: The source metal layer (9) is fixedly connected to the bottom of the source region (10), and gate trenches (11) are provided on the source metal layer (9) and the source region (10).

4. The ultrafast response low conduction loss power MOSFET according to claim 3, characterized in that: A high-K gate dielectric layer (12) is fixedly connected inside the gate trench (11), and a gate metal electrode (13) is fixedly connected on the high-K gate dielectric layer (12). The gate metal electrode (13) is disposed inside the gate trench (11).

5. The ultrafast response low conduction loss power MOSFET according to claim 2, characterized in that: The source region (10) is fixedly connected to a gradient doped drift layer (8) at the bottom, and a drain metal layer (7) is fixedly connected to the bottom of the gradient doped drift layer (8).

6. A power MOSFET with ultrafast response and low conduction loss according to claim 3 or 5, characterized in that: The drain metal layer (7), gradient doped drift layer (8), and source region (10) are all disposed inside the housing (1).

7. The ultrafast response low conduction loss power MOSFET according to claim 5, characterized in that: A dielectric trench-assisted depletion structure layer (14) is provided on the gradient doped drift layer (8).

8. The ultrafast response low conduction loss power MOSFET according to claim 1, characterized in that: The auxiliary mounting plate (2) is provided with auxiliary mounting holes.

Images