Relaxation oscillator and signal control method

Abstract

The application discloses a relaxation oscillator and a signal control method. The relaxation oscillator comprises a first capacitor and a second capacitor, a reference generating circuit, a charging switch, a discharging switch, a processing circuit, a comparison unit and a switch control logic circuit. According to the relaxation oscillator and the signal control method, the variation of the on-resistance of the switch is reduced by the complementary switch circuit, the influence of the on-resistance of the single switch on the vibration frequency accuracy is compensated, the non-overlapping control signals are generated by the switch control logic circuit to control the charging switch, the leakage current is prevented from being generated by the simultaneous on of the charging switch, and the threshold voltage of the comparison unit is controlled by the processing circuit to compensate the delay time of the comparison unit.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to a relaxation oscillator and a signal control method. Background Technology

[0002] Resistive-capacitive relaxor oscillators offer advantages such as fast startup, low power consumption, and ease of integration on CMOS chips, making them widely used in microcontrollers, smart sensors, and other applications. Their basic principle involves periodically charging and discharging a capacitor via a switch to generate an oscillation signal at a fixed frequency.

[0003] like Figure 1 As shown, a commonly used resistive-capacitive relaxation oscillator includes: a bias reference current IREF, a reference resistor R1, two capacitors C1 and C2, a charge / discharge switch controlled by control signals Φ1 and Φ2, two comparators, and an SR latch. A reference voltage VREF is generated through the bias reference current IREF and the reference resistor R1. The other two bias reference currents IREF charge capacitors C1 and C2. When the plate voltage VX of capacitor C1 or the plate voltage VY of capacitor C2 exceeds the reference voltage VREF, the corresponding discharge switch is controlled to discharge the capacitor. This alternating charging and discharging of capacitors C1 and C2 generates an oscillation signal with an oscillation period T≈2RC, where R is the resistance of the reference resistor R1, and C is the capacitance of capacitors C1 and C2.

[0004] On the one hand, the comparator has a certain toggle delay time Tdelay, which causes a time delay between the capacitor charging above the reference voltage VREF and the closing of the discharge switch. On the other hand, the charging switch on-resistance Ron is superimposed on the capacitor plate voltage. By derivation, the oscillation period T = 2(R + Ron)C + 2Tdelay. Both the delay time Tdelay and the on-resistance Ron vary greatly with process angle, power supply voltage and temperature, thus reducing the accuracy of the oscillation frequency.

[0005] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to provide a relaxor oscillator and a signal control method that can compensate for the on-resistance of the charging switch and the comparator switching delay, which vary with process angle, power supply voltage and temperature, so as to improve the accuracy of the oscillator output frequency.

[0007] To achieve the above objectives, embodiments of the present invention provide a relaxation oscillator, comprising: a first capacitor and a second capacitor, a reference generation circuit, a first charging switch and a second charging switch, a first discharging switch and a second discharging switch, a processing circuit, and a comparison unit.

[0008] A reference generation circuit generates a reference voltage and a reference current. The first terminals of the first and second charging switches are connected to the reference generation circuit to receive the reference current. The second terminals of the first and second charging switches are respectively connected to the first terminals of the first and second capacitors, and are used to alternately open to charge the first and second capacitors respectively using the reference current. The two terminals of the first discharge switch are respectively connected to the two terminals of the first capacitor, and the two terminals of the second discharge switch are respectively connected to the two terminals of the second capacitor, and are used to alternately open to discharge the first and second capacitors respectively. A processing circuit averages the voltage at the common node connecting the first terminals of the first and second charging switches, which varies with the voltage at the first terminal of the first capacitor or the first terminal of the second capacitor, and compares this averaged value with the reference voltage to output a comparison voltage. A comparison unit compares the voltages on the first and second capacitors with the comparison voltage and outputs a comparison signal.

[0009] In one or more embodiments of the present invention, the relaxor oscillator further includes a switch control logic circuit for outputting control signals for controlling the first charging switch and the second charging switch, the first discharging switch and the second discharging switch based on a comparison signal.

[0010] In one or more embodiments of the present invention, the first charging switch and the second charging switch are both complementary CMOS switches, each including an NMOS transistor and a PMOS transistor. The drain of the NMOS transistor is connected to the source of the PMOS transistor, and the source of the NMOS transistor is connected to the drain of the PMOS transistor. The gates of the NMOS transistor and the PMOS transistor are used to receive control signals.

[0011] In one or more embodiments of the present invention, the substrate of the NMOS transistor is connected to the source, and the substrate of the PMOS transistor is connected to the source.

[0012] In one or more embodiments of the present invention, the relaxor oscillator further includes a voltage regulator unit, a first terminal of which is connected to the input terminal of the processing circuit, and a second terminal of which is connected to a common node connecting the first terminals of the first charging switch and the second charging switch.

[0013] In one or more embodiments of the present invention, the voltage regulator unit includes a second resistor.

[0014] In one or more embodiments of the present invention, the comparison unit includes a first comparator and a second comparator. The first input terminal of the first comparator is connected to the first terminal of the first capacitor, the second input terminal of the first comparator is used to receive a comparison voltage, and the output terminal of the first comparator is used to output a first comparison signal. The first input terminal of the second comparator is connected to the first terminal of the second capacitor, the second input terminal of the second comparator is used to receive a comparison voltage, and the output terminal of the second comparator is used to output a second comparison signal.

[0015] In one or more embodiments of the present invention, the switch control logic circuit includes a first NAND gate, a second NAND gate, a first NOT gate, a second NOT gate, a third NOT gate, a fourth NOT gate, a fifth NOT gate, a sixth NOT gate, a seventh NOT gate, and an eighth NOT gate;

[0016] The first input terminal of the first NAND gate is used to receive a comparison signal. The output terminal of the first NAND gate is connected to the input terminal of the first NOT gate. The input terminal of the second NOT gate is connected to the output terminal of the first NOT gate. The input terminal of the third NOT gate is connected to the output terminal of the second NOT gate and the first input terminal of the second NAND gate. The input terminal of the fourth NOT gate is connected to the output terminal of the third NOT gate. The output terminal of the third NOT gate is used to output a first control signal. The output terminal of the fourth NOT gate is used to output a second control signal.

[0017] The second input terminal of the second NAND gate is used to receive a comparison signal. The output terminal of the second NAND gate is connected to the input terminal of the fifth NOT gate. The input terminal of the sixth NOT gate is connected to the output terminal of the fifth NOT gate. The input terminal of the seventh NOT gate is connected to the output terminal of the sixth NOT gate and the second input terminal of the first NAND gate. The input terminal of the eighth NOT gate is connected to the output terminal of the seventh NOT gate. The output terminal of the seventh NOT gate is used to output a third control signal. The output terminal of the eighth NOT gate is used to output a fourth control signal.

[0018] In one or more embodiments of the present invention, the reference generation circuit includes a current source, a current mirror unit, and a first resistor. The current source is used to provide a reference current. The current mirror unit is connected to the current source, the first resistor, a first charging switch, and a second charging switch. The current mirror unit is used to copy the reference current and transmit it to the first resistor, the first charging switch, and the second charging switch. The first resistor generates a reference voltage based on the reference current flowing through it.

[0019] In one or more embodiments of the present invention, the processing circuit includes an amplifier, a third resistor, and a third capacitor. The first input terminal of the amplifier is used to receive a reference voltage. The first terminal of the third resistor is connected to a common node connecting the first terminals of the first charging switch and the second charging switch. The second terminal of the third resistor is connected to the second input terminal of the amplifier. The first terminal of the third capacitor is connected to the second input terminal of the amplifier. The second terminal of the third capacitor is connected to the output terminal of the amplifier. The output terminal of the amplifier is used to output a comparison voltage.

[0020] This invention also discloses a signal control method for a relaxor oscillator, comprising:

[0021] A reference voltage and reference current are generated through a reference generation circuit;

[0022] The reference current is received through the first charging switch and the second charging switch, and the first capacitor and the second capacitor are charged respectively by the reference current through the alternating opening of the first charging switch and the second charging switch.

[0023] The first capacitor and the second capacitor are discharged by alternately opening the first discharge switch and the second discharge switch respectively;

[0024] The processing circuit takes the average value of the voltage at the common node connecting the first terminals of the first charging switch and the second charging switch, which varies with the voltage at the first terminal of the first capacitor or the first terminal of the second capacitor, and compares it with a reference voltage to output a comparison voltage.

[0025] The comparison unit compares the voltages on the first and second capacitors with the comparison voltage and outputs a comparison signal.

[0026] In one or more embodiments of the present invention, the signal control method further includes:

[0027] The control logic circuit outputs control signals for the first charging switch, the second charging switch, the first discharging switch, and the second discharging switch based on the comparison signal.

[0028] In one or more embodiments of the present invention, the control signals for controlling the first charging switch and the second charging switch are non-overlapping signals, and the control signals for controlling the first discharging switch and the second discharging switch are also non-overlapping signals.

[0029] Compared with existing technologies, the relaxation oscillator and signal control method according to embodiments of the present invention reduce the variation in switch on-resistance through complementary switching circuits, compensating for the influence of the on-resistance of a single switch on the accuracy of the oscillation frequency; generate non-overlapping control signals through switch control logic circuits to control the first and second charging switches, preventing leakage current caused by simultaneous conduction of the first and second charging switches; and control the threshold voltage of the comparison unit through processing circuits to compensate for the delay time of the comparison unit. The present invention has a simple structure and effectively improves the accuracy of the oscillation frequency without increasing the overall circuit power consumption. Attached Figure Description

[0030] Figure 1 This is a circuit diagram of a relaxation oscillator using existing technology.

[0031] Figure 2 This is a circuit schematic diagram of a relaxation oscillator according to Embodiment 1 of the present invention.

[0032] Figure 3 This is a circuit diagram of the switch control logic circuit according to Embodiment 1 of the present invention.

[0033] Figure 4 This is a waveform diagram of the control signal according to Embodiment 1 of the present invention.

[0034] Figure 5 This is a flowchart of a signal control method according to Embodiment 1 of the present invention. Detailed Implementation

[0035] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings, but it should be understood that the scope of protection of the present invention is not limited to the specific embodiments.

[0036] Unless otherwise expressly stated, throughout the specification and claims, the term "comprising" or its variations such as "including" or "comprises" shall be understood to include the stated elements or components without excluding other elements or other components.

[0037] The terms "coupled," "connected," or "linked" in this specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrical conduction medium, which may have parasitic inductance or capacitance. Indirect connections may also include connections made through other active or passive devices to achieve the same or similar functional purpose, such as connections through switches, follower circuits, or other circuits or components. Furthermore, in this invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another, and do not necessarily require or imply any actual relationship, quantity, or order between these technical features.

[0038] like Figure 2 As shown, a relaxation oscillator includes: a reference generation circuit 10, a voltage regulation unit 20, a first charging switch, a second charging switch, a first discharging switch M8, a second discharging switch M9, a processing circuit 30, a comparison unit 40, a switch control logic circuit 50, a first capacitor C1, and a second capacitor C2.

[0039] The reference generation circuit 10 is used to generate the reference voltage VREF and the reference current IREF.

[0040] The first terminals of the first charging switch and the second charging switch are connected to the reference generation circuit 10 to receive data. The second terminals of the first charging switch and the second charging switch are respectively connected to the first terminal of the first capacitor C1 and the first terminal of the second capacitor C2. By alternately turning on the first charging switch and the second charging switch, the first capacitor C1 and the second capacitor C2 are charged by the reference current IREF respectively.

[0041] The two ends of the first discharge switch M8 are connected to the two ends of the first capacitor C1, and the two ends of the second discharge switch M9 are connected to the two ends of the second capacitor C2, respectively, for alternating opening to discharge the first capacitor C1 and the second capacitor C2 respectively.

[0042] The first terminal of the voltage regulator unit 20 is connected to the input terminal of the processing circuit 30, and the second terminal of the voltage regulator unit 20 is connected to the common node connecting the first terminals of the first charging switch and the second charging switch.

[0043] The processing circuit 30 is used to average the voltage VM at the first terminal of the voltage regulator unit 20 and compare it with the reference voltage VREF to output a comparison voltage VC.

[0044] Comparison unit 40 is used to compare the voltages on the first capacitor C1 and the second capacitor C2 with the comparison voltage VC and output comparison signals VCMP and VCMN;

[0045] The switch control logic circuit 50 is used to output control signals Φ1P, Φ1N, Φ2P, and Φ2N based on the comparison signals VCMP and VCMN to control the first charging switch, the second charging switch, the first discharging switch M8, and the second discharging switch M9.

[0046] like Figure 2 As shown, the reference generation circuit 10 includes a current source A, a current mirror unit, and a first resistor R1.

[0047] Current source A is used to provide reference current IREF. The current mirror unit is connected to current source A, first resistor R1 and complementary switching circuit. The current mirror unit is used to copy the reference current IREF and send it to first resistor R1, first charging switch and second charging switch. First resistor R1 generates reference voltage VREF based on the reference current IREF flowing through it.

[0048] The current mirror unit includes a first MOSFET M1, a second MOSFET M2, and a third MOSFET M3. The sources of the first MOSFET M1, second MOSFET M2, and third MOSFET M3 are connected to the power supply voltage VDD, and the gates of the first MOSFET M1, second MOSFET M2, and third MOSFET M3 are interconnected. The gate and drain of the first MOSFET M1 are connected and simultaneously connected to the first terminal of current source A, and the second terminal of current source A is connected to ground. The drain of the second MOSFET M2 is connected to the first terminal of the first resistor R1. One of the replicated reference currents IREF flows through the first resistor R1 and outputs a reference voltage VREF at the first terminal of the first resistor R1. The second terminal of the first resistor R1 is connected to ground. The drain of the third MOSFET M3 is the output terminal of the reference generation circuit 10. Another replicated reference current IREF flows out from the drain of the third MOSFET M3 and flows into the complementary switching circuit through the voltage regulator unit 20. In this embodiment, the first MOSFET M1, the second MOSFET M2, and the third MOSFET M3 are all P-channel MOSFETs. In other embodiments, the first MOSFET M1, the second MOSFET M2, and the third MOSFET M3 can be N-channel MOSFETs.

[0049] In this embodiment, the current mirror unit is a single-layer structure. In other embodiments, it can also be a multi-layer structure, i.e., a cascode current mirror, thereby improving the accuracy of current replication and the stability of the current.

[0050] like Figure 2 As shown, the voltage regulator unit 20 includes a second resistor R2. The first end of the second resistor R2 is connected to the drain of the third MOSFET M3 to generate a voltage VM. The second end of the second resistor R2 is connected to the first end of the first charging switch and the first end of the second charging switch. The voltage regulator unit 20 regulates the voltage VM and prevents excessive charging current to the first capacitor C1 or the second capacitor C2 when the switch is turned on. In other embodiments, the second resistor R2 may be omitted.

[0051] like Figure 2 As shown, both the first charging switch and the second charging switch are complementary CMOS switches.

[0052] The first charging switch includes a first NMOS transistor M4 and a first PMOS transistor M5. The drain of the first NMOS transistor M4 is connected to the source of the first PMOS transistor M5 and is also connected to the second terminal of the second resistor R2. The source of the first NMOS transistor M4 is connected to the drain of the first PMOS transistor M5 and is also connected to the first terminal of the first capacitor C1. The gate of the first NMOS transistor M4 is used to receive the first control signal Φ1N, and the gate of the first PMOS transistor M5 is used to receive the second control signal Φ1P.

[0053] The second charging switch includes a second NMOS transistor M6 and a second PMOS transistor M7. The drain of the second NMOS transistor M6 is connected to the source of the second PMOS transistor M7 and is also connected to the second terminal of the second resistor R2. The source of the second NMOS transistor M6 is connected to the drain of the second PMOS transistor M7 and is also connected to the first terminal of the second capacitor C2. The gate of the second NMOS transistor M6 is used to receive the third control signal Φ2N, and the gate of the second PMOS transistor M7 is used to receive the fourth control signal Φ2P.

[0054] The substrate of the first NMOS transistor M4 is connected to its source, the substrate of the first PMOS transistor M5 is connected to its source, the substrate of the second NMOS transistor M6 is connected to its source, and the substrate of the second PMOS transistor M7 is connected to its source, thereby reducing their respective on-resistance. The first NMOS transistor M4 and the second NMOS transistor M6 are N-channel MOS transistors, and the first PMOS transistor M5 and the second PMOS transistor M7 are P-channel MOS transistors. In other embodiments, the first NMOS transistor M4, the second NMOS transistor M6, the first PMOS transistor M5, and the second PMOS transistor M7 can be replaced by other switches.

[0055] In this embodiment, an NMOS transistor and a PMOS transistor are connected in parallel to form a complementary CMOS switch. The substrate is connected to the source. Compared with a switch composed of a single MOS transistor, it has a smaller on-resistance and its impedance is less affected by changes in power supply voltage and temperature, which reduces the influence of the switch on-resistance on the oscillation period to a certain extent.

[0056] like Figure 2 As shown, the drain of the first discharge switch M8 is connected to the first terminal of the first capacitor C1, and the source of the first discharge switch M8 is connected to the second terminal of the first capacitor C1 and ground. When the first discharge switch M8 is turned on, the first capacitor C1 discharges to ground. The drain of the second discharge switch M9 is connected to the first terminal of the second capacitor C2, and the source of the second discharge switch M9 is connected to the second terminal of the second capacitor C2 and ground. When the second discharge switch M9 is turned on, the second capacitor C2 discharges to ground. The gate of the first discharge switch M8 is used to receive the third control signal Φ2N, and the gate of the second discharge switch M9 is used to receive the first control signal Φ1N.

[0057] In this embodiment, both the first discharge switch M8 and the second discharge switch M9 are N-channel MOSFETs. In other embodiments, the first discharge switch M8 and the second discharge switch M9 can be P-channel MOSFETs.

[0058] like Figure 2 As shown, the processing circuit 30 includes an amplifier EA, a third resistor R3, and a third capacitor C3.

[0059] The first terminal of the third resistor R3 is connected to the common node connecting the first terminals of the first and second charging switches. Specifically, the first terminal of the third resistor R3 is connected to the drain of the third MOSFET M3 and the first terminal of the second resistor R2. The second terminal of the third resistor R3 is connected to the second input terminal of amplifier EA, and the first input terminal of amplifier EA is used to receive the reference voltage VREF. The first terminal of the third capacitor C3 is connected to the second input terminal of amplifier EA, and the second terminal of the third capacitor C3 is connected to the output terminal of amplifier EA, which is used to output the comparison voltage VC.

[0060] In this embodiment, the first input terminal of amplifier EA is a positive input terminal, and the second input terminal of amplifier EA is a negative input terminal. In other embodiments, the positive and negative input terminals of amplifier EA can be interchanged.

[0061] like Figure 2 As shown, the comparison unit 40 includes a first comparator CMP1 and a second comparator CMP2. The first input terminal of the first comparator CMP1 is connected to the first terminal of the first capacitor C1 to receive the voltage VX at the first terminal of the first capacitor C1. The second input terminal of the first comparator CMP1 is used to receive the comparison voltage VC. The output terminal of the first comparator CMP1 is used to output a first comparison signal VCMP. The first input terminal of the second comparator CMP2 is connected to the first terminal of the second capacitor C2 to receive the voltage VY at the first terminal of the second capacitor C2. The second input terminal of the second comparator CMP2 is used to receive the comparison voltage VC. The output terminal of the second comparator CMP2 is used to output a second comparison signal VCMN.

[0062] In this embodiment, the first input terminal of the first comparator CMP1 and the first input terminal of the second comparator CMP2 are both positive input terminals, and the second input terminals of the first comparator CMP1 and the second comparator CMP2 are both negative input terminals. In other embodiments, the positive and negative input terminals of the first comparator CMP1 and the second comparator CMP2 can be interchanged.

[0063] like Figure 3As shown, the switch control logic circuit 50 includes a first NAND gate NAND1, a second NAND gate NAND2, a first NOT gate N1, a second NOT gate N2, a third NOT gate N3, a fourth NOT gate N4, a fifth NOT gate N5, a sixth NOT gate N6, a seventh NOT gate N7, and an eighth NOT gate N8.

[0064] The first input of the first NAND gate NAND1 is used to receive the first comparison signal VCMP. The output of the first NAND gate NAND1 is connected to the input of the first NOT gate N1. The input of the second NOT gate N2 is connected to the output of the first NOT gate N1. The input of the third NOT gate N3 is connected to the output of the second NOT gate N2 and the first input of the second NAND gate NAND2. The input of the fourth NOT gate N4 is connected to the output of the third NOT gate N3. The output of the third NOT gate N3 is used to output the first control signal Φ1N. The output of the fourth NOT gate N4 is used to output the second control signal Φ1P.

[0065] The second input of the second NAND gate NAND2 is used to receive the second comparison signal VCMN. The output of the second NAND gate NAND2 is connected to the input of the fifth NOT gate N5. The input of the sixth NOT gate N6 is connected to the output of the fifth NOT gate N5. The input of the seventh NOT gate N7 is connected to the output of the sixth NOT gate N6 and the second input of the first NAND gate NAND1. The input of the eighth NOT gate N8 is connected to the output of the seventh NOT gate N7. The output of the seventh NOT gate N7 is used to output the third control signal Φ2N. The output of the eighth NOT gate N8 is used to output the fourth control signal Φ2P.

[0066] like Figure 4 As shown, the first control signal Φ1N and the second control signal Φ1P are a set of control signals for controlling the first charging switch, and the third control signal Φ2N and the fourth control signal Φ2P are a set of control signals for controlling the second charging switch. Specifically, the first control signal Φ1N and the second control signal Φ1P are inverted signals to control the first NMOS transistor M4 and the first PMOS transistor M5 of the first charging switch to simultaneously turn on and off; the third control signal Φ2N and the fourth control signal Φ2P are inverted signals to control the second NMOS transistor M6 and the second PMOS transistor M7 of the second charging switch to simultaneously turn on and off. Furthermore, the first control signal Φ1N and the third control signal Φ2N, and the second control signal Φ1P and the fourth control signal Φ2P, form non-overlapping signals to prevent leakage current caused by the simultaneous conduction of the first and second charging switches.

[0067] When the first control signal Φ1N is high and the second control signal Φ1P is low, the first charging switch is turned on and the second discharging switch M9 is turned on, thereby charging the first capacitor C1 and discharging the second capacitor C2; when the third control signal Φ2N is high and the fourth control signal Φ2P is low, the second charging switch is turned on and the first discharging switch M8 is turned on, thereby charging the second capacitor C2 and discharging the first capacitor C1.

[0068] The node generating voltage VM is a common node, reflecting the voltage at the first terminal of the first capacitor C1 or the voltage at the first terminal of the second capacitor C2 at different time periods. In one time cycle, the first charging switch is on and the first discharging switch M8 is off, charging the first capacitor C1. The VM potential increases continuously with the voltage at the first terminal of the first capacitor C1. In the next time cycle, the second charging switch is on and the second discharging switch M9 is off, charging the second capacitor C2. Through non-overlapping control, the first and second charging switches will not be on simultaneously. At this time, the first charging switch is off, and the VM potential is no longer controlled by the voltage at the first terminal of the first capacitor C1, but increases continuously with the voltage at the first terminal of the second capacitor C2.

[0069] This application uses a common node VM to alternately reflect the charging voltage of two capacitors in a time-sharing manner, thereby monitoring for overshoot issues caused by comparator delays. To ensure that the common node VM accurately reflects the charging voltage of the two capacitors, this application employs non-overlapping control, preventing the first and second charging switches from conducting simultaneously. This avoids the problem of the second charging switch being turned on when the VM is representing the charging voltage of the first capacitor C1, which could lead to leakage current and affect the voltage VM.

[0070] When temperature or power supply voltage VDD causes an increase in the delay of the first comparator CMP1 and the second comparator CMP2, the peak charging voltages of voltages VX and VY will increase and be reflected in voltage VM. After the processing circuit 30 averages the voltage VM, it is compared with the reference voltage VREF to output a comparison voltage VC. Based on the comparison voltage VC, the first comparator CMP1 and the second comparator CMP2 can flip earlier, the capacitor charging time is shortened, thereby compensating for the delay time of the comparators and effectively improving the accuracy of the oscillation frequency.

[0071] like Figure 5 As shown, the present invention also discloses a signal control method for a relaxor oscillator, comprising:

[0072] The reference voltage VREF and reference current IREF are generated by the reference generation circuit 10.

[0073] The reference current is received through the first charging switch and the second charging switch, and the first capacitor C1 and the second capacitor C2 are charged by the reference current IREF through the alternating opening of the first charging switch and the second charging switch.

[0074] The first capacitor C1 and the second capacitor C2 are discharged by alternately opening the first discharge switch and the second discharge switch respectively.

[0075] The processing circuit 30 averages the voltage of the common node connecting the first terminals of the first charging switch and the second charging switch, which varies with the voltage of the first terminal of the first capacitor C1 or the first terminal of the second capacitor C2, and compares it with the reference voltage VREF to output a comparison voltage VC.

[0076] The comparison unit 40 compares the voltages on the first capacitor C1 and the second capacitor C2 with the comparison voltage VC and outputs comparison signals VCMP and VCMN.

[0077] The switch control logic circuit 50 outputs control signals Φ1N, Φ1P, Φ2N, and Φ2P based on the comparison signals VCMP and VCMN to control the first charging switch, the second charging switch, the first discharging switch M8, and the second discharging switch M9. Control signals Φ1N and Φ2N are non-overlapping signals, as are control signals Φ1P and Φ2P.

[0078] The foregoing description of specific exemplary embodiments of the invention is for illustrative and explanatory purposes. These descriptions are not intended to limit the invention to the precise forms disclosed, and it will be apparent that many changes and variations can be made in accordance with the foregoing teachings; the invention can be implemented in other forms, structures, arrangements, proportions, and with other components, materials, and parts. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application, thereby enabling those skilled in the art to implement and utilize various different exemplary embodiments and various different choices and modifications of the invention without departing from the scope and spirit of the invention. The scope of the invention is intended to be defined by the claims and their equivalents.

Claims

1. A relaxation oscillator characterized by, include: First capacitor and second capacitor; The reference generation circuit is used to generate reference voltage and reference current; A first charging switch and a second charging switch, the first terminals of the first charging switch and the second charging switch are connected to a reference generating circuit to receive a reference current, and the second terminals of the first charging switch and the second charging switch are respectively connected to the first terminals of the first capacitor and the second capacitor, for alternating switching on to charge the first capacitor and the second capacitor respectively through the reference current. A first discharge switch and a second discharge switch, wherein the two ends of the first discharge switch are respectively connected to the two ends of the first capacitor, and the two ends of the second discharge switch are respectively connected to the two ends of the second capacitor, for alternating switching on to discharge the first capacitor and the second capacitor respectively. The processing circuit is used to average the voltage of the common node connecting the first terminals of the first charging switch and the second charging switch, which varies with the voltage of the first terminal of the first capacitor or the first terminal of the second capacitor, and compare it with a reference voltage to output a comparison voltage. The comparison unit is used to compare the voltages on the first capacitor and the second capacitor with the comparison voltage and output a comparison signal. The relaxation oscillator further includes a voltage regulator unit. The first terminal of the voltage regulator unit is connected to the input terminal of the processing circuit and the output terminal of the reference generation circuit to receive the reference current. The second terminal of the voltage regulator unit is connected to the first terminal of the first charging switch and the second charging switch. The relaxation oscillator also includes a switch control logic circuit, which is used to output control signals for controlling the first charging switch and the second charging switch, the first discharging switch and the second discharging switch based on the comparison signal. The switch control logic circuit includes a first NAND gate, a second NAND gate, a first NOT gate, a second NOT gate, a third NOT gate, a fourth NOT gate, a fifth NOT gate, a sixth NOT gate, a seventh NOT gate, and an eighth NOT gate; The first input terminal of the first NAND gate is used to receive a comparison signal. The output terminal of the first NAND gate is connected to the input terminal of the first NOT gate. The input terminal of the second NOT gate is connected to the output terminal of the first NOT gate. The input terminal of the third NOT gate is connected to the output terminal of the second NOT gate and the first input terminal of the second NAND gate. The input terminal of the fourth NOT gate is connected to the output terminal of the third NOT gate. The output terminal of the third NOT gate is used to output a first control signal. The output terminal of the fourth NOT gate is used to output a second control signal. The second input terminal of the second NAND gate is used to receive a comparison signal. The output terminal of the second NAND gate is connected to the input terminal of the fifth NOT gate. The input terminal of the sixth NOT gate is connected to the output terminal of the fifth NOT gate. The input terminal of the seventh NOT gate is connected to the output terminal of the sixth NOT gate and the second input terminal of the first NAND gate. The input terminal of the eighth NOT gate is connected to the output terminal of the seventh NOT gate. The output terminal of the seventh NOT gate is used to output a third control signal. The output terminal of the eighth NOT gate is used to output a fourth control signal. Both the first charging switch and the second charging switch are complementary CMOS switches, each including an NMOS transistor and a PMOS transistor. The drain of the NMOS transistor is connected to the source of the PMOS transistor, and the source of the NMOS transistor is connected to the drain of the PMOS transistor. The gate of the NMOS transistor of the first charging switch is connected to the output of a third NOT gate to receive a first control signal. The gate of the PMOS transistor of the first charging switch is connected to the output of a fourth NOT gate to receive a second control signal. The gate of the NMOS transistor of the second charging switch is connected to the output of a seventh NOT gate to receive a third control signal. The gate of the PMOS transistor of the second charging switch is connected to the output of an eighth NOT gate to receive a fourth control signal.

2. The relaxation oscillator of claim 1, wherein, The substrate of the NMOS transistor is connected to the source, and the substrate of the PMOS transistor is connected to the source.

3. The relaxation oscillator of claim 1, wherein, The voltage regulator unit includes a second resistor.

4. The relaxation oscillator of claim 1, wherein, The comparison unit includes a first comparator and a second comparator. The first input terminal of the first comparator is connected to the first terminal of the first capacitor. The second input terminal of the first comparator is used to receive a comparison voltage. The output terminal of the first comparator is used to output a first comparison signal. The first input terminal of the second comparator is connected to the first terminal of the second capacitor. The second input terminal of the second comparator is used to receive a comparison voltage. The output terminal of the second comparator is used to output a second comparison signal.

5. The relaxation oscillator of claim 1, wherein, The reference generation circuit includes a current source, a current mirror unit, and a first resistor. The current source is used to provide a reference current. The current mirror unit is connected to the current source, the first resistor, a first charging switch, and a second charging switch. The current mirror unit is used to copy and transmit the reference current to the first resistor, the first charging switch, and the second charging switch. The first resistor generates a reference voltage based on the reference current flowing through it.

6. The relaxation oscillator of claim 1, wherein, The processing circuit includes an amplifier, a third resistor, and a third capacitor. The first input terminal of the amplifier is used to receive a reference voltage. The first terminal of the third resistor is connected to a common node connecting the first terminals of the first charging switch and the second charging switch. The second terminal of the third resistor is connected to the second input terminal of the amplifier. The first terminal of the third capacitor is connected to the second input terminal of the amplifier. The second terminal of the third capacitor is connected to the output terminal of the amplifier. The output terminal of the amplifier is used to output a comparison voltage.

7. A signal control method of a relaxation oscillator, characterized by, Based on the relaxor oscillator according to any one of claims 1 to 6, the signal control method includes: A reference voltage and reference current are generated through a reference generation circuit; The reference current is received through the first charging switch and the second charging switch, and the first capacitor and the second capacitor are charged respectively by the reference current through the alternating opening of the first charging switch and the second charging switch. The first capacitor and the second capacitor are discharged by alternately opening the first discharge switch and the second discharge switch respectively; The processing circuit takes the average value of the voltage at the common node connecting the first terminals of the first charging switch and the second charging switch, which varies with the voltage at the first terminal of the first capacitor or the first terminal of the second capacitor, and compares it with a reference voltage to output a comparison voltage. The comparison unit compares the voltages on the first and second capacitors with the comparison voltage and outputs a comparison signal.

8. The signal control method of a relaxation oscillator according to claim 7, wherein Also includes: The control logic circuit outputs control signals for the first charging switch, the second charging switch, the first discharging switch, and the second discharging switch based on the comparison signal.

9. The signal control method of a relaxation oscillator according to claim 8, wherein The control signals for controlling the first charging switch and the second charging switch are non-overlapping signals, and the control signals for controlling the first discharging switch and the second discharging switch are also non-overlapping signals.

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