Common mode level shifting circuit and clock buffer

Abstract

According to the embodiments of the present application, a common mode level conversion circuit and a clock buffer are disclosed. The common mode level conversion circuit comprises a first level conversion circuit, a first variable current source configured to receive a first input signal to generate a first output signal; a second level conversion circuit, a second variable current source configured to receive a second input signal to generate a second output signal; and a feedback circuit configured to receive the first output signal and the second output signal to output a first feedback signal; wherein the first input signal and the second input signal comprise a first common mode signal, the first output signal and the second output signal comprise a second common mode signal, and the current of the first variable current source and the second variable current source is controlled according to the first feedback signal to make the second common mode signal close to a preset value. The common mode level conversion circuit in the present application has a better signal-to-noise ratio.

Description

Technical Field

[0001] This invention relates to the field of power electronics, and more specifically, to a common-mode level conversion circuit and a clock buffer. Background Technology

[0002] Receivers often encounter problems where the common-mode signal in the input differential signal is too large or too small, which puts high demands on subsequent circuits. Therefore, it is necessary to set up a common-mode level conversion circuit in the receiver to convert the level of the common-mode signal in the input differential signal.

[0003] In existing technologies, the level of the common-mode signal in the input differential signal is converted using a resistor voltage divider. However, while changing the level of the common-mode signal in the input differential signal, this technology also alters the amplitude of the differential-mode signal, thus degrading the signal-to-noise ratio. Summary of the Invention

[0004] In view of this, the present invention proposes a common-mode level conversion circuit and a clock buffer to solve the technical problem that the prior art changes the amplitude of the differential signal in the input differential signal while changing the level of the common-mode signal in the input differential signal.

[0005] In a first aspect, embodiments of the present invention provide a common-mode level conversion circuit, comprising: a first level conversion circuit including a first variable current source configured to receive a first input signal to generate a first output signal; a second level conversion circuit including a second variable current source configured to receive a second input signal to generate a second output signal; and a feedback circuit configured to receive the first output signal and the second output signal and output a first feedback signal; wherein the first input signal and the second input signal include a first common-mode signal, the first output signal and the second output signal include a second common-mode signal, and the currents of the first variable current source and the second variable current source are controlled according to the first feedback signal to make the second common-mode signal approach a preset value.

[0006] Preferably, the current of the first variable current source and the common-mode current of the first level conversion circuit have the same trend of change; the current of the second variable current source and the common-mode current of the second level conversion circuit have the same trend of change; wherein, the common-mode current is configured to be a current generated based on the difference between the first common-mode signal and the second common-mode signal.

[0007] Preferably, when the current of the first variable current source and the second variable current source decreases, the second common-mode signal increases; when the current of the first variable current source and the second variable current source increases, the second common-mode signal decreases.

[0008] Preferably, the differential mode signals in the first input signal and the first output signal are substantially the same, and the differential mode signals in the second input signal and the second output signal are substantially the same.

[0009] Preferably, the feedback circuit includes: a common-mode level extraction circuit configured to receive the first output signal and the second output signal, and output the second common-mode signal; and a first operational amplifier configured to receive the second common-mode signal at its first input terminal, receive a first reference signal representing the preset value at its second input terminal, and output a first feedback signal to the control terminals of the first variable current source and the second variable current source at its output terminal.

[0010] Preferably, the first level conversion circuit further includes: a first RC circuit configured to receive the first input signal at its input terminal and to ground through the first variable current source at its output terminal; and a first fixed current source configured to be coupled between the common terminal of the first RC circuit and the first variable current source and the power supply; wherein the common terminal of the first fixed current source and the first variable current source outputs the first output signal.

[0011] Preferably, the second level conversion circuit further includes: a second RC circuit configured to receive the second input signal at its input terminal and to ground through the second variable current source at its output terminal; and a second fixed current source configured to be coupled between the common terminal of the second RC circuit and the second variable current source and the power supply; wherein the common terminal of the second fixed current source and the second variable current source outputs the second output signal.

[0012] Preferably, the first level conversion circuit further includes a third fixed current source coupled between the common terminal of the first RC circuit and the first variable current source and ground potential.

[0013] Preferably, the second level conversion circuit further includes: a fourth fixed current source coupled between the common terminal of the second RC circuit and the second variable current source and ground potential.

[0014] Preferably, both the first RC circuit and the second RC circuit include a first capacitor and a first resistor connected in parallel. The first end of the first capacitor and the first end of the first resistor are coupled to the input terminal of the corresponding RC circuit, and the second end of the first capacitor and the second end of the first resistor are coupled to the output terminal of the corresponding RC circuit.

[0015] Preferably, the first RC circuit and the second RC circuit further include a second resistor, which is coupled between the input terminal of the respective RC circuit and the ground potential.

[0016] Preferably, both the first variable current source and the second variable current source include at least a first power switch, and the feedback circuit outputs the first feedback signal to the control terminal of the first power switch in the first variable current source and the second variable current source to control the current passing through the first power switch.

[0017] Preferably, both the first variable current source and the second variable current source further include a third resistor, and the first power switch and the third resistor are connected in series between the output terminal of the corresponding level conversion circuit and the ground potential.

[0018] Preferably, both the first variable current source and the second variable current source further include a second power switch, and the second power switch, the first power switch and the third resistor are connected in series between the output terminal of the corresponding level conversion circuit and the ground potential.

[0019] Preferably, the first fixed current source and the second fixed current source include a fourth resistor, coupled between the common terminal of the corresponding RC circuit and the corresponding variable current source and the power supply.

[0020] Preferably, the first fixed current source and the second fixed current source further include at least a third power transistor, the third power transistor and the fourth resistor being connected in series between the common terminal of the corresponding RC circuit and the corresponding variable current source and the power supply.

[0021] Preferably, the third fixed current source and the fourth fixed current source include at least a fifth resistor and a fourth power transistor, wherein the fourth power transistor and the fifth resistor are connected in series and coupled between the common terminal of the corresponding RC circuit and the corresponding variable current source and the ground potential.

[0022] Preferably, the common-mode level extraction circuit includes: a first parallel structure composed of a first common-mode resistor and a first common-mode capacitor coupled in parallel, and a second parallel structure composed of a second common-mode resistor and a second common-mode capacitor coupled in parallel, wherein a first terminal of the first parallel structure receives the first output signal, a second terminal of the first parallel structure is coupled to the first terminal of the second parallel structure, a second terminal of the second parallel structure receives the second output signal, and the common terminal of the first parallel structure and the second parallel structure outputs the second common-mode signal.

[0023] Preferably, the first input signal and the second input signal are configured as input differential signals, and the first output signal and the second output signal are configured as output differential signals.

[0024] Secondly, embodiments of the present invention provide a clock buffer, comprising: any one of the common-mode level conversion circuits described above, configured to convert a first common-mode signal in the first input signal and the second input signal into a second common-mode signal in the first output signal and the second output signal; and a subsequent circuit configured to receive the first output signal and the second output signal to output a clock signal.

[0025] Compared with the prior art, the technical solution of the present invention has the following advantages: The common-mode level conversion circuit of the present invention includes a first level conversion circuit, including a first variable current source configured to receive a first input signal to generate a first output signal; a second level conversion circuit, including a second variable current source configured to receive a second input signal to generate a second output signal; and a feedback circuit configured to receive the first output signal and the second output signal, and output a first feedback signal; wherein the first input signal and the second input signal include a first common-mode signal, the first output signal and the second output signal include a second common-mode signal, and the currents of the first variable current source and the second variable current source are controlled according to the first feedback signal so that the second common-mode signal is close to a preset value. The first input signal and the second input signal are configured as input differential signals, and the first output signal and the second output signal are configured as output differential signals. The common-mode level conversion circuit of the present invention, while converting the level of the common-mode signal in the input differential signal, basically does not change the amplitude of the differential signal in the input differential signal, which has a significant advantage compared with the prior art. The common-mode level conversion circuit of this invention converts a first common-mode signal from the first input signal and the second input signal into a second common-mode signal from the first output signal and the second output signal. This conversion of a wide range of first common-mode signals into second common-mode signals adapts to the common-mode circuitry in subsequent stages, reducing the common-mode level range requirements of those stages. The common-mode level conversion circuit of this invention is compatible with both DC-coupled and AC-coupled operating modes, exhibits a superior signal-to-noise ratio, and demonstrates even greater advantages in DC-coupled operating mode. Attached Figure Description

[0026] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0027] Figure 1 This is a circuit diagram of a first embodiment of the common-mode level conversion circuit of the present invention;

[0028] Figure 2 This is a circuit diagram of Embodiment 2 of the common-mode level conversion circuit of the present invention;

[0029] Figure 3This is a circuit diagram of Embodiment 3 of the common-mode level conversion circuit of the present invention;

[0030] Figure 4 This is a circuit diagram of Embodiment 4 of the common-mode level conversion circuit of the present invention;

[0031] Figure 5 This is a circuit diagram of an embodiment of the feedback circuit of the present invention. Detailed Implementation

[0032] The present invention is described below based on embodiments, but the invention is not limited to these embodiments. In the detailed description of the invention below, certain specific details are described in detail. Those skilled in the art will fully understand the invention even without these details. To avoid obscuring the essence of the invention, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0033] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0034] Furthermore, it should be understood that in the following description, "circuit" refers to a conductive loop consisting of at least one element or sub-circuit connected by electrical or electromagnetic connections. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it can be directly coupled or connected to another element, or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0035] Unless the context explicitly requires it, the words "comprising," "including," and similar terms throughout the specification and claims should be interpreted as encompassing rather than being exclusive or exhaustive; that is, meaning "including but not limited to."

[0036] In the description of this invention, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0037] Figure 1 This is a circuit diagram of a first embodiment of the common-mode level conversion circuit of the present invention; as shown. Figure 1As shown, the common-mode level conversion circuit includes a first level conversion circuit 1, a second level conversion circuit 2, and a feedback circuit 3. The first level conversion circuit 1 is configured to receive a first input signal Vin1 to generate a first output signal Vo1; the second level conversion circuit 2 is configured to receive a second input signal Vin2 to generate a second output signal Vo2; the feedback circuit 3 is configured to receive the first output signal Vo1 and the second output signal Vo2 to output a first feedback signal Vfb to the first level conversion circuit 1 and the second level conversion circuit 2; wherein, the first input signal Vin1 and the second input signal Vin2 include a first common-mode signal, and the first output signal Vo1 and the second output signal Vo2 include a second common-mode signal, and the second common-mode signal is controlled to approach a preset value according to the first feedback signal Vfb.

[0038] In this embodiment, the first input signal Vin1 and the second input signal Vin2 are configured as input differential signals, meaning that the first input signal Vin1 and the second input signal Vin2 have the same magnitude but opposite polarities. The first output signal Vo1 and the second output signal Vo2 are configured as output differential signals, meaning that the first output signal Vo1 and the second output signal Vo2 have the same magnitude but opposite polarities.

[0039] The common-mode level conversion circuit of the present invention converts the level of the common-mode signal in the input differential signal while basically not changing the amplitude of the differential signal in the input differential signal. Therefore, the differential signals in the first input signal Vin1 and the first output signal Vo1 are basically the same, and the differential signals in the second input signal Vin2 and the second output signal Vo2 are basically the same.

[0040] In this embodiment, the first level conversion circuit 1 includes a first variable current source I1, and the second level conversion circuit 2 includes a second variable current source I2. The currents of the first variable current source I1 and the second variable current source I2 are controlled according to the first feedback signal Vfb so that the second common-mode signal is close to a preset value.

[0041] Furthermore, the current of the first variable current source I1 and the common-mode current of the first level conversion circuit 1 have the same trend of change; the current of the second variable current source I2 and the common-mode current of the second level conversion circuit 2 have the same trend of change; wherein, the common-mode current is configured to be the current generated based on the difference between the first common-mode signal and the second common-mode signal.

[0042] Furthermore, when the current of the first variable current source I1 and the second variable current source I2 decreases, the second common-mode signal increases; when the current of the first variable current source I1 and the second variable current source I2 increases, the second common-mode signal decreases.

[0043] In this embodiment, the first level conversion circuit 1 further includes a first RC circuit 11 and a first fixed current source Ip1. The input terminal of the first RC circuit 11 receives the first input signal Vin1, and its output terminal is grounded through a first variable current source I1. The first fixed current source Ip1 is coupled between the common terminal of the first RC circuit 11 and the first variable current source I1 and the power supply Vcc. The common terminal of the first fixed current source Ip1 and the first variable current source I1 outputs a first output signal Vo1. Correspondingly, the second level conversion circuit 2 further includes a second RC circuit 21 and a second fixed current source Ip2. The input terminal of the second RC circuit 21 receives the second input signal Vin2, and its output terminal is grounded through a second variable current source I2. The second fixed current source Ip2 is coupled between the common terminal of the second RC circuit 21 and the second variable current source I2 and the power supply Vcc. The common terminal of the second fixed current source Ip2 and the second variable current source I2 outputs a second output signal Vo2.

[0044] In this embodiment, the first RC circuit 11 includes a first capacitor C11 and a first resistor R11 connected in parallel. Specifically, the first terminals of the first capacitor C11 and the first resistor R11 are both coupled to the input terminal of the first RC circuit 11 to receive the first input signal Vin1, and the second terminals of the first capacitor C11 and the first resistor R11 are both coupled to the output terminal of the first RC circuit 11 to output the first output voltage Vo1. Correspondingly, the second RC circuit 21 includes a first capacitor C21 and a first resistor R21 connected in parallel. The first terminals of the first capacitor C21 and the first resistor R21 are both coupled to the input terminal of the second RC circuit 21 to receive the second input signal Vin2, and the second terminals of the first capacitor C21 and the first resistor R21 are both coupled to the output terminal of the second RC circuit 21 to output the second output voltage Vo2. This embodiment provides a specific implementation of the first RC circuit 11 and the second RC circuit 21, but the present invention does not limit this implementation.

[0045] In this embodiment, the feedback circuit 3 includes a common-mode level extraction circuit 31 and a first operational amplifier A1. The common-mode level extraction circuit 31 receives a first output signal Vo1 and a second output signal Vo2, extracts and outputs a second common-mode signal Vcm from the first output signal Vo1 and the second output signal Vo2. The first input terminal of the first operational amplifier A1 receives the second common-mode signal Vcm, its second input terminal receives a first reference signal Vref representing the preset value, and its output terminal outputs a first feedback signal Vfb to the control terminals of the first variable current source I1 and the second variable current source I2 to control the current of the first variable current source I1 and the second variable current source I2, thereby making the second common-mode signal Vcm close to the first reference signal Vref.

[0046] In this embodiment, the inverting input of the first operational amplifier A1 receives the first reference signal Vref, and the non-inverting input of the first operational amplifier A1 receives the second common-mode signal Vcm. However, the present invention does not limit this. In other embodiments, the non-inverting input of the first operational amplifier A1 receives the first reference signal Vref, and the inverting input of the first operational amplifier A1 receives the second common-mode signal Vcm.

[0047] In this embodiment, the first variable current source I1 and the second variable current source I2 increase with the increase of the feedback signal Vfb, but the present invention does not limit this. In other embodiments, the first variable current source I1 and the second variable current source I2 decrease with the increase of the feedback signal Vfb.

[0048] In this embodiment, when the second common-mode signal Vcm is greater than the first reference signal Vref, the first feedback signal Vfb increases, and the currents of the first variable current source I1 and the second variable current source I2 increase. Since the currents of the first fixed current source Ip1 and the second fixed current source Ip2 remain unchanged, the common-mode current in the first level conversion circuit 1 and the common-mode current in the second level conversion circuit 2 increase. The common-mode current is the current generated on the first resistor by the difference between the first common-mode signal and the second common-mode signal, that is, the common-mode current in the first level conversion circuit 1 is equal to (first common-mode signal - second common-mode signal) / R11, and the common-mode current in the second level conversion circuit 2 is equal to (first common-mode signal - second common-mode signal) / R21. Since the first common-mode signal remains unchanged, the second common-mode signal decreases until the second common-mode signal Vcm is equal to the first reference signal Vref; when the second common-mode signal Vcm is smaller than... When the first reference signal Vref is reached, the first feedback signal Vfb decreases, and the currents of the first variable current source I1 and the second variable current source I2 decrease. Since the currents of the first fixed current source Ip1 and the second fixed current source Ip2 remain unchanged, the common-mode current in the first level conversion circuit 1 and the common-mode current in the second level conversion circuit 2 decrease. The common-mode current is the current generated on the first resistor by the difference between the first common-mode signal and the second common-mode signal. That is, the common-mode current in the first level conversion circuit 1 is equal to (first common-mode signal - second common-mode signal) / R11, and the common-mode current in the second level conversion circuit 2 is equal to (first common-mode signal - second common-mode signal) / R21. Since the first common-mode signal remains unchanged, the second common-mode signal increases until the second common-mode signal Vcm is equal to the first reference signal Vref, thereby dynamically controlling the second common-mode signal Vcm to be equal to the first reference signal Vref.

[0049] In this embodiment, the corresponding parts of the first level conversion circuit 1 and the second level conversion circuit 2 are symmetrical, that is, R11 = R21, C11 = C21, I1 = I2, Ip1 = Ip2, but the present invention does not limit this.

[0050] Figure 1 The common-mode level conversion circuit described herein can operate in either DC-coupled (i.e., direct current coupling) or AC-coupled (i.e., alternating current coupling) mode. In some embodiments, both the first RC circuit 11 and the second RC circuit 21 further include a second resistor (such as R12 and R22 in embodiments three and four). The second resistor is coupled between the input terminal of the first RC circuit 11 or the second RC circuit 21 and ground potential, so as to facilitate better operation of the common-mode level conversion circuit in AC-coupled (i.e., alternating current coupling) mode. This is hereby described.

[0051] Figure 2 This is a circuit diagram of Embodiment 2 of the common-mode level conversion circuit of the present invention. The difference from Embodiment 1 is that: the first level conversion circuit 1 further includes a third fixed current source Ip3, and the second level conversion circuit 2 further includes a fourth fixed current source Ip4. The third fixed current source Ip3 is coupled between the common terminal of the first RC circuit 11 and the first variable current source I1 and the ground potential; the fourth fixed current source Ip4 is coupled between the common terminal of the second RC circuit 21 and the second variable current source I2 and the ground potential. The remaining parts and working methods are similar to those of Embodiment 1, and will not be described in detail here.

[0052] The third fixed current source Ip3 serves as the compensation current for the first variable current source I1. Therefore, the current range of the first variable current source I1 in this embodiment is smaller than that of the first variable current source I1 in Embodiment 1. Correspondingly, the fourth fixed current source Ip4 serves as the compensation current for the second variable current source I2. Therefore, the current range of the second variable current source I2 in this embodiment is smaller than that of the second variable current source I2 in Embodiment 1.

[0053] In this embodiment, the corresponding parts of the first level conversion circuit 1 and the second level conversion circuit 2 are symmetrical, that is, R11 = R21, C11 = C21, I1 = I2, Ip1 = Ip2, Ip3 = Ip4, but the present invention does not limit this.

[0054] Figure 3 This is a circuit diagram of Embodiment 3 of the common-mode level conversion circuit of the present invention; the difference from Embodiment 1 is that the specific structures of the first variable current source I1, the second variable current source I2, the first fixed current source Ip1 and the second fixed current source Ip2 are given.

[0055] In this embodiment, the first variable current source I1 includes a first power switch Q11. The feedback circuit 3 outputs a first feedback signal Vfb to the control terminal of the first power switch Q11 to control the current flowing through the first power switch Q11. Optionally, the first variable current source I1 further includes a third resistor R13. The first power switch Q11 and the third resistor R13 are connected in series and coupled between the output terminal of the first level conversion circuit 1 and ground potential. The second variable current source I2 includes a first power switch Q21. The feedback circuit 3 outputs a first feedback signal Vfb to the control terminal of the first power switch Q21 to control the current flowing through the first power switch Q21. Optionally, the second variable current source I2 further includes a third resistor R23. The first power switch Q21 and the third resistor R23 are connected in series and coupled between the output terminal of the second level conversion circuit 2 and ground potential. The third resistor is the source degradation resistor of the first power switch, intended to reduce the influence of the thermal noise of the corresponding first power switch on the output noise. The structures of the first variable current source I1 and the second variable current source I2 given in this embodiment are only schematic diagrams, and the present invention does not limit them. In other embodiments, the first variable current source I1 and the second variable current source I2 can be other structures. Any structure that can realize the functions of the first variable current source I1 and the second variable current source I2 is within the protection scope of the present invention.

[0056] In this embodiment, the first fixed current source Ip1 includes a fourth resistor R14, coupled between the common terminal of the first RC circuit 11 and the first variable current source I1 and the power supply Vcc; the second fixed current source Ip2 includes a fourth resistor R24, coupled between the common terminal of the second RC circuit 21 and the second variable current source I2 and the power supply Vcc. In this embodiment, the fixed current source implemented using only resistors is more suitable for applications with high noise requirements compared to a fixed current source implemented using a power switch or a combination of a power switch and a resistor. The structures of the first fixed current source Ip1 and the second fixed current source Ip2 given in this embodiment are only illustrative, and the present invention does not limit them. In other embodiments, the first fixed current source Ip1 and the second fixed current source Ip2 can be other structures, and any structure that can realize the functions of the first fixed current source Ip1 and the second fixed current source Ip2 is within the protection scope of the present invention.

[0057] In this embodiment, when the common-mode level conversion circuit operates in DC-coupled mode: when the second common-mode signal Vcm is greater than the first reference signal Vref, the first feedback signal Vfb increases, that is, the voltage at the control terminals of the first power switches Q11 and Q21 increases, thereby increasing the current flowing through the first power switches Q11 and Q21. Since the currents of the first fixed current source Ip1 and the second fixed current source Ip2 remain unchanged, the common-mode current in the first level conversion circuit 1 and the common-mode current in the second level conversion circuit 2 increase. The common-mode current is the current generated on the first resistor by the difference between the first common-mode signal and the second common-mode signal, that is, the common-mode current in the first level conversion circuit 1 is equal to (first common-mode signal - second common-mode signal) / R11, and the common-mode current in the second level conversion circuit 2 is equal to (first common-mode signal - second common-mode signal) / R21. Since the first common-mode signal remains unchanged, the second common-mode signal decreases until the second common-mode signal Vcm equals the first reference signal Vref. When the second common-mode signal Vcm is less than the first reference signal Vref, the first feedback signal Vfb decreases, meaning the voltage at the control terminals of the first power switches Q11 and Q21 decreases, thus reducing the current flowing through the first power switches Q11 and Q21. Since the currents of the first fixed current source Ip1 and the second fixed current source Ip2 remain unchanged, the common-mode current in the first level conversion circuit 1 and the common-mode current in the second level conversion circuit 2 decrease. The common-mode current is the current generated on the first resistor by the difference between the first common-mode signal and the second common-mode signal. That is, the common-mode current in the first level conversion circuit 1 is equal to (first common-mode signal - second common-mode signal) / R11, and the common-mode current in the second level conversion circuit 2 is equal to (first common-mode signal - second common-mode signal) / R21. Since the first common-mode signal remains unchanged, the second common-mode signal increases until the second common-mode signal Vcm equals the first reference signal Vref, thereby dynamically controlling the second common-mode signal Vcm to equal the first reference signal Vref.

[0058] In extreme cases, the first feedback signal Vfb output by feedback circuit 3 causes the first power switches Q11 and Q12 to approach the closed state, and the current flowing through the first power switches Q11 and Q21 decreases to 0, i.e., there is no current. At this time, the second common-mode signal is equal to the output voltage of the first level conversion circuit 1 or the output voltage of the second level conversion circuit 2. That is, the second common-mode signal is equal to the sum of the voltage division of the power supply Vcc and the first common-mode signal on the first resistor and the first common-mode signal. That is, the second common-mode signal is equal to (Vcc-first common-mode signal)*R11 / (R11+R14)+first common-mode signal or (Vcc-first common-mode signal)*R21 / (R21+R24)+first common-mode signal. At this time, the second common-mode signal and the first reference signal Vref are not much different and are still within the common-mode range of the subsequent circuit.

[0059] When the common-mode level conversion circuit operates in AC coupling mode: feedback circuit 3 does not operate, and no current flows through the first power switches Q11 and Q21. At this time, the second common-mode signal is equal to the output voltage of the first level conversion circuit 1 or the output voltage of the second level conversion circuit 2, that is, the sum of the voltage division of the first resistor and the second resistor on the power supply voltage Vcc. That is, the second common-mode signal is equal to Vcc(R11+R12) / (R11+R14+R12) or Vcc(R21+R22) / (R21+R24+R22).

[0060] In this embodiment, the corresponding parts of the first level conversion circuit 1 and the second level conversion circuit 2 are symmetrical, that is, R11 = R21, C11 = C21, R12 = R22, R13 = R23, R14 = R24, etc., but the present invention does not limit this.

[0061] Figure 4 This is a circuit diagram of Embodiment 4 of the common-mode level conversion circuit of the present invention; the difference from Embodiment 2 is that the specific structures of the first variable current source I1, the second variable current source I2, the first fixed current source Ip1, the second fixed current source Ip2, the third fixed current source Ip3 and the fourth fixed current source Ip4 are given.

[0062] In this embodiment, the first variable current source I1, the second variable current source I2, the first fixed current source Ip1, the second fixed current source Ip2, the third fixed current source Ip3, and the fourth fixed current source Ip4 are all cascode current sources, but the present invention does not impose any limitations on them.

[0063] Specifically, the first variable current source I1 includes a second power switch Q12, a first power switch Q11, and a third resistor R13, which are connected in series between the output terminal of the first level conversion circuit 1 and ground potential. The second variable current source I2 includes a second power switch Q22, a first power switch Q21, and a third resistor R23, which are connected in series between the output terminal of the second level conversion circuit 2 and ground potential.

[0064] Furthermore, the first fixed current source Ip1 includes a fourth resistor R14, a third power switch Q13, and a fifth power switch Q15, which are connected in series between the power supply VCC and the output terminal of the first level conversion circuit 1. The second fixed current source Ip2 includes a fourth resistor R24, a third power switch Q23, and a fifth power switch Q25, which are connected in series between the power supply VCC and the output terminal of the second level conversion circuit 2. The third fixed current source Ip3 includes a fourth power switch Q14, a sixth power switch Q16, and a fifth resistor R15, which are connected in series between the output terminal of the first level conversion circuit 1 and ground potential. The fourth fixed current source Ip4 includes a fourth power switch Q24, a sixth power switch Q26, and a fifth resistor R25. The fourth power switch Q24, the sixth power switch Q26, and the fifth resistor R25 are connected in series and coupled between the output terminal of the second level conversion circuit 2 and the ground potential.

[0065] The structures of the first variable current source I1, the second variable current source I2, the first fixed current source Ip1, the second fixed current source Ip2, the third fixed current source Ip3, and the fourth fixed current source Ip4 given in this embodiment are merely illustrative and are not limited by this invention. Any structure that can realize the functions of the first variable current source I1, the second variable current source I2, the first fixed current source Ip1, the second fixed current source Ip2, the third fixed current source Ip3, and the fourth fixed current source Ip4 is within the protection scope of this invention.

[0066] In this embodiment, the corresponding parts of the first level conversion circuit 1 and the second level conversion circuit 2 are symmetrical, that is, R11 = R21, C11 = C21, R12 = R22, R13 = R23, R14 = R24, etc., but the present invention does not limit this.

[0067] Figure 5 This is a circuit diagram of an embodiment of the feedback circuit of the present invention, as shown below. Figure 5As shown, operational amplifier A1 is a PMOS input folded cascoded operational amplifier, which will not be described in detail here. The common-mode level extraction circuit 31 includes a first parallel structure composed of a first common-mode resistor Rc1 and a first common-mode capacitor Cc1 connected in parallel and coupled together, and a second parallel structure composed of a second common-mode resistor Rc2 and a second common-mode capacitor Cc2 connected in parallel and coupled together. The first terminal of the first parallel structure receives the first output signal Vo1, the second terminal of the first parallel structure is coupled to the first terminal of the second parallel structure, the second terminal of the second parallel structure receives the second output signal Vo2, and the common terminal of the first parallel structure and the second parallel structure outputs the second common-mode signal Vcm.

[0068] This embodiment provides a schematic structure of the common-mode level extraction circuit 31 and the operational amplifier A1, but the present invention does not limit this. Any structure that can realize the functions of the common-mode level extraction circuit 31 and the operational amplifier A1 is within the protection scope of the present invention.

[0069] The present invention also provides a clock buffer, including the above-mentioned common-mode level conversion circuit and subsequent circuit. The common-mode level conversion circuit is configured to convert a first common-mode signal in the first input signal and the second input signal into a second common-mode signal in the first output signal and the second output signal. The subsequent circuit is configured to receive the first output signal and the second output signal to output a clock signal.

[0070] Although the embodiments are described and illustrated separately above, some common technologies are involved. Those skilled in the art can replace and integrate them between the embodiments. If there is any content not explicitly described in one embodiment, then another embodiment that is described can be referred to.

[0071] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A common-mode level conversion circuit, characterized in that, include: A first level conversion circuit includes a first fixed current source and a first variable current source connected in series, and a first RC circuit, configured to receive a first input signal to generate a first output signal, wherein the output terminal of the first RC circuit is coupled to a common terminal of the first fixed current source and the first variable current source. The second level conversion circuit includes a second fixed current source and a second variable current source connected in series, and a second RC circuit, configured to receive a second input signal to generate a second output signal, wherein the output terminal of the second RC circuit is coupled to a common terminal of the second fixed current source and the second variable current source. and The feedback circuit is configured to receive the first output signal and the second output signal, and output a first feedback signal; The first input signal and the second input signal include a first common-mode signal, and the first output signal and the second output signal include a second common-mode signal. The current of the first variable current source and the second variable current source is controlled according to the first feedback signal so that the second common-mode signal is close to a preset value.

2. The common-mode level conversion circuit according to claim 1, characterized in that: The current of the first variable current source and the common-mode current of the first level conversion circuit have the same trend of change; The current of the second variable current source and the common-mode current of the second level conversion circuit have the same trend. The common-mode current is configured to be a current generated based on the difference between the first common-mode signal and the second common-mode signal.

3. The common-mode level conversion circuit according to claim 1, characterized in that: When the currents of the first variable current source and the second variable current source decrease, the second common-mode signal increases; When the currents of the first variable current source and the second variable current source increase, the second common-mode signal decreases.

4. The common-mode level conversion circuit according to claim 1, characterized in that: The differential mode signals in the first input signal and the first output signal are substantially the same, and the differential mode signals in the second input signal and the second output signal are substantially the same.

5. The common-mode level conversion circuit according to claim 1, characterized in that, The feedback circuit includes: A common-mode level extraction circuit is configured to receive the first output signal and the second output signal, and output the second common-mode signal; and The first operational amplifier is configured to receive the second common-mode signal at its first input terminal, receive a first reference signal representing the preset value at its second input terminal, and output a first feedback signal to the control terminals of the first variable current source and the second variable current source at its output terminal.

6. The common-mode level conversion circuit according to claim 1, characterized in that, The first RC circuit is configured to receive the first input signal at its input terminal and to ground through the first variable current source at its output terminal; The first output signal is output from the common terminal of the first fixed current source and the first variable current source.

7. The common-mode level conversion circuit according to claim 6, characterized in that, The second RC circuit is configured to receive the second input signal at its input terminal and to ground through the second variable current source at its output terminal; The second output signal is output from the common terminal of the second fixed current source and the second variable current source.

8. The common-mode level conversion circuit according to claim 7, characterized in that, The first level conversion circuit further includes: A third fixed current source is coupled between the common terminal of the first RC circuit and the first variable current source and ground potential.

9. The common-mode level conversion circuit according to claim 8, characterized in that, The second level conversion circuit also includes: A fourth fixed current source is coupled between the common terminal of the second RC circuit and the second variable current source and ground potential.

10. The common-mode level conversion circuit according to claim 7, characterized in that: Both the first RC circuit and the second RC circuit include a first capacitor and a first resistor connected in parallel. The first end of the first capacitor and the first end of the first resistor are coupled to the input terminal of the corresponding RC circuit, and the second end of the first capacitor and the second end of the first resistor are coupled to the output terminal of the corresponding RC circuit.

11. The common-mode level conversion circuit according to claim 10, characterized in that: The first RC circuit and the second RC circuit also include a second resistor, which is coupled between the input terminal of the respective RC circuit and the ground potential.

12. The common-mode level conversion circuit according to claim 1, characterized in that: Both the first variable current source and the second variable current source include at least a first power switch. The feedback circuit outputs the first feedback signal to the control terminal of the first power switch in the first variable current source and the second variable current source to control the current passing through the first power switch.

13. The common-mode level conversion circuit according to claim 12, characterized in that: Both the first variable current source and the second variable current source further include a third resistor, and the first power switch and the third resistor are connected in series between the output terminal of the corresponding level conversion circuit and the ground potential.

14. The common-mode level conversion circuit according to claim 13, characterized in that: Both the first variable current source and the second variable current source further include a second power switch. The second power switch, the first power switch, and the third resistor are connected in series between the output terminal of the corresponding level conversion circuit and the ground potential.

15. The common-mode level conversion circuit according to any one of claims 7-9, characterized in that: The first fixed current source and the second fixed current source each include a fourth resistor, which is coupled between the common terminal of the corresponding RC circuit and the corresponding variable current source and the power supply.

16. The common-mode level conversion circuit according to claim 15, characterized in that: The first fixed current source and the second fixed current source further include at least a third power transistor, which is connected in series with the fourth resistor between the common terminal of the corresponding RC circuit and the corresponding variable current source and the power supply.

17. The common-mode level conversion circuit according to claim 9, characterized in that: The third fixed current source and the fourth fixed current source each include at least a fifth resistor and a fourth power transistor, wherein the fourth power transistor and the fifth resistor are connected in series and coupled between the common terminal of the corresponding RC circuit and the corresponding variable current source and the ground potential.

18. The common-mode level conversion circuit according to claim 5, characterized in that, The common-mode level extraction circuit includes: The first parallel structure is formed by the first common-mode resistor and the first common-mode capacitor connected in parallel and coupled together. The second parallel structure is formed by the parallel coupling of the second common-mode resistor and the second common-mode capacitor. Wherein, the first end of the first parallel structure receives the first output signal, the second end of the first parallel structure is coupled to the first end of the second parallel structure, the second end of the second parallel structure receives the second output signal, and the common end of the first parallel structure and the second parallel structure outputs the second common-mode signal.

19. The common-mode level conversion circuit according to claim 1, characterized in that: The first input signal and the second input signal are configured as input differential signals, and the first output signal and the second output signal are configured as output differential signals.

20. A clock buffer, characterized in that, include: The common-mode level conversion circuit according to any one of claims 1-19 is configured to convert a first common-mode signal in the first input signal and the second input signal into a second common-mode signal in the first output signal and the second output signal. The subsequent circuit is configured to receive the first output signal and the second output signal to output a clock signal.

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