A substrate satisfying wire bonding of chips of different sizes and a design method thereof

CN115942604BActive Publication Date: 2026-11-03华天科技(南京)有限公司
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Patent Information

Application Number
CN202211711275.7
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2022-12-29
Publication Date
2026-11-03
Estimated Expiration
2042-12-29

AI Technical Summary

Technical Problem

In existing technologies, it is difficult for the same substrate to be compatible with chips of different sizes, resulting in an inappropriate length between the chip pad and the gold finger, which affects the packaging effect.

Method used

Design a substrate with at least two rows of gold fingers. Select gold fingers at different positions according to the chip size for wire bonding. Achieve electrical connection through the gold wires. Use a special process to manufacture the substrate to ensure it can accommodate chips of different sizes.

Benefits of technology

This design enables wire bonding of chips of different sizes to share the same substrate, reducing substrate design and production costs, improving work efficiency, and lowering mold opening costs.

✦ Generated by Eureka AI based on patent content.

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Abstract

The application discloses a substrate satisfying wire bonding of chips of different sizes and a design method thereof. The substrate satisfying wire bonding of chips of different sizes comprises a substrate body, wherein chips are arranged on the substrate body, and at least two rows of gold fingers are arranged on the surface of the substrate body. When wire bonding, the gold fingers at different positions are selected according to the size of the chips. In the substrate satisfying wire bonding of chips of different sizes and the design method thereof, the special design of the shared substrate is adopted, two or more rows of gold fingers are arranged on the surface of the substrate, and the internal design is designed to be conductive. According to the size of the chips, the gold fingers at different positions can be selected for wire bonding, the design requirement that chips of different sizes share the same substrate for press welding and wire bonding can be met, the time and frequency of substrate design and sampling are reduced, chips of different sizes can be verified synchronously, the work efficiency is improved, and the cost of substrate re-molding and the like is saved, and the production cost is significantly reduced.
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Description

Technical Field

[0001] This invention belongs to the field of substrate design technology, specifically relating to a substrate and its design method that can meet the requirements of wire bonding for chips of different sizes. Background Technology

[0002] The design of memory product substrates suffers from the problem of shared substrates, meaning that the same substrate can be compatible with multiple design schemes and various chip models. Because different chip models have different sizes, issues arise where the length of the wire bonding from the chip pad to the substrate's gold fingers can be either too long or too short. Therefore, designing a substrate that can accommodate wire bonding for chips of different sizes is of significant practical importance. Summary of the Invention

[0003] To address the technical problems existing in the prior art, the purpose of this invention is to provide a substrate and its design method that can meet the requirements of wire bonding for chips of different sizes.

[0004] To achieve the above objectives and technical effects, the technical solution adopted by this invention is as follows:

[0005] A substrate for wire bonding of chips of different sizes includes a substrate body on which a chip is disposed. At least two rows of gold fingers are spaced apart on the surface of the substrate body. During wire bonding, the gold fingers at different positions are selected according to the size of the chip.

[0006] In a substrate provided by the present invention that satisfies wire bonding of chips of different sizes, a plurality of wire bonding pads are equally spaced along the edge of the chip, and the distance between the wire bonding pads and the gold fingers of different rows determines which row of gold fingers is selected for wire bonding.

[0007] In a substrate for bonding chips of different sizes provided by the present invention, two rows of gold fingers are provided on the surface of the substrate body, namely a first row of gold fingers and a second row of gold fingers. Each bonding pad is face-to-face with one gold finger in the first row of gold fingers and one gold finger in the second row of gold fingers. The distance between the bonding pad and the corresponding gold finger in the first row of gold fingers is denoted as D1, and the distance between the bonding pad and the corresponding gold finger in the second row of gold fingers is denoted as D2. If D1 < 300 μm, the bonding pad on the chip is electrically connected to the second row of gold fingers. If 300 μm < D1 < 2500 μm, the bonding pad on the chip is electrically connected to the first row of gold fingers.

[0008] In a substrate provided by the present invention that satisfies the wire bonding of chips of different sizes, if D1 < 300 μm, each wire bonding pad on the chip is electrically connected to a gold finger at a corresponding position in the second row of gold fingers through a gold wire.

[0009] In a substrate provided by the present invention that satisfies the bonding of chips of different sizes, if 300μm < D1 < 2500μm, each bonding pad on the chip is electrically connected to a gold finger at a corresponding position in the first row of gold fingers through a gold wire.

[0010] In a substrate provided by the present invention that satisfies the wire bonding of chips of different sizes, two gold fingers in different rows and facing each other are connected by copper metal.

[0011] This invention also provides a method for designing a substrate to meet the requirements of wire bonding for chips of different sizes, comprising the following steps:

[0012] 1) The substrate body is manufactured according to conventional processes, and copper foil is laid on the top of the substrate body;

[0013] 2) Etch copper pillars on both sides of the copper foil and connect them to the two ends of the lower copper foil;

[0014] 3) After the copper foil and copper pillars are formed, fill the surrounding area with green oil. After completion, electroplate gold fingers on the two copper pillars on the left and right sides, and completely fill the surrounding area with green oil.

[0015] In the design method of a substrate that meets the requirements of bonding chips of different sizes provided by the present invention, in step 1), the length of the copper foil is 1 to 2.5 mm.

[0016] In the design method of a substrate for bonding chips of different sizes provided by the present invention, in step 2), copper pillars are etched on both sides of the copper foil to form a U-shaped groove. The depth of the copper pillars is 60-90 μm, which is 1 / 3 to 1 / 2 of the thickness of the substrate body.

[0017] In the design method of a substrate that meets the requirements of bonding chips of different sizes provided by the present invention, in step 3), the distance between two adjacent rows of gold fingers is 1 to 2.5 mm.

[0018] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0019] This invention discloses a substrate and its design method for wire bonding of chips of different sizes. The substrate includes a substrate body, on which a chip is disposed. At least two rows of gold fingers are spaced apart on the surface of the substrate body. During wire bonding, the gold fingers at different positions are selected according to the size of the chip. In this invention, a special design of a shared substrate is adopted. The gold fingers on the substrate surface can be arranged in two or more rows according to actual needs, with internal conductivity. Wire bonding at different positions of the gold fingers can be selected according to the size of the chip, thereby meeting the design requirements of sharing the same substrate for bonding of chips of different sizes. At the same time, it reduces the time and number of substrate design and prototyping, allows for simultaneous engineering verification of chips of different sizes, improves work efficiency, and saves costs such as re-molding the substrate, significantly reducing production costs. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the structure when the first row of gold fingers is wired in Embodiment 1 of the present invention;

[0021] Figure 2 This is a schematic diagram of the structure when the second row of gold fingers is wired in Embodiment 1 of the present invention;

[0022] Figure 3 This is a schematic diagram of the structure when the two rows of gold fingers are connected in Embodiment 1 of the present invention;

[0023] Figure 4 This is a flowchart illustrating the manufacturing process of connecting two rows of gold fingers in Embodiment 1 of the present invention. Detailed Implementation

[0024] The present invention will now be described in detail so that its advantages and features can be more easily understood by those skilled in the art, thereby providing a clearer and more explicit definition of the scope of protection of the present invention.

[0025] The following provides a brief overview of one or more aspects to offer a basic understanding of them. This overview is not an exhaustive summary of all conceived aspects, nor is it intended to identify key or decisive elements of all aspects, nor to define the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form to prepare for the more detailed descriptions that follow.

[0026] Definitions:

[0027] The pad is an interface that connects the internal components of the chip to the chip package.

[0028] like Figure 1-4 As shown, a substrate for bonding chips of different sizes includes a substrate body 1, on which a chip 2 is disposed. A plurality of bonding pads 6 are evenly spaced along the edge of the chip 2. At least two rows of gold fingers are spaced apart on the surface of the substrate body 1. Two gold fingers in different rows and facing each other are connected by copper metal 7. During bonding, the choice of which row of gold fingers to use can be determined according to the size of the chip 2 or the distance between the bonding pads 6 and the gold fingers in different rows, to prevent the bonding wire from being too short or too long, which would prevent encapsulation. The bonding pads 6 and the selected gold fingers are electrically connected by gold wires 5.

[0029] A method for designing a substrate suitable for wire bonding of chips of different sizes includes the following steps:

[0030] 1) Fabricate the substrate body 1 according to conventional processes, and lay a layer of copper foil on its top layer, such as... Figure 4 As shown in a;

[0031] The length of the copper foil depends on the product size; if it is too small, it will be impossible to distinguish the first and second rows of gold fingers, and if it is too large, there will be insufficient space for design.

[0032] 2) Etch copper pillars on both sides of the copper foil, connecting them to the ends of the lower copper foil, such as... Figure 4 As shown in b;

[0033] Among them, copper pillars are etched on the left and right sides to form U-shaped grooves. The depth of the copper pillars is 1 / 3 to 1 / 2 of the thickness of the substrate body 1, so as to play a connection role and at the same time not to touch the circuit of the lower layer of the substrate body 1.

[0034] 3) After the copper foil and copper pillars are formed, fill the surrounding area with green solder mask. Then, electroplate gold contacts onto the two copper pillars on the left and right sides, ensuring the surrounding area is completely filled with green solder mask. Figure 4 As shown in c;

[0035] The gold fingers are exposed and used to adjust their position during wire bonding. The distance between two adjacent rows of gold fingers is the spacing between the two copper pillars of the U-shaped groove.

[0036] Example 1

[0037] like Figure 1-4 As shown, a substrate for bonding chips of different sizes includes a substrate body 1, on which a chip 2 is disposed. A plurality of bonding pads 6 are evenly spaced along the edge of the chip 2. The surface of the substrate body 1 is designed with two rows of gold fingers, namely a first row of gold fingers 3 and a second row of gold fingers 4. Each bonding pad 6 is face-to-face with one gold finger of the first row of gold fingers 3 and one gold finger of the second row of gold fingers 4. The two face-to-face gold fingers of different rows are connected by copper metal 7. During bonding, the size of the chip 2 or the distance between the bonding pad 6 and the gold fingers of different rows can be determined to determine which row of gold fingers to use, so as to prevent the bonding wire from being too short or too long, which would prevent the packaging from being impossible.

[0038] The shortest distance (D1) between the punch-down pad 6 and the corresponding gold finger in the first row of gold fingers 3 is denoted as D1. The shortest distance (D2) between the punch-down pad 6 and the corresponding gold finger in the second row of gold fingers 4 is denoted as D2. The principle for selecting the punch-down position is as follows:

[0039] If 300μm < D1 < 2500μm, select the first row of gold fingers 3 for wire bonding. In this case, each bonding pad 6 is electrically connected to a corresponding gold finger in the second row of gold fingers 4 via gold wire 5. Figure 1 As shown;

[0040] If D1 < 300μm, select the second row of gold fingers 4 for wire bonding. In this case, each bonding pad 6 is electrically connected to a corresponding gold finger in the second row of gold fingers 4 via gold wire 5. Figure 2 As shown.

[0041] This embodiment also discloses a design method for a substrate that meets the requirements for wire bonding of chips of different sizes, including the following steps:

[0042] 1) Fabricate the substrate body 1 according to conventional processes, and lay a layer of copper foil on its top layer, such as... Figure 4 As shown in a;

[0043] The thickness of the substrate body 1 is 180μm, and the length of the copper foil depends on the product size, generally 1 to 2.5mm. If it is too small (<1mm), it is impossible to distinguish the first row and the second row of gold fingers, and if it is too large (>2.5mm), there is not enough space for design.

[0044] 2) Etch copper pillars on both sides of the copper foil, connecting them to the ends of the lower copper foil, such as... Figure 4 As shown in b;

[0045] Among them, copper pillars are etched on the left and right sides to form U-shaped grooves. The depth of the copper pillars is 60-90μm, which is 1 / 3 to 1 / 2 of the thickness of the substrate body 1, so as to achieve a connection function and at the same time, it will not touch the circuit of the lower layer of the substrate body 1.

[0046] 3) After the copper foil and copper pillars are formed, fill the surrounding area with green solder mask. Then, electroplate gold contacts onto the two copper pillars on the left and right sides, ensuring the surrounding area is completely filled with green solder mask. Figure 4 As shown in c;

[0047] Among them, the gold fingers are exposed on the outside and are used to adjust their position when welding wires. The distance between two adjacent rows of gold fingers is the distance between the two copper pillars of the U-shaped groove (1~2.5mm).

[0048] Any parts or structures not specifically described in this invention can be made using existing technologies or products, and will not be elaborated upon here.

[0049] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention specification, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A method for designing a substrate to accommodate wire bonding of chips of different sizes, characterized in that, The substrate for bonding chips of different sizes includes a substrate body on which a chip is disposed. At least two rows of gold fingers are spaced apart on the surface of the substrate body. Two gold fingers in different rows that face each other are connected by copper metal. During bonding, the gold fingers at different positions are selected according to the size of the chip or the distance between the bonding pad and the gold fingers in different rows to prevent the bonding wire from being too short or too long, which would prevent it from being packaged. The design method includes the following steps: 1) The substrate body is manufactured according to conventional processes, and copper foil is laid on the top of the substrate body; 2) Etch copper pillars on both sides of the copper foil, connecting them to the two ends of the lower copper foil; 3) After the copper foil and copper pillars are formed, fill the surrounding area with green oil. After completion, electroplate gold fingers on the two copper pillars on the left and right sides, and completely fill the surrounding area with green oil.

2. The design method for a substrate that meets the requirements for bonding chips of different sizes according to claim 1, characterized in that, In step 1), the length of the copper foil is 1~2.5mm.

3. The design method for a substrate that meets the requirements for bonding chips of different sizes according to claim 1, characterized in that, In step 2), copper pillars are etched on both sides of the copper foil to form U-shaped grooves. The depth of the copper pillars is 60~90μm, which is 1 / 3~1 / 2 of the thickness of the substrate body.

4. The design method for a substrate that meets the requirements for bonding chips of different sizes according to claim 1, characterized in that, In step 3), the distance between two adjacent rows of gold fingers is 1~2.5mm.

5. The design method for a substrate that meets the requirements for bonding chips of different sizes according to claim 1, characterized in that, The chip edge is provided with several bonding pads at equal intervals. The distance between the bonding pads and the gold fingers in different rows determines which row of gold fingers to bond.

6. The design method for a substrate that meets the requirements for bonding chips of different sizes according to claim 5, characterized in that, The substrate body has two rows of gold fingers on its surface, namely the first row of gold fingers and the second row of gold fingers. Each bonding pad is face-to-face with one gold finger in the first row of gold fingers and one gold finger in the second row of gold fingers. The distance between the bonding pad and the corresponding gold finger in the first row of gold fingers is denoted as D1, and the distance between the bonding pad and the corresponding gold finger in the second row of gold fingers is denoted as D2. If D1 < 300μm, the bonding pad on the chip is electrically connected to the second row of gold fingers. If 300μm < D1 < 2500μm, the bonding pad on the chip is electrically connected to the first row of gold fingers.

7. The design method for a substrate that meets the requirements for bonding chips of different sizes according to claim 6, characterized in that, If D1 < 300μm, each bonding pad on the chip is electrically connected to a corresponding gold finger in the second row of gold fingers via a gold wire.

8. The design method for a substrate that meets the requirements for bonding chips of different sizes according to claim 6, characterized in that, If 300μm < D1 < 2500μm, each bonding pad on the chip is electrically connected to a corresponding gold finger in the first row of gold fingers via a gold wire.

Citation Information

Patent Citations

  • Universal packaging substrate and its application device

    CN101145548A

  • Manufacturing method of goldfinger circuit board

    CN102427681A