Electrostatic discharge protection circuit, driving circuit, pre-driving circuit and integrated circuit layout thereof

Abstract

The present disclosure relates to electrostatic discharge protection circuit, driving circuit, and pre-driver circuit and integrated circuit layout thereof. An integrated circuit layout of a pre-driver circuit includes a plurality of class one transistor regions having a density less than a predetermined level, and a class two base region surrounding the class one transistor regions in a complete ring. The present disclosure also provides an ESD circuit with better voltage resistance, and an output stage circuit with better stability.

Description

Technical Field

[0001] This invention relates to ESD (Electrostatic Discharge) protection circuits, drive circuits, and pre-drive circuits and their integrated circuit layouts, particularly to ESD protection circuits, drive circuits, and pre-drive circuits and their integrated circuit layouts that can increase withstand voltage or increase circuit stability. Background Technology

[0002] With the advancement of technology, integrated circuits (ICs) are becoming increasingly powerful and complex. However, as circuits become more complex and components become smaller, the withstand voltage of ESD protection circuit components and the stability of output stage circuits have become important considerations when designing ICs.

[0003] Therefore, a novel circuit design mechanism is needed to improve the withstand voltage of circuit components in ESD protection circuits and the circuit stability of output stage circuits. Summary of the Invention

[0004] Therefore, one object of the present invention is to provide an ESD protection circuit that can improve the withstand voltage of the circuit elements of the ESD protection circuit.

[0005] Another objective of this invention is to provide a pre-drive circuit that can improve the circuit stability of the pre-drive circuit.

[0006] An embodiment of the present invention provides an ESD protection circuit, comprising: an RC (capacitor-resistor) circuit; a protection transistor coupled to a first voltage source and a second voltage source, for providing a conduction path between the first voltage source and the second voltage source according to a control voltage, wherein a second voltage provided by the second voltage source is lower than a first voltage provided by the first voltage source; and a NOR gate coupled between the RC circuit and the protection transistor, for providing the control voltage according to the output of the RC circuit and a predetermined voltage.

[0007] An embodiment of the present invention provides a driving circuit coupled to a first voltage source and a second voltage source, comprising: a first type transistor coupled to the second voltage source; a second type transistor connected in series with the first type transistor, and a control terminal of the second type transistor coupled to the first voltage source; and a first type transistor coupled between the first voltage source and the second type transistor.

[0008] An embodiment of the present invention provides a pre-drive circuit, comprising: a voltage level conversion circuit for converting a first input voltage into a first conversion voltage, or a second input voltage into a second conversion voltage, wherein the first input voltage is higher than the second input voltage, and the first conversion voltage is higher than the second conversion voltage; and a pre-drive circuit comprising at least one inverter, the inverter operating at the first input voltage and the second conversion voltage, or operating at the first conversion voltage and the second input voltage.

[0009] An embodiment of the present invention provides an integrated circuit layout for a pre-driven circuit, comprising: a plurality of transistor-like regions having a density less than a predetermined level; and a dual-base region surrounding the transistor-like regions in a complete circle.

[0010] According to the foregoing embodiments, the withstand voltage of the circuit elements of the ESD protection circuit and the circuit stability of the output stage circuit can be improved, thus improving the problems in the prior art. Attached Figure Description

[0011] Figure 1 A circuit diagram of an ESD protection circuit according to an embodiment of the present invention is shown.

[0012] Figure 2 An illustration of an embodiment of the present invention is shown. Figure 1 The detailed circuit diagram of the ESD protection circuit shown is shown.

[0013] Figure 3 An illustration of an embodiment of the present invention is shown. Figure 1 The integrated circuit layout of the ESD protection circuit is shown.

[0014] Figure 4 A circuit diagram of a driving circuit according to an embodiment of the present invention is shown.

[0015] Figure 5 and Figure 6 Circuit diagrams of pre-drive circuits according to different embodiments of the present invention are shown.

[0016] Figure 7 An illustration of an embodiment of the present invention is shown. Figure 5 and Figure 6 The integrated circuit layout of the pre-drive circuit is shown.

[0017] Figure 8 The illustration depicts an embodiment of the present invention. Figure 7 The diagram shows Rule 6. Detailed Implementation

[0018] The present invention will be described below with reference to several embodiments. Please note that the terms "first," "second," and similar descriptions in the following description are only used to define different elements, parameters, data, signals, or steps, and are not intended to limit their order. For example, the first transistor and the second transistor can be two transistors with the same structure but independent of each other.

[0019] Figure 1 A circuit diagram of an ESD protection circuit according to an embodiment of the present invention is shown. Figure 1 As shown, the ESD protection circuit 100 includes: an RC (capacitor-resistor) circuit 101, a NOR gate 103, and a protection transistor 105. The protection transistor 105 is coupled to a first voltage source and a second voltage source, where a second voltage V2 provided by the second voltage source is lower than a first voltage V1 provided by the first voltage source. In one embodiment, the second voltage V2 is ground. The protection transistor 105 is used to provide a conduction path between the first voltage source and the second voltage source according to a control voltage Vc; that is, the protection transistor 105 is turned on (conducted) or turned off (not conducted) according to the control voltage Vc. The NOR gate 103 is coupled between the RC circuit 101 and the protection transistor 105, and is used to provide the control voltage Vc according to a predetermined voltage PV and the output of the RC circuit 101. In one embodiment, the RC circuit 101 includes as follows: Figure 1 The resistor R1 and capacitor C1 are shown, and the protection transistor 105 is an NMOS (N-Metal-Oxide-Semiconductor), but not limited to it.

[0020] When an ESD event occurs, the output of RC circuit 101 changes, causing NOR gate 103 to turn on protection transistor 105 to provide a current path for the large current caused by the ESD event. Conventional ESD protection circuits typically use an inverter to turn on protection transistor 105 based on an ESD event. However, when the IC using ESD protection circuit 100 starts operating and rapidly charges the capacitor in RC circuit 101, it may pull up the inverter output, causing protection transistor 105 to turn on falsely. Using NOR gate 103, which receives a predetermined voltage PV, as in this invention, provides a stable output, ensuring that protection transistor 105 is not falsely turned on and improving this problem. Furthermore, to further increase the voltage difference between the first voltage V1 and the second voltage V2 that protection transistor 105 can withstand, in one embodiment, a step-down element is connected in series with protection transistor 105. This step-down element reduces the voltage received by protection transistor 105, thereby reducing the voltage difference directly experienced by protection transistor 105. In one embodiment, the step-down element is... Figure 1The diode D1 shown is not limited to any particular type; it can also be a transistor such as a MOS or a BJT (bipolar junction transistor).

[0021] Figure 2 An illustration of an embodiment of the present invention is shown. Figure 1 The detailed circuit diagram of the ESD protection circuit shown is as follows. Figure 2 As shown, NOR gate 103 includes a first NMOS N1, a second NMOS N2, a first PMOS P1, and a second PMOS P2. The connections between the first NMOS N1, the second NMOS N2, the first PMOS P1, the second PMOS P2, and other circuits, as well as the relationships with the received signals, have been described in detail. Figure 2 middle.

[0022] Figure 2 The transistor in the middle protection transistor 105 can be replaced by other transistors to achieve the same effect. For example, it can be replaced by a PMOS or other different types of BJTs to achieve the same effect. Therefore, Figure 2 The NOR gate 103 can be represented as comprising the following elements: a first-type transistor (e.g., a first NMOS N1) coupled to a second voltage source (e.g., a voltage source providing V2), a guard transistor 105, and a control terminal (e.g., a gate terminal) of the first-type transistor coupled to an RC circuit 101; a second-type transistor (e.g., a second NMOS N2) coupled to the second voltage source, the guard transistor 105, and the first-type transistor, and a control terminal (e.g., a gate terminal) of the second-type transistor receiving a predetermined voltage PV; a first-type second-type transistor (e.g., a first PMOS P1) coupled to a first voltage source (e.g., a voltage source providing V1), and a control terminal of the first-type second-type transistor P1 for receiving the predetermined voltage PV; and a second-type second-type transistor (e.g., a second PMOS P2) coupled to the first-type transistor, the second-type transistor, the first-type second-type transistor, and the guard transistor 105, and a control terminal (e.g., a gate terminal) of the second-type second-type transistor coupled to an RC circuit 101 and the control terminal of the first-type transistor. Figure 2 In one embodiment, the Class I transistor is an NMOS and the Class II transistor is a PMOS, while in another embodiment, the Class I transistor is a PMOS and the Class II transistor is an NMOS.

[0023] In addition, Figure 2 In one embodiment, the ESD protection circuit 100 further includes a resistor R2 and a capacitor C2. The predetermined voltage PV is generated by coupling the resistor R2 and the capacitor C2 with the voltage V3, but the predetermined voltage PV can also be generated in other ways.

[0024] The present invention also provides an integrated circuit layout for ESD protection circuitry to improve the withstand voltage capability of the protection transistor 105. Figure 3 An illustration of an embodiment of the present invention is shown. Figure 1 The diagram shows the integrated circuit layout of the ESD protection circuit. Figure 3 In the embodiment, the example of the protection transistor 105 being an NMOS is used for illustration, but Figure 3 The concepts disclosed in the embodiments can be applied to other types of transistors. For example... Figure 3 As shown, an impedance layer SL is provided on the drain region D of the protection transistor 105. This impedance layer SL may cover the entire drain region D or only a portion of the drain region D. The impedance layer SL provides impedance, thereby increasing the resistance of the protection transistor 105 and thus improving the breakdown voltage capability of the protection transistor 105. The impedance layer SL may be a silicide blocking layer (SAB) or any material that provides impedance.

[0025] In addition to ESD protection circuits, this invention also provides an improved method for driving circuits. Figure 4 A circuit diagram of a drive circuit 400 according to an embodiment of the present invention is shown. Figure 4 As shown, the driving circuit 400 includes a first NMOS N1, a second NMOS N2, and a first PMOS P1. The first PMOS P1 is coupled to a first voltage source providing a first voltage V1, and the first NMOS N1 is coupled to a second voltage source providing a first voltage V2. The second NMOS N2 is coupled between the first PMOS P1 and the first NMOS N1, and its gate receives the first voltage V1. The first voltage V1 is higher than the second voltage V2. In one embodiment, the second voltage V2 is a ground voltage.

[0026] In the prior art, the driving circuit 400 only includes a first NMOS N1 and a first PMOS P1. In this case, parasitic capacitance exists at the drain and gate of the first NMOS N1. Therefore, when the voltage at the drain of the first NMOS N1 increases instantaneously, it also causes the voltage at its gate to increase instantaneously. Under these circumstances, the breakdown voltage of the first NMOS N1 is easily exceeded, thus the first NMOS N1 is easily damaged, leading to IC damage. However, in this invention… Figure 4 In one embodiment, the driving circuit 400 further includes a second NMOS N2, whose gate receives a fixed first voltage V1. Therefore, even if the voltage at the drain of the second NMOS N2 increases instantaneously, the first NMOS N1 and the second NMOS N2 will not have the problems of conventional driving circuits, which can increase the stability of the circuit.

[0027] However, please note that Figure 4 The transistors in the drive circuit 400 can be replaced with other transistors to achieve the same effect. For example, in one embodiment, the first NMOS N1 and the second NMOS N2 are replaced with PMOS transistors, and the first PMOS P1 is replaced with an NMOS transistor. Alternatively, they can be replaced with different types of BJTs (bipolar junction transistors). Therefore, Figure 4 The driving circuit 400 can be represented as including the following elements: a first type transistor (e.g., a first NMOS N1) coupled to the second voltage source (e.g., a voltage source providing V2); a second type transistor (e.g., a second NMOS N2) connected in series with the first type transistor, and a control terminal (e.g., a gate) of the second type transistor coupled to the first voltage source; and a first type transistor (e.g., a first PMOS P1) coupled between the first voltage source (e.g., a voltage source providing V1) and the second type transistor. Figure 4 In one embodiment, the Class I transistor is an NMOS and the Class II transistor is a PMOS, while in another embodiment, the Class I transistor is a PMOS and the Class II transistor is an NMOS.

[0028] Apart from Figure 4 In addition to the driving circuit described above, the present invention also provides an improved method for the pre-driving circuit. Figure 5 and Figure 6 Circuit diagrams of a pre-drive circuit 600 according to different embodiments of the present invention are shown. Figure 5 As shown, the pre-drive circuit 600 includes a voltage level conversion circuit 601 and a thrust enhancement stage circuit 603. The voltage level conversion circuit 601 converts a first input voltage Vin1 into a first converted voltage Vt1, without converting the second input voltage Vin2. The first input voltage Vin1 is higher than the second input voltage Vin2. In one embodiment, the second input voltage Vin2 is ground. Furthermore, the thrust enhancement stage circuit 603 may be coupled to... Figure 4 The driving circuit 400 shown. The pre-driving circuit 600 and the driving circuit 400 can be regarded as an output stage circuit.

[0029] The thrust enhancement stage circuit 603 includes inverters IV4-IV7 operating at the first conversion voltage Vt1 and the second input voltage Vin2. In one embodiment, in addition to the voltage level conversion circuit 601 and the thrust enhancement stage circuit 603, the pre-drive circuit 600 may further include other inverters IV1, IV2 and a logic gate LG1. Inverters IV1, IV2 and logic gate LG1 can operate at the first conversion voltage Vt1 and the second input voltage Vin2. Inverters IV1, IV2 and logic gate LG1 can operate at the same voltage as the thrust enhancement stage circuit 603. In one embodiment, the pre-drive circuit 600 may not include inverters IV1, IV2 and logic gate LG1.

[0030] Figure 5 The advantage of this architecture is that the voltage converted by the voltage level conversion circuit 601 is affected by the moment the drive circuit 400 is turned on or off, causing it to rise or fall. This can affect the operation of other circuits or the stability of the drive circuit 400's withstand voltage. However, in this invention... Figure 5 In this embodiment, the components in the pre-drive circuit 600 are operated using a converted first input voltage Vt1 and an unconverted second input voltage Vin2. This allows the components in the pre-drive circuit 600, as well as the components in the drive circuit 400, to have safe voltage across and operate at a more stable voltage.

[0031] Figure 6 The pre-drive circuit 700 shown includes and Figure 5 The circuit architecture is the same as that of the pre-drive circuit 600 shown, such as Figure 6 As shown, the pre-drive circuit 700 includes a voltage level conversion circuit 701 and a thrust enhancement stage circuit 703. Figure 6 and Figure 5 The difference in this embodiment is that the voltage level conversion circuit 701 in the pre-drive circuit 700 is used to convert a second input voltage Vin2 into a first conversion voltage Vt2, without converting the first input voltage Vin1. In one embodiment, the first input voltage Vin1 is higher than the second input voltage Vin2, and Figure 5 The first conversion voltage Vt1 in the embodiment is higher than Figure 6 The second conversion voltage Vt2 in the circuit. The pre-drive circuit 700 and the drive circuit 400 can be regarded as an output stage circuit.

[0032] And in Figure 6In one embodiment, the thrust enhancement stage circuit 703 includes inverters IV4-IV7 operating on the first input voltage Vin1 and the second conversion voltage Vt2. In another embodiment, in addition to the voltage level conversion circuit 701 and the thrust enhancement stage circuit 703, the pre-drive circuit 700 may further include other inverters IV1, IV2 and a logic gate LG1. Inverters IV1, IV2 and logic gate LG1 also operate on the first input voltage Vin1 and the second conversion voltage Vt2. In one embodiment, the pre-drive circuit 700 does not include inverters IV1, IV2 and logic gate LG1.

[0033] As mentioned earlier, the advantage of this is that the voltage converted by the voltage level conversion circuit 701 will rise or fall momentarily when the drive circuit 400 is turned on or off, thus affecting the operation of other circuits or the stability of the withstand voltage of the drive circuit 400. However, in this invention... Figure 6 In this embodiment, the components in the pre-drive circuit 700 are operated using an unconverted first input voltage Vin1 and a converted second conversion voltage Vt2. This allows the components in the pre-drive circuit 700, as well as the components in the drive circuit 400, to have safe voltage across and operate at a more stable voltage.

[0034] Figure 5 and Figure 6 The illustrated embodiments can be used in combination or independently. For example, in one embodiment, Figure 5 The thrust enhancement stage circuit 603 and Figure 6 The thrust enhancement stage circuit 703 can be a separate circuit. In another embodiment, Figure 5 The thrust enhancement stage circuit 603 and Figure 6 The thrust enhancement stage circuit 703 in the circuit consists of the upper bridge circuit and the lower bridge circuit in the same pre-drive circuit.

[0035] therefore, Figure 5 and Figure 6 The embodiments described herein can be briefly described as follows: a voltage level conversion circuit for converting a first input voltage (e.g., Vin1) into a first conversion voltage (e.g., Vt1), or converting a second input voltage (e.g., Vin2) into a second conversion voltage (e.g., Vt2), wherein the first input voltage is higher than the second input voltage, and the first conversion voltage is higher than the second conversion voltage; and a thrust enhancement stage circuit including at least one inverter (e.g., IV4-IV7, the inverter operating on the first input voltage and the second conversion voltage, or operating on the first conversion voltage and the second input voltage. Other logic or inverters are located between pre-drive circuits and can operate on the first input voltage and the second conversion voltage, or operate on the first conversion voltage and the second input voltage.

[0036] In addition to the circuit, this invention also provides an integrated circuit layout for the pre-drive circuit to further increase the stability of the circuit. Figure 7 An illustration of an embodiment of the present invention is shown. Figure 5 and Figure 6 The diagram shows the integrated circuit layout of the pre-drive circuit. However, please note that... Figure 7 The integrated circuit layout shown can also be used on other pre-driven circuits.

[0037] For ease of description and understanding, the descriptions are listed below. Figure 7 The meaning of each component symbol shown in the diagram:

[0038] NW: N well region

[0039] DNW: Deep N well region

[0040] NBO: N-base region, also known as NTAP or N-body, N-butting.

[0041] PBO: P-base region, also known as PTAP or P-body, P-butting.

[0042] D: Drain region of NMOS region.

[0043] S: Source region of NMOS region.

[0044] G: Gate region of NMOS region, please note. Figure 7 Only a portion of the gate region G is shown in this embodiment. A drain region D, a source region S, and a gate region G form an NMOS transistor. Figure 7 In this embodiment, an NMOS region contains two NMOS transistors, but this is not a limitation.

[0045] CH: Contact hole.

[0046] Please note that in Figure 7 In the embodiment, the NMOS may be located in the P-well region, which is located between the NMOS and the deep N-well region but is not shown.

[0047] Rule 1, Rule 2, Rule 3, Rule 4, and Rule 5 represent... Figure 7 The integrated circuit layout shown adopts which rules? For example, if a contact hole CH is marked with Rule 3, it means that this location conforms to Rule 3. The details of Rules 1, 2, 3, 4, and 5 are as follows:

[0048] Rule 1

[0049] The density of the NMOS region is less than a predetermined level, for example, no more than two rows. Furthermore, the P-base region (PBO) completely surrounds the NMOS region, for example, in... Figure 7 In this embodiment, the P-base region PBO is arranged in a complete rectangle. The advantage of this approach is that it increases the influence of the P-base region PBO on the NMOS region, thereby reducing the occurrence of parasitic BJT effects.

[0050] Rule 1 is even more possible Figure 7 As shown, the P-base region PBO is extended so that the P-base region PBO and the source region S are directly connected, thereby further enhancing the influence of the P-base region PBO on the NMOS region.

[0051] Rule 2

[0052] The distance between the NMOS region and the P-base region PBO is less than a maximum distance threshold (e.g., less than 2.27 μm) and greater than a minimum distance threshold (e.g., greater than 0.5 μm). This is advantageous because if the NMOS region and the P-base region PBO are too far apart, the influence of the P-base region PBO on the NMOS region is reduced, making it more susceptible to parasitic BJT effects. Conversely, if the NMOS region and the P-base region PBO are too close, the NMOS's breakdown voltage will decrease, making it more prone to damage.

[0053] Rule 3

[0054] The P-base region PBO has a minimum width that can accommodate three or more rows of contact holes CH, such as Figure 7 As shown. This structure can reduce the resistance and increase the grounding capability of the circuit.

[0055] Rule 4

[0056] The drain region D and source region S of the NMOS region are arranged as follows: source region S-drain region D-drain region D-source region S, for example Figure 7 The SDDS arrangement shown is such that the distance between the source region S and the drain region D is greater than a predetermined threshold, meaning the distance between terminal regions at different potentials is greater than a predetermined threshold. This avoids mutual interference between terminal regions at different potentials and prevents them from affecting the withstand voltage.

[0057] Rule 5

[0058] The distance between the P-base region (PBO) and the N-well region (NW) is greater than a first predetermined critical value, and the distance between the N-base region (NBO) and the deep N-well region (DNW) is greater than a second predetermined critical value. The first and second predetermined critical values ​​may be the same or different. This prevents the occurrence of parasitic BJT effects. Please note that... Figure 7A PMOS transistor can exist between the upper and lower N-base regions (NBO) in the upper middle section, but it is not shown in this figure and will be implemented later. Figure 8 The details are as follows.

[0059] Rule 6

[0060] In other embodiments, a PMOS region may be further included, and the deep N-well region DNW overlaps with a portion of the N-well region NW but not with all or part of the PMOS region.

[0061] Figure 8 An illustration is provided according to an embodiment of the present invention. Figure 7 The diagram illustrates Rule 6. Please also note that, for the sake of simplicity, [the diagram is missing here]. Figure 8 The PMOS and NMOS regions are illustrated using simplified diagrams of the PMOS region Pa…Pd and the NMOS region Na…Nd. The NMOS region Na…Nd may contain… Figure 7 The structure described herein. For example, the NMOS region Na may have Figure 7 The structure of the NMOS region in the upper right corner of the region enclosed by the P-base region PBO, and the NMOS region Ne can contain Figure 7 The structure of the NMOS region in the lower left corner of the region enclosed by the P-base region PBO is shown. The PMOS region Pa…Pd is the same as the NMOS region Na…Nd. In detail, the drain region D and source region S of the PMOS region Pa…Pd can be arranged the same as the drain region D and source region S of the NMOS region Na…Nd, but the P-base region PBO is replaced by the N-base region NBO and is located in the N-well region NW instead of the P-well region.

[0062] like Figure 8 As shown, the deep N-well region DNW overlaps with part of the N-well region NW, but not with all or part of the PMOS region. Specifically, Figure 8 The deep N-well region DNW overlaps with the N-well region NW but not with any PMOS region Pa…Pd, conforming to Rule 6. However, if the deep N-well region DNW extends to… Figure 8 The position of the dashed line in DNW1 overlaps with the PMOS region Pc, which does not conform to Rule 6. Similarly, if the deep N-well region DNW extends to... Figure 8 The position of the dashed line in DNW2 overlaps with the PMOS region Pa…Pd, which does not conform to Rule 6.

[0063] Figure 7 Although the embodiments are illustrated using an NMOS integrated circuit layout, they can also be applied to PMOS integrated circuit layouts, such as... Figure 8 As shown, when applied to PMOS, the polarity of some regions is reversed; for example, the P-well region becomes the N-well region (NW), and the P-base region (PBO) becomes the N-base region (NBO). Therefore, Figure 7 Rules 1, 2, 3, 4, and 5 of the embodiment can be represented as follows. Furthermore, in Figure 7 In one embodiment, type 1 represents N-type, type 2 represents P-type, the first terminal region represents the drain region D, and the second terminal region represents the source region S. In another embodiment, type 1 represents P-type, and type 2 represents N-type, but the first terminal region still represents the drain region D, and the second terminal region still represents the source region S.

[0064] Rule 1

[0065] The density of the Class I transistor regions is less than a predetermined level, for example, no more than two rows. Furthermore, the Class II base regions completely encircle these Class I transistor regions.

[0066] Rule 1 is even more possible Figure 7 As shown, the base region of the second transistor is extended so that the base region of the second transistor and the second terminal region are directly connected, so as to further enhance the influence of the base region of the second transistor on the first transistor region.

[0067] Rule 2

[0068] The distance between the Class I transistor region and the Class II base region is less than a maximum distance threshold and greater than a minimum distance threshold.

[0069] Rule 3

[0070] The base region of a type II electrode has a minimum width that can accommodate two or more rows of contact holes.

[0071] Rule 4

[0072] The first terminal region and the second terminal region of the transistor-like region are arranged as follows: the second terminal region - the first terminal region - the first terminal region - the second terminal region. Furthermore, the distance between the second terminal region and the first terminal region is greater than a predetermined threshold value, meaning the distance between terminal regions at different potentials is greater than a predetermined threshold value.

[0073] Rule 5

[0074] The distance between the Class II base region and the Class I well region is greater than a first predetermined critical value, and the distance between the Class I base region and the Class I deep well region is greater than a second predetermined critical value. The first predetermined critical value and the second predetermined critical value may be the same or different.

[0075] The foregoing embodiments can be used in combination or independently. For example, Figure 5 and Figure 6 The pre-drive circuit shown may be coupled to an ESD circuit, or may include, but is not limited to, [specific features]. Figure 4The drive circuit 400 is shown. This ESD circuit or pre-drive circuit, or drive circuit, can use the aforementioned architecture, but other architectures can also be used.

[0076] According to the foregoing embodiments, the withstand voltage of the circuit elements of the ESD protection circuit and the circuit stability of the pre-drive circuit, drive circuit or overall output stage circuit can be improved, thus improving the problems in the prior art.

[0077] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

[0078] [Symbol Explanation]

[0079] 100 ESD protection circuit

[0080] 101 RC circuit

[0081] 103 NOR gate

[0082] 105 Protective Transistor

[0083] 400 drive circuit

[0084] 600, 700 pre-drive circuit

[0085] 601, 701 Voltage Level Conversion Circuit

[0086] 603 and 703 thrust enhancement stage circuits

[0087] Capacitors C1 and C2

[0088] D1 diode

[0089] resistors R1 and R2

[0090] N1 First NMOS

[0091] N2 Second NMOS

[0092] Na,Nb,Nc,Nd,Ne NMOS

[0093] Pa, Pb, Pc, Pd, Pe PMOS

[0094] P1 First PMOS

[0095] P2 Second PMOS

[0096] Inverters IV1, IV2, IV3, IV4, IV5, IV6, IV7

[0097] LG1 logic gate

[0098] NW N well area

[0099] DNW Deep N Well Area

[0100] NBO N base region

[0101] PBO P base region

[0102] D. Drainage Zone

[0103] S source region

[0104] G gate region

[0105] CH contact hole

[0106] SL impedance layer

Claims

1. A pre-driving circuit, comprising: A voltage level conversion circuit receives a first input voltage and a second input voltage. The voltage level conversion circuit is configured to: convert the first input voltage to a first converted voltage without converting the second input voltage, or convert the second input voltage to a second converted voltage without converting the first input voltage, wherein the first input voltage is higher than the second input voltage, and the first converted voltage is higher than the second converted voltage; and A thrust enhancement stage circuit includes at least one inverter, wherein: When the voltage level conversion circuit converts the second input voltage to the second converted voltage without converting the first input voltage, the inverter operates at the first input voltage and the second converted voltage. When the voltage level conversion circuit converts the first input voltage to the first converted voltage without converting the second input voltage, the inverter operates at the first converted voltage and the second input voltage.

2. The pre-drive circuit according to claim 1, wherein the thrust enhancement stage circuit is coupled to a drive circuit, the drive circuit being coupled to a first voltage source and a second voltage source, and comprising: A first-class transistor is coupled to the second voltage source; A second type of transistor is connected in series with the first type of transistor, and a control terminal of the second type of transistor is coupled to the first voltage source; and A first type of two transistor is coupled between the first voltage source and the second type of one transistor.

3. A combinational circuit, comprising: The pre-drive circuit according to any one of claims 1 to 2; and An electrostatic discharge protection circuit, coupled to the pre-drive circuit, includes: A capacitor-resistor circuit; A protection transistor, coupled to a first voltage source and a second voltage source, is used to provide a conduction path between the first voltage source and the second voltage source according to a control voltage, wherein a second voltage provided by the second voltage source is lower than a first voltage provided by the first voltage source; and A NOR gate is coupled between the capacitor-resistor circuit and the protection transistor to provide the control voltage based on the output of the capacitor-resistor circuit and a predetermined voltage.

4. The combinational circuit of claim 3, wherein the NOR gate comprises: A first type of transistor is coupled to the second voltage source, the protection transistor, and a control terminal of the first type of transistor is coupled to the capacitor-resistor circuit. A second type of transistor is coupled to the second voltage source, the protection transistor and the first type of transistor, and a control terminal of the second type of transistor receives the predetermined voltage. A first-type dual transistor, coupled to the first voltage source, and a control terminal of the first-type dual transistor for receiving the predetermined voltage; and A second type of two transistor is coupled to the first type of one transistor, the second type of one transistor, the first type of two transistor, and the protection transistor, and a control terminal of the second type of two transistor is coupled to the capacitor-resistor circuit and the control terminal of the first type of one transistor.

5. An integrated circuit layout for use in the pre-drive circuit according to claim 1, the integrated circuit layout comprising: A plurality of transistor-like regions, wherein the density of these transistor-like regions is less than a predetermined level; and A type of dual-base region, forming a complete ring around these type-one transistor regions.

6. The integrated circuit layout according to claim 5, wherein each of the types of transistor regions includes a first terminal region and a second terminal region, and the type of dual base regions further extend to be directly connected to the second terminal region.

7. The integrated circuit layout according to claim 5, wherein the distance between each type of transistor region and the type of dual base region is less than a maximum distance threshold and greater than a minimum distance threshold.

8. The integrated circuit layout according to claim 5, wherein each of the transistor regions comprises a first terminal region and a second terminal region, the first terminal regions and the second terminal regions of the transistor regions are arranged in the following manner: the second terminal region-the first terminal region-the first terminal region-the second terminal region, and the distance between the second terminal region and the first terminal region is greater than a predetermined threshold value.

9. The integrated circuit layout according to claim 5, further comprising: Category 1 well area; Category 1, Deep Well Area; One type of base region; The distance between the two base regions of this type and the one well region of this type is greater than a first predetermined critical value, and the distance between the one base region of this type and the one deep well region of this type is greater than a second predetermined critical value.

10. The integrated circuit layout according to claim 9, wherein the type of transistor region is an NMOS region, the type of well region is an N-well region, the type of deep well region is a deep N-well region, and overlaps with a portion of the type of well region but not with all or part of the PMOS region.

Images