Display panel, manufacturing method and display device

Abstract

The application discloses a display panel, a preparation method and a display device. The display panel comprises a display area and a non-display area located at the periphery of the display area, and further comprises a substrate, a composite dielectric layer located on one side of the substrate, the composite dielectric layer comprising a first via hole penetrating through the composite dielectric layer at least partially, and a conductive layer, at least part of the conductive layer being located on the side of the composite dielectric layer away from the substrate, the conductive layer comprising a power signal line. In the non-display area, the power signal line and the first via hole at least partially overlap in the thickness direction of the display panel, and the power signal line at least partially covers the bottom and sidewall of the first via hole. By increasing the coverage area of the power signal line, the resistance of the power signal line is effectively reduced, the light-emitting effect of the display panel is increased, and the power consumption of the display panel is effectively reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel, a preparation method and a display device. BACKGROUND

[0002] With the rapid development of active-matrix organic light emitting diode (AMOLED), the AMOLED display panel has a wider viewing angle, higher refresh rate and thinner size, and has the characteristics of self-luminous, wide viewing angle, short response time, high luminous efficiency, wide color gamut, low operating voltage, etc., and is considered to be the most potential display device. However, on the basis of existing materials and process equipment, it is difficult to manufacture a low-power-consumption AMOLED display panel; at the same time, the production process of the existing AMOLED display panel is complex and difficult, which does not save the production cost. SUMMARY

[0003] The present application provides a display panel, a preparation method and a display device, which increases the coverage area of the power signal line, effectively reduces the resistance of the power signal line, increases the light-emitting effect of the display panel, and can effectively reduce the power consumption of the display panel.

[0004] In a first aspect, an embodiment of the present application provides a display panel, comprising: a display area and a non-display area located at the periphery of the display area,

[0005] The display panel further comprises a substrate;

[0006] A composite dielectric layer is located on one side of the substrate, and the composite dielectric layer comprises a first via penetrating at least partially through the composite dielectric layer;

[0007] A conductive layer is located at least partially on the side of the composite dielectric layer away from the substrate, and the conductive layer comprises a power signal line;

[0008] In the non-display area, the power signal line and the first via at least partially overlap in the thickness direction of the display panel, and the power signal line at least partially covers the bottom and sidewall of the first via.

[0009] In a second aspect, an embodiment of the present application provides a preparation method of a display panel, comprising:

[0010] Providing a substrate;

[0011] Preparation of a composite dielectric layer on one side of the substrate;

[0012] Preparation of a conductive layer on the side of the composite dielectric layer away from the substrate, and the conductive layer comprises a power signal line;

[0013] A first via hole is prepared in the non-display area. Along the thickness direction of the display panel, the power signal line at least partially overlaps with the first via hole, and the power signal line at least partially covers the bottom and sidewall of the first via hole.

[0014] In a third aspect, an embodiment of the present invention provides a display device comprising the display panel according to any one of the first aspects.

[0015] The technical solution of an embodiment of the present invention is that a display panel includes a display area and a non-display area located outside the display area. The display panel also includes a substrate, a composite dielectric layer located on one side of the substrate, the composite dielectric layer including a first via that at least partially penetrates the composite dielectric layer; and a conductive layer, at least a portion of which is located on a side of the composite dielectric layer away from the substrate. The conductive layer includes a power signal line, which is used to transmit the power signal line to the display area, thereby driving each light-emitting element in the display area to emit light. Within the non-display area, along the thickness direction of the display panel, the power signal line at least partially overlaps with the first via, and the power signal line at least partially covers the bottom and sidewalls of the first via, thereby increasing the coverage area of ​​the power signal line, reducing the resistance of the power signal line, and increasing the luminous efficiency of the display panel.

[0016] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 This is a schematic structural diagram of a display panel in the prior art;

[0019] Figure 2 A schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0020] Figure 3 A schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0021] Figure 4 for Figure 2 A schematic diagram of a cross-sectional structure along the section line AA';

[0022] Figure 5 for Figure 2Another cross-sectional structure schematic view along the cross-sectional line AA';

[0023] Figure 6 For Figure 2 Another cross-sectional structure schematic view along the cross-sectional line AA';

[0024] Figure 7 For Figure 2 Another cross-sectional structure schematic view along the cross-sectional line AA';

[0025] Figure 8 For Figure 3 Another cross-sectional structure schematic view along the cross-sectional line AA';

[0026] Figure 9 For Figure 3 Another cross-sectional structure schematic view along the cross-sectional line BB';

[0027] Figure 10 For Figure 3 Another cross-sectional structure schematic view along the cross-sectional line AA';

[0028] Figure 11 For Figure 3 Another cross-sectional structure schematic view along the cross-sectional line BB';

[0029] Figure 12 For Figure 3 Another cross-sectional structure schematic view along the cross-sectional line AA';

[0030] Figure 13 For Figure 3 Another cross-sectional structure schematic view along the cross-sectional line AA';

[0031] Figure 14 Another structure schematic view of a display panel provided by the embodiment of the present application;

[0032] Figure 15 For Figure 14 Another cross-sectional structure schematic view along the cross-sectional line CC';

[0033] Figure 16 For Figure 14 Another cross-sectional structure schematic view along the cross-sectional line CC';

[0034] Figure 17 A flow schematic view of a preparation method of a display panel provided by the embodiment of the present application;

[0035] Figure 18 A flow schematic view of a preparation method of another display panel provided by the embodiment of the present application;

[0036] Figure 19A schematic flow chart of another method for manufacturing a display panel provided by an embodiment of the present invention;

[0037] Figure 20 A schematic flow chart of another method for manufacturing a display panel provided by an embodiment of the present invention;

[0038] Figure 21 A schematic flow chart of another method for manufacturing a display panel provided by an embodiment of the present invention;

[0039] Figure 22 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0040] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0041] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0042] Figure 1 FIG. 1 is a schematic diagram of a structure of a display panel in the prior art. Figure 1 As shown, in the non-display area 11 of the display panel 10, at least a substrate 12, at least one inorganic insulating layer 13 located on one side of the substrate 12, and a plurality of metal traces 14 spaced apart on the side of the substrate 12 away from the inorganic insulating layer 13. The metal traces 14 are used to transmit power signals. In the prior art, the resistance of the metal traces 14 is usually reduced by increasing the line width or thickness of the metal traces 14. However, increasing the line width of the metal traces 14 is likely to cause a short circuit risk between adjacent metal traces 14, or increasing the thickness of the metal traces 14 increases the difficulty of the etching process and increases the preparation cost.

[0043] To solve the above technical problems, the display panel provided by the embodiment of the present application comprises a display area and a non-display area located at the periphery of the display area, and further comprises a substrate, a composite dielectric layer located at one side of the substrate, the composite dielectric layer comprising a first via hole penetrating through the composite dielectric layer at least partially; a conductive layer, at least part of the conductive layer being located at the side of the composite dielectric layer away from the substrate, the conductive layer comprising a power signal line. In the non-display area, the power signal line and the first via hole at least partially overlap along the thickness direction of the display panel, and the power signal line at least partially covers the bottom and sidewall of the first via hole, thereby increasing the coverage area of the power signal line, reducing the resistance of the power signal line, increasing the light-emitting efficiency of the display panel, and reducing the power consumption of the display panel.

[0044] The above is the core idea of the present application, and the technical solutions in the embodiments of the present application will be described clearly and completely in combination with the drawings in the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0045] Figure 2 A structural schematic diagram of a display panel provided by the embodiment of the present application is shown in FIG. 1, Figure 3 A structural schematic diagram of another display panel provided by the embodiment of the present application is shown in FIG. 2, Figure 4 A structural schematic diagram of another display panel provided by the embodiment of the present application is shown in FIG. 3, Figure 2 A structural schematic diagram of another display panel provided by the embodiment of the present application is shown in FIG. 4, Figure 5 A structural schematic diagram of another display panel provided by the embodiment of the present application is shown in FIG. 5, Figure 2 A structural schematic diagram of another display panel provided by the embodiment of the present application is shown in FIG. 6, Figure 6 A structural schematic diagram of another display panel provided by the embodiment of the present application is shown in FIG. 7, Figure 2 A structural schematic diagram of another display panel provided by the embodiment of the present application is shown in FIG. 8, Figure 7 A structural schematic diagram of another display panel provided by the embodiment of the present application is shown in FIG. 9, Figure 2 A structural schematic diagram of another display panel provided by the embodiment of the present application is shown in FIG. 10, as shown in FIGS. 1-10, Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 As shown in FIGS. 1-10, the display panel 100 comprises a display area 101 and a non-display area 102 located at the periphery of the display area 101, and further comprises a substrate 103, a composite dielectric layer 104 located at one side of the substrate 103, the composite dielectric layer 104 comprising a first via hole 107 penetrating through the composite dielectric layer 104 at least partially, a conductive layer 105, at least part of the conductive layer 105 being located at the side of the composite dielectric layer 104 away from the substrate 103, the conductive layer 105 comprising a power signal line 106, and in the non-display area 102, there exists at least partial overlap between the power signal line 106 and the first via hole 107 along the thickness direction X of the display panel 100, and the power signal line 106 at least partially covers the bottom and sidewall of the first via hole 107. ​​​​​

[0046] The display area is provided with pixel circuits, light emitting elements, etc. The non-display area is provided with a shift register, a driving chip, a pad, etc. The display panel 100 comprises a substrate 103, which can be a rigid substrate or a flexible substrate. The material of the substrate 103 can be selected according to actual design requirements, and the embodiments of the present application do not make specific limitations. A composite dielectric layer 104 is arranged on one side of the substrate 103, and the composite dielectric layer 104 is composed of multiple film layers. The composite dielectric layer 104 can include a gate insulating layer, a capacitor insulating layer, an interlayer insulating layer, and an interlayer dielectric layer, etc. The materials of the various film layers in the composite dielectric layer 104 can be the same or different, and can include any one or any two or more of silicon oxide, silicon nitride, and silicon oxynitride, which can be selected according to actual design requirements. Due to space limitations, at least part of the first via hole 107 that penetrates the composite dielectric layer 104 can be formed in the non-display area 102. The etching depth of the first via hole 107 and the etching shape of the first via hole 107 can be selected according to actual design requirements. In the example, the first via hole 107 is a cuboid. The conductive layer 105 is prepared on the side of the composite dielectric layer 104 away from the substrate 103, and the conductive layer 105 is patterned to form a plurality of spaced-apart power signal lines 106. Adjacent power signal lines 106 do not contact to avoid short circuit. Optionally, in any plane perpendicular to the light-emitting surface of the display panel 100, the shape of the power signal line 106 is at least one of a U shape, a few character shape, a wave shape, or an arch shape. Figure 4 and Figure 5 In the example, the shape of part of the power signal line 106 is a few character shape. Figure 6 In the example, the shape of part of the power signal line 106 is a U shape. Figure 7 In the example, the shape of part of the power signal line 106 is a wave shape. The specific shape can be selected according to actual design requirements. At the same time, the composition material of the power signal line 106 can include one or more of Mo, Ti, Al, Ag, and Cu conductive metals. Therefore, the power signal line 106 can be a single-layer structure or a multi-layer structure. The material and the number of layers of the power signal can be selected according to actual design requirements, and the embodiments of the present application do not make specific limitations. In the non-display area 102, along the thickness direction X of the display panel 100, the power signal line 106 at least partially overlaps the first via hole 107. As shown in Figure 4 and Figure 6 As shown in Figure 5 and Figure 7As shown, the power signal line 106 at least partially covers the bottom and sidewall of the first via 107, and the partial power signal line 106 is arranged in a three-dimensional manner, which effectively increases the coverage area of the power signal line 106, reduces the resistance of the power signal line 106, and then increases the voltage division when driving the thin film transistor in the pixel circuit, thereby increasing the driving current and increasing the light-emitting efficiency of the light-emitting element in the display area 101. At the same time, the light-emitting element can be lit using a smaller driving current at the same brightness, thereby effectively reducing the power consumption of the display panel 100. At the same time, the three-dimensional arrangement of the power signal line 106 does not increase the horizontal extension length of the power signal line 106, avoids increasing the area of the non-display area 102 of the display panel 100, and is not conducive to narrow frame design.

[0047] It should be noted that the cross-sectional structure diagram only exemplarily shows the structure of the power signal line, and other signal transmission lines such as data signal transmission lines in the non-display area have the same or similar structure as the prior art, which is not shown here.

[0048] The embodiment of the present application forms a first via in the composite dielectric layer, and then prepares a conductive layer to form a power signal line. In the non-display area, the power signal line and the first via at least partially overlap along the thickness direction of the display panel, and the power signal line at least partially covers the bottom and sidewall of the first via, thereby increasing the coverage area of the power signal line, reducing the resistance of the power signal line, and effectively reducing the power consumption of the display panel.

[0049] Optionally, with reference to Figure 4 , Figure 5 , Figure 6 and Figure 7 , the power signal line 106 at least includes a first power signal line part 1061, a second power signal line part 1062, and a third power signal line part 1063. The second power signal line part 1062 is connected with the first power signal line part 1061 and the third power signal line part 1063 respectively. The first power signal line part 1061 is located on the side of the composite dielectric layer 104 away from the substrate 103 and contacts the surface of the side of the composite dielectric layer 104 away from the substrate 103. The second power signal line part 1062 covers the sidewall of the first via 107. The third power signal line part 1063 covers the bottom of the first via 107.

[0050] As shown in Figure 4 and Figure 6 , the same power signal line 106 overlaps with at least one first via 107. In any plane perpendicular to the light-emitting surface of the display panel 100, for example, as shown in Figure 4 , the cross section of the power signal line 106 is a reversed U shape or a combination of multiple reversed U shapes; as shown in Figure 6As shown, the cross-section of the power signal line 106 is a U-shape or a combination of multiple U-shapes; the power signal line 106 may include different types of first power signal lines 114 and second power signal lines 115, the first power signal line 114 includes three first power signal line sections 1061 located on the side of the composite dielectric layer 104 away from the substrate 103 and in contact with the surface of the composite dielectric layer 104 away from the substrate 103, four second power signal line sections 1062 covering the side walls of the first via 107 and two third power signal line sections 1063 covering the bottom of the first via 107, the first power signal line section 1061, the second power signal line section 1062, the third power signal line section 1063, the second power signal line section 1062, the first power signal line section 1061, the second power signal line section 1062, the third power signal line section 1063, the second power signal line section 1062 and the first power signal line section 1061 are connected in sequence. The second power signal line 115 includes two first power signal line divisions 1061 located on the side of the composite dielectric layer 104 away from the substrate 103 and in contact with the surface of the composite dielectric layer 104 away from the substrate 103, two second power signal line divisions 1062 covering the side walls of the first via 107, and a third power signal line division 1063 covering the bottom of the first via 107. The first power signal line division 1061, the second power signal line division 1062, the third power signal line division 1063, the second power signal line division 1062 and the first power signal line division 1061 are connected in sequence.

[0051] like Figure 5 and Figure 7 As shown, the same power signal line 106 overlaps with at least one first via hole 107, and in any plane perpendicular to the light-emitting surface of the display panel 100, as shown in FIG. Figure 5 As shown, the cross section of the power signal line 106 is in the shape of a cross or a combination of multiple crosses; Figure 7As shown, the cross section of the power signal line 106 is in a wave shape or a combination of multiple wave shapes. The power signal line 106 can include different types of first power signal line 114 and second power signal line 115, the first power signal line 114 includes two first power signal line sections 1061 located on the side of the composite dielectric layer 104 away from the substrate 103 and in contact with the surface of the side of the composite dielectric layer 104 away from the substrate 103, four second power signal line sections 1062 covering the sidewalls of the first via 107, and three third power signal line sections 1063 covering the bottom of the first via 107, the third power signal line sections 1063, the second power signal line sections 1062, the first power signal line sections 1061, the second power signal line sections 1062, the third power signal line sections 1063, the second power signal line sections 1062, the first power signal line sections 1061, the second power signal line sections 1062, and the third power signal line sections 1063 are sequentially connected. The second power signal line 115 includes one first power signal line section 1061 located on the side of the composite dielectric layer 104 away from the substrate 103 and in contact with the surface of the side of the composite dielectric layer 104 away from the substrate 103, two second power signal line sections 1062 covering the sidewalls of the first via 107, and two third power signal line sections 1063 covering the bottom of the first via 107, the third power signal line sections 1063, the second power signal line sections 1062, the first power signal line sections 1061, the second power signal line sections 1062, and the third power signal line sections 1063 are sequentially connected. The above Figure 4 、 Figure 5 、 Figure 6 and Figure 7 The arrangement of the power signal line 106 in the above embodiments can effectively increase the coverage area of the power signal line 106, thereby effectively reducing the resistance of the power signal line 106. The cross-sectional shape of the power signal line 106 is not limited to the above embodiments.

[0052] Optionally, Figure 8 is another cross-sectional structure schematic view along the cross-sectional line AA' in Figure 3 is another cross-sectional structure schematic view along the cross-sectional line AA' in Figure 9 is another cross-sectional structure schematic view along the cross-sectional line BB' in Figure 3 is another cross-sectional structure schematic view along the cross-sectional line BB' in Figure 10 is another cross-sectional structure schematic view along the cross-sectional line AA' in Figure 3 is another cross-sectional structure schematic view along the cross-sectional line AA' in Figure 11 is another cross-sectional structure schematic view along the cross-sectional line BB' in Figure 3 is another cross-sectional structure schematic view along the cross-sectional line BB' in Figure 8 、 Figure 9 、 Figure 10 and Figure 11As shown, the display panel 100 further comprises a first auxiliary metal layer 108 located in the non-display area 102, the first auxiliary metal layer 108 is located on the side of the substrate 103 close to the composite dielectric layer 104 or on the side of the substrate 103 away from the composite dielectric layer 104, and the first auxiliary metal layer 108 is electrically connected to the power signal line 106 through the second via hole 109.

[0053] As shown in Figure 8 and Figure 9 , the display panel 100 is a rigid display panel, the substrate 103 is a rigid substrate, in the non-display area 102, the first auxiliary metal layer 108 is located on the side of the substrate 103 close to the composite dielectric layer 104, and a first buffer layer 20 is usually arranged between the substrate 103 and the composite dielectric layer 104, the first buffer layer 20 is located on the side of the substrate 103 close to the composite dielectric layer 104, the first auxiliary metal layer 108 is prepared on the side of the first buffer layer 20 away from the substrate 103, and a second buffer layer 21 is prepared to cover the first auxiliary metal layer 108 to protect the first auxiliary metal layer 108.

[0054] As shown in Figure 10 and Figure 11 , the display panel 100 is a flexible display panel, the substrate 103 is a flexible substrate, in the non-display area 102, the first auxiliary metal layer 108 is located on the side of the substrate 103 away from the composite dielectric layer 104, before the substrate 103 is prepared, a sacrificial layer 22 and a second buffer layer 21 are prepared on a glass substrate, the first auxiliary metal layer 108 is prepared on the side of the second buffer layer 21 away from the sacrificial layer 22, and a third buffer layer 23 is prepared to cover the first auxiliary metal layer 108 to protect the first auxiliary metal layer 108. The substrate 103 is prepared on the side of the third buffer layer 23 away from the sacrificial layer 22. Different layout modes of the first auxiliary metal layer 108 are selected according to different types of the substrate 103. In the non-display area 102, the first auxiliary metal layer 108 is arranged in the display panel 100, and the first auxiliary metal layer 108 can be electrically connected to the power signal line 106 through the second via hole 109, so that the first auxiliary metal layer 108 and the power signal line 106 are connected in parallel, effectively reducing the resistance. At the same time, the power signal line 106 can be adaptively reduced in size, reducing the contact between adjacent power signal lines 106, reducing the risk of short circuit, and reducing the width of the lower step in the non-display area 102, realizing the miniaturization design of the display panel 100. At the same time, since the first auxiliary metal layer 108 is only connected in parallel with the power signal line 106, the size of the first auxiliary metal layer 108 can be appropriately increased according to the space size, further reducing the resistance of the metal trace.

[0055] Optionally, continuing to refer to Figure 8 , Figure 9 , Figure 10 and Figure 11The conductive layer 105 and the first auxiliary metal layer 108 at least partially overlap in the thickness direction X of the display panel 100.

[0056] The first auxiliary metal layer 108 can be spaced apart and multiple, the projection area of each first auxiliary metal layer 108 and the corresponding power signal line 106 can be the same or different, and each power signal line 106 in the conductive layer 105 can be electrically connected to the corresponding first auxiliary metal layer 108. When the conductive layer 105 is electrically connected to the first auxiliary metal layer 108, that is, when the first auxiliary metal layer 108 is connected in parallel with the power signal line 106, the power signal line 106 and the first auxiliary metal layer 108 at least partially overlap in the thickness direction X of the display panel 100 to realize the electrical connection through the hole. In order to avoid the risk of short circuit between adjacent power signal lines 106, the size of the power signal line 106 in the conductive layer 105 can be appropriately reduced, but it is necessary to ensure that the power signal line 106 and the corresponding first auxiliary metal layer 108 overlap in the thickness direction X of the display panel 100 to ensure the parallel effect of the power signal line 106 and the first auxiliary metal layer 108, thereby reducing the metal trace resistance.

[0057] Optionally, Figure 12 For Figure 3 Another cross-sectional structure schematic diagram along the cross-sectional line AA' in the above embodiment, Figure 13 For Figure 3 Another cross-sectional structure schematic diagram along the cross-sectional line AA' in the above embodiment, as shown in Figure 12 And Figure 13 The projection area of the conductive layer 105 is smaller than the projection area of the first auxiliary metal layer 108 in the thickness direction X of the display panel 100.

[0058] Under the premise of ensuring the parallel effect of the power signal line 106 and the first auxiliary metal layer 108, considering the space size of the position where the first auxiliary metal layer 108 is located and the fact that the first auxiliary metal layer 108 is only used for connection with the power signal line 106, the size of the first auxiliary metal layer 108 can be appropriately increased when the space is sufficient, thereby improving the space utilization rate. In order to avoid the risk of short circuit between adjacent power signal lines 106, the size of the power signal line 106 can be appropriately reduced, thereby reducing the size of the lower step in the non-display area 102, which is beneficial to the narrow frame design of the display panel 100. As shown in Figure 12 And Figure 13 The projection of each power signal line 106 can completely fall within the projection range of the corresponding first auxiliary metal layer 108 in the thickness direction X of the display panel 100, thereby further reducing the metal trace resistance, improving the light-emitting efficiency, and ensuring the display effect of the display panel 100.

[0059] Optionally, Figure 14Another structural schematic diagram of a display panel provided by an embodiment of the present application, Figure 15 For Figure 14 A cross-sectional structural schematic diagram along the cross-sectional line CC' in the display panel, Figure 16 For Figure 14 A cross-sectional structural schematic diagram along the cross-sectional line CC' in the display panel, as shown in Figure 14 , Figure 15 and Figure 16 The display panel 100 also includes a second auxiliary metal layer 110 located in the display area 101, the second auxiliary metal layer 110 is located on the side of the substrate 103 close to the composite dielectric layer 104 or on the side of the substrate 103 away from the composite dielectric layer 104, and the second auxiliary metal layer 110 is electrically connected to the power signal line 106 through a third via hole 111.

[0060] In the display area 101, the second auxiliary metal layer 110 can also be provided, so that the second auxiliary metal layer 110 is connected in parallel with the power signal line 106 in the display area 101, further reducing the metal trace resistance, to ensure the display effect of the display panel 100. The first auxiliary metal layer 108 and the second auxiliary metal layer 110 can be prepared in the same layer, and the preparation materials can be the same. The composition material of the first auxiliary metal layer 108 and the second auxiliary metal layer 110 can be one or more of Mo, Ti, Al, Ag, Cu and other conductive metals, which can be selected according to actual design requirements. As shown in Figure 15 The display panel 100 is a rigid display panel, in the display area 101, the second auxiliary metal layer 110 is located on the side of the substrate 103 close to the composite dielectric layer 104, and a first buffer layer 20 is usually provided between the substrate 103 and the composite dielectric layer 104, the first buffer layer is located on the side of the substrate 103 close to the composite dielectric layer 104, the second auxiliary metal layer 110 is prepared on the side of the first buffer layer 20 away from the substrate 103, and a second buffer layer 21 is prepared to cover the second auxiliary metal layer 110, to protect the second auxiliary metal layer 110.

[0061] As shown in Figure 16As shown, the display panel 100 is a flexible display panel, and the substrate 103 is a flexible substrate. In the display area 101, the second auxiliary metal layer 110 is located on the side of the substrate 103 away from the composite dielectric layer 104. Before the substrate 103 is prepared, the sacrificial layer 22, the second buffer layer 21, and the second auxiliary metal layer 110 are prepared on a glass substrate in sequence. The second auxiliary metal layer 110 is prepared on the side of the second buffer layer 21 away from the sacrificial layer 22, and the third buffer layer 23 is prepared to cover the second auxiliary metal layer 110, thereby protecting the second auxiliary metal layer 110. Then, the substrate 103 is prepared on the side of the third buffer layer 23 away from the sacrificial layer 22. Different layout modes of the second auxiliary metal layer 110 are selected according to different types of the substrate 103. In the display area 101, the display panel 100 is provided with the second auxiliary metal layer 110. The second auxiliary metal layer 110 can be electrically connected to the power signal line 106 through the third via hole 111, so that the second auxiliary metal layer 110 located in the display area 101 is connected in parallel with the power signal line 106 located in the display area 101, thereby further effectively reducing the resistance. In addition, the first buffer layer 20, the second buffer layer 21, the third buffer layer 23, and the sacrificial layer 22 located in the display area 101 of the display panel 100 are prepared in the same layer as the first buffer layer 20, the second buffer layer 21, the third buffer layer 23, and the sacrificial layer 22 located in the non-display area 102, and have the same structure.

[0062] Optionally, continuing to refer to Figure 15 and Figure 16 , the display area 101 further includes a first thin film transistor 112 and a second thin film transistor 113. In the thickness direction X of the display panel 100, the second auxiliary metal layer 110 at least partially overlaps the second thin film transistor 113.

[0063] The display panel 100 includes display panels 100 of different types of thin film transistors, which can be selected. The first thin film transistor 112 is a low-temperature polysilicon thin film transistor, and the second thin film transistor 113 is an oxide semiconductor thin film transistor. The first thin film transistor 112 is a low-temperature polysilicon thin film transistor, which has the advantages of high switching speed, high carrier mobility, and low power consumption. The second thin film transistor 113 is an oxide semiconductor thin film transistor, which has the advantages of simple preparation process and small leakage current. The display panel 100 includes two types of thin film transistors, which can fully utilize the advantages of the two types of thin film transistors, thereby ensuring good display performance of the display panel 100. Due to the influence of the preparation material of the second thin film transistor 113, it is easy to be affected by external light. Therefore, a light blocking layer is usually arranged at the position corresponding to the second thin film transistor 113. Since the second auxiliary metal layer 110 is arranged in the display area 101 of the display panel 100, the second auxiliary metal layer 110 can be reused as a light blocking layer, which simplifies the preparation process, reduces the preparation difficulty, reduces the intensity of light irradiated on the second thin film transistor 113, reduces the display difference of the display panel 100, reduces the display unevenness of the display panel 100, and ensures the display effect of the display panel 100.

[0064] Optionally, with reference to Figure 4 、 Figure 5 、 Figure 6 and Figure 7 , the power signal line 106 includes a first power signal line 114 and a second power signal line 115. The voltage value of the first power signal transmitted by the first power signal line 114 is greater than the voltage value of the second power signal transmitted by the second power signal line 115.

[0065] The power signal line 106 is used to transmit the power signal transmitted by the driving chip to each pixel circuit in the display area 101, thereby ensuring the normal display effect of the display panel 100. The power signal line 106 includes a first power signal line 114 and a second power signal line 115. The first power signal line 114 and the second power signal line 115 respectively transmit power signals with opposite polarities. The voltage value of the first power signal transmitted by the first power signal line 114 is greater than the voltage value of the second power signal transmitted by the second power signal line 115. That is, the first power signal line 114 is a PVDD power line, which is used to transmit a PVDD power signal. The second power signal line 115 is a PVEE power line, which is used to transmit a PVEE power signal. In combination with the data signal, the light-emitting control signal, the scanning signal and the reference voltage signal in the pixel circuit, the light-emitting element connected to the pixel circuit is driven to emit light, thereby realizing the display effect.

[0066] Optionally, with reference to Figure 4 、 Figure 5 、 Figure 6And Figure 7 The first power signal line 114 is arranged in the same layer as the second power signal line 115.

[0067] The first power signal line 114 and the second power signal line 115 are prepared by the same metal and the same process in the same layer, without the need to increase additional process steps, effectively reducing the preparation difficulty and cost. The preparation material of the first power signal line 114 and the second power signal line 115 can be one or more of conductive metals such as Mo, Ti, Al, Ag, Cu, etc. For example, it can be a laminated structure Ti / Al / Ti formed by multiple metal materials. The specific material and structure selection can be selected according to actual design requirements, and the embodiments of the present application are not specifically limited.

[0068] Optionally, the shape of the frame of the display panel 100 can include but is not limited to a rectangle as shown in Figure 2 or a circle as shown in Figure 3 The display panel 100 can also be shaped, that is, irregularly shaped, which can be selected according to actual design requirements to meet different needs of users.

[0069] Based on the same inventive concept, the embodiments of the present application also provide a preparation method of a display panel, or it can be understood that the preparation method of the display panel can form the display panel provided in the above embodiments, so the preparation method of the display panel also has the beneficial effects of the above display panel. The same parts can be understood with reference to the above explanation and description of the display panel, and will not be repeated here.

[0070] Figure 17 A flowchart of a preparation method of a display panel provided by the embodiments of the present application is shown in Figure 17 The method comprises the following steps:

[0071] S101, providing a substrate.

[0072] The substrate can be a rigid substrate formed of glass or silicon wafer, or a flexible substrate formed of ultra-thin glass, metal foil or high molecular plastic material, and the selection of the specific substrate material can be selected according to actual design requirements, and the embodiments of the present application are not specifically limited.

[0073] S102, preparing a composite dielectric layer on one side of the substrate.

[0074] The plurality of inorganic insulating layers are sequentially deposited on the substrate side to form a composite dielectric layer, each inorganic insulating layer can at least include a gate insulating layer, a capacitor insulating layer and an interlayer insulating layer sequentially formed along the side close to the substrate, each inorganic insulating layer can be formed by chemical vapor deposition or atomic layer deposition, and the constituent material can include any one or any two or more of silicon oxide, silicon nitride and silicon oxynitride. Meanwhile, a first buffer layer is arranged between the substrate and the composite dielectric layer to protect the substrate.

[0075] S103, in the non-display area, a first via hole is prepared in the composite dielectric layer.

[0076] The composite dielectric layer composed of the plurality of inorganic insulating layers is etched in the non-display area to form a plurality of first via holes, and the etching depth and etching shape can be selected according to specific design requirements, which are not limited in the embodiments of the present application.

[0077] S104, a conductive layer is prepared on the side of the composite dielectric layer away from the substrate, and the conductive layer includes a power signal line. In the thickness direction of the display panel, the power signal line at least partially overlaps the first via hole, and the power signal line at least partially covers the bottom and sidewall of the first via hole.

[0078] The metal material is deposited on the side of the composite dielectric layer away from the substrate to form a conductive layer, the conductive layer is designed in a pattern, thereby forming a plurality of power signal lines, the power signal lines include different types, and the power signal lines do not contact each other. And part of the conductive layer is deposited in the first via hole, so that at least part of the conductive layer covers the bottom and sidewall of the first via hole, so as to ensure the coverage area of the power signal line, thereby reducing the resistance of the power signal line, and thereby reducing the power consumption of the display panel.

[0079] The embodiments of the present application effectively increase the coverage area of the power signal line by forming the first via hole in the composite dielectric layer and depositing the conductive layer on the side of the composite dielectric layer away from the substrate and in the first via hole, thereby forming the power signal line, thereby reducing the resistance of the power signal line, increasing the driving current, and thereby effectively improving the luminous efficiency of the display panel.

[0080] Optionally, Figure 18 Another flowchart of a preparation method of a display panel provided by the embodiments of the present application is shown in the figure, Figure 19 Another flowchart of a preparation method of a display panel provided by the embodiments of the present application is shown in the figure, Figure 18 And Figure 19 As shown in the figure, the method comprises:

[0081] S201, providing a substrate.

[0082] S202, a composite dielectric layer is prepared on one side of the substrate, and the composite dielectric layer at least includes a first insulating layer, a second insulating layer and a third insulating layer which are sequentially stacked on one side of the substrate.

[0083] S203, in the non-display area, the third insulating layer, the second insulating layer and the first insulating layer are sequentially etched by an etching process to form a first via hole.

[0084] In the non-display area, the third insulating layer 1043, the second insulating layer 1042 and the first insulating layer 1042 in the composite dielectric layer 104 are sequentially etched to form a plurality of first via holes 107 which penetrate the third insulating layer 1043, the second insulating layer 1042 and the first insulating layer 1041.

[0085] S204, a conductive layer material is deposited in the composite dielectric layer away from one side of the substrate and in the first via hole to form a power signal line, and in the thickness direction of the display panel, the power signal line at least partially overlaps the first via hole, and the power signal line at least partially covers the bottom and the sidewall of the first via hole.

[0086] In the first via hole 107 and on the side of the composite dielectric layer 104 away from the substrate, a conductive layer material is deposited, which can be one or more of Mo, Ti, Al, Ag, Cu and other conductive metals, and the deposition process can deposit one or more layers, so that the conductive material in the first via hole 107 and the conductive layer material on the surface of the corresponding composite dielectric layer 104 are continuously arranged, ensuring that each power signal line 106 formed is continuous and avoiding short circuit. That is, the power signal line 106 formed by the conductive layer material at least covers the bottom and the sidewall of the first via hole 107 to increase the coverage area of the power signal line 106, thereby effectively reducing the resistance of the power signal line 106. The power signal line 106 includes a first power signal line 114 and a second power signal line 115 which transmit different power signals. An inorganic insulating layer 120 is prepared on the side of the conductive material away from the substrate 103 to protect part of the composite dielectric layer 104 and the power signal line 106.

[0087] The embodiment of the present application sequentially etches the third insulating layer, the second insulating layer and the first insulating layer in the composite dielectric layer to form a first via hole, and then deposits a conductive layer in the composite dielectric layer away from one side of the substrate and in the first via hole to form a power signal line, thereby effectively increasing the coverage area of the power signal line, reducing the resistance of the power signal line, increasing the driving current, and effectively improving the luminous efficiency of the display panel.

[0088] Optionally, Figure 20 Another flowchart of a preparation method of a display panel provided by the embodiment of the present application is shown in the figure, Figure 21 Another flowchart of a preparation method of a display panel provided by the embodiment of the present application is shown in the figure,Figure 20 and Figure 21 As shown in the method comprises:

[0089] S301, providing a substrate.

[0090] S302, preparing a composite dielectric layer on one side of the substrate, the composite dielectric layer at least comprising a first insulating layer, a second insulating layer and a third insulating layer stacked in sequence on one side of the substrate.

[0091] S303, in the non-display area, by the first etching process, etching part of the third insulating layer, along the thickness direction of the display panel, the thickness of the etched part of the third insulating layer is less than the thickness of the unetched third insulating layer.

[0092] Among them, the third insulating layer 1043 far away from the substrate 103 side is first etched by the first etching process, and the third insulating layer 1043 is etched, so that along the thickness direction of the display panel, the thickness of the etched part of the third insulating layer 1043 is less than the thickness of the unetched third insulating layer 1043, at this time the composite dielectric layer 104 as a whole presents different thickness distribution state.

[0093] S304, by the second etching process, continuing to etch the part of the third insulating layer and the second insulating layer and the first insulating layer, forming a first via.

[0094] Among them, along the thickness direction of the display panel, the etched third insulating layer 1043 and the corresponding second insulating layer 1042 and first insulating layer 1041 are etched to form a first via 107, wherein the two etching processes can be the same or different, which can be selected according to the actual design requirements.

[0095] S305, depositing conductive layer material in the composite dielectric layer far away from the substrate side and the first via, forming a power signal line, along the thickness direction of the display panel, the power signal line and the first via at least partially overlap, and the power signal line at least partially covers the bottom and sidewall of the first via.

[0096] The embodiment of the application first etches part of the third insulating layer far away from the substrate side in the composite dielectric layer, then etches the etched part of the third insulating layer and the second insulating layer and the first insulating layer to form a first via, and then deposits a conductive layer in the composite dielectric layer far away from the substrate side and the first via, thereby forming a power signal line, effectively increasing the coverage area of the power signal line, thereby reducing the resistance of the power signal line, increasing the driving current, and thereby effectively improving the luminous efficiency of the display panel.

[0097] Figure 22 A structural schematic diagram of a display device provided by the embodiment of the application is shown in Figure 22As shown, the display device 200 comprises the display panel 100 described in the above embodiments.

[0098] It should be noted that the display device provided in the embodiment has the same or corresponding beneficial effects of the display panel in the above embodiments, which will not be described herein. The display device 200 provided in the embodiment can be a mobile phone as shown, or any electronic product with a display function, including but not limited to the following categories: television, notebook computer, desktop display, tablet computer, digital camera, smart bracelet, smart glasses, vehicle-mounted display, medical equipment, industrial control equipment, touch interaction terminal, etc., and the embodiment of the present application does not make special limitations. Figure 22

[0099] The above specific embodiments do not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent replacement and improvement made within the spirit and principles of the present application shall be included in the protection scope of the present application.​

Claims

1. A display panel, characterized in that: include: a display area and a non-display area located outside the display area, The display panel further includes a substrate; a composite dielectric layer, located on one side of the substrate, the composite dielectric layer comprising a first via hole at least partially penetrating the composite dielectric layer; a conductive layer, at least a portion of which is located on a side of the composite dielectric layer away from the substrate, and the conductive layer includes a power signal line; In the non-display area, along the thickness direction of the display panel, the power signal line at least partially overlaps with the first via hole, and the power signal line at least partially covers the bottom and sidewalls of the first via hole; The display panel further includes a first auxiliary metal layer located in the non-display area, the first auxiliary metal layer being located on a side of the substrate close to the composite dielectric layer or on a side of the substrate away from the composite dielectric layer, and the first auxiliary metal layer being electrically connected to the power signal line through a second via hole; Wherein, when the display panel is a rigid display panel, the first auxiliary metal layer is located on the side of the substrate close to the composite dielectric layer, a first buffer layer is provided between the substrate and the composite dielectric layer, the first buffer layer is located on the side of the substrate close to the composite dielectric layer, a first auxiliary metal layer is prepared on the side of the first buffer layer away from the substrate, and a second buffer layer is prepared to cover the first auxiliary metal layer; When the display panel is a flexible display panel, the first auxiliary metal layer is located on the side of the substrate away from the composite dielectric layer. Before preparing the substrate, a sacrificial layer and a second buffer layer are first prepared on a glass substrate, the first auxiliary metal layer is prepared on the side of the second buffer layer away from the sacrificial layer, and a third buffer layer is prepared to cover the first auxiliary metal layer, and then the substrate is prepared on the side of the third buffer layer away from the sacrificial layer.

2. The display panel according to claim 1, wherein: The power signal line includes at least a first power signal line section, a second power signal line section, and a third power signal line section, wherein the second power signal line section is connected to the first power signal line section and the third power signal line section respectively. The first power signal line section is located on the side of the composite dielectric layer away from the substrate and contacts the surface of the composite dielectric layer away from the substrate; the second power signal line section covers the side wall of the first via hole; and the third power signal line section covers the bottom of the first via hole.

3. The display panel according to claim 1, wherein: Along a thickness direction of the display panel, the conductive layer at least partially overlaps with the first auxiliary metal layer.

4. The display panel according to claim 3, wherein: Along the thickness direction of the display panel, a projected area of ​​the conductive layer is smaller than a projected area of ​​the first auxiliary metal layer.

5. The display panel according to claim 1, wherein: The display panel also includes a second auxiliary metal layer located in the display area, the second auxiliary metal layer is located on the side of the substrate close to the composite dielectric layer or on the side of the substrate away from the composite dielectric layer, and the second auxiliary metal layer is electrically connected to the power signal line through a third via.

6. The display panel according to claim 5, wherein: The display area further includes a first thin film transistor and a second thin film transistor. Along the thickness direction of the display panel, the second auxiliary metal layer at least partially overlaps with the second thin film transistor.

7. The display panel according to claim 6, wherein: The first thin film transistor is a low-temperature polysilicon thin film transistor, and the second thin film transistor is an oxide semiconductor thin film transistor.

8. The display panel according to claim 1, wherein: In any plane perpendicular to the light-emitting surface of the display panel, the shape of the power signal line is at least one of a U-shape, an X-shape, a wave shape or an arch shape.

9. The display panel according to claim 1, wherein: The power signal line includes a first power signal line and a second power signal line. The voltage value of a first power signal transmitted by the first power signal line is greater than the voltage value of a second power signal transmitted by the second power signal line.

10. The display panel according to claim 9, wherein: The first power signal line and the second power signal line are arranged on the same layer.

11. The display panel according to claim 1, wherein The frame of the display panel is in a circular or rectangular shape.

12. A method for preparing a display panel, for preparing the display panel according to any one of claims 1 to 11, characterized in that: include: providing a substrate; preparing a composite dielectric layer on one side of the substrate; In the non-display area, forming a first via hole in the composite dielectric layer; A conductive layer is prepared on the side of the composite dielectric layer away from the substrate, and the conductive layer includes a power signal line; along the thickness direction of the display panel, the power signal line at least partially overlaps with the first via hole, and the power signal line at least partially covers the bottom and side wall of the first via hole.

13. The method for manufacturing a display panel according to claim 12, wherein: The composite dielectric layer comprises at least a first insulating layer, a second insulating layer and a third insulating layer stacked in sequence on one side of the substrate. Forming a first via hole in the composite dielectric layer includes: By etching the third insulating layer, the second insulating layer and the first insulating layer in sequence, a first via hole is formed; A conductive layer is prepared on a side of the composite dielectric layer away from the substrate, wherein the conductive layer includes a power signal line, including: The conductive layer material is deposited on a side of the composite dielectric layer away from the substrate and in the first via hole to form a power signal line.

14. The method for manufacturing a display panel according to claim 12, wherein: The composite dielectric layer comprises at least a first insulating layer, a second insulating layer and a third insulating layer stacked in sequence on one side of the substrate; Forming a first via hole in the composite dielectric layer includes: etching a portion of the third insulating layer through a first etching process, wherein a thickness of the etched portion of the third insulating layer is smaller than a thickness of the unetched portion of the third insulating layer along a thickness direction of the display panel; Through a second etching process, continue to etch the third insulating layer, the second insulating layer, and the first insulating layer to form a first via hole; A conductive layer is prepared on a side of the composite dielectric layer away from the substrate, wherein the conductive layer includes a power signal line, including: The conductive layer material is deposited on a side of the composite dielectric layer away from the substrate and in the first via hole to form a power signal line.

15. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 11.

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