Non-volatile multi-valued logic memory integrated with nitride devices and methods of making the same

Abstract

The application discloses a nonvolatile multi-value logic memory integrated with a nitride device, and mainly solves the problems of high power consumption, short service life, low logic state contrast and low storage density of the existing nitride nonvolatile memory. The nonvolatile multi-value logic memory comprises, from bottom to top, a substrate, a field effect transistor, a floating gate layer, a resonant tunneling diode, an isolation layer, a gate contact layer and a gate electrode. The field effect transistor is composed of a nucleation layer, a buffer layer, a back barrier layer, a channel layer, an insertion layer, a first barrier layer and source-drain electrodes. The resonant tunneling diode is composed of a second barrier layer, a first quantum well layer, a third barrier layer, a second quantum well layer and a fourth barrier layer. The opening and closing of the channel are controlled by regulating the carrier concentration of the channel of the heterojunction interface of the field effect transistor, and the multi-value state output current is realized by the differential negative resistance effect of the resonant tunneling diode. The application has the advantages of low power consumption, long service life, high logic state contrast, high reliability and the like, and can be used for high-density storage and multi-value logic circuits.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, and specifically relates to a non-volatile memory that can be used for high-density storage and multi-valued logic circuits. Background Technology

[0002] Currently, there are three main types of traditional memory. Flash memory is essentially a metal-oxide-semiconductor field-effect transistor with an additional floating gate layer to store charge. Data is represented by the amount of charge in the floating gate layer, which is isolated by the oxide layer. Its advantages include long data retention time, requiring only a small voltage to read data, but a large voltage to modify it. Compared to flash memory, dynamic random access memory (DRAM) has a relatively fast response time, but data is lost from the storage cell when it is read because the capacitors used to store data can leak charge, requiring a refresh every tens of milliseconds. Static random access memory (SRAM) has relatively good data retention capabilities, but typically requires six transistors per cell, resulting in a large chip area.

[0003] In digital computing applications, static random access memory (SRAM) is used to manufacture caches and is integrated into the central processing unit (CPU); dynamic random access memory (DRAM) is used to manufacture RAM modules as the computer's main memory; and flash memory is used to manufacture hard drives. Therefore, developing a general-purpose memory that can simultaneously meet the performance requirements of these traditional memory types is a current research hotspot. Improving the integration of computer components and simplifying computer manufacturing processes are of great significance for the development of next-generation computing technologies.

[0004] To meet the requirements of non-volatile storage and low logic state switching energy in general-purpose memories, the main technological approach has become the development of new processes, the application of new materials, the innovation of new structures, and the discovery of new principles based on existing non-volatile memories. In 2023, the Advanced Industrial Science and Technology Research Institute of Japan reported a nitride non-volatile memory in the paper "Enhancement of nonvolatile memory characteristics caused by GaN / AlN resonant tunnellingdiodes," the structure of which is as follows: Figure 1 As shown, from bottom to top, it includes a substrate, a GaN buffer layer, and an n... + GaN emitter ohmic contact layer, first GaN isolation layer, first AlN barrier layer, GaN quantum well layer, second AlN barrier layer, second GaN isolation layer, n + GaN collector ohmic contact layer and collector electrode, in n + An emitter electrode is located on one side of the GaN emitter ohmic contact layer, and these layers are covered by a passivation layer. This memory has the following drawbacks:

[0005] 1. Because the memory is manufactured using metal-organic chemical vapor deposition, the active area interface has poor quality, the dislocation distribution is uneven, and the device leakage is serious. Even when no erase or write operation is performed, a large current still flows through the memory, which cannot be turned off, resulting in high static power consumption of the memory.

[0006] 2. After multiple erase and write operations, the output characteristics of this memory will degrade, resulting in poor erase and write durability and a short lifespan.

[0007] 3. The device adopts a double-barrier single quantum well structure. The peak voltage and valley voltage in the differential negative resistance region are close, and the peak and valley currents are relatively small. The current value of the memory in the two logic states is not much different, which is not conducive to the differentiation of the memory logic states.

[0008] 4. Because this device uses a double-barrier single quantum well structure, it generally only has one differential negative resistance region, which makes it difficult to implement multi-valued logic. This limits the application of memory in multi-valued logic circuits and makes it difficult to implement more complex circuit functions with a smaller number of devices. Summary of the Invention

[0009] The purpose of this invention is to address the shortcomings of the existing technologies mentioned above by proposing a non-volatile multi-valued logic memory integrating nitride devices and its fabrication method, so as to improve the device's lifespan and reliability, reduce device power consumption, improve logic state contrast, and realize multi-valued logic storage.

[0010] The technical solution to achieve the objective of this invention is as follows:

[0011] 1. A non-volatile multi-valued logic memory integrating nitride devices, comprising, from bottom to top, a substrate, a buffer layer, a second barrier layer, a first quantum well layer, a third barrier layer, an isolation layer, a gate contact layer, and a gate electrode, wherein these layers and electrodes are externally encapsulated by a passivation layer, and the second barrier layer, the first quantum well layer, and the third barrier layer constitute a double-barrier single-quantum-well resonant tunneling diode, characterized in that:

[0012] A nucleation layer is added between the substrate and the buffer layer;

[0013] Between the buffer layer and the second barrier layer, a back barrier layer, a channel layer, an insertion layer, a first barrier layer, and a floating gate layer are sequentially added. The floating gate layer has source electrodes and drain electrodes on both sides. The nucleation layer, buffer layer, back barrier layer, channel layer, insertion layer, first barrier layer, source electrode, drain electrode, and gate electrode constitute a nitride field-effect transistor. The on and off states of the channel are realized by controlling the carrier concentration of the heterojunction interface channel in the field-effect transistor.

[0014] A second quantum well layer and a fourth quantum well layer are sequentially added between the third barrier layer and the isolation layer. The second quantum well layer, the fourth quantum well layer, and the double-barrier single quantum well resonant tunneling diode constitute a triple-barrier double quantum well resonant tunneling diode. The multi-valued output current is realized through the differential negative resistance effect of the resonant tunneling diode.

[0015] Furthermore, the materials and parameters of each layer constituting the triple-barrier double-quantum-well resonant tunneling diode are as follows:

[0016] The thickness of the second barrier layer is 1nm-3nm, the thickness of the third barrier layer is 1nm-3nm, and the thickness of the fourth barrier layer is 1nm-3nm. All three barrier layers are made of any one of AlN, AlGaN, InAlN, InAlGaN, ScAlN, YAlN, AlPN, BAlN, and BPN materials.

[0017] The thickness of the first quantum well layer is 1nm-3nm, and the thickness of the second quantum well layer is 1nm-3nm. Both quantum well layers are made of any one of GaN, InGaN, and InN materials.

[0018] The thickness of the isolation layer is 4nm-15nm, and it is made of any one of GaN, InGaN, and InN materials.

[0019] The thickness of the gate contact layer is 50nm-200nm, and the doping concentration is 1x10⁻⁶. 19 cm -3 -1x10 20 cm -3 between n + GaN, n + InGaN or n + Any of the InN materials.

[0020] Furthermore, the materials and parameters of each layer constituting the field-effect transistor are as follows:

[0021] The thickness of the nucleation layer is 3nm-1000nm, and it can be any one of AlN, GaN, or AlGaN materials.

[0022] The thickness of the buffer layer is 500nm-2000nm, and it is made of any one of AlN, GaN, or AlGaN materials;

[0023] The thickness of the back barrier layer is 5nm-50nm, and it can be any one of AlGaN, InGaN, and InAlN materials.

[0024] The thickness of the channel layer is 10nm-100nm, and it is made of any one of GaN, InGaN, and AlGaN materials.

[0025] The thickness of the insertion layer is 1nm-2nm, and it is made of AlN material;

[0026] The thickness of the first barrier layer is 3nm-30nm, and it is made of any one of AlN, AlGaN, InAlN, InAlGaN, ScAlN, YAlN, AlPN, BAlN, or BPN materials.

[0027] Furthermore, the substrate is made of any one of the following materials: sapphire, silicon, silicon carbide, diamond, gallium nitride, aluminum nitride, and boron nitride.

[0028] Furthermore, the thickness of the floating gate layer is 4nm-15nm, and it is made of any one of GaN, InGaN, or InN materials.

[0029] Furthermore, the passivation layer is made of any one of SiN, Al2O3, or HfO2 materials.

[0030] 2. A method for fabricating a non-volatile multi-valued logic memory integrating nitride devices, characterized by comprising the following steps:

[0031] 1) Use metal-organic chemical vapor deposition or molecular beam epitaxy to grow a nucleation layer of 3nm-1000nm on a substrate.

[0032] 2) Use metal-organic chemical vapor deposition or molecular beam epitaxy to grow a buffer layer of 500nm-2000nm on the nucleation layer;

[0033] 3) Use metal-organic chemical vapor deposition or molecular beam epitaxy to grow a back barrier layer with a thickness of 5nm-50nm on the buffer layer.

[0034] 4) Use metal-organic chemical vapor deposition or molecular beam epitaxy to grow a 10nm-100nm channel layer on the back barrier layer.

[0035] 5) Using metal-organic chemical vapor deposition or molecular beam epitaxy, grow an AlN insertion layer with a thickness of 1nm-2nm on the channel layer;

[0036] 6) Using metal-organic chemical vapor deposition or molecular beam epitaxy, a first barrier layer with a thickness of 3nm-30nm is grown on the AlN insertion layer;

[0037] 7) Using molecular beam epitaxy, a floating gate layer with a thickness of 4nm-15nm is grown on the first barrier layer;

[0038] 8) Using molecular beam epitaxy, a second barrier layer with a thickness of 1nm-3nm is grown on the floating gate layer;

[0039] 9) Using molecular beam epitaxy, a first quantum well layer with a thickness of 1nm-3nm is grown on the second barrier layer;

[0040] 10) Using molecular beam epitaxy, a third barrier layer with a thickness of 1 nm-3 nm is grown on the first quantum well layer;

[0041] 11) Using molecular beam epitaxy, a second quantum well layer with a thickness of 1 nm-3 nm is grown on the third barrier layer;

[0042] 12) Using molecular beam epitaxy, a fourth barrier layer with a thickness of 1 nm-3 nm is grown on the second quantum well layer;

[0043] 13) Using molecular beam epitaxy, an isolation layer with a thickness of 4nm-15nm was grown on the fourth barrier layer;

[0044] 14) Using molecular beam epitaxy, a gate contact layer with a thickness of 50nm-200nm is grown on the isolation layer;

[0045] 15) Using conventional optical lithography, a mesa isolation pattern is formed on the gate contact layer. Then, using photoresist as a mask, the gate contact layer is etched to the top of the buffer layer using inductively coupled plasma etching method with BCl3 / Cl2 gas source to form a square mesa isolation shallow trench with a depth of 200nm-800nm.

[0046] 16) Using photoresist as a mask, a gate electrode region is set on the gate contact layer, and metal Ti / Au is deposited in this region using an electron beam evaporation process to form the gate electrode;

[0047] 17) Using the gate electrode metal as a mask, the gate contact layer is etched to the upper surface of the first barrier layer using the inductively coupled plasma etching method and the BCl3 / Cl2 gas source, forming a square mesa from the floating gate layer to the gate electrode.

[0048] 18) Using photoresist as a mask, dry etching is used to etch the first barrier layer up to the top of the channel layer to form a groove for the source-drain ohmic contact region.

[0049] 19) Growing Si with a doping concentration of (0.5-5)×10⁻⁶ in the grooves of the source-drain ohmic contact region using metal-organic chemical vapor deposition or molecular beam epitaxy. 20 cm -3n-type GaN material is used to form ohmic contact regions; using photoresist as a mask, ohmic contact metal Ti / Al / Ni / Au is first deposited in the ohmic contact regions using electron beam evaporation process, and then annealed at 830℃ in a nitrogen atmosphere to form source and drain electrodes.

[0050] 20) A passivation layer with a thickness of 50nm-200nm is deposited over the entire sample area using plasma-enhanced chemical vapor deposition or atomic layer deposition.

[0051] 21) Using photoresist as a mask, reactive ion etching is employed with an SF6 gas source to etch the passivation layer to form gate electrode vias, source electrode vias, and drain electrode vias.

[0052] 22) Using traditional optical lithography, gate electrode, source electrode and drain electrode pin patterns are formed on the passivation layer. Then, using photoresist as a mask, an Au metal layer is evaporated on each electrode pin pattern using electron beam evaporation process to form the interconnection between each electrode and the corresponding electrode pin, thus completing the fabrication of the memory.

[0053] Compared with the prior art, the present invention has the following advantages:

[0054] 1. The present invention forms a field-effect transistor structure by adding a back barrier layer, a channel layer, an insertion layer and a first barrier layer between the buffer layer and the second barrier layer, and adding a nucleation layer between the substrate and the buffer layer. The high mobility two-dimensional electron gas present at the heterojunction interface in the structure can be used to amplify the longitudinal current flowing through the resonant tunneling structure, thereby improving the contrast of the memory logic state.

[0055] 2. The present invention adds a second quantum well layer and a fourth barrier layer sequentially above the double-barrier single quantum well resonant tunneling diode to form a triple-barrier double quantum well resonant tunneling diode structure. This structure has multi-region differential negative resistance characteristics, can realize multi-valued logic storage, effectively improves storage density, and simplifies storage circuit design.

[0056] 3. Because the floating gate layer added in this invention is located between the first barrier layer of the field-effect transistor and the resonant tunneling diode structure, electrons can pass through the first barrier layer into the floating gate layer during write operations, and can flow out of the gate from the floating gate layer through resonant tunneling during erase operations. This reduces the number of times the first barrier layer is penetrated and the probability of it being damaged, making it less prone to degradation and extending the working life of the memory. At the same time, since the floating gate layer can act as a capping layer for the field-effect transistor, it can raise the conduction band of the heterojunction interface channel of the field-effect transistor, realize the turn-off of the memory, and significantly reduce the static power consumption of the device.

[0057] 4. Because this invention uses molecular beam epitaxy technology, it can precisely control the growth thickness of the layer structure, resulting in a small dislocation density at the epitaxial interface and uniform layer structure thickness. This can reduce device leakage current and improve the stability and reliability of the memory.

[0058] 5. This invention forms a three-terminal device by integrating a resonant tunneling diode and a field-effect transistor. It achieves multi-valued output current through the differential negative resistance effect of the resonant tunneling diode and controls the opening and closing of the channel by adjusting the carrier concentration of the heterojunction interface channel in the field-effect transistor, thus realizing precise control of the memory output characteristics. Attached Figure Description

[0059] Figure 1 This is a structural diagram of an existing nitride non-volatile memory;

[0060] Figure 2 This is a structural diagram of the non-volatile multi-valued logic memory integrating nitride devices according to the present invention;

[0061] Figure 3 This is a schematic diagram of the process for fabricating a non-volatile multi-valued logic memory integrating nitride devices according to the present invention. Detailed Implementation

[0062] The embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0063] Reference Figure 2 This example integrates a non-volatile multi-valued logic memory with nitride devices, including a substrate 1, a nucleation layer 2, a buffer layer 3, a back barrier layer 4, a channel layer 5, an insertion layer 6, a first barrier layer 7, a floating gate layer 8, a second barrier layer 9, a first quantum well layer 10, a third barrier layer 11, a second quantum well layer 12, a fourth barrier layer 13, an isolation layer 14, a gate contact layer 15, a passivation layer 16, a gate electrode, a source electrode, and a drain electrode, wherein:

[0064] The substrate 1 is made of any one of the following materials: sapphire, silicon, silicon carbide, diamond, gallium nitride, aluminum nitride, and boron nitride.

[0065] The nucleation layer 2 is located on the substrate 1 and is made of any one of AlN, GaN, or AlGaN materials, with a thickness of 3nm-1000nm.

[0066] The buffer layer 3 is located above the nucleation layer 2, and it is made of any one of AlN, GaN, or AlGaN materials, with a thickness of 500nm-2000nm.

[0067] The back barrier layer 4 is located above the buffer layer 3, and it is made of any one of AlGaN, InGaN, and InAlN materials, with a thickness of 5nm-50nm.

[0068] The channel layer 5 is located above the back barrier layer 4, and it is made of any one of GaN, InGaN, and AlGaN materials, with a thickness of 10nm-100nm.

[0069] The insertion layer 6 is located above the channel layer 5 and is made of AlN material with a thickness of 1nm-2nm.

[0070] The first barrier layer 7 is located above the insertion layer 6, and it is made of any one of AlN, AlGaN, InAlN, InAlGaN, ScAlN, YAlN, AlPN, BAlN, and BPN, with a thickness of 3nm-30nm.

[0071] The floating gate layer 8 is located above the first barrier layer 7, and it is made of any one of GaN, InGaN, and InN materials, with a thickness of 4nm-15nm.

[0072] The second barrier layer 9 is located above the floating gate layer 8, and it adopts any one of AlN, AlGaN, InAlN, InAlGaN, ScAlN, YAlN, AlPN, BAlN, and BPN, with a thickness of 1nm-3nm.

[0073] The first quantum well layer 10 is located above the second barrier layer 9, and it is made of any one of GaN, InGaN, and InN, with a thickness of 1nm-3nm.

[0074] The third barrier layer 11 is located above the first quantum well layer 10, and it adopts any one of AlN, AlGaN, InAlN, InAlGaN, ScAlN, YAlN, AlPN, BAlN, and BPN, with a thickness of 1nm-3nm.

[0075] The second quantum well layer 12 is located above the third barrier layer 11, and it is made of any one of GaN, InGaN, and InN, with a thickness of 1nm-3nm.

[0076] The third barrier layer 13 is located above the first quantum well layer 12, and it is made of any one of AlN, AlGaN, InAlN, InAlGaN, ScAlN, YAlN, AlPN, BAlN, and BPN, with a thickness of 1nm-3nm.

[0077] The isolation layer 14 is located above the fourth barrier layer 13, and it is made of any one of GaN, InGaN, and InN, with a thickness of 4nm-15nm.

[0078] The gate contact layer 15 is located above the isolation layer 14 and has a doping concentration of 1x10⁻⁶.19 cm -3 -1x10 20 cm -3 Between 50nm and 200nm, n + GaN, n + InGaN or n + InN;

[0079] The gate electrode is located above the gate contact layer 15;

[0080] The source electrode and drain electrode are located on both sides of the floating gate layer 8;

[0081] The gate electrode, source electrode, and drain electrode all extend upwards with electrode leads;

[0082] The passivation layer 16 is made of any one of SiN, Al2O3, and HfO2 materials and is wrapped around the outside of all layers except the electrode pins.

[0083] The second barrier layer 9, the first quantum well layer 10, the third barrier layer 11, the second quantum well layer 12, and the fourth barrier layer 13 constitute a three-barrier double quantum well resonant tunneling diode, which realizes multi-valued output current through the differential negative resistance effect of the diode.

[0084] The nucleation layer 2, buffer layer 3, back barrier layer 4, channel layer 5, insertion layer 6, and first barrier layer 7, along with the source electrode, gate electrode, and drain electrode, constitute a nitride field-effect transistor. The opening and closing of the channel are achieved by controlling the carrier concentration of the heterojunction interface channel in the field-effect transistor.

[0085] Reference Figure 3 The present invention provides three embodiments for fabricating a non-volatile multi-valued logic memory integrating nitride devices.

[0086] Example 1: Using molecular beam epitaxy, an AlN nucleation layer, a GaN buffer layer, and an Al2O3 layer were fabricated on a gallium nitride substrate. 0.6 Ga 0.4 N-back barrier layer, GaN channel layer, Al 0.25 Ga 0.75 The first barrier layer (N), the floating gate layer (GaN), the second, third, and fourth barrier layers (AlN), the first and second quantum well layers (GaN), and n + The GaN gate contact layer doping concentration is 1x10⁻⁶. 20 cm -3 Non-volatile multi-valued logic memory integrating nitride devices.

[0087] Step 1: Use molecular beam epitaxy (MBE) to epitaxially form an AlN nucleation layer (2), such as... Figure 3 (a).

[0088] The set temperature is 750℃, the nitrogen flow rate is 0.6 sccm, and the aluminum beam equilibrium vapor pressure is 0.6 × 10⁻⁶. -7 Torr, with a nitrogen RF source power of 380W, used molecular beam epitaxy to epitaxially form an AlN nucleation layer (2) with a thickness of 3nm on a gallium nitride substrate (1).

[0089] Step 2, use molecular beam epitaxy to epitaxially grow a GaN buffer layer (3), such as Figure 3 (b)

[0090] The set temperature is 750℃, the nitrogen flow rate is 0.6 sccm, and the gallium beam equilibrium vapor pressure is 3.5 × 10⁻⁶. -7 Torr, with a nitrogen RF source power of 380W, used molecular beam epitaxy to epitaxially grow a GaN buffer layer (3) with a thickness of 500nm on the AlN nucleation layer (2).

[0091] Step 3: Use molecular beam epitaxy to epitaxially grow Al 0.6 Ga 0.4 N-back barrier layer (4), such as Figure 3 (c)

[0092] The set temperature is 750℃, the nitrogen flow rate is 0.6 sccm, and the aluminum beam equilibrium vapor pressure is 0.6 × 10⁻⁶. -7 Torr, the equilibrium vapor pressure of the gallium beam is 3.5 × 10⁻⁶. -7 Torr, with a nitrogen RF source power of 380W, used molecular beam epitaxy to epitaxially grow 50nm thick Al on a GaN buffer layer. 0.6 Ga 0.4 N-back barrier layer (4).

[0093] Step four, use molecular beam epitaxy to epitaxially grow a GaN channel layer (5), such as... Figure 3 (d)

[0094] The set temperature is 750℃, the nitrogen flow rate is 0.6 sccm, and the gallium beam equilibrium vapor pressure is 3.5 × 10⁻⁶. -7 Torr, with a nitrogen RF source power of 380W, uses molecular beam epitaxy on Al 0.6 Ga 0.4 A GaN channel layer (5) with a thickness of 100 nm is epitaxially formed on the N-back barrier layer (4).

[0095] Step 5: Epitaxially grow the AlN insertion layer (6) using molecular beam epitaxy, as shown below. Figure 3 (e).

[0096] The set temperature is 750℃, the nitrogen flow rate is 0.6 sccm, and the aluminum beam equilibrium vapor pressure is 0.6 × 10⁻⁶. -7 Torr, with a nitrogen RF source power of 380W, used molecular beam epitaxy to epitaxially grow an AlN insertion layer (6) with a thickness of 1nm on the GaN channel layer (5).

[0097] Step 6: Epitaxial growth of Al using molecular beam epitaxy. 0.25 Ga 0.75 N first barrier layer (7), such as Figure 3 (f).

[0098] The set temperature is 750℃, the nitrogen flow rate is 0.6 sccm, and the aluminum beam equilibrium vapor pressure is 0.6 × 10⁻⁶. -7 Torr, the equilibrium vapor pressure of the gallium beam is 6.5 × 10⁻⁶. -7 Torr, with a nitrogen RF source power of 380W, molecular beam epitaxy was used to epitaxially grow a 30nm thick Al layer on the AlN insertion layer (6). 0.25 Ga 0.75 N is the first barrier layer (7).

[0099] Step 7: Epitaxial GaN floating gate layer (8) is performed using molecular beam epitaxy (MBE), as follows: Figure 3 (g)

[0100] The set temperature is 750℃, the nitrogen flow rate is 0.6 sccm, and the gallium beam equilibrium vapor pressure is 6.5 × 10⁻⁶. -7 Torr, with a nitrogen RF source power of 380W, uses molecular beam epitaxy on Al 0.25 Ga 0.75 An epitaxial GaN floating gate layer (8) with a thickness of 15 nm is formed on the first barrier layer (7).

[0101] Step 8: Epitaxially grow the second barrier layer of AlN using molecular beam epitaxy (9), as follows: Figure 3 (h).

[0102] The set temperature is 750℃, the nitrogen flow rate is 0.6 sccm, and the aluminum beam equilibrium vapor pressure is 1.2 × 10⁻⁶. -7 Torr, with a nitrogen RF source power of 380W, used molecular beam epitaxy to epitaxially form an AlN second barrier layer (9) with a thickness of 1.5nm on the GaN floating gate layer (8).

[0103] Step nine, use molecular beam epitaxy to epitaxially grow the first GaN quantum well layer (10), as follows: Figure 3 (i).

[0104] The set temperature is 750℃, the nitrogen flow rate is 0.6 sccm, and the gallium beam equilibrium vapor pressure is 6.5 × 10⁻⁶. -7 Torr, with a nitrogen RF source power of 380W, used molecular beam epitaxy to epitaxially grow a GaN first quantum well layer (10) with a thickness of 2.5nm on the AlN second barrier layer (9).

[0105] Step 10: Epitaxially grow the third barrier layer of AlN (11) using molecular beam epitaxy, as follows: Figure 3 (j).

[0106] The set temperature is 750℃, the nitrogen flow rate is 0.6 sccm, and the aluminum beam equilibrium vapor pressure is 1.2 × 10⁻⁶. -7 Torr, with a nitrogen RF source power of 380W, used molecular beam epitaxy to epitaxially form an AlN third barrier layer (11) with a thickness of 1.5nm on the GaN first quantum well layer (10).

[0107] Step 11: Epitaxially grow a second GaN quantum well layer (12) using molecular beam epitaxy, as follows: Figure 3 (k).

[0108] The set temperature is 750℃, the nitrogen flow rate is 0.6 sccm, and the gallium beam equilibrium vapor pressure is 6.5 × 10⁻⁶. -7 Torr, with a nitrogen RF source power of 380W, used molecular beam epitaxy to epitaxially form a GaN second quantum well layer (12) with a thickness of 2.5nm on the AlN third barrier layer (11).

[0109] Step 12: Epitaxially grow the fourth barrier layer of AlN (13) using molecular beam epitaxy, as follows: Figure 3 (l).

[0110] The set temperature is 750℃, the nitrogen flow rate is 0.6 sccm, and the aluminum beam equilibrium vapor pressure is 1.2 × 10⁻⁶. -7 Torr, with a nitrogen RF source power of 380W, uses molecular beam epitaxy to epitaxially grow an AlN fourth barrier layer (13) with a thickness of 1.5nm on the GaN second quantum well layer (12), which together with the second barrier layer (9), the first quantum well layer (10), the third barrier layer (11), and the second quantum well layer (12) to form a triple-barrier double quantum well resonant tunneling diode.

[0111] Step thirteen, use molecular beam epitaxy to epitaxially grow a GaN isolation layer (14), such as Figure 3 (m).

[0112] The set temperature is 750℃, the nitrogen flow rate is 0.6 sccm, and the gallium beam equilibrium vapor pressure is 6.5 × 10⁻⁶. -7Torr, with a nitrogen RF source power of 380W, used molecular beam epitaxy to epitaxially grow a GaN isolation layer (14) with a thickness of 15nm on the fourth barrier layer (13) of AlN.

[0113] Step fourteen, use molecular beam epitaxy to epitaxially measure n + GaN gate contact layer (15), such as Figure 3 (n).

[0114] The set temperature is 750℃, the nitrogen flow rate is 0.6 sccm, and the gallium beam equilibrium vapor pressure is 6.5 × 10⁻⁶. -7 Torr, the equilibrium vapor pressure of the silicon beam is 3.5 × 10⁻⁶. -8 Torr, with a nitrogen RF source power of 380W, molecular beam epitaxy was used to epitaxially grow a 200nm thick GaN isolation layer (14) with a doping concentration of 1x10⁻¹⁰. 20 cm -3 n + GaN gate contact layer (15).

[0115] Step 15, in n + A mesh-like mesa isolation trench with a depth of 800 nm is formed by homogenization, photolithography, development, and etching on the GaN gate contact layer (15). Figure 3 (o).

[0116] 15.1) A mesa isolation pattern is formed on the gate contact layer (15) using photolithography:

[0117] 15.1.1) Spin-coat AZ5214 photoresist onto the gate contact layer (15), i.e., first spin-coat at a rotation speed of 500 rad / min and an acceleration of 1000 rad. 2 Spin coat for 3 seconds at a speed of 4000 rad / min; then spin coat at a speed of 4000 rad / min and an acceleration of 2000 rad. 2 Spin coat at 30s for 3min, then bake at 95℃ for 90s;

[0118] 15.1.2) Traditional optical lithography is used to expose and process the AZ5214 photoresist on the gate contact layer (15);

[0119] 15.1.3) The exposed photoresist was developed using RZX-3038 developer for 45 seconds to form a grid-like mesa isolation pattern.

[0120] 15.2) The gate contact layer (15) is etched according to the mesa isolation pattern to form mesa isolation:

[0121] With process conditions set at Cl2 gas flow rate of 10 sccm, BCl3 gas flow rate of 25 sccm, and etching time of 300 s, inductively coupled plasma etching method was adopted, using photoresist as a mask, and the gate contact layer (15) was etched according to the mesa isolation pattern to form a grid-like mesa isolation shallow trench with a depth of 800 nm.

[0122] Step sixteen: Fabricate the gate electrode using electron beam evaporation technology, such as... Figure 3 (p).

[0123] n after tabletop isolation + A mask is fabricated on the GaN gate contact layer (15), the gate electrode fabrication area is selected, and the vacuum level is set to be less than 1.4 × 10⁻⁶. -3 Pa, power range of 400-800W, evaporation rate of The process conditions, after the tabletop is isolated, n + Ti / Au metal composites with metal thicknesses of 0.04 μm / 0.5 μm are deposited on the GaN gate contact layer to complete the gate electrode fabrication.

[0124] Step seventeen: Using inductively coupled plasma etching (ICP-E) technology, a square mesa is etched to form, such as... Figure 3 (q).

[0125] With process conditions set at a Cl2 gas flow rate of 10 sccm, a BCl3 gas flow rate of 25 sccm, and an etching time of 150 s, using the gate electrode metal as a mask, an inductively coupled plasma etching process was employed to etch n. + GaN gate contact layer (15) to Al 0.25 Ga 0.75 On the upper surface of the first barrier layer (7), a square mesa is formed from the floating gate layer to the gate electrode.

[0126] Step 18: Using a dry etching process, etch grooves to form the source / drain ohmic contact area, such as... Figure 3 (r).

[0127] With process conditions set at a Cl2 flow rate of 20 sccm, a reaction chamber pressure of 15 mTorr, and an electrode power of 220 W, using photoresist as a mask, in Al 0.25 Ga 0.75 Select the source-drain ohmic contact region on the first barrier layer (7) and remove Al. 0.25 Ga 0.75 The first barrier layer (7), the AlN insertion layer (6), and the partial GaN channel layer (5) form a source-drain ohmic contact region groove.

[0128] Step nineteen: A Si-doped n-type GaN layer is grown in the groove of the source-drain ohmic contact region using molecular beam epitaxy to form the ohmic contact region. The source and drain electrodes are then fabricated using electron beam evaporation. Figure 3 (s).

[0129] The set temperature is 750℃, the nitrogen flow rate is 0.6 sccm, and the gallium beam equilibrium vapor pressure is 6.5 × 10⁻⁶. -7 Torr, the equilibrium vapor pressure of the silicon beam is 3.5 × 10⁻⁶. -8 Torr, with a nitrogen RF source power of 380W, deposits 50nm thick Si with a doping concentration of 5×10⁻⁶ in the source-drain ohmic contact region trench. 20 cm -3 An n-type GaN layer is formed to create an ohmic contact region;

[0130] In Al 0.25 Ga 0.75 A mask is fabricated on the first barrier layer (7) with a vacuum level of less than 1.4 × 10⁻⁶. -3 Pa, power range of 400-800W, evaporation rate of Under the specified process conditions, a Ti / Al / Ni / Au metal combination is deposited on the ohmic contact region of the source and drain electrodes, with a metal thickness of 0.05μm / 0.12μm / 0.08μm / 0.08μm; then, rapid thermal annealing is performed for 30s in a nitrogen atmosphere at a temperature of 830℃ to form the source electrode and drain electrode. The source and drain electrodes, together with the gate electrode, nucleation layer (2), buffer layer (3), back barrier layer (4), channel layer (5), insertion layer (6), and first barrier layer (7), constitute a field-effect transistor.

[0131] Step 20: Deposit an Al2O3 passivation layer (16) using atomic layer deposition (ALD) technology, such as... Figure 3 (t).

[0132] The process conditions were set as follows: time 40s, pressure 2000mTorr, temperature 300℃, Al(CH3)3 flow rate 850sccm, H2O flow rate 350sccm, and N2 flow rate 1000sccm. An Al2O3 passivation layer with a thickness of 50nm was deposited over the entire sample area using atomic layer deposition (16).

[0133] Step 21: Prepare gate electrode vias, source electrode vias, and drain electrode vias on the Al2O3 passivation layer (16), as follows: Figure 3 (u).

[0134] With process conditions set at 1500 mTorr pressure, 200 W power, 8 sccm SF6 flow rate, 10 sccm CHF3 flow rate, and 150 sccm He flow rate, using photoresist as a mask, reactive ion etching was employed to etch the Al2O3 passivation layer (16) to the metal surfaces of the gate electrode, source electrode, and drain electrode, forming gate electrode vias, source electrode vias, and drain electrode vias, respectively.

[0135] Step twenty-two: Using optical lithography and electron beam evaporation, electrode pins are brought out from each electrode via to complete the memory fabrication, such as... Figure 3 (v).

[0136] First, using traditional optical lithography, the gate electrode, source electrode, and drain electrode pin patterns are formed respectively; then, the... Under the specified process conditions, Au metal with a thickness of 80 nm was evaporated on each electrode pin pattern using electron beam evaporation, and then soaked in acetone to form gate electrode pins, source electrode pins and drain electrode pins that are interconnected with the gate electrode, source electrode and drain electrode, respectively, thus completing the memory fabrication.

[0137] Example 2: Using molecular beam epitaxy, Al was fabricated on an aluminum nitride substrate. 0.8 Ga 0.2 N nucleation layer, Al 0.6 Ga 0.4 N buffer layer, In 0.1 Ga 0.9 N-back barrier layer, In 0.05 Ga 0.95 N-channel layer, AlN first barrier layer, InN floating gate layer, Al 0.4 Ga 0.6 N represents the first, second, and fourth barrier layers; InN represents the first and second quantum well layers; n + The InN gate contact layer doping concentration is 5x10⁻⁶. 19 cm -3 Non-volatile multi-valued logic memory integrating nitride devices.

[0138] Step 1, epitaxial Al 0.8 Ga 0.2 N nucleation layer (2), such as Figure 3 (a).

[0139] Molecular beam epitaxy was used to epitaxially grow Al atoms with a thickness of 200 nm on an aluminum nitride substrate (1). 0.8 Ga 0.2 N nucleation layer (2).

[0140] The process conditions for molecular beam epitaxy were: temperature 650℃, nitrogen flow rate 3.0 sccm, and aluminum beam equilibrium vapor pressure 3.2 × 10⁻⁶.-7 Torr, the equilibrium vapor pressure of the gallium beam is 6.5 × 10⁻⁶. -7 The Torr uses a nitrogen-based radio frequency source with a power of 380W.

[0141] Step 2, epitaxial Al 0.6 Ga 0.4 N buffer layer (3), such as Figure 3 (b)

[0142] Using molecular beam epitaxy, in Al 0.8 Ga 0.2 An 800 nm thick Al layer is epitaxially grown on the N nucleation layer (2). 0.6 Ga 0.4 N buffer layer (3).

[0143] The process conditions for molecular beam epitaxy were: temperature 650℃, nitrogen flow rate 3.0 sccm, and aluminum beam equilibrium vapor pressure 3.2 × 10⁻⁶. -7 Torr, the equilibrium vapor pressure of the gallium beam is 9.5 × 10⁻⁶. -7 The Torr uses a nitrogen-based radio frequency source with a power of 380W.

[0144] Step 3, Extension In 0.1 Ga 0.9 N-back barrier layer (4), such as Figure 3 (c)

[0145] Using molecular beam epitaxy, in Al 0.6 Ga 0.4 The In layer with an epitaxial thickness of 5 nm is placed on the N buffer layer (3). 0.1 Ga 0.9 N-back barrier layer (4).

[0146] The process conditions for molecular beam epitaxy were: temperature 500℃, nitrogen flow rate 1.2 sccm, and indium beam equilibrium vapor pressure 2.1 × 10⁻⁶. -7 Torr, the equilibrium vapor pressure of the gallium beam is 6.5 × 10⁻⁶. -7 The Torr uses a nitrogen-based radio frequency source with a power of 380W.

[0147] Step 4, Extension In 0.05 Ga 0.95 N-channel layer (5), such as Figure 3 (d)

[0148] Using molecular beam epitaxy, in In 0.1 Ga 0.9 An In layer with a thickness of 10 nm is epitaxially layered on the N-back barrier layer (4). 0.05 Ga 0.95 N-channel layer (5).

[0149] The process conditions for molecular beam epitaxy were: temperature 500℃, nitrogen flow rate 1.2 sccm, and indium beam equilibrium vapor pressure 2.1 × 10⁻⁶. -7 Torr, the equilibrium vapor pressure of the gallium beam is 3.2 × 10⁻⁶. -7 The Torr uses a nitrogen-based radio frequency source with a power of 380W.

[0150] Step 5, epitaxial AlN insertion layer (6), as follows Figure 3 (e).

[0151] Using molecular beam epitaxy, in In 0.05 Ga 0.95 An AlN insertion layer (6) with a thickness of 1.5 nm is deposited on the N-channel layer (5).

[0152] The process conditions for molecular beam epitaxy were: temperature 500℃, nitrogen flow rate 1.2 sccm, and aluminum beam equilibrium vapor pressure 3.2 × 10⁻⁶. -7 The Torr uses a nitrogen-based radio frequency source with a power of 380W.

[0153] Step 6, epitaxial AlN first barrier layer (7), as follows Figure 3 (f).

[0154] Using molecular beam epitaxy, a first AlN barrier layer (7) with a thickness of 3 nm was deposited on the AlN insertion layer (6).

[0155] The process conditions for molecular beam epitaxy were: temperature 500℃, nitrogen flow rate 1.2 sccm, and aluminum beam equilibrium vapor pressure 3.2 × 10⁻⁶. -7 The Torr uses a nitrogen-based radio frequency source with a power of 380W.

[0156] Step 7, epitaxial InN floating gate layer (8), as follows Figure 3 (g)

[0157] Using molecular beam epitaxy, an InN floating gate layer (8) with a thickness of 4 nm was deposited on the first barrier layer (7) of AlN.

[0158] The process conditions for molecular beam epitaxy were: temperature 500℃, nitrogen flow rate 1.2 sccm, and indium beam equilibrium vapor pressure 2.1 × 10⁻⁶. -7 The Torr uses a nitrogen-based radio frequency source with a power of 380W.

[0159] Step 8, epitaxial Al 0.4 Ga 0.6 N second barrier layer (9), such as Figure 3 (h).

[0160] Molecular beam epitaxy was used to epitaxially grow Al with a thickness of 3 nm on the InN floating gate layer (8). 0.4Ga 0.6 N is the second barrier layer (9).

[0161] The process conditions for molecular beam epitaxy were: temperature 500℃, nitrogen flow rate 1.2 sccm, and aluminum beam equilibrium vapor pressure 3.2 × 10⁻⁶. -7 Torr, the equilibrium vapor pressure of the gallium beam is 3.5 × 10⁻⁶. -7 The Torr uses a nitrogen-based radio frequency source with a power of 380W.

[0162] Step 9, epitaxial InN first quantum well layer (10), as follows Figure 3 (i).

[0163] Using molecular beam epitaxy, in Al 0.4 Ga 0.6 An InN first quantum well layer (10) with a thickness of 1 nm is deposited on the N second barrier layer (9).

[0164] The process conditions for molecular beam epitaxy were: temperature 500℃, nitrogen flow rate 1.2 sccm, and indium beam equilibrium vapor pressure 2.1 × 10⁻⁶. -7 The Torr uses a nitrogen-based radio frequency source with a power of 380W.

[0165] Step 10, epitaxial Al 0.4 Ga 0.6 N is the third barrier layer (11), such as Figure 3 (j).

[0166] Molecular beam epitaxy was used to epitaxially grow an Al layer with a thickness of 3 nm on the first quantum well layer (10) of InN. 0.4 Ga 0.6 N is the third barrier layer (11).

[0167] The process conditions for molecular beam epitaxy were: temperature 500℃, nitrogen flow rate 1.2 sccm, and aluminum beam equilibrium vapor pressure 3.2 × 10⁻⁶. -7 Torr, the equilibrium vapor pressure of the gallium beam is 3.5 × 10⁻⁶. -7 The Torr uses a nitrogen-based radio frequency source with a power of 380W.

[0168] Step 11, epitaxial InN second quantum well layer (12), as follows Figure 3 (k).

[0169] Using molecular beam epitaxy, in Al 0.4 Ga 0.6 An InN second quantum well layer (12) with a thickness of 1 nm is deposited on the N third barrier layer (11).

[0170] The process conditions for molecular beam epitaxy were: temperature 500℃, nitrogen flow rate 1.2 sccm, and indium beam equilibrium vapor pressure 2.1 × 10⁻⁶. -7 The Torr uses a nitrogen-based radio frequency source with a power of 380W.

[0171] Step 12, epitaxial Al 0.4 Ga 0.6 N is the fourth barrier layer (13), such as Figure 3 (l).

[0172] Molecular beam epitaxy was used to epitaxially grow an Al layer with a thickness of 3 nm on the second quantum well layer (12) of InN. 0.4 Ga 0.6 The fourth barrier layer (13) together with the second barrier layer (9), the first quantum well layer (10), the third barrier layer (11), and the second quantum well layer (12) constitute a three-barrier double quantum well resonant tunneling diode.

[0173] The process conditions for molecular beam epitaxy were: temperature 500℃, nitrogen flow rate 1.2 sccm, and aluminum beam equilibrium vapor pressure 3.2 × 10⁻⁶. -7 Torr, the equilibrium vapor pressure of the gallium beam is 3.5 × 10⁻⁶. -7 The Torr uses a nitrogen-based radio frequency source with a power of 380W.

[0174] Step 13, epitaxial InN isolation layer (14), as follows Figure 3 (m).

[0175] Using molecular beam epitaxy, in Al 0.4 Ga 0.6 An InN isolation layer (14) with a thickness of 4 nm is deposited on the fourth barrier layer (13).

[0176] The process conditions for molecular beam epitaxy were: temperature 500℃, nitrogen flow rate 1.2 sccm, and indium beam equilibrium vapor pressure 2.1 × 10⁻⁶. -7 The Torr uses a nitrogen-based radio frequency source with a power of 380W.

[0177] Step 14, extension n + InN gate contact layer (15), such as Figure 3 (n).

[0178] Molecular beam epitaxy was used to deposit a 50 nm thick layer with a doping concentration of 5 x 10⁻⁶ on the InN isolation layer (14). 19 cm -3 n + InN gate contact layer (15).

[0179] The process conditions for molecular beam epitaxy were: temperature 500℃, nitrogen flow rate 1.2 sccm, and indium beam equilibrium vapor pressure 2.1 × 10⁻⁶. -7 Torr, the equilibrium vapor pressure of the silicon beam is 3.2 × 10⁻⁶. -7 The Torr uses a nitrogen-based radio frequency source with a power of 380W.

[0180] Step 15, in n + A mesh-like mesa isolation trench with a depth of 200 nm is formed on the InN gate contact layer (15) through homogenization, photolithography, development, and etching. Figure 3 (o).

[0181] 15a) A mesa isolation pattern is formed on the gate contact layer (15) using photolithography:

[0182] The specific implementation of this step is the same as step 15.1) in Embodiment 1.

[0183] 15b) Etch the gate contact layer (15) according to the mesa isolation pattern to form mesa isolation:

[0184] Using inductively coupled plasma etching, photoresist is used as a mask to etch the gate contact layer (15) according to the mesa isolation pattern, forming a mesh-like mesa isolation shallow trench with a depth of 200nm.

[0185] The process conditions for inductively coupled plasma etching are as follows: Cl2 gas flow rate of 10 sccm, BCl3 gas flow rate of 25 sccm, and etching time of 100 s.

[0186] Step 16, fabricate the gate electrode, such as Figure 3 (p).

[0187] n after tabletop isolation + A mask is fabricated on the InN gate contact layer (15), the gate electrode fabrication area is selected, and electron beam evaporation is used to fabricate the gate electrode on the mesa after isolation. + Metal is deposited on the InN gate contact layer (15) to form the gate electrode, wherein the deposited metal is a Ti / Au metal combination with a metal thickness of 0.02μm / 0.3μm.

[0188] The process conditions used for metal deposition are: vacuum degree less than 1.4 × 10⁻⁶. -3 Pa, power range of 400-800W, evaporation rate of

[0189] Step 17: Etch to form the square mesa of the memory, such as... Figure 3 (q).

[0190] Using inductively coupled plasma etching (ICP-C) with the gate electrode metal as a mask, n is etched. +A square mesa is formed from the InN gate contact layer (15) to the upper surface of the AlN first barrier layer (7), extending from the floating gate layer to the gate electrode.

[0191] The etching process conditions are: Cl2 gas flow rate of 10 sccm, BCl3 gas flow rate of 25 sccm, and etching time of 100 s.

[0192] Step 18: Dry etching forms grooves in the source-drain ohmic contact region, such as... Figure 3 (r).

[0193] Using a dry etching method with photoresist as a mask, the source-drain ohmic contact region was selected on the AlN first barrier layer (7), and the AlN first barrier layer (7), AlN insertion layer (6), and part of In were removed. 0.05 Ga 0.95 The N-channel layer (5) forms a groove for the source-drain ohmic contact region.

[0194] The etching process conditions were: Cl2 flow rate of 15 sccm, reaction chamber pressure of 11 mTorr, and electrode power of 180 W.

[0195] Step 19: Deposit a Si-doped n-type GaN layer to form an ohmic contact region, and fabricate the source and drain electrodes, as shown below. Figure 3 (s).

[0196] A 10 nm thick Si-doped n-type GaN layer with a Si doping concentration of 1.0 × 10⁻⁶ was deposited in the groove of the source-drain ohmic contact region using molecular beam epitaxy. 20 cm -3 .

[0197] The process conditions for molecular beam epitaxy were: temperature 650℃, nitrogen flow rate 1.2 sccm, and gallium beam equilibrium vapor pressure 5.0 × 10⁻⁶. -7 Torr, the equilibrium vapor pressure of the silicon beam is 3.2 × 10⁻⁶. -8 The Torr uses a nitrogen-based radio frequency source with a power of 380W.

[0198] A mask is fabricated on the AlN first barrier layer (7), and a Ti / Al / Ni / Au metal combination is deposited on the source-drain ohmic contact region using electron beam evaporation technology with a metal thickness of 0.02μm / 0.05μm / 0.04μm / 0.04μm. Then, rapid thermal annealing is performed in a nitrogen atmosphere at 830℃ to fabricate the source electrode and drain electrode. The source-drain electrode, together with the gate electrode, nucleation layer (2), buffer layer (3), back barrier layer (4), channel layer (5), insertion layer (6), and first barrier layer (7), constitutes a field-effect transistor.

[0199] The process conditions used for metal deposition are: vacuum degree less than 1.5 × 10⁻⁶. -3Pa, power range of 500-800W, evaporation rate of The process conditions for rapid hot annealing are: temperature 830℃ and time 30s.

[0200] Step 20, deposit a SiN passivation layer (16), as follows Figure 3 (t).

[0201] A 200 nm thick SiN passivation layer was deposited over the entire sample area using plasma-enhanced chemical vapor deposition (16).

[0202] The process conditions used in the plasma-enhanced chemical vapor deposition method are: time 60s, pressure 2200mTorr, temperature 350℃, SiH4 flow rate 13.5sccm, NH3 flow rate 10sccm, and N2 flow rate 1000sccm.

[0203] Step 21: Gate electrode vias, source electrode vias, and drain electrode vias are fabricated on the SiN passivation layer (16), as follows: Figure 3 (u).

[0204] Using photoresist as a mask, reactive ion etching is used to etch the SiN passivation layer (16) to the metal surfaces of the gate electrode, source electrode and drain electrode, forming the gate electrode via, source electrode via and drain electrode via, respectively.

[0205] The process conditions used in the reactive ion etching method are: pressure of 1500 mTorr, power of 200 W, SF6 flow rate of 8 sccm, CHF3 flow rate of 10 sccm, and He flow rate of 150 sccm.

[0206] Step 22, extend each electrode pin from each electrode via, such as... Figure 3 (v).

[0207] Using traditional optical lithography, the metal pin patterns of the gate electrode, source electrode, and drain electrode are formed on each electrode via by photolithography.

[0208] Using electron beam evaporation, according to The process involves evaporating 80 nm thick Au metal onto each electrode pin at a certain rate, followed by soaking in acetone to form gate electrode pins, source electrode pins, and drain electrode pins that interconnect with the gate electrode, source electrode, and drain electrode, thus completing the memory fabrication.

[0209] Example 3: Using metal-organic chemical vapor deposition and molecular beam epitaxy, a GaN nucleation layer, a GaN buffer layer, and an In layer were fabricated on a silicon carbide substrate. 0.17 Al 0.83 N-back barrier layer, Al 0.05 Ga 0.95N-channel layer, In 0.1 Al 0.9 N is the first barrier layer, In 0.1 Ga 0.9 N-floating gate layer, In 0.1 Al 0.9 N represents the first, second, and fourth potential barrier layers, In 0.1 Ga 0.9 N is the first and second quantum well layers, n + In 0.1 Ga 0.9 The doping concentration of the N-gate contact layer is 1x10. 19 cm -3 Non-volatile multi-valued logic memory integrating nitride devices.

[0210] Step A, depositing a GaN nucleation layer (2), as follows Figure 3 (a).

[0211] Using metal-organic chemical vapor deposition, a GaN nucleation layer (2) with a thickness of 1000 nm was deposited on a silicon carbide substrate (1) under the following process conditions: temperature of 1150 °C, pressure of 60 Torr, gallium source flow rate of 200 sccm, ammonia flow rate of 5000 sccm, and hydrogen flow rate of 3500 sccm.

[0212] Step B, deposit a GaN buffer layer (3), as follows Figure 3 (b)

[0213] Using metal-organic chemical vapor deposition, a GaN buffer layer (3) with a thickness of 2000 nm was deposited on the GaN nucleation layer (2) under the process conditions of a temperature of 1150℃, a pressure of 60 Torr, a gallium source flow rate of 200 sccm, an ammonia flow rate of 6000 sccm, and a hydrogen flow rate of 5000 sccm.

[0214] Step C, depositing In 0.17 Al 0.83 N-back barrier layer (4), such as Figure 3 (c)

[0215] Using metal-organic chemical vapor deposition (MOCVD), under the following process conditions: temperature 750℃, pressure 300 Torr, indium source flow rate 120 sccm, aluminum source flow rate 4 sccm, ammonia flow rate 6000 sccm, and hydrogen flow rate 5000 sccm, an In layer with a thickness of 12 nm was deposited on the GaN buffer layer (3). 0.17 Al 0.83 N-back barrier layer (4).

[0216] Step D, Al deposition 0.05 Ga0.95 N-channel layer (5), such as Figure 3 (d)

[0217] Using metal-organic chemical vapor deposition (MOCVD), under the following process conditions: temperature 850℃, pressure 40 Torr, aluminum source flow rate 10 sccm, gallium source flow rate 50 sccm, ammonia flow rate 6000 sccm, and hydrogen flow rate 5000 sccm, in In... 0.17 Al 0.83 An Al layer with a thickness of 20 nm is deposited on the N-back barrier layer (4). 0.05 Ga 0.95 N-channel layer (5).

[0218] Step E, deposit the AlN insertion layer (6), as follows Figure 3 (e).

[0219] Using metal-organic chemical vapor deposition (MOCVD), under the following process conditions: temperature 850℃, pressure 40 Torr, aluminum source flow rate 10 sccm, ammonia flow rate 6000 sccm, and hydrogen flow rate 5000 sccm, in Al... 0.05 Ga 0.95 An AlN insertion layer (6) with a thickness of 2 nm is deposited on the N-channel layer (5).

[0220] Step F, depositing In 0.1 Al 0.9 N first barrier layer (7), such as Figure 3 (f).

[0221] Using metal-organic chemical vapor deposition (MOCVD), under the following process conditions: temperature 780°C, pressure 300 Torr, indium source flow rate 60 sccm, aluminum source flow rate 20 sccm, ammonia flow rate 6000 sccm, and hydrogen flow rate 5000 sccm, an In layer with a thickness of 12 nm was deposited on the AlN insertion layer (6). 0.1 Al 0.9 N is the first barrier layer (7).

[0222] Step G, growth In 0.1 Ga 0.9 N-floating gate layer (8), such as Figure 3 (g)

[0223] Using molecular beam epitaxy (MBE), at a temperature of 540℃, a nitrogen flow rate of 0.8 sccm, and an indium beam equilibrium vapor pressure of 0.8 × 10⁻⁶, an MBE was achieved. -7 Torr, the equilibrium vapor pressure of the gallium beam is 5.2 × 10⁻⁶. -7 Torr, with a nitrogen RF source power of 320W, in In 0.1 Al 0.9An 8nm thick In layer is grown on the first barrier layer (7) of N. 0.1 Ga 0.9 N-floating gate layer (8).

[0224] Step H, growth In 0.1 Al 0.9 N second barrier layer (9), such as Figure 3 (h).

[0225] Using molecular beam epitaxy (MBE), at a temperature of 540℃, a nitrogen flow rate of 0.8 sccm, and an indium beam equilibrium vapor pressure of 0.8 × 10⁻⁶, an MBE was achieved. -7 Torr, the equilibrium vapor pressure of the aluminum beam is 0.8 × 10⁻⁶. -7 Torr, with a nitrogen RF source power of 320W, in In 0.1 Ga 0.9 An In layer with a thickness of 1 nm is grown on the N-floating gate layer (8). 0.1 Al 0.9 N is the second barrier layer (9).

[0226] Step I, Growth In 0.1 Ga 0.9 N first quantum well layer (10), as Figure 3 (i).

[0227] Using molecular beam epitaxy (MBE), at a temperature of 540℃, a nitrogen flow rate of 0.8 sccm, and an indium beam equilibrium vapor pressure of 0.8 × 10⁻⁶, an MBE was achieved. -7 Torr, the equilibrium vapor pressure of the gallium beam is 5.2 × 10⁻⁶. -7 Torr, with a nitrogen RF source power of 320W, in In 0.1 Al 0.9 An In layer with a thickness of 1 nm is grown on the second barrier layer (9) of N. 0.1 Ga 0.9 N is the first quantum well layer (10).

[0228] Step J, growth In 0.1 Al 0.9 N is the third barrier layer (11), such as Figure 3 (j).

[0229] Using molecular beam epitaxy (MBE), at a temperature of 540℃, a nitrogen flow rate of 0.8 sccm, and an indium beam equilibrium vapor pressure of 0.8 × 10⁻⁶, an MBE was achieved. -7 Torr, the equilibrium vapor pressure of the aluminum beam is 0.8 × 10⁻⁶. -7 Torr, with a nitrogen RF source power of 320W, in In 0.1 Ga 0.9 An In layer with a thickness of 3 nm is grown on the first quantum well layer (10) of N.0.1 Al 0.9 N is the third barrier layer (11).

[0230] Step K, growth In 0.1 Ga 0.9 N second quantum well layer (12), as Figure 3 (k).

[0231] Using molecular beam epitaxy (MBE), at a temperature of 540℃, a nitrogen flow rate of 0.8 sccm, and an indium beam equilibrium vapor pressure of 0.8 × 10⁻⁶, an MBE was achieved. -7 Torr, the equilibrium vapor pressure of the gallium beam is 5.2 × 10⁻⁶. -7 Torr, with a nitrogen RF source power of 320W, in In 0.1 Al 0.9 An In layer with a thickness of 1 nm is grown on the third barrier layer (11) of N. 0.1 Ga 0.9 N-second quantum well layer (12).

[0232] Step L, growth In 0.1 Al 0.9 N is the fourth barrier layer (13), such as Figure 3 (l).

[0233] Using molecular beam epitaxy (MBE), at a temperature of 540℃, a nitrogen flow rate of 0.8 sccm, and an indium beam equilibrium vapor pressure of 0.8 × 10⁻⁶, an MBE was achieved. -7 Torr, the equilibrium vapor pressure of the aluminum beam is 0.8 × 10⁻⁶. -7 Torr, with a nitrogen RF source power of 320W, in In 0.1 Ga 0.9 An In layer with a thickness of 3 nm is grown on the second quantum well layer (12). 0.1 Al 0.9 The fourth barrier layer (13) together with the second barrier layer (9), the first quantum well layer (10), the third barrier layer (11), and the second quantum well layer (12) constitute a three-barrier double quantum well resonant tunneling diode.

[0234] Step M, growth In 0.1 Ga 0.9 N isolation layer (14), such as Figure 3 (m).

[0235] Using molecular beam epitaxy (MBE), at a temperature of 540℃, a nitrogen flow rate of 0.8 sccm, and an indium beam equilibrium vapor pressure of 0.8 × 10⁻⁶, an MBE was achieved. -7 Torr, the equilibrium vapor pressure of the gallium beam is 5.2 × 10⁻⁶. -7 Torr, with a nitrogen RF source power of 320W, in In 0.1Al 0.9 An 8 nm thick In layer is grown on the fourth barrier layer (13) of N. 0.1 Ga 0.9 N isolation layer (14).

[0236] Step N, growth n + In 0.1 Ga 0.9 N gate contact layer (15), such as Figure 3 (n).

[0237] Using molecular beam epitaxy (MBE), at a temperature of 540℃, a nitrogen flow rate of 0.5 sccm, and an indium beam equilibrium vapor pressure of 0.8 × 10⁻⁶, an MBE was achieved. -7 Torr, the equilibrium vapor pressure of the gallium beam is 5.2 × 10⁻⁶. -7 Torr, the equilibrium vapor pressure of the silicon beam is 3.0 × 10⁻⁶. -8 Torr, with a nitrogen RF source power of 320W, in In 0.1 Ga 0.9 A 100 nm thick N-isolation layer (14) with a doping concentration of 1 x 10⁻⁶ is grown on the N-isolation layer (14). 19 cm -3 In 0.1 Ga 0.9 N-gate contact layer (15).

[0238] Step O, in n + In 0.1 Ga 0.9 A mesh-like mesa isolation trench with a depth of 400 nm is formed on the N gate contact layer (15) through homogenization, photolithography, development, and etching. Figure 3 (o).

[0239] O1) A mesa isolation pattern is formed on the gate contact layer (15) using photolithography:

[0240] The specific implementation of this step is the same as step 15.1) in Embodiment 1.

[0241] O2) The gate contact layer (15) is etched according to the mesa isolation pattern to form mesa isolation:

[0242] Using photoresist as a mask, inductively coupled plasma etching is used under the process conditions of Cl2 gas flow rate of 10 sccm, BCl3 gas flow rate of 25 sccm, and etching time of 200 s. The gate contact layer (15) is etched according to the mesa isolation pattern to form a mesh-like mesa isolation with a depth of 400 nm.

[0243] Step P, fabricate the gate electrode, as follows: Figure 3 (p).

[0244] n after tabletop isolation+ In 0.1 Ga 0.9 A mask is fabricated on the N-gate contact layer (15), the gate electrode fabrication area is selected, and electron beam evaporation technology is used to evaporate the material at a vacuum level of less than 1.5 × 10⁻⁶. -3 Pa, power range of 300-800W, evaporation rate of Under the process conditions, at n + In 0.1 Ga 0.9 A gate electrode is fabricated on the N gate contact layer (15), wherein the deposited metal is a Ti / Au metal combination with a metal thickness of 0.03μm / 0.4μm.

[0245] Step Q: Etch the gate contact layer (15) to form a square mesa of the memory, such as... Figure 3 (q).

[0246] Using the gate electrode metal as a mask, an inductively coupled plasma etching process was employed. Under the process conditions of a Cl2 gas flow rate of 10 sccm, a BCl3 gas flow rate of 25 sccm, and an etching time of 200 s, n was etched. + In 0.1 Ga 0.9 N gate contact layer (15) to In 0.1 Al 0.9 The first barrier layer (7) forms a square mesa from the floating gate layer to the gate electrode.

[0247] Step R involves dry etching to form grooves in the source / drain ohmic contact region, such as... Figure 3 (r).

[0248] Using photoresist as a mask, in In 0.1 Al 0.9 On the first barrier layer (7), the source and drain ohmic contact regions were selected. Using dry etching technology, under the process conditions of Cl2 flow rate of 18 sccm, reaction chamber pressure of 12 mTorr, and electrode power of 160 W, In was removed. 0.1 Al 0.9 The first barrier layer (7), the AlN insertion layer (6), and part of the Al 0.05 Ga 0.95 The N-channel layer (5) forms a groove for the source-drain ohmic contact region.

[0249] Step S involves depositing a Si-doped n-type GaN layer to form an ohmic contact region, and fabricating the source and drain electrodes, as shown below. Figure 3 (s).

[0250] Using process conditions of 1150℃, 60 Torr, gallium source flow rate of 50 sccm, silicon source flow rate of 800 sccm, ammonia flow rate of 5000 sccm, and hydrogen flow rate of 3500 sccm, a 30 nm thick layer of Si with a doping concentration of 0.5 × 10⁻⁶ was deposited in the ohmic contact region trench of the source-drain electrode. 20 cm -3 An n-type GaN layer is formed to create an ohmic contact region;

[0251] In 0.1 Al 0.9 A mask is fabricated on the first barrier layer (7) of N, and electron beam evaporation is performed at a vacuum level of less than 1.6 × 10⁻⁶. -3 Pa, power range of 600-900W, evaporation rate of Under the specified process conditions, metal is deposited on the source-drain ohmic contact region, wherein the deposited metal is a Ti / Al / Ni / Au metal combination with a metal thickness of 0.02μm / 0.2μm / 0.05μm / 0.05μm;

[0252] Then, a rapid thermal annealing process is carried out in a nitrogen atmosphere at a temperature of 830°C for 30 seconds to complete the fabrication of the source electrode and the drain electrode. The source and drain electrodes, together with the gate electrode, nucleation layer (2), buffer layer (3), back barrier layer (4), channel layer (5), insertion layer (6), and first barrier layer (7), constitute a field-effect transistor.

[0253] Step T, deposit an HfO2 passivation layer (16), as follows Figure 3 (t).

[0254] Using atomic layer deposition, under the following conditions, a 100 nm thick HfO2 passivation layer was deposited over the entire memory region (16) at a time of 70 s, a temperature of 280 °C, an ethyl methylamino hafnium flow rate of 1200 sccm, an H2O flow rate of 110 sccm, and an N2 flow rate of 1000 sccm.

[0255] Step U, prepare gate electrode vias, source electrode vias, and drain electrode vias on the HfO2 passivation layer (16), such as Figure 3 (u).

[0256] Using photoresist as a mask, reactive ion etching is used to etch the HfO2 passivation layer (16) to the metal surfaces of the gate electrode, source electrode and drain electrode under the process conditions of 1500 mTorr pressure, 200 W power, 8 sccm SF6 flow rate, 10 sccm CHF3 flow rate and 150 sccm He flow rate, respectively forming the gate electrode via, source electrode via and drain electrode via.

[0257] Step V: Lead out each electrode pin from each electrode via, such as... Figure 3 (v).

[0258] Using traditional optical lithography, the metal pin patterns of the gate electrode, source electrode, and drain electrode are formed by photolithography.

[0259] On the electrode pin patterns, electron beam evaporation technology is used to... Au metal with a thickness of 80 nm is evaporated at a high speed and then immersed in acetone to form gate electrode pins, source electrode pins and drain electrode pins that are interconnected with the gate electrode, source electrode and drain electrode, respectively, thus completing the memory fabrication.

[0260] The above descriptions are merely three specific examples of the present invention and do not constitute any limitation on the present invention. Obviously, those skilled in the art, after understanding the content and principles of the present invention, can make various modifications and changes in form and detail without departing from the principles and structure of the present invention. For example, in addition to the already used gallium nitride, aluminum nitride, and silicon carbide materials, the substrate can also be any one of sapphire, silicon, diamond, and boron nitride materials; in addition to the already used InAlN, AlN, and AlGaN materials, the first barrier layer can also be any one of InAlGaN, ScAlN, YAlN, AlPN, BAlN, and BPN materials; in addition to the already used InAlN, AlN, and AlGaN materials, the second, third, and fourth barrier layers can also be any one of InAlGaN, ScAlN, YAlN, AlPN, BAlN, and BPN materials; the doping concentration of the gate contact layer can also be any one of the already used 1x10⁻¹⁰. 20 cm -3 5x10 19 cm -3 1x10 19 cm -3 It can also be used in 1x10 19 cm -3 -1x10 20 cm -3 The concentration can be any value between these parameters; however, these modifications and changes based on the ideas of this invention are still within the scope of the claims of this invention.

Claims

1. A non-volatile multi-valued logic memory integrating nitride devices, comprising, from bottom to top, a substrate (1), a buffer layer (3), a second barrier layer (9), a first quantum well layer (10), a third barrier layer (11), an isolation layer (14), a gate contact layer (15), and a gate electrode, wherein these layers and electrodes are externally encapsulated by a passivation layer (16), and the second barrier layer (9), the first quantum well layer (10), and the third barrier layer (11) constitute a double-barrier single-quantum-well resonant tunneling diode, characterized in that: A nucleation layer (2) is added between the substrate (1) and the buffer layer (3); Between the buffer layer (3) and the second barrier layer (9), a back barrier layer (4), a channel layer (5), an insertion layer (6), a first barrier layer (7), and a floating gate layer (8) are sequentially provided. The floating gate layer (8) has a source electrode and a drain electrode on both sides. The nucleation layer (2), buffer layer (3), back barrier layer (4), channel layer (5), insertion layer (6), first barrier layer (7), source electrode, drain electrode, and gate electrode constitute a nitride field-effect transistor. The on and off states of the channel are realized by adjusting the carrier concentration of the heterojunction interface channel in the field-effect transistor. A second quantum well layer (12) and a fourth quantum well layer (13) are sequentially added between the third barrier layer (11) and the isolation layer (14). The second quantum well layer (12), the fourth quantum well layer (13) and the double-barrier single quantum well resonant tunneling diode constitute a triple-barrier double quantum well resonant tunneling diode. The multi-valued output current is realized through the differential negative resistance effect of the resonant tunneling diode.

2. The memory as claimed in claim 1, characterized in that, The materials and parameters of each layer constituting the triple-barrier double-quantum-well resonant tunneling diode are as follows: The thickness of the second barrier layer (9) is 1 nm-3 nm, the thickness of the third barrier layer (11) is 1 nm-3 nm, and the thickness of the fourth barrier layer (13) is 1 nm-3 nm. All three barrier layers are made of any one of AlN, AlGaN, InAlN, InAlGaN, ScAlN, YAlN, AlPN, BAlN, and BPN materials. The thickness of the first quantum well layer (10) is 1 nm-3 nm, and the thickness of the second quantum well layer (12) is 1 nm-3 nm. Both quantum well layers are made of any one of GaN, InGaN, and InN materials. The thickness of the isolation layer (14) is 4 nm-15 nm, and it is made of any one of GaN, InGaN, and InN materials; The thickness of the gate contact layer (15) is 50 nm-200 nm, and the doping concentration is 1 x 10⁻⁶. 19 cm -3 -1x10 20 cm -3 between n + GaN, n + InGaN or n + InN material.

3. The memory as claimed in claim 1, characterized in that, The materials and parameters of each layer constituting a field-effect transistor are as follows: The thickness of the nucleation layer (2) is 3 nm-1000 nm, and it can be any one of AlN, GaN, or AlGaN materials; The thickness of the buffer layer (3) is 500 nm-2000 nm, and it is made of any one of AlN, GaN, or AlGaN materials; The thickness of the back barrier layer (4) is 5 nm-50 nm, and it can be any one of AlGaN, InGaN, and InAlN materials. The thickness of the channel layer (5) is 10 nm-100 nm, and it is made of any one of GaN, InGaN, or AlGaN materials; The thickness of the insertion layer (6) is 1 nm-2 nm, and it is made of AlN material; The thickness of the first barrier layer (7) is 3 nm-30 nm, and it is made of any one of AlN, AlGaN, InAlN, InAlGaN, ScAlN, YAlN, AlPN, BAlN, or BPN materials.

4. The memory as claimed in claim 1, characterized in that, The substrate (1) is made of any one of the following materials: sapphire, silicon, silicon carbide, diamond, gallium nitride, aluminum nitride, and boron nitride.

5. The memory as claimed in claim 1, characterized in that, The thickness of the floating gate layer (8) is 4 nm-15 nm, and it is made of any one of GaN, InGaN, or InN materials.

6. The memory as claimed in claim 1, characterized in that, The passivation layer (16) is made of any one of SiN, Al2O3, or HfO2.

7. A method for fabricating a non-volatile multi-valued logic memory integrating nitride devices, characterized in that, Includes the following steps: 1) Using metal-organic chemical vapor deposition or molecular beam epitaxy, a nucleation layer (2) of 3 nm-1000 nm is grown on the substrate (1). 2) Using metal-organic chemical vapor deposition or molecular beam epitaxy, a buffer layer (3) of 500 nm-2000 nm is grown on the nucleation layer (2). 3) Using metal-organic chemical vapor deposition or molecular beam epitaxy, a back barrier layer (4) with a thickness of 5 nm-50 nm is grown on the buffer layer (3). 4) Using metal-organic chemical vapor deposition or molecular beam epitaxy, a channel layer (5) of 10 nm-100 nm is grown on the back barrier layer (4). 5) Using metal-organic chemical vapor deposition or molecular beam epitaxy, an AlN insertion layer (6) with a thickness of 1 nm-2 nm is grown on the channel layer (5). 6) Using metal-organic chemical vapor deposition or molecular beam epitaxy, a first barrier layer (7) with a thickness of 3 nm-30 nm is grown on the AlN insertion layer (6). 7) Using molecular beam epitaxy, a floating gate layer (8) with a thickness of 4 nm-15 nm is grown on the first barrier layer (7). 8) Using molecular beam epitaxy, a second barrier layer (9) with a thickness of 1 nm-3 nm is grown on the floating gate layer (8). 9) Using molecular beam epitaxy, a first quantum well layer (10) with a thickness of 1 nm-3 nm is grown on the second barrier layer (9). 10) Using molecular beam epitaxy, a third barrier layer (11) with a thickness of 1 nm-3 nm is grown on the first quantum well layer (10). 11) Using molecular beam epitaxy, a second quantum well layer (12) with a thickness of 1 nm-3 nm is grown on the third barrier layer (11). 12) Using molecular beam epitaxy, a fourth barrier layer (13) with a thickness of 1 nm-3 nm is grown on the second quantum well layer (12). 13) Using molecular beam epitaxy, an isolation layer (14) with a thickness of 4 nm-15 nm is grown on the fourth barrier layer (13). 14) Using molecular beam epitaxy, a gate contact layer (15) with a thickness of 50 nm-200 nm is grown on the isolation layer (14). 15) Using conventional optical lithography, a mesa isolation pattern is formed on the gate contact layer (15). Then, using photoresist as a mask, the gate contact layer (15) is etched to the upper part of the buffer layer (3) using an inductively coupled plasma etching method with a BCl3 / Cl2 gas source to form a square mesa isolation shallow trench with a depth of 200 nm-800 nm. 16) Using photoresist as a mask, a gate electrode region is set on the gate contact layer (15), and metal Ti / Au is deposited in the region by electron beam evaporation to form a gate electrode; 17) Using the gate electrode metal as a mask, the gate contact layer (15) to the upper surface of the first barrier layer (7) is etched using the inductively coupled plasma etching method with a BCl3 / Cl2 gas source to form a square mesa from the floating gate layer (8) to the gate electrode. 18) Using photoresist as a mask, dry etching method is used to etch the first barrier layer (7) up to the top of the channel layer (5) to form a source-drain ohmic contact region groove. 19) Growing Si with a doping concentration of (0.5-5)×10⁻⁶ in the grooves of the source-drain ohmic contact region using metal-organic chemical vapor deposition or molecular beam epitaxy. 20 cm -3 n-type GaN material is used to form the ohmic contact region; using photoresist as a mask, an electron beam evaporation process is employed to first deposit the ohmic contact metal Ti / Al / Ni / Au in the ohmic contact region, and then at 830 nm... o Annealing under a nitrogen atmosphere to form source and drain electrodes; 20) A passivation layer with a thickness of 50 nm-200 nm was deposited over the entire sample area using plasma-enhanced chemical vapor deposition or atomic layer deposition (16). 21) Using photoresist as a mask, reactive ion etching is used with SF6 gas source to etch the passivation layer (16) to form gate electrode vias, source electrode vias and drain electrode vias; 22) Using traditional optical lithography, gate electrode, source electrode and drain electrode pin patterns are formed on the passivation layer (16). Then, using photoresist as a mask, an Au metal layer is evaporated on each electrode pin pattern using electron beam evaporation process to form the interconnection between each electrode and the corresponding electrode pin, thus completing the fabrication of the memory.

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