A pvt drift monitoring jump detection circuit

Abstract

The present disclosure provides a PVT drift monitoring timing jump detection circuit, which comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first inverter and a second inverter; so as to realize that when the length of a timing critical path exceeds one clock cycle, the jump detection circuit outputs a pre_error signal when the high level of a signal jumps in the next clock cycle, which is used by an adaptive adjustment system to dynamically adjust the voltage.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit design technology, specifically to a PVT drift monitoring and jump detection circuit. Background Technology

[0002] Chips are affected by fluctuations in process, voltage, and temperature (PVT) during operation. Traditional worst-case design methodologies leave a certain design margin during circuit design to ensure that the chip can still operate normally under worst conditions. However, as the voltage drops to near the subthreshold, a much larger margin is required to ensure normal operation, resulting in a significant waste of performance and power consumption. To solve this problem, adaptive voltage regulation technology has been proposed. It adaptively adjusts the chip's current operating voltage by monitoring the chip's current operating status in real time. The key to adaptive voltage regulation technology lies in monitoring the chip's operating status; therefore, a transition detection unit that detects signal transitions that occur too late is urgently needed. Summary of the Invention

[0003] (a) Technical problems to be solved

[0004] To address the aforementioned issues, this disclosure provides a PVT drift monitoring and jump detection circuit, which at least partially solves the technical problems of traditional adaptive voltage regulation technology, such as the difficulty in dynamically adjusting voltage.

[0005] (II) Technical Solution

[0006] This disclosure provides a PVT drift monitoring and transition detection circuit, including: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first inverter, and a second inverter; the source of the first PMOS transistor is connected to the positive terminal of the power supply, the gate of the first PMOS transistor is connected to a clock signal, the sources of the second and fourth PMOS transistors are connected to the drain of the first PMOS transistor and the input of the first inverter, with the connection node being VVDD; the output of the first inverter is connected to the pre_error signal; the negative terminal of the power supply is connected to ground; the drain of the first NMOS transistor and the source of the third PMOS transistor are connected to the second PMOS transistor. The drain of the S transistor is connected; the drain of the third NMOS transistor and the source of the fifth PMOS transistor are connected to the drain of the fourth PMOS transistor; the gate of the second PMOS transistor and the gate of the third PMOS transistor are connected to the drain of the fifth PMOS transistor, the source of the third NMOS transistor and the drain of the fourth NMOS transistor; the gate of the fourth PMOS transistor and the gate of the fifth PMOS transistor are connected to the drain of the third PMOS transistor, the source of the first NMOS transistor and the drain of the second NMOS transistor; the gate of the first NMOS transistor, the gate of the second NMOS transistor and the input of the second inverter are connected to the input signal; the gate of the third NMOS transistor and the gate of the fourth NMOS transistor are connected to the output of the second inverter; the source of the second NMOS transistor and the source of the fourth NMOS transistor are connected to ground.

[0007] Furthermore, during the preparation phase, the clock is low, the first PMOS transistor is turned on, and the power supply charges the connection node VVDD.

[0008] Furthermore, when the input signal changes, the connection node VVDD remains at a high level due to the charging of the power supply, unaffected by the input signal. After passing through the first inverter, the output pre_error signal is at a low level.

[0009] Furthermore, during the detection phase, the clock is high, the first PMOS transistor is turned off, the power supply stops charging the connection node VVDD, and the connection node VVDD becomes floating.

[0010] Furthermore, when the input signal transitions from low to high, the second and third PMOS transistors remain on, while the first and second NMOS transistors turn on, forming a path from the connection node VVDD to the ground. The charge in the connection node VVDD will dissipate and drop to a low level. After passing through the first inverter, the output pre_error signal becomes high.

[0011] Furthermore, when the input signal transitions from high to low, the fourth and fifth PMOS transistors remain on, while the third and fourth NMOS transistors turn on, forming a path from the connection node VVDD to the ground. The charge in the connection node VVDD will be lost and drop to a low level. After passing through the first inverter, the output pre_error signal becomes high.

[0012] Furthermore, when the input signal remains at a low level, the second NMOS transistor and the fourth PMOS transistor remain off, there is no path from the connection node VVDD to the ground line, the connection node VVDD will remain at a high level, and after passing through the first inverter, the output pre_error signal is at a low level.

[0013] Furthermore, when the input signal remains at a high level, the fourth NMOS transistor and the second PMOS transistor remain in the off state, there is no path from the connection node VVDD to the ground line, the connection node VVDD will remain at a high level, and after passing through the first inverter, the output pre_error signal is at a low level.

[0014] (III) Beneficial Effects

[0015] The PVT drift monitoring transition detection circuit disclosed herein operates in two phases: a preparation phase and a detection phase. During the preparation phase, the clock is low, the first PMOS transistor is turned on, and the power supply VDD charges the connection node VVDD, ensuring that the output signal pre_error after passing through the first inverter is low. During the detection phase, the clock is high, the first PMOS transistor is turned off, the power supply VDD stops charging the connection node VVDD, and the 0-1 transition of the input signal turns on the first NMOS transistor, the second NMOS transistor, the second PMOS transistor, and the third PMOS transistor, forming a discharge path for the connection node VVDD. The 1-0 transition of the input signal turns on the third NMOS transistor, the fourth NMOS transistor, the fourth PMOS transistor, and the fifth PMOS transistor, forming a discharge path for the connection node VVDD. The connection node VVDD is discharged to a low level through the discharge path, and the output signal pre_error after passing through the first inverter is high. Thus, the function of detecting signal transitions at a high clock level is achieved. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a circuit diagram of a PVT drift monitoring timing jump detection circuit provided in this disclosure;

[0018] Figure 2 This is a schematic diagram of the working principle of a PVT drift monitoring timing jump detection circuit provided in this disclosure. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0020] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0021] The purpose of this disclosure is to provide a PVT drift monitoring transition detection circuit, so that when the critical path length exceeds one clock cycle and the signal transitions to a high level in the next clock cycle, the transition detection circuit outputs a pre_error signal for use by the adaptive adjustment system to dynamically adjust the voltage.

[0022] like Figure 1 As shown, this disclosure discloses a PVT drift monitoring timing jump detection circuit, which includes: a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a first inverter INV1, and a second inverter INV2;

[0023] The source of the first PMOS transistor MP1 is connected to the positive terminal of the power supply VDD, and the gate of the first PMOS transistor MP1 is connected to the clock signal CLK. Figure 2 The signal CLK in the first inverter is connected to the source of the second PMOS transistor MP2 and the source of the fourth PMOS transistor MP4, which are connected to the drain of the first PMOS transistor MP1 and the input of the first inverter INV1, with the connection node being VVDD; the output of the first inverter INV1 is connected to the pre_error signal. Figure 2 The pre_error signal in the signal is connected; the negative terminal of the power supply VDD is connected to the ground wire;

[0024] The drain of the first NMOS transistor MN1 and the source of the third PMOS transistor MP3 are connected to the drain of the second PMOS transistor MP2; the drain of the third NMOS transistor MN3 and the source of the fifth PMOS transistor MP5 are connected to the drain of the fourth PMOS transistor MP4; the gate of the second PMOS transistor MP2 and the gate of the third PMOS transistor MP3 are connected to the drain of the fifth PMOS transistor MP5, the source of the third NMOS transistor MN3 and the drain of the fourth NMOS transistor MN4, with the connection node being V2; the gate of the fourth PMOS transistor MP4 and the gate of the fifth PMOS transistor MP5 are connected to the drain of the third PMOS transistor MP3, the source of the first NMOS transistor MN1 and the drain of the second NMOS transistor MN2, with the connection node being V1;

[0025] The gate of the first NMOS transistor MN1, the gate of the second NMOS transistor MN2, the input of the second inverter INV2, and the input signal D ( Figure 2The signal D in the circuit is connected; the gate of the third NMOS transistor MN3 and the gate of the fourth NMOS transistor MN4 are connected to the output DN of the second inverter INV2; the source of the second NMOS transistor MN2 and the source of the fourth NMOS transistor MN4 are connected to the ground line VSS.

[0026] Its working principle is as follows: During the preparation phase: the clock is low, the first PMOS transistor MP1 is turned on, and the power supply VDD charges the connection node VVDD. Due to the charging of the power supply VDD, the level of the connection node VVDD is unaffected by the input signal and remains at a high level. After passing through the first inverter INV1, the output pre_error signal is low. During the detection phase: the clock is high, the first PMOS transistor MP1 is turned off, and the power supply VDD stops charging the connection node VVDD, making the connection node VVDD float. When the input signal D transitions from low to high, the second PMOS transistor MP2 and the third PMOS transistor MP3 remain on, while the first NMOS transistor MN1 and the second NMOS transistor MN2 change from off to on, forming a path from the connection node VVDD to ground. The charge in the connection node VVDD will dissipate, causing it to drop to a low level. After passing through the first inverter INV1, the output pre_error signal becomes high. When the input signal D transitions from high to low, the fourth PMOS transistor MP4 and the fifth PMOS transistor MP5 remain on, while the third NMOS transistor MN3 and the fourth NMOS transistor MN4 turn on, forming a path from the connection node VVDD to ground. The charge in the connection node VVDD dissipates, causing it to drop to a low level. After passing through the first inverter INV1, the output pre_error signal becomes high. When the input signal D remains low, the second NMOS transistor MN2 and the fourth PMOS transistor MP4 remain off, leaving no path from the connection node VVDD to ground. The connection node VVDD will remain high, and after passing through the first inverter INV1, the output pre_error signal will be low. When the input signal D remains high, the fourth NMOS transistor MN4 and the second PMOS transistor MP2 remain off, leaving no path from the connection node VVDD to ground. The connection node VVDD will remain high, and after passing through the first inverter INV1, the output pre_error signal will be low.

[0027] The specific function of this disclosure is as follows: During the period when the clock signal CLK is low, the power supply VDD charges the connection node VVDD through MP1, keeping it at a high level. During this period, the output signal pre_error remains at a low level. When the clock signal CLK reaches a high level, MP1 is turned off, and the power supply VDD stops charging the connection node VVDD. The 0-1 transition of the input signal D will turn on the first NMOS transistor MN1 and the second NMOS transistor MN2, forming a charge discharge path MP2-MN1 & MP3-MN2 from the connection node VVDD to the ground VSS together with the already turned-on second PMOS transistor MP2 and third PMOS transistor MP3. The 1-0 transition of the input signal D will turn on the third NMOS transistor MN3 and the fourth NMOS transistor MN4, forming a charge discharge path MP4-MN3 & MP5-MN4 from the connection node VVDD to the ground VSS together with the already turned-on fourth PMOS transistor MP4 and fifth PMOS transistor MP5. The connection node VVDD discharges through the charge discharge path, its potential becoming low. After passing through the first inverter INV1, the output pre_error signal is high. If the input signal D remains unchanged, the above path will not open, the connection node VVDD will remain high, and the output pre_error signal will be low after passing through the first inverter INV1. This achieves the function of detecting signal transitions at a high clock level.

[0028] The specific embodiments described above further illustrate the purpose, technical solutions, and beneficial effects of this disclosure. It should be understood that the above descriptions are merely specific embodiments of this disclosure and are not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A PVT drift monitoring and jump detection circuit, characterized in that, include: First PMOS transistor, second PMOS transistor, third PMOS transistor, fourth PMOS transistor, fifth PMOS transistor, first NMOS transistor, second NMOS transistor, third NMOS transistor, fourth NMOS transistor, first inverter and second inverter; The source of the first PMOS transistor is connected to the positive terminal of the power supply, the gate of the first PMOS transistor is connected to the clock signal, the source of the second PMOS transistor and the source of the fourth PMOS transistor are connected to the drain of the first PMOS transistor and the input of the first inverter, with the connection node being VVDD; the output of the first inverter is connected to the pre_error signal; the negative terminal of the power supply is connected to the ground line. The drain of the first NMOS transistor and the source of the third PMOS transistor are connected to the drain of the second PMOS transistor; the drain of the third NMOS transistor and the source of the fifth PMOS transistor are connected to the drain of the fourth PMOS transistor; the gate of the second PMOS transistor and the gate of the third PMOS transistor are connected to the drain of the fifth PMOS transistor, the source of the third NMOS transistor and the drain of the fourth NMOS transistor; the gate of the fourth PMOS transistor and the gate of the fifth PMOS transistor are connected to the drain of the third PMOS transistor, the source of the first NMOS transistor and the drain of the second NMOS transistor. The gates of the first NMOS transistor, the second NMOS transistor, and the input of the second inverter are connected to the input signal; the gates of the third NMOS transistor and the fourth NMOS transistor are connected to the output of the second inverter; the sources of the second NMOS transistor and the fourth NMOS transistor are connected to ground.

2. The PVT drift monitoring and jump detection circuit according to claim 1, characterized in that, During the preparation phase, the clock is low, the first PMOS transistor is turned on, and the power supply charges the connection node VVDD.

3. The PVT drift monitoring and jump detection circuit according to claim 1, characterized in that, When the input signal changes, the connection node VVDD remains at a high level due to the charging of the power supply, unaffected by the input signal. After passing through the first inverter, the output pre_error signal is at a low level.

4. The PVT drift monitoring and jump detection circuit according to claim 1, characterized in that, During the detection phase, the clock is high, the first PMOS transistor is turned off, the power supply stops charging the connection node VVDD, and the connection node VVDD becomes floating.

5. The PVT drift monitoring and jump detection circuit according to claim 1, characterized in that, When the input signal transitions from low to high, the second PMOS transistor and the third PMOS transistor remain on, while the first NMOS transistor and the second NMOS transistor turn on, forming a path from the connection node VVDD to the ground. The charge in the connection node VVDD will dissipate and drop to a low level. After passing through the first inverter, the output pre_error signal becomes high.

6. The PVT drift monitoring and jump detection circuit according to claim 1, characterized in that, When the input signal transitions from high to low, the fourth PMOS transistor and the fifth PMOS transistor remain on, while the third NMOS transistor and the fourth NMOS transistor change from off to on, forming a path from the connection node VVDD to the ground. The charge in the connection node VVDD will dissipate and drop to a low level. After passing through the first inverter, the output pre_error signal becomes high.

7. The PVT drift monitoring and jump detection circuit according to claim 1, characterized in that, When the input signal remains low, the second NMOS transistor and the fourth PMOS transistor remain off, there is no path from the connection node VVDD to the ground, the connection node VVDD will remain high, and after passing through the first inverter, the output pre_error signal will be low.

8. The PVT drift monitoring and jump detection circuit according to claim 1, characterized in that, When the input signal remains high, the fourth NMOS transistor and the second PMOS transistor remain off, and there is no path from the connection node VVDD to the ground. The connection node VVDD will remain high, and after passing through the first inverter, the output pre_error signal will be low.

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