Adjustable square wave delay circuit with self-calibration structure

Abstract

The application discloses a square wave delay circuit with a self-calibration structure, which utilizes a rising edge delay multiplexing mode to realize the delay of square wave double edges, i.e., rising edges and falling edges, to ensure the duty cycle of input and output square waves to be consistent and shield the influence caused by PVT variation; the self-calibration structure is utilized to reduce the delay error caused by process deviation and other non-ideal factors; and the DAC is utilized to control the delay time, so that high-resolution delay adjustment can be realized, and a stable and adjustable square wave delay circuit is realized.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, specifically relating to an adjustable square wave delay circuit with a self-calibration structure. Background Technology

[0002] Stable and adjustable square wave delay circuits play an important role in signal processing, data acquisition, and time-to-digital converters. Current square wave delay circuits, such as the one disclosed in CN207166471U for thyristor delay triggering, have drawbacks such as the difficulty in maintaining strict consistency between the rising and falling edge delays of the square wave, and the significant influence of non-ideal factors such as process deviations on the delay. Summary of the Invention

[0003] To address the problems existing in the background technology, this invention proposes an adjustable square wave delay circuit with a self-calibration structure. By adding a self-calibration structure to the circuit, the influence of non-ideal factors such as process deviations on the circuit delay is reduced. The circuit structure ensures that the rising edge delay of the square wave is equal to the falling edge delay, avoiding the delay circuit from affecting the duty cycle of the square wave. By using a DAC to control the delay time, high-resolution delay adjustment can be achieved, ultimately realizing a stable and adjustable square wave delay circuit.

[0004] An adjustable square wave delay circuit with a self-calibration structure includes an adjustable rising edge delay unit, a delay calibration counter, and a rising edge delay multiplexing unit. The rising edge delay multiplexing unit includes a data selector and a narrow pulse sampling output unit. The adjustable rising edge delay unit is connected to the data selector, which serves as the input terminal of the entire circuit. The adjustable rising edge delay unit, the delay calibration counter, and the narrow pulse sampling output unit are interconnected, with the narrow pulse sampling output unit serving as the output terminal of the entire circuit.

[0005] The square wave signal is input from the IN terminal of the data selector, the inverted square wave signal is input from the INB terminal of the data selector, and the delayed square wave signal is output from the OUT terminal of the narrow pulse sampling output unit.

[0006] The beneficial effects achieved by this invention are as follows:

[0007] (1) By using the rising edge delay multiplexing method, the delay of the square wave with equal duration on both sides (rising edge and falling edge) is achieved, which ensures that the duty cycle of the input and output square waves is consistent, and the method can shield the influence of PVT changes.

[0008] (2) Use self-calibrating structure to reduce delay error caused by non-ideal factors such as process deviation.

[0009] (3) By using DAC to control the delay time, high-resolution delay adjustment can be achieved, realizing a stable and adjustable square wave delay circuit. Attached Figure Description

[0010] Figure 1 This is a top-level topology diagram of the system in an embodiment of the present invention.

[0011] Figure 2 This is an internal circuit diagram of the rising edge delay unit in an embodiment of the present invention.

[0012] Figure 3 This is an internal circuit diagram of the delay calibration counter in an embodiment of the present invention.

[0013] Figure 4 The delay step size Δ in this embodiment of the invention t Schematic diagram.

[0014] Figure 5 This is a schematic diagram of the delay calibration principle in an embodiment of the present invention.

[0015] Figure 6 This is a timing diagram for delay calibration in an embodiment of the present invention (n=3).

[0016] Figure 7 This is a timing diagram of bidirectional delay in an embodiment of the present invention. Detailed Implementation

[0017] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings.

[0018] The top-level topology of the square wave delay circuit proposed in this invention is as follows: Figure 1 As shown, the square wave signal requiring delay is input from the left IN terminal, and INB is the inverted signal of the input signal. The delayed square wave signal is output from the right OUT terminal. The top-level circuit consists of an adjustable rising edge delay unit, a delay calibration counter, and a rising edge delay multiplexing unit. The following is a detailed explanation of the system workflow and the principles of the sub-modules.

[0019] First, the system performs delay calibration. During calibration, the input pulse of the adjustable rising edge delay unit is the reference clock CLK_REF, which is generated by a crystal oscillator and has high accuracy and stability. VREF is configured in the maximum delay state, that is, the DAC input Bit_0<7:0> is configured as all 1s. The calibration timing is as follows: Figure 6 As shown, when the delay calibration is completed within half a cycle of CLK_REF, the OK signal output is 1. At this point, the system's maximum configurable delay time is calibrated to half of the reference clock cycle. The system switches the square wave to be delayed as the input, delays the rising and falling edges of the square wave, and finally outputs OUT. The timing is as follows. Figure 7 As shown.

[0020] The working principle of the entire system will be explained in detail below by describing the specific working principles of the system sub-modules.

[0021] Adjustable rising edge delay unit: Figure 2 This is the internal circuit diagram of the adjustable rising edge delay module. The pulse is input from the CIN terminal, I0 is the external pull-down bias current, and the current mirror composed of PM0 and PM1 replicates the current I0. When CIN is high, PM2 is turned on and NM0 is turned off. At this time, the current I0 charges the capacitor array, and the capacitor voltage rises linearly. When the capacitor voltage reaches the switching voltage VREF of the output stage comparator, the COUT terminal outputs high, thus achieving the delay of the rising edge. REF The voltage is generated by an external 8-bit DAC. The DAC input signal is Bit_0<7:0>, and the total delay can be set by adjusting Bit_0<7:0>. When CIN is low, PM2 is off and NM0 is on. Since there is no current limit to the discharge, the capacitor discharges rapidly, and the COUT output is low, so there is almost no delay for the falling edge. The capacitor array consists of C <n:0>Composition, parameter: C <1> =2C <0> C <2> =2C <1> C <3> =2C <2> , ......, C <n> ＝2C <n-1> 。M <n:0>The control signal for selecting the switching transistor for the capacitor is Bit_1. <n:0>The total capacitance can be configured. This programmable capacitor array is designed to work with a delay calibration counter to generate different delay step values. The specific delay calculation process is as follows:

[0022] Delay step size Δ t Delay step size Δ t like Figure 4 The figure shows the delay change corresponding to the smallest bit change in the DAC input Bit_0<7:0>. The relationship between the voltage difference and current across the capacitor array is known to be: V CAP Given the voltage difference across the capacitor array, we get t represents time, when V CAP =VREF comparator toggles, by have to Where Δ VREF Where LSB is the DAC voltage, and C is the total capacitance actually connected.

[0023] Total delay td: The total delay can be set by configuring the input bits 0<7:0> of the 8-bit DAC. Total delay td = t0 + nΔ t (n is the decimal representation of Bit_0<7:0>, and t0 is the system delay). It can be seen that the total delay is linearly related to the input Bit_0<7:0>.

[0024] Delay calibration counter: Figure 3 This is the internal schematic diagram of the delay calibration counter. Figure 6 This is a timing diagram of the calibration process. (DFF trigger) <n:0>An n-bit binary counter is constructed. DFF_4 and DFF_5 form a 2-bit shift register, whose output is connected to an XNOR gate XNOR_0. Its function is to detect whether calibration is complete; if calibration is complete (OK), it is 1; otherwise, it is 0. The specific working principle of this module is as follows: the CLK_REF signal, after passing through a rising edge delay unit, outputs a Cali_pulse signal. When calibration is incomplete, the rising edge of this signal triggers the n-bit binary counter to count, and the counter outputs Bit_1. <n:0>This signal controls the switching on and off of the capacitor array inside the rising edge delay unit. As the count increases, the total capacitance of the capacitor array increases, and the delay step value also increases accordingly, corresponding to an increase in the maximum delay. Figure 5 As shown, V CAP The slope of the voltage rise decreases as the total connected capacitance increases, and the charging time to VREF also increases linearly. When the total delay increases to half a cycle of the CLK_REF signal, the charging and discharging times of the capacitor array coincide, the Cali_pulse pulse disappears, the counter stops counting, and the counter output stops changing. The Q output of the shift register composed of DFF_4 and DFF_5 has consistent data after the rising edges of the two CLK_REF signals, and the output of the XNOR_0 gate is set to 1, thus determining that the calibration is complete.

[0025] Rising edge delay multiplexing unit: Figure 1 The input data selector and narrow pulse sampling output unit constitute the rising edge delay multiplexing unit. Figure 7 For timing purposes, this unit's function is to solve the problem of maintaining strict consistency between the rising and falling edge delays of a square wave. The input square wave signal IN and its inverted signal INB are connected from... Figure 1 The leftmost input is connected to the input data selector. The control signal of the data selector is OUTB, which is the inverted signal of the final output waveform. Assuming that OUT is 0 at the beginning, OUTB is 1, which selects the IN signal. After the system calibration is completed, TG0 and TG1 are turned on, and TG2 and TG3 are turned off. The input square wave signal IN is sent to the rising edge delay multiplexing unit via net1. The output is sent to the clock input of flip-flop DFF_0 via the transmission gate TG1 and net2. The data input D of the flip-flop is connected to VDD. When the net2 signal has a rising edge, the net3 output is high. QB is delayed after passing through the inverter chain (a 5-stage inverter chain is used here) and then DFF_0 is reset. net3 is pulled low, and finally a narrow pulse is generated. This narrow pulse signal is connected to the clock input of DFF_1 via net3. The data input D of DFF_1 is connected to the input square wave signal IN. The DFF_1 flip-flop samples the input square wave IN on the rising edge of a narrow pulse, outputting OUT. When OUT is 1 and OUTB = 0, the rising edge of the input square wave is delayed. At this time, OUTB controls the input data selector to switch INB to the input. The same steps are used to delay the falling edge of the input square wave IN. Since the rising edge delay and falling edge delay follow the exact same signal path, changes in the circuit's PVT will have the same effect on both the rising and falling edge delays. Therefore, the system maintains strict consistency between the rising and falling edge delays.

[0026] The above description is only a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. Any equivalent modifications or changes made by those skilled in the art based on the content disclosed in the present invention should be included within the scope of protection set forth in the claims. < / n-1> < / n>

Claims

1. An adjustable square wave delay circuit with a self-calibration structure, characterized in that: The circuit includes an adjustable rising edge delay unit, a delay calibration counter, and a rising edge delay multiplexing unit. The rising edge delay multiplexing unit includes a data selector and a narrow pulse sampling output unit. The adjustable rising edge delay unit is connected to the data selector, which serves as the input terminal of the entire circuit. The adjustable rising edge delay unit, the delay calibration counter, and the narrow pulse sampling output unit are interconnected, with the narrow pulse sampling output unit serving as the output terminal of the entire circuit. The square wave signal is input from the IN terminal of the data selector, the inverted square wave signal is input from the INB terminal of the data selector, and the delayed square wave signal is output from the OUT terminal of the narrow pulse sampling output unit. In the adjustable rising edge delay unit, the pulse is input from the CIN terminal, I0 is the external pull-down bias current, and the current mirror composed of PMOS transistors PM0 and PM1 replicates the current I0. When CIN is high, PM2 is turned on and NMOS transistor NM0 is turned off. At this time, the current I0 charges the capacitor array, and the capacitor voltage rises linearly. When the capacitor voltage reaches the switching voltage VREF of the output stage comparator, the COUT terminal outputs high, thus delaying the rising edge. The VREF voltage is generated by an external 8-bit DAC, and the DAC input signal is Bit_0<7:0>. The total delay is set by adjusting Bit_0<7:0>. When CIN is low, PM2 is turned off and NM0 is turned on, the capacitor discharges rapidly, and the COUT output is low, with no delay for the falling edge. In a delay calibration counter, flip-flop DFF <n:0> An n-bit binary counter is formed, where DFF_4 and DFF_5 form a 2-bit shift register, and its output is connected to an XNOR gate XNOR_0. Its function is to detect whether the calibration is complete. If the calibration is complete, it is 1, otherwise it is 0. In the delay calibration counter, the CLK_REF signal is output as the Cali_pulse signal after passing through the rising edge delay unit. When calibration is not complete, the rising edge of this signal will trigger an n-bit binary counter to count, and the counter output signal is Bit_1. <n:0> This signal controls the on / off state of the capacitor array inside the rising edge delay unit. As the count increases, the total capacitance of the capacitor array increases accordingly, and the delay step value also increases, corresponding to an increase in the maximum delay. The slope of the V-CAP voltage rise decreases as the total connected capacitance increases, and the time to charge to VREF also increases linearly. When the total delay increases to half a cycle of the CLK_REF signal, the charging and discharging times of the capacitor array coincide, the Cali_pulse pulse disappears, the counter stops counting, and the output of the counter stops changing. The Q terminal of the shift register composed of DFF_4 and DFF_5 has consistent data after two rising edges of CLK_REF, and the output of the XNOR_0 gate is ok, which is 1, realizing the judgment that the calibration is completed.

2. The adjustable square wave delay circuit with self-calibration structure according to claim 1, characterized in that: The capacitor array consists of capacitor C <n:0>and capacitor-selective switching transistor M <n:0>Composition, of which C <1> =2C <0> C <2> =2C <1> C <3> =2C <2> , ......, C <n> =2C <n-1>Capacitor-selective switch M <n:0>The corresponding control signal is Bit_1 <n:0> This allows for the configuration of the total connected capacitor size; the function of the capacitor array is to generate different delay step values ​​in conjunction with the delay calibration counter. < / n> 3. The adjustable square wave delay circuit with self-calibration structure according to claim 2, characterized in that: The specific calculation process for the delay of the capacitor array is as follows: The delay step size is defined as the delay amount corresponding to the smallest bit change in the DAC input Bit_0<7:0>. The relationship between the voltage difference and current across the capacitor array is given by the following formula: , Given the voltage difference across the capacitor array, we get t represents time. The time comparator flips, by have to ,in This is the LSB voltage of the DAC. This refers to the total capacitance actually connected. The total delay is set by configuring the input bits 0<7:0> of the 8-bit DAC. The total delay td = , This is the decimal representation of Bit_0<7:0>. The system delay is linearly related to the input Bit_0<7:0>.

4. The adjustable square wave delay circuit with self-calibration structure according to claim 1, characterized in that: The rising edge delay multiplexing unit is used to keep the rising and falling edge delays of the square wave consistent. The input square wave signal IN and the inverted signal INB of the input square wave are input to the input data selector. The control signal of the data selector is OUTB, which is the inverted signal of the final output waveform OUT of the narrow pulse sampling output unit.

5. The adjustable square wave delay circuit with self-calibration structure according to claim 4, characterized in that: In the rising edge delay multiplexing unit, OUT is initially 0, then OUTB is 1, strobing the IN signal. After calibration, transmission gates TG0 and TG1 are open, while TG2 and TG3 are closed. The input square wave signal IN passes through the data selector and TG0 to obtain the net1 signal, which is then sent to the rising edge delay multiplexing unit. The output passes through transmission gate TG1 to obtain the net2 signal, which is sent to the clock input of flip-flop DFF_0. The data input D of this flip-flop is connected to VDD. When the net2 signal has a rising edge, the Q output of flip-flop DFF_0 is high, and the QB output is... After a delay following the inverter chain, DFF_0 is reset, the net3 signal is pulled low, and a narrow pulse is generated. This narrow pulse signal is connected to the clock input of DFF_1, and the data input D of DFF_1 is connected to the input square wave signal IN. The DFF_1 flip-flop samples the input square wave IN on the rising edge of the narrow pulse and outputs OUT. When OUT is 1 and OUTB=0, the delay of the rising edge of the input square wave is completed. At this time, OUTB controls the input data selector to switch INB to the input. The same steps are used to delay the falling edge of the input square wave IN.

Images