A production test method based on digital ATE tester

Abstract

The present application relates to the technical field of ATE tester mass production testing, in particular to a kind of mass production testing method based on digital ATE tester, comprising: according to the test requirement of chip, final ATE tester model confirmation is carried out by test cost analysis, FPGA is initialized;The SYNC frame chip is confirmed by the interface of FPGA, the Serdes signal output by chip is decoded and PRBS test, FPGA feedback ATE pass / fail signal;After test, the data of ADC is collected using FPGA and the ADC data is converted, ATE and FPGA are handshake interaction, the collection of the SNR parameter value of ADC is completed, ATE is compared by limiting value setting to the parameter value received, to output the test data of this parameter and judge whether it is in chip parameter index range, finally feedback FPGA test completion signal, FPGA returns to initialization waiting state.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of ATE mass production testing, in particular to a mass production testing method based on a digital ATE tester. BACKGROUND

[0002] At present, Serdes technology is widely used in high-speed communication systems, and Serdes chips emerge as the times require. With the continuous improvement of China's technology, people's requirements for integrated circuit manufacturing level and chip operating speed are also getting higher and higher. However, due to the rapid development of chip scale, the chip testing time has become longer and longer. In the production process, not only the quality of the chip needs to be ensured, but also the cost of the chip needs to be controlled. Therefore, for mass production of a high-speed integrated Serdes chip, the problem of high-cost testing is faced. For example, for a chip integrating 12.5Gbps rate Serdes and high-speed ADC, a general ATE tester cannot meet its testing requirements, and a high-speed hybrid circuit ATE tester needs to be selected, which requires the use of relatively expensive high-speed digital board cards and high-speed hybrid signal test board cards, thereby increasing the testing cost. How to realize all the tests required for the chip under the premise of ensuring the testing accuracy and stability and reduce the hardware cost of the ATE itself and the testing cost of the chip has become a difficulty in the prior art.

[0003] Therefore, people need a mass production testing method based on a digital ATE tester to solve the above problems. SUMMARY

[0004] The present application aims to provide a mass production testing method based on a digital ATE tester to solve the problems raised in the background art.

[0005] In order to solve the above technical problems, the present application provides the following technical scheme: a mass production testing method based on a digital ATE tester, comprising the following steps:

[0006] Z1: determining the model of the ATE tester according to the testing requirements of the chip and initializing the FPGA chip;

[0007] Z2: confirming the SYNC frame chip through the interface of the FPGA, decoding the Serdes signal output by the SYNC frame chip and performing PRBS testing;

[0008] Z3: after the testing is passed, collecting the ADC data by using the FPGA and converting the ADC data, performing handshake interaction between the ATE and the FPGA, feeding back the FPGA testing completion signal to the FPGA, and returning the FPGA to the initialization waiting state.

[0009] Further, in step Z1 : the number of digital channels, digital rate, vector depth, power supply capability and peripheral circuit required test resource information are determined for the OS, Scan, Mbist, Function and DC / AC test requirements of the chip, all ATE testers that meet the test requirements are analyzed and compared for production unit price and hardware manufacturing cost of test board and changekit, the model of low-cost ATE tester is selected, a test board is integrated with an FPGA, an HMC7044 chip, an external signal source and a power supply to complete the interconnection of hardware, the FPGA is powered during the entire production test process and is continuously powered, and the FPGA is initialized after power-on.

[0010] Further, in step Z2: the FPGA is in an idle state after initialization, if the PLL of the HMC7044 is in a lock state, the FPGA enters a waiting start test state, when the ATE provides a start test signal to the FPGA output, the FPGA performs internal configuration on the SPI, the FPGA is used as a master device and the chip under test is used as a slave device, SPI read-write operation is performed according to the internal setting of the chip, if the SPI read-write is successful, the Serdes sync signal is started to be tested, and if the SPI read-write fails, a fail bit is fed back to the ATE.

[0011] Further, if the SPI read and write are successful, the HMC7044 chip provides a clock signal required for Serdes testing, and a SYNC frame chip is confirmed through a JESD204B interface of the FPGA. The Serdes signal output by the SYNC frame chip is a pair of high-speed serial differential signals. The SYNC frame chip uses 8b / 10b encoding Serdes technology to first convert parallel data into 10b code streams through an 8b / 10b encoder at the sending end, and then converts the new code streams into high-speed serial signals through a serializer for transmission on a high-speed differential signal line. After receiving the high-speed differential signal, the FPGA first deserializes it into 10b code streams and then decodes it through an 8b / 10b decoder to obtain the original code stream data, thereby completing data transmission. Serdes technology is a device that converts parallel data into serial data for transmission and converts received serial data into parallel data. Serdes technology needs to be implemented in digital-analog hardware and is used for high-speed transmission of advanced serial-parallel conversion devices. Serdes technology can reduce wiring conflicts, that is, when data is serial and there is no separate clock line, the clock is embedded in the data stream, thereby also solving the problem of signal clock offset limiting data transmission rate. In addition, Serdes technology has strong anti-noise and anti-interference ability, reduces switching noise, has strong expansion capability, has lower power consumption and packaging cost; the line coding mechanism converts input original data into a format that can be received by the receiver while ensuring that there is enough clock information in the data stream to provide the clock recovery circuit of the receiving end. The line coding technology provides a method for aligning data to bytes / words, can maintain good direct current balance, increases the transmission distance of data, provides a more effective error detection mechanism, and 8B / 10B encoding is the output transmission encoding standard. In order to ensure direct current balance and sufficient dense level conversion, it is widely used in high-speed serial buses. 8B / 10B encoding takes bytes as the unit, maps data into 10-bit width data, so that the number of 1 and 0 in the encoded binary data stream is basically consistent, while ensuring byte synchronization and easy implementation.

[0012] Further, for the PRBS test, the DFT technology is introduced. First, a built-in self-test module is used to send PRBS, which is verified after conversion by the internal circuit, so as to achieve the purpose of self-test of the chip. The SYNC frame chip enters the inner loop mode and shields all parallel input ports, output ports and transmit-receive ports. The internally running PRBS code stream will not pass through the transmit-receive module. The multiplexing state port output level state of the FPGA is output, and the PRBS verification comparison result is used. If the PRBS verification comparison result is pass, it indicates that the port output high level SYNC frame signal is stable, and then the ADC data is collected. If the PRBS verification comparison result is fail, it indicates that the port output is low level, and the SYNC frame signal is unstable, and then the fail bit is fed back to the ATE. PRBS refers to a pseudo-random sequence containing only 0 and 1. The pseudo-random code PRBS is used for testing the high-speed serial channel, mainly for testing the error code rate. The error code rate is an index for measuring the accuracy of data transmission in a specified time. For a digital communication system, the smaller the error code rate, the higher the reliability. Fourier transform is a basic operation in digital signal processing, and is widely used in the field of expressing and analyzing discrete time domain signals. Discrete Fourier transform technology is the Fourier analysis method, which is the most basic method of signal analysis. Fourier transform is the core of Fourier analysis. Through it, the signal is transformed from the time domain to the frequency domain, and then the frequency spectrum structure and change law of the signal are studied. The signal can be converted from the time sequence space to the frequency domain, and the signal is analyzed from the frequency point of view to find the hidden frequency in the time domain.

[0013] Further, in step Z3: the SYNC frame signal is stable, the FPGA collects the ADC data and performs collection, and if the signal level state of the multiplexing state port output of the FPGA is high, it indicates that the ADC data collection is successful, and then the FFT transform is performed on the ADC; if the signal level state of the output of the multiplexing state port of the FPGA is low, it indicates that the ADC data collection fails, and then the fail bit is fed back to the ATE.

[0014] Further, if the ADC data is successfully collected, the HMC provides a reference signal for the ADC, the ADC samples the reference signal under the control of the sampling clock and converts the ADC data using FFT, sets the correct frequency range, judges whether the frequency value of the converted data is within the correct frequency range, if the frequency value is within the correct frequency range, SNR calculation is performed on the ADC; if the frequency value is not within the correct frequency range, a fail bit is fed back to the ATE; FFT is an algorithm for computing the discrete Fourier transform or its inverse transform of a digital signal sequence, FFT is a high-efficiency fast algorithm of DFT, since the operation amount of DFT is proportional to the square of the number of transform points, when the number of transform points is larger than the operation amount, it is not practical to directly apply DFT algorithm for spectral transformation, so FFT is used to convert the ADC data, which reduces the calculation amount and improves the operation speed.

[0015] Further, if the frequency value is within the correct range, the FPGA collects the data converted by FFT, and calculates SNR through the following formula:

[0016]

[0017] wherein, P s represents the power of the signal, P n represents the power of the noise, and the FPGA outputs the SNR value to the ATE tester; SNR refers to the ratio between the useful signal and the noise signal, the higher the signal-to-noise ratio of the device, the less noise it produces, in general, the larger the signal-to-noise ratio, the smaller the noise mixed in the signal, the higher the sound quality of the sound playback, otherwise the opposite.

[0018] Further, the ATE and the FPGA perform handshake interaction to collect the SNR parameter value of the ADC, set the parameter limit value, the ATE compares the collected parameter value with the parameter limit value to judge whether the parameter value is within the chip parameter range, if the parameter value is within the chip parameter range, the test results of the function test pass or fail and the SNR parameter are captured; if the parameter value is not within the chip parameter range, a fail bit is fed back to the ATE; the test results of the function test pass or fail and the SNR parameter captured by the ATE are converted into digital signals and output to the measurement datalog, after the ATE test is completed, a test completion signal is fed back to the FPGA, the FPGA returns to the initialization waiting state, thereby waiting for the test of the subsequent chip; the FPAG is suitable for high-speed sampling rate, high data rate and high-speed sampling frequency, especially in the case of fixed or repeated tasks and trial production, system development, the FPGA mainly pre-processes high-speed data, can reduce the speed of data, realize complex algorithms, the logic inside the FPGA can be changed according to the demand, and the development cost is reduced.

[0019] Compared with the prior art, the present application has the advantages of:

[0020] The ATE in the present application has the test function of general digital circuit, cooperates with the clock signal provided by the power supply and signal source on the external LoadBoard board, selects the model of the low-cost ATE tester according to the analysis and comparison between test costs, initializes the FPGA, configures the SPI internally after the ATE output starts the test signal, decodes the Serdes signal and performs PRBS test after the SPI configuration is successful, collects the ADC data by the FGPA, converts the ADC data by FFT and judges whether the frequency value of the converted data is in the correct range, calculates the SNR of the ADC, feeds back the FPGA test completion signal after the ATE test is completed, and the FPGA returns to the initialization waiting state, so as to wait for the test of the subsequent chip; not only realizes the parallel test requirement of the integrated Serdes and high-speed ADC chip, but also effectively reduces the test cost of mass production. BRIEF DESCRIPTION OF DRAWINGS

[0021] The accompanying drawings are included to provide a further understanding of the present application, and constitute a part of the specification, illustrate the present application together with the embodiments thereof, and explain the present application, and do not constitute a limitation of the present application. In the drawings:

[0022] Figure 1 is a flow chart of a mass production test method based on a digital ATE tester of the present application;

[0023] Figure 2 is a FPGA test flow control chart of the mass production test based on the digital ATE tester of the present application;

[0024] Figure 3 is a test hardware structure chart of the mass production test based on the digital ATE tester of the present application;

[0025] Figure 4 is a test structure chart of the mass production test based on the digital ATE tester of the present application. DETAILED DESCRIPTION

[0026] The preferred embodiments of the present application are described below in conjunction with the accompanying drawings, and it should be understood that the preferred embodiments described herein are only used to illustrate and explain the present application, and do not limit the present application.

[0027] The preferred embodiments of the present application are described below in conjunction with the accompanying drawings, and it should be understood that the preferred embodiments described herein are only used to illustrate and explain the present application, and do not limit the present application. Figures 1-4 The present application is further described below in conjunction with the preferred embodiments.

[0028] Embodiment one:

[0029] As Figure 1As shown, the embodiment provides a mass production test method based on a digital ATE tester, which is based on the mass production test implementation in the embodiment and includes the following steps:

[0030] Z1: As Figure 2 and Figure 3 As shown, the test resource information required by the digital channel number, digital rate, vector depth, power supply capacity and peripheral circuit for the OS, Scan, Mbist, Function and DC / AC of the chip is determined, the mass production unit price of the ATE tester and the hardware manufacturing cost of the test board and changekit are analyzed and compared, the model of the low-cost ATE tester is selected, an FPGA, an HMC7044 chip, an external signal source and a power supply are integrated on the test board to complete the interconnection of the hardware, the FPGA is used for power supply during the whole mass production test process and the power supply is uninterrupted throughout the process, and the FPGA is initialized after power-on.

[0031] Z2: As Figure 4 shown, two sites are used for testing at the same time, the FPGA mainly includes state ctrl, spidriver, JESD204B, 7044driver, CFG table and preprocess; state ctrl refers to a state control module, spi driver refers to an spi driver module, JESD204B refers to a JESD204B control and data analysis module, 7044driver refers to an HMC7044 spi driver module, CFG table refers to a configuration table, and preprocess refers to a preprocessing module; after the FPGA is initialized, it is in an idle state, if the PLL of the HMC7044 is in a lock state, the FPGA enters a waiting start test state, when the ATE provides a test signal output by the FPGA to start, the FPGA performs internal configuration on the SPI, the SPI refers to a serial peripheral interface, the internal SPI register of the chip under test is used, the FPGA is used as a master device and the chip under test is used as a slave device, SPI read-write operation is performed according to the internal setting of the chip, if the SPI read-write is successful, the Serdes sync signal starts to be tested; if the SPI read-write fails, a fail bit is fed back to the ATE;

[0032] If the SPI read and write are successful, the HMC7044 chip provides the clock signal required for Serdes test, and the SYNC frame chip is confirmed through the JESD204B interface of the FPGA. The Serdes signal output by the SYNC frame chip is a pair of high-speed serial differential signals. The SYNC frame chip uses 8b / 10b encoding Serdes technology to convert parallel data into 10b code stream at the sending end through an 8b / 10b encoder, and then converts the new code stream into a high-speed serial signal for transmission on a high-speed differential signal line. After receiving the high-speed differential signal, the FPGA first deserializes it into a 10b code stream and then decodes it through an 8b / 10b decoder to obtain the original code stream data, thereby completing data transmission. Serdes technology is a device that converts parallel data into serial data for transmission and converts received serial data into parallel data. Serdes technology requires digital-to-analog hardware implementation and is used for high-speed transmission of advanced serial-to-parallel conversion devices. The line coding mechanism converts the input original data into a format that can be received by the receiver while ensuring that there is enough clock information in the data stream to provide the clock recovery circuit at the receiving end. 8B / 10B encoding is the output transmission encoding standard, which is widely used in high-speed serial buses. 8B / 10B encoding uses bytes as units to map data into 10-bit width data, so that the number of 1s and 0s in the encoded binary data stream remains basically consistent.

[0033] For PRBS test, DFT technology is introduced. First, a built-in self-test module is used to send PRBS, which is verified after being converted by internal circuit, so as to achieve the purpose of self-test of the chip. The SYNC frame chip enters the inner loop mode and shields all parallel input ports, output ports and transmit-receive ports. The internally running PRBS code stream will not pass through the transmit-receive module. The level state of the multiplexing state port of the FPGA is output. The PRBS verification comparison result is used. If the PRBS verification comparison result is pass, it indicates that the port outputs high-level SYNC frame signal stably, and then the ADC data is collected. If the PRBS verification comparison result is fail, it indicates that the port outputs low-level, and the SYNC frame signal is unstable, and then fail bit is fed back to ATE. PRBS refers to a pseudo-random sequence containing only 0 and 1. PRBS is used for testing high-speed serial channels. The main purpose is to test the error rate. The error rate is an index for measuring the accuracy of data transmission within a specified time. For a digital communication system, the smaller the error rate is, the higher the reliability is. Fourier transform is a basic operation in digital signal processing, which is widely used in the field of expressing and analyzing discrete time domain signals. Discrete Fourier transform technology is the most basic method of signal analysis. Fourier transform is the core of Fourier analysis. Through it, the signal is transformed from time domain to frequency domain, and then the frequency spectrum structure and variation law of the signal are studied. The signal can be converted from time sequence space to frequency domain. From the perspective of frequency, the hidden frequency in time domain is found.

[0034] Z3: The SYNC frame signal is stable, the FPGA collects ADC data and performs collection, if the signal level state output by the multiplexing state port of the FPGA is high, it indicates that the ADC data collection is successful, then the FFT transform is performed on the ADC; if the signal level state output by the multiplexing state port of the FPGA is low, it indicates that the ADC data collection fails, then fail bit is fed back to ATE;

[0035] If the ADC data collection is successful, HMC7044 provides a reference signal for the ADC. The ADC samples the reference signal under the control of the sampling clock and converts the ADC data using FFT. The frequency correct range is set. It is judged whether the frequency value of the converted data is within the frequency correct range. If the frequency value is within the frequency correct range, SNR calculation is performed on the ADC. If the frequency value is not within the frequency correct range, fail bit is fed back to ATE.

[0036] If the frequency value is within the correct range, the FPGA collects the data after FFT conversion, and calculates SNR through the following formula:

[0037]

[0038] wherein, P s represents the power of the signal, P n represents the power of the noise, the FPGA outputs the SNR value to the ATE tester; the SNR refers to the ratio between the useful signal and the noise signal, wherein the useful signal refers to the output signal voltage under the specified input voltage, and the noise signal refers to the residual noise voltage of the output when the input voltage is cut off; the higher the signal-to-noise ratio of the device indicates that the device produces less noise; in general, the greater the signal-to-noise ratio, the smaller the noise mixed in the signal, the higher the sound quality of the sound playback, otherwise the opposite;

[0039] The ATE and the FPGA perform handshake interaction to complete collection of the SNR parameter value of the ADC, set a parameter limit value, the ATE compares the collected parameter value with the parameter limit value to determine whether the parameter value is within the chip parameter range, if the parameter value is within the chip parameter range, the test result of the SNR parameter and the pass or fail of the function test are captured; if the parameter value is not within the chip parameter range, a fail bit is fed back to the ATE; the test result of the SNR parameter and the pass or fail of the function test captured by the ATE are converted into a digital signal and output to the measurement datalog, after the ATE test is completed, a test completion signal is fed back to the FPGA, the FPGA returns to an initialization waiting state, thereby waiting for the test of the subsequent chip; the handshake interaction is that after the FPGA outputs one period of data, a signal is sent to the ATE to prompt that the SNR test data can be captured, after the ATE captures the period of data, a signal is fed back to the FPGA, the FPGA outputs the next period of data to the ATE, thereby completing the capture of the data.

[0040] Finally, it should be noted that: the above only for the preferred examples of the present application, and not for limiting the present application, although the present application is described in detail with reference to the foregoing examples, for those skilled in the art, it still can modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for volume production testing based on a digital ATE tester, characterized by: The method comprises the following steps: Z1: determining the model of the ATE tester according to the test requirements of the chip and initializing the FPGA chip; Z2: confirming the SYNC frame chip through the interface of the FPGA, decoding the Serdes signal output by the SYNC frame chip and performing PRBS test; Z3: after the test is passed, collecting the ADC data by using the FPGA and converting the ADC data, the ATE and the FPGA perform handshake interaction, feedback is given to the FPGA test completion signal, and the FPGA returns to the initialization waiting state; the ATE and the FPGA perform handshake interaction, feedback is given to the FPGA test completion signal, and the FPGA returns to the initialization waiting state, specifically, the ATE and the FPGA perform handshake interaction to complete the collection of the SNR parameter value of the ADC, the parameter limit value is set, the ATE compares the collected parameter value with the parameter limit value to determine whether the parameter value is within the chip parameter range, if the parameter value is within the chip parameter range, the test results of the function test pass or fail and the SNR parameter are captured; if the parameter value is not within the chip parameter range, a fail bit is fed back to the ATE; the test results of the function test pass or fail and the SNR parameter captured by the ATE are converted into digital signals and output to the measurement datalog, after the ATE test is completed, the FPGA test completion signal is fed back, and the FPGA returns to the initialization waiting state, thereby waiting for the test of subsequent chips.

2. The volume production test method based on a digital ATE tester according to claim 1, characterized in that: In step Z1: the test resource information required by the digital channel number, the digital rate, the vector depth, the power supply capacity and the peripheral circuit is determined according to the test requirements of the OS, Scan, Mbist, Function and DC / AC of the chip, the production unit price of all ATE testers meeting the test requirements and the hardware manufacturing cost of the test board and changekit are analyzed and compared, the model of the low-cost ATE tester is selected, an FPGA, an HMC chip, an external signal source and a power supply are integrated on the test board to complete the interconnection of hardware, the FPGA is powered during the entire production test process and is continuously powered, and the FPGA is initialized after power-on.

3. The method of claim 2, wherein: the test program is executed by the digital ATE tester. In step Z2: after the FPGA is initialized, the FPGA is in an idle state, if the PLL of the HMC is in a lock state, the FPGA enters a waiting start test state, when the ATE provides a test signal output to the FPGA to start, the FPGA performs internal configuration on the SPI, the FPGA is used as a master device and the chip under test is used as a slave device, SPI read-write operation is performed according to the internal setting of the chip, if the SPI read-write operation is successful, the Serdes sync signal is tested; if the SPI read-write operation fails, a fail bit is fed back to the ATE.

4. The volume production test method based on a digital ATE tester according to claim 3, characterized by: SPI read-write success, HMC chip provides Serdes test required clock signal, through the interface of FPGA to confirm SYNC frame chip, SYNC frame chip uses encoding Serdes technology in the sending end first through the encoder to convert parallel data into new code stream, and then uses the serializer to convert the new code stream into high-speed serial signal on the high-speed differential signal line, FPGA receives high-speed differential signal, first deserializes the new code stream and then decodes through the decoder to obtain the original code stream data to complete the transmission of data.

5. The method of claim 4, wherein: Using DFT technology to test PRBS, first through a built-in self-test module, send PRBS in its after internal circuit conversion to verify comparison, SYNC frame chip into the inner ring mode and shield all parallel input port, output port and send and receive port, internal running PRBS code stream will not pass through the send and receive module, through the multiplexing state port output level state, using PRBS verification comparison result, if the PRBS verification comparison result is pass, then collect ADC data; if the PRBS verification comparison result is fail, then feedback fail bit to ATE.

6. The volume production test method based on a digital ATE tester according to claim 5, characterized by: In step Z3: SYNC frame signal is stable, FPGA collects ADC data and collects, if the signal level state of the multiplexing state port output of FPGA is high, indicating that the ADC data collection is successful, then do FFT transform to ADC; if the signal level state of the multiplexing state port output of FPGA is low, indicating that the ADC data collection fails, then feedback fail bit to ATE.

7. The method of claim 6, wherein: the test program is executed by the digital ATE tester. If the ADC data collection is successful, HMC provides reference signal for ADC, ADC samples the reference signal under the control of sampling clock and uses FFT to convert ADC data, sets the correct frequency range, judges whether the frequency value of the converted data is in the correct frequency range, if the frequency value is in the correct frequency range, then calculates SNR of ADC; if the frequency value is not in the correct frequency range, then feedback fail bit to ATE.

8. The volume production test method based on a digital ATE tester according to claim 7, characterized by: If the frequency value is in the correct range, FPGA collects the data after FFT conversion, calculates SNR through the following formula: ； wherein, represents the power of the signal, represents the power of the noise, the FPGA outputs the SNR value to the ATE tester.

Images