High dynamic range tof pixel structure and driving method

Abstract

The application discloses a kind of high dynamic range TOF pixel structure and driving method, including two readout links, and the structure of two readout links is symmetrically distributed about photodiode, each readout link includes respectively: first transfer transistor source electrode connects photodiode negative pole, grid electrode TG1 signal, drain electrode connects FD node;Gain selection transistor source electrode connects FD node, grid electrode DCG signal, drain electrode connects gain expansion capacitor and reset transistor source electrode;Reset transistor source electrode connects gain selection transistor drain electrode, grid electrode RST signal, drain electrode connects VDD signal;Third transfer transistor source electrode connects PD negative pole, grid electrode TG3 signal, drain electrode connects gain expansion capacitor;First source follower transistor grid electrode connects FD node, source electrode connects power transistor drain electrode, drain electrode connects VDD signal;Power transistor drain electrode connects the source electrode of first source follower transistor, grid electrode PC signal, source electrode connects external current source;Using global shutter working mode, and combining high gain and low gain two gain modes, high dynamic range imaging of TOF image sensor can be realized.

Description

Technical Field

[0001] This invention relates to a 3D image sensor integrated circuit, and more particularly to a high dynamic range TOF pixel structure and driving method. Background Technology

[0002] 3D image sensors, capable of acquiring depth information of target objects, are core components of machine vision. Time-of-Flight (ToF) image sensors calculate the distance to the target object by measuring the time required for modulated light to travel between the object and the sensor. TOF image sensors offer advantages such as low power consumption and low cost, and are widely used in consumer electronics, industrial manufacturing, automotive, and security monitoring.

[0003] In environments where target object distance information is complex, high dynamic range (HDR) Time-of-Flight (TOF) image sensors are needed. HDR TOF image sensors often employ a fusion of high-gain and low-gain imaging signals. However, in low-gain mode, the photodiode collects more electrons, resulting in lower transmission efficiency. This leads to increased errors in the imaging distance information for TOF operation. Therefore, this invention is proposed. Summary of the Invention

[0004] The purpose of this invention is to provide a high dynamic range TOF pixel structure and driving method to solve the above-mentioned technical problems existing in the prior art.

[0005] The objective of this invention is achieved through the following technical solution:

[0006] The high dynamic range TOF pixel structure of the present invention includes two readout links, and the structures of the two readout links are symmetrically distributed about the photodiode PD. Each readout link includes:

[0007] The source of the first transmission transistor is connected to the negative terminal of the photodiode PD, the gate is connected to the TG1 signal, and the drain is connected to the FD node.

[0008] The source of the gain selection transistor is connected to the FD node, the gate is connected to the DCG signal, and the drain is connected to the gain extension capacitor Chdr and the source of the reset transistor.

[0009] The source of the reset transistor is connected to the drain of the gain selection transistor, the gate is connected to the RST signal, and the drain is connected to the VDD signal.

[0010] The source of the third transmission transistor TG3 is connected to the negative terminal of PD, the gate is connected to the TG3 signal, and the drain is connected to Chdr.

[0011] The gate of the first source follower transistor is connected to the FD node, the source is connected to the drain of the power supply transistor, and the drain is connected to the VDD signal.

[0012] The power transistor drain is connected to the source of the first source follower transistor, the gate is connected to the PC signal, and the source is connected to an external current source;

[0013] The first switch transistor source is connected to the source of the first source follower transistor, the gate is connected to the S1 signal, and the drain is connected to the capacitor C1 and the source of the second switch transistor;

[0014] The second switch transistor gate is connected to the S2 signal, and the drain is connected to the capacitor C2 and the gate of the second source follower transistor;

[0015] The second source follower transistor drain is connected to the VDD signal, and the source is connected to the source of the row selection transistor;

[0016] The row selection transistor gate is connected to the SEL signal, and the drain is connected to the first readout link column output signal line.

[0017] The driving method of the high dynamic range TOF pixel structure includes a high gain mode working time sequence and a low gain mode working time sequence.

[0018] Compared with the prior art, the high dynamic range TOF pixel structure and the driving method provided by the application have the advantages of high dynamic range and high transmission efficiency, and can realize high dynamic range imaging of a TOF image sensor by adopting a global shutter working mode and combining two gain modes. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 The high dynamic range TOF pixel structure provided by the embodiment of the application is shown in the figure;

[0020] Figure 2 The high gain mode working time sequence of the embodiment of the application is shown in the figure;

[0021] Figure 3 The low gain mode working time sequence of the embodiment of the application is shown in the figure;

[0022] In the figure, the letter codes are conventional codes in the art, and the corresponding Chinese names are as follows:

[0023] Name Chinese name PD photodiode FD ]]> ​ floating diffusion node Chdr ]]> ​ gain expansion capacitor Light modulated light signal PC current source strobe signal RST reset signal DCG gain selection signal TG1 first transfer signal TG2 second transfer signal TG3 third transfer signal TG4 fourth transfer signal S1 first switch signal S2 second switch signal SEL row select signal VDD power signal C1 signal storage capacitor 1 C2 signal storage capacitor 2 DETAILED DESCRIPTION

[0024] Clearly, the embodiments described are only a part of all the embodiments of the present application, and do not constitute a limitation of the present application. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts are within the scope of the present application.

[0025] First, the terms that can be used in the present application are described as follows:

[0026] The term "and / or" means either one or both, for example, X and / or Y means three cases including "X", "Y" or "X and Y".

[0027] The terms "include", "contain", "have", "possess" or other similar semantic descriptions should be interpreted as non-exclusive inclusion. For example, including a technical feature element (such as raw materials, components, ingredients, carriers, dosage forms, materials, sizes, parts, components, mechanisms, devices, steps, processes, methods, reaction conditions, processing conditions, parameters, algorithms, signals, data, products or articles, etc.) should be interpreted as not only including the explicitly listed technical feature element, but also including other technical feature elements not explicitly listed in the art.

[0028] The term "consisting of" means excluding any technical feature element not explicitly listed. If this term is used in the claims, the term will make the claim closed, so that it does not contain technical feature elements other than the explicitly listed technical feature elements, except for conventional impurities related thereto. If the term only appears in a certain clause of the claim, it is only limited to the elements explicitly listed in that clause, and the elements described in other clauses are not excluded from the overall claim.

[0029] Unless otherwise specifically provided or limited, the terms "mount", "connect", "connect", "fix", and the like should be broadly understood, for example: can be fixedly connected, can also be detachably connected, or integrally connected; can be mechanically connected, can also be electrically connected; can be directly connected, can also be indirectly connected through an intermediate medium, can be internal communication of two elements. For those of ordinary skill in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0030] The terms "central", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like indicate the orientation or positional relationship shown in the drawings, which are only for the convenience of description and simplification of description, and do not mean that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting herein.

[0031] The contents not described in detail in the embodiments of the present application belong to the prior art known to those skilled in the art. If the specific conditions are not indicated in the embodiments of the present application, the conventional conditions or the conditions recommended by the manufacturer are used. If the reagents or instruments used in the embodiments of the present application are not indicated by the manufacturer, they are all conventional products that can be purchased on the market.

[0032] The high dynamic range TOF pixel structure of the present application includes two readout links, and the structures of the two readout links are symmetrically distributed about the photodiode PD, each readout link comprising:

[0033] The source electrode of the first transfer transistor is connected to the negative electrode of the photodiode PD, the gate electrode is connected to the TG1 signal, and the drain electrode is connected to the FD node;

[0034] The source electrode of the gain selection transistor is connected to the FD node, the gate electrode is connected to the DCG signal, and the drain electrode is connected to the gain expansion capacitor Chdr and the source electrode of the reset transistor;

[0035] The source electrode of the gain selection transistor is connected to the FD node, the gate electrode is connected to the DCG signal, and the drain electrode is connected to the gain expansion capacitor Chdr and the source electrode of the reset transistor;

[0036] The source electrode of the gain selection transistor is connected to the FD node, the gate electrode is connected to the DCG signal, and the drain electrode is connected to the gain expansion capacitor Chdr and the source electrode of the reset transistor;

[0037] The source electrode of the gain selection transistor is connected to the FD node, the gate electrode is connected to the DCG signal, and the drain electrode is connected to the gain expansion capacitor Chdr and the source electrode of the reset transistor;

[0038] The source electrode of the gain selection transistor is connected to the FD node, the gate electrode is connected to the DCG signal, and the drain electrode is connected to the gain expansion capacitor Chdr and the source electrode of the reset transistor;

[0039] The source electrode of the gain selection transistor is connected to the FD node, the gate electrode is connected to the DCG signal, and the drain electrode is connected to the gain expansion capacitor Chdr and the source electrode of the reset transistor;

[0040] The source electrode of the gain selection transistor is connected to the FD node, the gate electrode is connected to the DCG signal, and the drain electrode is connected to the gain expansion capacitor Chdr and the source electrode of the reset transistor;

[0041] The source electrode of the gain selection transistor is connected to the FD node, the gate electrode is connected to the DCG signal, and the drain electrode is connected to the gain expansion capacitor Chdr and the source electrode of the reset transistor;

[0042] The row selection transistor has a gate connected to the SEL signal and a drain connected to the first readout link column output signal line.

[0043] The driving method of the high dynamic range TOF pixel structure includes a high gain mode working sequence and a low gain mode working sequence.

[0044] The high gain mode working sequence includes:

[0045] A reset phase:

[0046] The modulated light source is turned off, the PC signal is at a low level, the RST signal, the DCG signal, the TG1 signal and the TG2 signal are at a high level, and the PD and the FD nodes are reset;

[0047] Then, the S1 and S2 signals are pulled up to a high level, the capacitors C1 and C2 are reset, and the TG1 and TG2 are lowered to a low level;

[0048] Then, the DCG and RST signals are lowered to a low level, the PC signal is pulled up to a high level, and the S2 signal is lowered to a low level, at which time the reset signal is stored in the S2;

[0049] An exposure phase:

[0050] The modulated light source is turned on, the TG1 and TG2 signals remain the same frequency as the modulated light to turn on and off, the TG1 on signal remains the same phase as the modulated light high signal, and the TG2 on signal remains the opposite phase as the modulated light high signal;

[0051] A readout phase:

[0052] The S1 signal is first lowered to a low level, the SEL signal is pulled up to a high level, then the PC signal is lowered to a low level, and the RST and DCG signals are pulled up to a high level;

[0053] First, the reset voltage in the capacitor C2 is sampled, and the voltage is denoted as Vrsth;

[0054] Then, the S2 signal pulse is turned on, and the signal voltage in the C2 is sampled, and the voltage is denoted as Vsigh;

[0055] In the high gain model working, the TG3 and TG4 signals remain at a low level;

[0056] According to the signal conservation law, the voltage signals accumulated and read out by the first link and the second link are respectively:

[0057]

[0058] The low gain mode working sequence includes:

[0059] The DCG signal is kept high;

[0060] Reset stage:

[0061] The modulated light source is turned off, the PC signal is at low level, the RST signal, the TG1 signal and the TG2 signal are at high level, and the PD and the FD node are reset;

[0062] Then, the S1 and S2 signals are pulled up to high level, the capacitors C1 and C2 are reset, and the TG1 and TG2 are lowered to low level;

[0063] Then, the RST signal is lowered to low level, the PC signal is pulled up to high level, and the S2 signal is lowered to low level, at this time, the reset signal is stored in S2;

[0064] Exposure stage:

[0065] The modulated light source is turned on, the TG1, TG2, TG3 and TG4 signals remain the same frequency as the modulated light to turn on and off, the TG1 and TG3 on signals remain the same phase as the modulated light high signal, and the TG2 and TG4 on signals remain opposite phase as the modulated light high signal;

[0066] Readout stage:

[0067] The S1 signal is first lowered to low level, the SEL signal is pulled up to high level, then the PC signal is lowered to low level, and the RST and DCG signals are pulled up to high level;

[0068] First, the reset voltage in the capacitor C2 is sampled, and the voltage is recorded as Vrstl;

[0069] Then, the S2 signal pulse is turned on, and the signal voltage in C2 is sampled, and the voltage is recorded as Vsigl;

[0070] According to the signal conservation law, the accumulated readout voltage signals of the first link and the second link are respectively:

[0071]

[0072] In the imaging signal synthesis, the first link output is fused into a signal V1 by V1h and V1l, and the second link output is fused into a signal V2 by V2h and V2l, to realize high dynamic range imaging of a TOF image sensor;

[0073] If the modulated light signal period is T, the calculation of the modulated light flight time is:

[0074]

[0075] The target object distance information is calculated as:

[0076]

[0077] wherein c is the speed of light.

[0078] In summary, the high dynamic range TOF pixel structure and driving method of the embodiment of the present application can realize high dynamic range imaging of the TOF image sensor by the structural design, the global shutter working mode, and the combination of the two gain modes in cooperation with the corresponding driving timing control scheme.

[0079] In order to more clearly show the technical solutions provided by the present application and the technical effects generated, the present application is described in detail below with specific embodiments.

[0080] Embodiment 1

[0081] A high dynamic range TOF pixel structure, the basic circuit structure is as shown in Figure 1 :

[0082] The pixel has two readout links, and the structures of the two readout links are symmetrically distributed. Taking the first readout link as an example for description. The source electrode of the first transfer transistor is connected to the negative electrode of the photodiode PD, the gate electrode is connected to the TG1 signal, and the drain electrode is connected to the FD node; the source electrode of the gain selection transistor is connected to the FD node, the gate electrode is connected to the DCG signal, and the drain electrode is connected to the gain expansion capacitor Chdr and the source electrode of the reset transistor; the source electrode of the reset transistor is connected to the drain electrode of the gain selection transistor, the gate electrode is connected to the RST signal, and the drain electrode is connected to the VDD signal; the source electrode of the third transfer transistor TG3 is connected to the negative electrode of the PD, the gate electrode is connected to the TG3 signal, and the drain electrode is connected to the Chdr; the gate electrode of the first source follower transistor is connected to the FD node, the source electrode is connected to the drain electrode of the power transistor, and the drain electrode is connected to the VDD signal; the drain electrode of the power transistor is connected to the source electrode of the first source follower transistor, the gate electrode is connected to the PC signal, and the source electrode is connected to the external current source; the source electrode of the first switch transistor is connected to the source electrode of the first source follower transistor, the gate electrode is connected to the S1 signal, and the drain electrode is connected to the capacitor C1 and the source electrode of the second switch transistor; the gate electrode of the second switch transistor is connected to the S2 signal, and the drain electrode is connected to the capacitor C2 and the gate electrode of the second source follower transistor; the drain electrode of the second source follower transistor is connected to the VDD signal, and the source electrode is connected to the source electrode of the row selection transistor; the gate electrode of the row selection transistor is connected to the SEL signal, and the drain electrode is connected to the column output signal line of the first readout link. The structure of the second readout link is symmetrically distributed with the first readout link with respect to the PD.

[0083] Figure 2 and Figure 3 are the high gain mode and low gain mode working timing of the TOF image sensor pixel of the present application, respectively.

[0084] When the pixel works in the high gain mode (as shown in Figure 2as shown): In the reset stage, the modulated light source is off, the PC signal is at low level, the RST signal, the DCG signal, the TG1 signal and the TG2 signal are at high level, and the PD and the FD nodes are reset. Then the S1 and S2 signals are pulled up to high level, the capacitors C1 and C2 are reset, and the TG1 and TG2 are lowered to low level. Then the DCG and RST signals are lowered to low level, the PC signal is pulled up to high level, and the S2 signal is lowered to low level, at which time the reset signal is stored in the S2. In the exposure stage, the modulated light source is on, the TG1 and TG2 signals are kept on and off at the same frequency as the modulated light, the TG1 on signal is kept at the same phase as the modulated light high signal, and the TG2 on signal is kept at the opposite phase as the modulated light high signal. In the readout stage, the S1 signal is first lowered to low level, the SEL signal is pulled up to high level, then the PC signal is lowered to low level, and the RST and DCG signals are pulled up to high level. First, the reset voltage in the capacitor C2 is sampled, and the voltage is recorded as Vrsth. Then the S2 signal is pulsed on, and the signal voltage in the C2 is sampled, and the voltage is recorded as Vsigh. In the high-gain model operation, the TG3 and TG4 signals are kept at low level. According to the signal conservation law, the accumulated readout voltage signals of the first link and the second link are respectively:

[0085]

[0086] When the pixel works in the low-gain mode (as shown): Figure 3 The DCG signal is kept at high level. In the reset stage, the modulated light source is off, the PC signal is at low level, the RST signal and the TG1 signal and the TG2 signal are at high level, and the PD and the FD nodes are reset. Then the S1 and S2 signals are pulled up to high level, the capacitors C1 and C2 are reset, and the TG1 and TG2 are lowered to low level. Then the RST signal is lowered to low level, the PC signal is pulled up to high level, and the S2 signal is lowered to low level, at which time the reset signal is stored in the S2. In the exposure stage, the modulated light source is on, the TG1, TG2, TG3 and TG4 signals are kept on and off at the same frequency as the modulated light, the TG1 and TG3 on signals are kept at the same phase as the modulated light high signal, and the TG2 and TG4 on signals are kept at the opposite phase as the modulated light high signal. In the readout stage, the S1 signal is first lowered to low level, the SEL signal is pulled up to high level, then the PC signal is lowered to low level, and the RST and DCG signals are pulled up to high level. First, the reset voltage in the capacitor C2 is sampled, and the voltage is recorded as Vrstl. Then the S2 signal is pulsed on, and the signal voltage in the C2 is sampled, and the voltage is recorded as Vsigl. According to the signal conservation law, the accumulated readout voltage signals of the first link and the second link are respectively:

[0087]

[0088] Generally, more integral electrons can be accommodated in a pixel under low gain condition. The TOF pixel structure of the present application can improve the charge transfer efficiency of the pixel under low gain condition while realizing different gain mode outputs. Finally, in the imaging signal synthesis, the first link output is fused by V1h and V1l into signal V1, the second link output is fused by V2h and V2l into signal V2, and high dynamic range imaging of the TOF image sensor is realized. If the period of the modulated light signal is T, the flight time of the modulated light can be calculated as:

[0089]

[0090] The target object distance information is calculated as:

[0091]

[0092] Where c is the speed of light.

[0093] The above merely provides the preferred embodiment of the present application, but the protection scope of the present application is not limited to this. Any change or replacement within the technical range disclosed by the present application can be easily thought by those skilled in the art, and should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims. The information disclosed in the background section of the present application is merely intended to deepen the understanding of the general background of the present application, and should not be regarded as acknowledging or implying in any form that the information constitutes the prior art known by those skilled in the art.

Claims

1. A driving method of a high dynamic range TOF pixel structure, characterized in that: the high dynamic range TOF pixel structure comprises two readout chains, and the structures of the two readout chains are symmetrically distributed about a photodiode PD, each readout chain comprising: a first transfer transistor having a source electrode connected to a negative electrode of the photodiode PD, a gate electrode connected to a TG1 signal, and a drain electrode connected to an FD node; a gain selection transistor having a source electrode connected to the FD node, a gate electrode connected to a DCG signal, and a drain electrode connected to a gain expansion capacitor Chdr and a reset transistor source electrode; the reset transistor having a source electrode connected to a drain electrode of the gain selection transistor, a gate electrode connected to an RST signal, and a drain electrode connected to a VDD signal; a third transfer transistor TG3 having a source electrode connected to the negative electrode of the PD, a gate electrode connected to a TG3 signal, and a drain electrode connected to the Chdr; a first source follower transistor having a gate electrode connected to the FD node, a source electrode connected to a drain electrode of a power supply transistor, and a drain electrode connected to the VDD signal; the power supply transistor having a source electrode connected to the source electrode of the first source follower transistor, a gate electrode connected to a PC signal, and a source electrode connected to an external current source; a first switch transistor having a source electrode connected to the source electrode of the first source follower transistor, a gate electrode connected to an S1 signal, and a drain electrode connected to a capacitor C1 and a source electrode of a second switch transistor; the second switch transistor having a gate electrode connected to an S2 signal, a drain electrode connected to a capacitor C2, and a gate electrode connected to a second source follower transistor; the second source follower transistor having a drain electrode connected to the VDD signal, and a source electrode connected to a source electrode of a row selection transistor; the row selection transistor having a gate electrode connected to an SEL signal, and a drain electrode connected to a first readout chain column output signal line; the driving method comprises a high gain mode working sequence and a low gain mode working sequence; the high gain mode working sequence comprises: a reset phase: a modulated light source is turned off, the PC signal is at a low level, the RST signal, the DCG signal, the TG1 signal, and the TG2 signal are at a high level, and the PD and the FD node are reset; then the S1 and S2 signals are pulled up to a high level, the capacitors C1 and C2 are reset, and the TG1 and TG2 are lowered to a low level; then the DCG and RST signals are lowered to a low level, the PC signal is pulled up to a high level, and the S2 signal is lowered to a low level, at which time a reset signal is stored in the S2; an exposure phase: the modulated light source is turned on, the TG1 and TG2 signals are kept on and off at the same frequency as the modulated light, the TG1 on signal is kept at the same phase as the modulated light high signal, and the TG2 on signal is kept at the opposite phase of the modulated light high signal; a readout phase: the S1 signal is first lowered to a low level, the SEL signal is pulled up to a high level, then the PC signal is lowered to a low level, and the RST and DCG signals are pulled up to a high level; first, the reset voltage in the capacitor C2 is sampled, and the voltage is recorded as Vrsth; then the S2 signal is pulsed on, and the signal voltage in the C2 is sampled, and the voltage is recorded as Vsigh; in the high gain model working, the TG3 and TG4 signals remain at a low level; according to the signal conservation law, the voltage signals accumulated and read out by the first and second chains are respectively: the low gain mode working sequence comprises: the DCG signal is kept at a high level; a reset phase: ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The modulated light source is turned off, the PC signal is at low level, the RST signal, the TG1 signal and the TG2 signal are at high level, and the PD and the FD node are reset; Then the S1 and S2 signals are pulled up to high level, the capacitors C1 and C2 are reset, and the TG1 and TG2 are lowered to low level; Then, the RST signal is lowered to low level, the PC signal is pulled up to high level, and the S2 signal is lowered to low level, at this time, the reset signal is stored in S2; Exposure stage: The modulated light source is turned on, the TG1, TG2, TG3 and TG4 signals remain the same frequency as the modulated light to turn on and off, the TG1 and TG3 on signals remain the same phase as the modulated light high signal, and the TG2 and TG4 on signals remain opposite phase as the modulated light high signal; Readout stage: The S1 signal is first lowered to low level, the SEL signal is pulled up to high level, then the PC signal is lowered to low level, and the RST and DCG signals are pulled up to high level; First, the reset voltage in the capacitor C2 is sampled, and the voltage is recorded as Vrstl; Then the S2 signal pulse is turned on, and the signal voltage in C2 is sampled, and the voltage is recorded as Vsigl; According to the signal conservation law, the accumulated readout voltage signals of the first link and the second link are respectively:

2. The driving method of the high dynamic range TOF pixel structure according to claim 1, characterized in that, When the imaging signal is synthesized, the first link output is fused by V1h and V1l as signal V1, the second link output is fused by V2h and V2l as signal V2, and high dynamic range imaging of the TOF image sensor is realized; If the modulated light signal period is T, then the calculation of the modulated light flight time is: The target object distance information is calculated as: Where c is the speed of light.

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