Semiconductor structure and method of manufacturing the same

Abstract

The application provides a semiconductor structure and a preparation method thereof, and relates to the technical field of semiconductors. The preparation method of the semiconductor structure comprises the following steps: providing a substrate with a bit line contact region; and forming a first conductive layer and a second conductive layer in the bit line contact region. The first conductive layer and the second conductive layer are formed through two deposition processes, respectively, and the concentration of the doped impurities in the first conductive layer is less than that in the second conductive layer. Since the lower the concentration of the doped impurities, the higher the filling capacity, the formation of a gap can be avoided when the first conductive layer is formed. In addition, the first conductive layer has a small aspect ratio when surrounding the contact hole in the bit line contact region. When the second conductive layer is formed, the formation of a gap in the second conductive layer can be avoided. Thus, when the bit line and the isolation side wall are subsequently formed, the isolation side wall will not be damaged, and thus the electrical connection between the capacitor contact structure and the bit line will not occur, thereby improving the yield of the semiconductor structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] Dynamic random access memory (DRAM) is a semiconductor memory that allows for high-speed, random writing and reading of data and is widely used in data storage devices or apparatuses.

[0003] Dynamic random access memory (DRAM) typically includes multiple repeating storage cells. Each storage cell includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line through a bit line contact structure, and the drain is electrically connected to the capacitor through a capacitive contact. The word line voltage on the word line can control the transistor to turn on and off, so that data information stored in the capacitor can be read or written to the capacitor through the bit line.

[0004] However, when forming the bit line contact structure, gaps are easily formed within the bit line contact structure. These gaps can cause electrical connections between the capacitor contact structure and the bit line, thereby reducing the yield of the semiconductor structure. Summary of the Invention

[0005] In view of the above problems, this application provides a semiconductor structure and its fabrication method to prevent the formation of gaps in the bit line contact structure, thereby preventing electrical connection between the capacitor contact structure and the bit line and improving the yield of the semiconductor structure.

[0006] To achieve the above objectives, the embodiments of this application provide the following technical solutions:

[0007] A first aspect of this application provides a method for fabricating a semiconductor structure, which includes the following steps:

[0008] A substrate is provided, wherein the substrate has a plurality of spaced bit line contact areas;

[0009] A first conductive layer is formed in each bit line contact area, and the first conductive layer forms a contact hole in each bit line contact area;

[0010] A second conductive layer is formed in each of the contact holes, the second conductive layer and the first conductive layer constitute a conductive layer, wherein the concentration of doped impurities in the second conductive layer is greater than the concentration of doped impurities in the first conductive layer.

[0011] In some embodiments, the concentration of doped impurities in the second conductive layer is 1.5 to 3 times the concentration of doped impurities in the first conductive layer.

[0012] In some embodiments, the step of forming a first conductive layer in the bit line contact region includes:

[0013] A first initial conductive layer is formed in each bit line contact region, and the first initial conductive layer forms a central hole in each bit line contact region.

[0014] Etching gas is introduced into the intermediate hole to remove part of the first initial conductive layer. The remaining first initial conductive layer constitutes the first conductive layer, and the first conductive layer forms a contact hole in the bit line contact area.

[0015] In some embodiments, the longitudinal section is a cross section perpendicular to the substrate, and the longitudinal section shape of the contact hole is a trapezoid with a larger top and a smaller bottom.

[0016] In some embodiments, the longitudinal section is a cross section perpendicular to the substrate, and the longitudinal section shape of the contact hole is V-shaped.

[0017] In some embodiments, the angle between the sidewall of the contact hole and the direction perpendicular to the substrate is between 10° and 20°.

[0018] In some embodiments, the thickness of the first conductive layer along the first direction is between 0 and 6 nm.

[0019] In some embodiments, the thickness of the first conductive layer on the bottom wall of the bit line contact area is between 5 and 8 nm.

[0020] In some embodiments, the thickness of the first initial conductive layer along the first direction is between 5 and 18 nm.

[0021] In some embodiments, the thickness of the first initial conductive layer on the bottom wall of the bit line contact region is between 10 and 18 nm.

[0022] In some embodiments, both the first conductive layer and the second conductive layer are made of polycrystalline silicon, and the doped impurities are all phosphorus ions.

[0023] In some embodiments, prior to the step of forming the first conductive layer within the bit line contact region, the fabrication method further includes:

[0024] A protective layer is formed on the sidewall of the bit line contact area.

[0025] In some embodiments, the thickness of the protective layer is between 3 and 6 nm, and the material of the protective layer includes polycrystalline silicon.

[0026] In some embodiments, the etching gas includes chlorine gas, and the etching temperature is between 250°C and 320°C.

[0027] A second aspect of this application provides a semiconductor structure, which is prepared by the semiconductor structure preparation method described in the above embodiments.

[0028] In the semiconductor structure and its fabrication method provided in this application embodiment, a first conductive layer and a second conductive layer are formed through two deposition processes, and the concentration of doped impurities in the first conductive layer is less than that in the second conductive layer. Since the lower the concentration of doped impurities, the higher the filling capacity, gaps can be avoided when forming the first conductive layer. Secondly, the contact hole formed in the bit line contact area of ​​the first conductive layer has a small aspect ratio, which can also avoid the formation of gaps in the second conductive layer when forming the second conductive layer, thereby avoiding the formation of gaps in the conductive layer. In this way, the isolation sidewalls will not be damaged when the bit line structure and isolation sidewalls are formed subsequently, and the capacitor contact structure will not be electrically connected to the bit line, thus improving the yield of the semiconductor structure.

[0029] In addition to the technical problems solved by the embodiments of this application, the technical features constituting the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the semiconductor structure and its preparation method provided by the embodiments of this application, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further explained in detail in the specific implementation. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 A schematic diagram of the semiconductor structure provided in the related technology. Figure 1 ;

[0032] Figure 2 A schematic diagram of the semiconductor structure provided in the related technology. Figure 2 ;

[0033] Figure 3 A process flow diagram of the method for fabricating the semiconductor structure provided in the embodiments of this application;

[0034] Figure 4 This is a schematic diagram of the structure forming the bit line contact region in the semiconductor structure fabrication method provided in the embodiments of this application;

[0035] Figure 5This is a schematic diagram of the structure forming the protective layer in the method for preparing the semiconductor structure provided in the embodiments of this application;

[0036] Figure 6 This is a schematic diagram of the structure forming the first initial conductive layer in the method for preparing the semiconductor structure provided in the embodiments of this application;

[0037] Figure 7 This is a schematic diagram of the structure for forming contact holes in the semiconductor structure fabrication method provided in the embodiments of this application. Figure 1 ;

[0038] Figure 8 This is a schematic diagram of the structure for forming contact holes in the semiconductor structure fabrication method provided in the embodiments of this application. Figure 2 ;

[0039] Figure 9 Schematic diagram of the formation of the second conductive layer in the semiconductor structure fabrication method provided in this application embodiment. Figure 1

[0040] Figure 10 Schematic diagram of the formation of the second conductive layer in the semiconductor structure fabrication method provided in this application embodiment. Figure 2 .

[0041] Figure label:

[0042] 10: Substrate; 11: Active region;

[0043] 12: Isolation structure; 13: Bit line contact area;

[0044] 20: Conductive layer; 21: First conductive layer;

[0045] 22: Second conductive layer; 23: First initial conductive layer;

[0046] 24: Center hole; 25: Contact hole;

[0047] 30: Mask layer; 40: Protective layer. Detailed Implementation

[0048] In the fabrication process of semiconductor structures, bit line structures and isolation sidewalls covering the bit line structures are usually formed first. The bit line structure includes stacked bit line contact structures and bit lines. After the bit line structure and isolation sidewalls are formed, capacitive contact structures are formed between adjacent isolation sidewalls. The capacitive contact structures are used to connect the active region of the capacitor and the substrate to realize data storage.

[0049] like Figure 1 and Figure 2As shown, when forming the bit line contact structure, a bit line contact area is first formed in the substrate 10, and then a conductive layer 20 is formed in the bit line contact area. However, since the bit line contact area has a large aspect ratio, gaps will be formed in the conductive layer 20. When etching the conductive layer 20 to form the bit line contact structure, the gaps will be exposed, causing some areas of the bit line contact structure to break. Consequently, when forming the isolation sidewall, the insulating material used to form the isolation sidewall will fill the gaps, causing the isolation sidewall to break at the gaps and not completely cover the bit line. Correspondingly, when forming the capacitor contact structure later, the capacitor contact structure is prone to electrical connection with the bit line structure, reducing the yield of the semiconductor structure.

[0050] To address the aforementioned technical problems, in this embodiment, a first conductive layer and a second conductive layer are formed through two deposition processes. The concentration of doped impurities in the first conductive layer is lower than that in the second conductive layer. Since a lower concentration of doped impurities results in higher filling capacity, gaps can be avoided when forming the first conductive layer. Furthermore, the first conductive layer forms a contact hole within the bit line contact area. This contact hole has a small aspect ratio, which also prevents gaps from forming in the second conductive layer, thus avoiding gaps within the conductive layer. Consequently, the isolation sidewalls will not be damaged during the subsequent formation of the bit line structure and isolation sidewalls, preventing electrical connection between the capacitor contact structure and the bit line, thereby improving the yield of the semiconductor structure.

[0051] To make the above-mentioned objectives, features, and advantages of the embodiments of this application more apparent and understandable, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0052] Figure 3 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this application. Figures 4 to 10 The diagram below illustrates the various stages of semiconductor structure fabrication. Figures 4 to 10 The methods for fabricating semiconductor structures are described in detail.

[0053] This embodiment does not limit the semiconductor structure. The following description will take dynamic random access memory (DRAM) as an example, but this embodiment is not limited to this. Other semiconductor structures are also possible in this embodiment.

[0054] like Figure 3 As shown, the method for fabricating a semiconductor structure provided in this application includes the following steps:

[0055] Step S100: Provide a substrate having a plurality of spaced bit line contact areas.

[0056] For example, such as Figure 4 As shown, the substrate 10 serves as a support component for the dynamic random access memory, supporting other components disposed thereon. The substrate 10 may be made of a semiconductor material, which may be one or more of silicon, germanium, silicon-germanium compounds, and silicon-carbon compounds.

[0057] The substrate 10 has a plurality of active regions 11 and an isolation structure 12 for separating the various active regions 11, wherein the plurality of active regions 11 may be arranged at intervals, and the active regions 11 are used to house semiconductor devices, such as transistors and capacitors.

[0058] The fabrication process of the isolation structure 12 typically involves patterning the substrate 10 to form isolation trenches within the substrate 10, and then depositing silicon oxide within the isolation trenches using a deposition process to form the isolation structure 12. The isolation structure 12 is used to achieve insulation between the various active regions 11.

[0059] The substrate 10 has multiple bit line contact regions 13, which can be spaced apart on the substrate 10. When forming multiple bit line contact regions 13, a patterned mask layer 30 can be formed on the substrate 10. Then, using the mask layer 30 as a mask, a portion of the thickness of the substrate 10 is removed by etching gas or etching solution to form the bit line contact regions 13 in the substrate 10.

[0060] When forming the patterned mask layer 30, a photoresist layer of a certain thickness can be formed on the mask layer 30 by coating process. Then, a mask pattern is formed on the photoresist layer by exposure, etching and development process. Then, the mask layer 30 that is not covered by the mask pattern is removed by using etching solution or etching gas to form a pattern in the mask layer 30.

[0061] The mask layer 30 can be a single film layer or a composite film layer. For example, the mask layer 30 may include a silicon nitride layer, a polysilicon layer and a silicon oxide layer stacked sequentially. The silicon nitride layer is disposed on the substrate 10. In this embodiment, by making the mask layer 30 a composite film layer, the pattern can be transferred to the silicon oxide layer first during the pattern transfer process, and then transferred to the polysilicon layer, the silicon nitride layer and the substrate 10 in sequence. This can improve the accuracy of the pattern transfer process and ensure the accuracy of the pattern of the bit line contact area 13.

[0062] It should be noted that after the bit line contact area 13 is formed, a protective layer 40 can be formed in the bit line contact area 13, or a conductive layer 20 can be formed directly. The following embodiments are illustrated by taking the formation of a protective layer 40 in the bit line contact area 13 as an example.

[0063] For example, such as Figure 5 As shown, a protective layer 40 is formed on the sidewall of the bit line contact area 13. This protective layer 40 is used to protect the isolation structure 12 exposed within the bit line contact area 13, preventing damage to the isolation structure 12 during subsequent cleaning of the bit line contact area 13. The material of the protective layer 40 includes polycrystalline silicon.

[0064] In this embodiment, the thickness of the protective layer 40 is between 3 and 6 nm, such as Figure 5 As shown, along the X direction in the figure, the protective layer 40 has a certain thickness D1, which is between 3 and 6 nm.

[0065] If the thickness of the protective layer 40 is less than 3nm, it will result in the protective layer 40 being too thin, causing damage to the isolation structure 12 during the subsequent cleaning of the bit line contact area 13. If the thickness of the protective layer 40 is greater than 6nm, it will result in the area enclosed by the protective layer 40 being too small, increasing the aspect ratio of the area, resulting in gaps still existing in the bit line contact structure formed subsequently.

[0066] Therefore, this embodiment limits the thickness of the protective layer 40, which not only protects the isolation structure 12 but also prevents gaps in the subsequent bit line contact structure, thereby avoiding electrical connection between the capacitor contact structure and the bit line structure and improving the yield of the semiconductor structure.

[0067] Step S200: A first conductive layer is formed in each bit line contact area, and the first conductive layer forms a contact hole in each bit line contact area.

[0068] The first conductive layer 21 is formed by a deposition process, which may include at least one of physical vapor deposition, chemical vapor deposition, and atomic layer deposition.

[0069] Step S300: A second conductive layer is formed in each contact hole. The second conductive layer and the first conductive layer constitute a conductive layer, wherein the concentration of doped impurities in the second conductive layer is greater than the concentration of doped impurities in the first conductive layer. Figure 9 and Figure 10 As shown.

[0070] The second conductive layer 22 can also be formed by a deposition process, such as physical vapor deposition, chemical vapor deposition, and atomic layer deposition.

[0071] In this embodiment, the material of the first conductive layer 21 and the second conductive layer 22 is polycrystalline silicon, and the doping impurities are all phosphorus ions. The concentration of the doping impurities in the second conductive layer 22 is 1.5 to 3 times the concentration of the doping impurities in the first conductive layer 21.

[0072] For example, the concentration of doped impurities in the first conductive layer 21 is 1E20 to 10E20, that is, the concentration of doped impurities in the first conductive layer 21 is 1*10 20 ~10*10 20 The concentration of doped impurities in the second conductive layer 22 is 15E20~30E20, that is, the concentration of doped impurities in the second conductive layer 22 is 15*10. 20 ~30*10 20 .

[0073] Compared with related technologies where the conductive layer 20 is formed through a single deposition process, in this embodiment, the conductive layer 20 is formed through two deposition processes. Specifically, the first deposition process is used to form the first conductive layer 21, and the second deposition process is used to form the second conductive layer 22. The concentration of doped impurities in the first conductive layer 21 is lower than that in the second conductive layer 22. Since the lower the concentration of doped impurities, the higher the filling capacity, gaps can be avoided when forming the first conductive layer 21. Furthermore, a contact hole 25 is formed in the bit line contact area 13 of the first conductive layer 21. This contact hole 25 has a small aspect ratio, which also avoids gaps in the second conductive layer 22 when forming the second conductive layer 22, and thus avoids gaps in the conductive layer 20. This prevents damage to the isolation sidewalls when forming the bit line structure and isolation sidewalls, and prevents electrical connection between the capacitor contact structure and the bit line, thereby improving the yield of the semiconductor structure.

[0074] Furthermore, the higher concentration of doped impurities in the second conductive layer 22 can improve the conductivity of the second conductive layer 22, thereby improving the conductivity of the conductive layer 20 and enhancing the performance of the semiconductor structure.

[0075] In some embodiments, the process of forming a first conductive layer 21 in each bit line contact region 13 can be implemented in the following manner.

[0076] For example, such as Figure 6 As shown, a first initial conductive layer 23 is formed in each bit line contact area 13 using a deposition process. The first initial conductive layer 23 extends outside the bit line contact area 13 and covers the mask layer 30. The first initial conductive layer 23 forms a central hole 24 in each bit line contact area 13.

[0077] In this embodiment, the deposition process may include at least one of physical vapor deposition, chemical vapor deposition, and atomic layer deposition.

[0078] Along the first direction, the thickness of the first initial conductive layer 23 is between 5 and 18 nm, and the thickness of the first initial conductive layer 23 is as follows: Figure 6 If the thickness of the first initial conductive layer 23 is less than 5 nm, it is not conducive to the subsequent formation of the first conductive layer 21. If the thickness of the first initial conductive layer 23 is greater than 18 nm, the thickness of the first initial conductive layer 23 is too large, making it difficult to form the intermediate hole 24 and increasing the difficulty of the subsequent formation and removal of the first initial conductive layer 23. Therefore, in this embodiment, the thickness of the first initial conductive layer 23 is limited to between 5 and 18 nm, which can facilitate the formation of the first conductive layer 21 and reduce the difficulty of the preparation of the first conductive layer 21.

[0079] The first direction can be Figure 6 The X direction in the equation.

[0080] Secondly, the thickness of the first initial conductive layer 23 located on the bottom wall of the bit line contact region 13 is between 10 and 18 nm. Figure 6 The number D3 is indicated in the text.

[0081] If the thickness of the first initial conductive layer 23 on the bottom wall of the bit line contact area 13 is less than 10 nm, the thickness of the subsequently formed first conductive layer 21 in the direction perpendicular to the substrate 10 will be too small, resulting in a large depth of the contact hole 25. This will cause a void to be formed in the subsequently formed second conductive layer 22.

[0082] If the thickness of the first initial conductive layer 23 on the bottom wall of the bit line contact area 13 is greater than 18 nm, it will reduce the depth of the subsequently formed contact hole 25, resulting in a lower conductivity of the subsequently formed second conductive layer 22, and thus reducing the conductivity of the conductive layer 20.

[0083] Therefore, in this embodiment, the thickness of the first initial conductive layer 23 located on the bottom wall of the bit line contact region 13 is limited to between 10 and 18 nm. This can prevent the formation of voids in the second conductive layer 22 and improve the conductivity of the conductive layer 20, thereby improving the performance of the semiconductor structure.

[0084] like Figure 7 As shown, after the first initial conductive layer 23 is formed, etching gas is introduced into the intermediate hole 24. The etching gas can etch part of the first initial conductive layer 23. The retained first initial conductive layer 23 constitutes the first conductive layer 21, and the first conductive layer 21 forms a contact hole 25 in the bit line contact area.

[0085] The etching gas includes chlorine, and the etching temperature is between 250°C and 320°C. If the etching temperature is below 250°C, the etching rate will decrease, the etching time will increase, and the production cost will increase. If the etching temperature is above 320°C, the first initial conductive layer 23 will be over-etched, reducing the thickness of the first conductive layer 21. As a result, the contact hole 25 will still have a high aspect ratio. Therefore, this embodiment limits the etching temperature to reduce both production costs and the aspect ratio of the contact hole 25, and to prevent the formation of voids in the bit line contact structure.

[0086] In this embodiment, the shape of the contact hole 25 can be selected in various ways. For example, taking the cross-section perpendicular to the substrate 10 as the longitudinal section, the longitudinal section shape of the contact hole 25 is trapezoidal, and the trapezoid has a structure that is larger at the top and smaller at the bottom, as shown in the figure. Figure 7 As shown; for example, taking the section perpendicular to the base 10 as the longitudinal section, the longitudinal section shape of the contact hole 25 is V-shaped, and its structure is as follows. Figure 8 As shown, by defining the shape of the contact hole 25 in this embodiment, the subsequent deposition of the second conductive layer 22 can be facilitated, and voids can be prevented from forming in the second conductive layer 22.

[0087] In some embodiments, such as Figure 7 and Figure 8 As shown, the angle between the sidewall of the contact hole 25 and the direction perpendicular to the substrate 10 is between 10° and 20°, and the angle between the sidewall of the contact hole 25 and the Y direction is... Figure 7 and Figure 8 α in the middle.

[0088] If the angle between the sidewall of the contact hole 25 and the direction perpendicular to the substrate 10 is less than 10°, the top opening of the contact hole 25 will be too small, which will increase the difficulty of subsequent deposition of the second conductive layer 22 and will still cause voids to form in the second conductive layer 22.

[0089] If the angle between the sidewall of the contact hole 25 and the direction perpendicular to the substrate 10 is greater than 20°, the depth of the contact hole 25 will be too small, resulting in the thickness of the subsequently formed second conductive layer 22 being too small, reducing the conductivity of the second conductive layer 22, and consequently reducing the conductivity of the conductive layer 20 and the performance of the semiconductor structure.

[0090] Therefore, this embodiment limits the angle between the sidewall of the contact hole 25 and the direction perpendicular to the substrate 10, which can prevent the formation of voids in the second conductive layer 22 and increase the conductivity of the conductive layer 20.

[0091] In some embodiments, along the first direction, the thickness of the first conductive layer 21 is between 0 and 6 nm. Figure 7In the X direction, the thickness of the first conductive layer 21 is D4, and the thickness D4 of the first conductive layer 21 is between 0 and 6 nm. The thickness of the first conductive layer 21 can be uniform, that is, the thickness of the first conductive layer 21 can be equal everywhere along the direction perpendicular to the substrate 10; or the thickness of the first conductive layer 21 can be gradually varied along the direction perpendicular to the substrate 10, for example, as... Figure 7 As shown, the thickness of the first conductive layer 21 located at the top of the contact hole 25 can be 0 to 3 nm, and the thickness of the first conductive layer 21 located at the bottom of the contact hole 25 can be 3 to 6 nm.

[0092] This embodiment limits the thickness of the first conductive layer 21, which can prevent the formation of voids in the first conductive layer 21 and ensure the conductivity of the conductive layer 20, thereby improving the performance of the semiconductor structure.

[0093] In some embodiments, continue to refer to Figure 7 The thickness of the first conductive layer 21 located on the bottom wall of the bit line contact area 13 is between 5 and 8 nm.

[0094] Along the direction perpendicular to the substrate 10, the thickness D5 of the first conductive layer 21 is between 5 and 8 nm. If the thickness D5 of the first conductive layer 21 is less than 5 nm, the contact hole 25 will still have a depth-to-width ratio, which will cause gaps to easily form in the second conductive layer 22 when it is formed. This will cause the capacitor contact structure and bit line structure to be electrically connected in the subsequent formation, reducing the yield of the semiconductor structure.

[0095] If the thickness D5 of the first conductive layer 21 is greater than 8nm, the depth of the contact hole 25 will be too small, which will result in the thickness of the second conductive layer 22 being too small, reducing the conductivity of the second conductive layer 22, which in turn will reduce the conductivity of the conductive layer 20 and reduce the performance of the semiconductor structure.

[0096] Therefore, in this embodiment, the thickness of the first conductive layer 21 is limited along the direction perpendicular to the substrate 10. This can prevent the subsequent capacitor contact structure from being electrically connected to the bit line structure, thereby improving the yield of the semiconductor structure, and can also ensure the conductivity of the conductive layer 20, thereby improving the performance of the semiconductor structure.

[0097] The semiconductor structure provided in the second aspect of this application is obtained by the semiconductor structure preparation method in the above embodiments. Therefore, the bit line contact structure in the semiconductor structure in this embodiment includes a first conductive layer 21 and a second conductive layer 22 stacked together. The first conductive layer 21 and the second conductive layer 22 are dense structures without gaps. In this way, when bit lines and isolation sidewalls are formed subsequently, the isolation sidewalls will not be damaged, and the capacitor contact structure and the bit line structure will not be electrically connected, thereby improving the yield of the semiconductor structure.

[0098] In addition, the second conductive layer 22 has a high concentration of doped impurities, which ensures that there are no voids in the second conductive layer 22 while also improving the conductivity of the second conductive layer 22, thereby improving the conductivity of the bit line contact structure and improving the performance of the semiconductor structure.

[0099] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0100] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with an embodiment or example that are included in at least one embodiment or example of this application.

[0101] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.

[0102] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, Includes the following steps: A substrate is provided, wherein the substrate has a plurality of spaced bit line contact areas; A first conductive layer is formed in each bit line contact area, and the first conductive layer forms a contact hole in each bit line contact area; A second conductive layer is formed in each of the contact holes, the second conductive layer and the first conductive layer constitute a conductive layer, wherein the concentration of doped impurities in the second conductive layer is greater than the concentration of doped impurities in the first conductive layer; The step of forming the first conductive layer in the bit line contact region includes: A first initial conductive layer is formed in each bit line contact region, and the first initial conductive layer forms a central hole in each bit line contact region. Etching gas is introduced into the intermediate hole to remove part of the first initial conductive layer. The remaining first initial conductive layer constitutes the first conductive layer, and the first conductive layer forms a contact hole in the bit line contact area. Prior to the step of forming the first conductive layer within the bit line contact region, the fabrication method further includes: A protective layer is formed on the sidewall of the bit line contact area; Along the first direction, the thickness of the first initial conductive layer is between 5 and 18 nm; The thickness of the first initial conductive layer located on the bottom wall of the bit line contact area is between 10 and 18 nm.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The concentration of doped impurities in the second conductive layer is 1.5 to 3 times that of doped impurities in the first conductive layer.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that, The longitudinal section of the contact hole is a trapezoid with a larger top and a smaller bottom, with the cross section perpendicular to the base as the longitudinal section.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that, The longitudinal section of the contact hole is V-shaped, with the cross section perpendicular to the substrate as the longitudinal section.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that, The angle between the sidewall of the contact hole and the direction perpendicular to the substrate is between 10° and 20°.

6. The method for preparing a semiconductor structure according to any one of claims 1 to 4, characterized in that, Along the first direction, the thickness of the first conductive layer is between 0 and 6 nm.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that, The thickness of the first conductive layer located on the bottom wall of the bit line contact area is between 5 and 8 nm.

8. The method for preparing a semiconductor structure according to any one of claims 1 to 4, characterized in that, Both the first conductive layer and the second conductive layer are made of polycrystalline silicon, and the doped impurities are phosphorus ions.

9. The method for preparing a semiconductor structure according to claim 1, characterized in that, The thickness of the protective layer is between 3 and 6 nm, and the material of the protective layer includes polycrystalline silicon.

10. The method for preparing a semiconductor structure according to claim 1, characterized in that, The etching gas includes chlorine, and the etching temperature is 250-320°C.

11. A semiconductor structure, characterized in that, The semiconductor structure is prepared by the method according to any one of claims 1-10.

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