A wiring structure of an electronic paper pixel structure

Abstract

This invention provides a wiring structure for an electronic paper pixel structure, including a first gate and a second gate, as well as a first gate line and a second gate line. The first gate is connected to the first gate line, and the second gate is connected to the second gate line. The two gates in the pixel structure are controlled by two independent gate lines. During wiring, the first gate line in each row of pixels is connected to the independent signal line in a grouped collinear manner, which can reduce the number of wiring lines on the edge of the electronic paper product by at least half, thereby achieving the effect of narrowing the edge.

Description

Technical Field

[0001] This invention relates to the field of electronic paper, and more specifically, to a wiring structure for an electronic paper pixel structure. Background Technology

[0002] With the development of digital technology, more and more display devices are entering people's lives, such as electronic paper (EP). Electronic paper can maintain its display for a long time when the power is off, and has advantages such as being light, thin, low power consumption, and simple in manufacturing process, so it is becoming increasingly popular.

[0003] Electronic paper can be divided into color electronic paper and monochrome electronic paper. Its display principle is to use an electric field to drive color particles in microcapsules, so that the color particles are arranged in a specific way to display the desired font or pattern.

[0004] The electric field of electronic paper is typically provided by the pixel structure, which includes pixel electrodes and thin-film transistors (TFTs). In a typical electronic paper pixel structure, each pixel electrode is controlled by two series-connected TFTs to maintain its on / off state. This ensures that the voltage signal in the pixel electrode is maintained for a longer period even when power is off, allowing the electronic paper to retain the final display image for an extended period even when power is off.

[0005] Each pixel in an electronic paper display consists of a gate line and a source line. Each gate line connects to the IC gate output, and each source line connects to the IC source output. The pixel density is the resolution, a crucial indicator of electronic paper display performance. An 800×600 resolution product requires 800 gate lines and 600 source lines. Higher resolution requires more gate or source lines, resulting in a larger number of bezel traces, which severely impacts the electronic paper's appearance and hinders its ability to achieve narrow bezels.

[0006] Currently, the traditional electronic paper pixel structure is as follows: Figure 1 As shown, this is a dual-gate design, consisting of a first gate 1b and a second gate 1c. The two gates are connected by only one gate line 1. This pixel structure is disclosed in patent application CN201310386300.3, which discloses that gates 111 and 112 are both connected by a scan line 11. The wiring structure of an electronic paper product with the above pixel structure is shown in the attached figure. Figure 2 As shown, attached Figure 2The diagram shows the wiring of a product with the above pixel structure and a resolution of 800×600. This pixel structure places the gate lines of odd-numbered rows of pixels on the left (g1, g3, g5...) and the gate lines of even-numbered rows of pixels on the right (g2, g4, g6...). This means there are 400 gate lines on each side of the product. As people's requirements for image clarity are increasing, the resolution is also increasing. This directly leads to the need for larger and larger bezels on electronic paper with this pixel structure, which seriously affects the appearance of electronic paper. Especially in an era where people are pursuing full-screen electronic products, this is not conducive to the requirement of narrow bezels for electronic paper. Summary of the Invention

[0007] The problem solved by this invention is to provide a wiring structure for electronic paper pixel structure, which reduces the number of wirings on the edge of electronic paper products and narrows the edge.

[0008] To address the aforementioned issues, an electronic paper pixel structure wiring structure is proposed. The electronic paper has n rows of pixels, n first gate lines, and n second gate lines, where n ≥ 1. The n rows of pixels are distributed sequentially from top to bottom. The first gate of all pixels in each row is connected to one of the first gate lines, and the second gate of all pixels in each row is connected to one of the second gate lines. The electronic paper also includes several gate terminals and N independent signal lines, where N is an even number. Each gate terminal is individually connected to an IC via a lead-out line. The first gate lines are connected to one of the gate terminals or one of the lead-out lines. The N independent signal lines are evenly divided into M groups, and the n second gate lines are also divided into M groups, where M is an even number. When the n second gate lines cannot be evenly divided into M groups, one group of second gate lines has a certain number of more or fewer lines than the other groups. Each group of independent signal lines is collinearly connected to one of the groups of second gate lines. The independent signal lines are used to receive positive and negative voltages.

[0009] The beneficial effects of this invention are as follows: by grouping the second gate line with independent signal lines and allowing each group of independent signal lines to be collinearly connected to one of the second gate lines, the number of gate lines is greatly reduced compared to the traditional routing method where the number of gate lines corresponds to the number of rows of pixels. Since n may be odd or cannot be evenly divided into M groups, and since M is even, the number of second gate lines in one group may be several more or fewer than the number of second gate lines in the other groups. When the IC starts scanning each row of pixels, the first gate line of the scanned pixel in that row receives a positive voltage through the IC, and the second gate line receives a positive voltage through the corresponding connected independent signal line, thus completing signal writing. For pixels in other rows that have not been scanned, the first gate line receives a negative voltage through the IC, and the second gate line receives a negative voltage through the corresponding connected independent signal line, thus preventing signal writing.

[0010] Furthermore, N / 2 independent signal lines are positioned to the left of the n rows of pixels, while the remaining independent signal lines are positioned to the right of the n rows of pixels. This prevents messy routing and ensures orderly routing.

[0011] Furthermore, in each row of pixels, the first gate line is positioned above the second gate line; both the first and second gate lines extend horizontally and are vertically parallel to each other. This design prevents messy wiring and ensures orderly and regular wiring.

[0012] Furthermore, n is an even number, the number of gate terminals is even, and is n / 2; the n first gate lines are divided into two groups, the first group is from the 1st to the n / 2nd, and the second group is from the n / 2+1th to the nth; the odd-numbered first gate lines in the first group correspond one-to-one with the odd-numbered first gate lines in the second group, and the even-numbered first gate lines in the first group correspond one-to-one with the even-numbered first gate lines in the second group; a gate terminal is provided on the left side of the odd-numbered first gate line in the first group, and a gate terminal is provided on the right side of the even-numbered first gate line in the first group.

[0013] The beneficial effects are that the number of gate terminals is n / 2, which further reduces the number of traces, and the gate terminals are set in odd and even rows on the left and right sides of the first gate line to prevent the traces from being messy and to make the traces orderly.

[0014] Furthermore, in the first group, the odd-numbered first gate line is connected to the corresponding gate terminal on the left; the even-numbered first gate line in the first group is connected to the corresponding gate terminal on the right; in the second group, the odd-numbered first gate line is collinearly connected to the gate terminal lead-out line corresponding to the odd-numbered first gate line in the left first group; and the even-numbered first gate line in the second group is collinearly connected to the gate terminal lead-out line corresponding to the even-numbered first gate line in the right first group. The beneficial effect is that it is equivalent to collinearly connecting two first gate lines, further reducing the number of traces. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the traditional electronic paper pixel structure;

[0016] Figure 2 A schematic diagram of the wiring for an electronic paper product using a traditional pixel structure;

[0017] Figure 3 This is a schematic diagram of the electronic paper pixel structure of the present invention;

[0018] Figure 4 A schematic diagram of the wiring of an electronic paper product using the pixel structure of this invention;

[0019] Appendix Figure 1 and attached Figure 2 Explanation of the marking:

[0020] 1a - Gate line, 1a.1 - First gate, 1a.2 - Second gate, 2a - Source line, 3a - TFT transistor, 4a - Drain, 5a - COM electrode, 6a - Connecting hole, 7a - Pixel electrode, 8a - Second gate line, g - Gate terminal.

[0021] Other figure labels explanations:

[0022] 1-First gate line, 1b-First gate, 1c-Second gate, 2-Source line, 3-TFT transistor, 4-Drain, 5-COM electrode, 6-Connection hole, 7-Pixel electrode, 8-Second gate line, 9-Gate terminal, 10-Independent signal line Detailed Implementation

[0023] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0024] In the description of the invention, it should be noted that the terms "upper," "lower," "left," "right," "front," and "rear," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use. They are used only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. (The appendix to the embodiments of the invention is also included.) Figure 1 The system uses a coordinate system XY, where the positive direction of the X-axis represents the right, the negative direction of the X-axis represents the left, the positive direction of the Y-axis represents the up, and the negative direction of the Y-axis represents the down.

[0025] It should be noted that the resolution of electronic paper displays varies. For ease of description and simplification, Examples 1 to 3 are described using 800 rows of pixels. Examples 4 to 6 describe the cases where the n second gate lines 8 cannot be evenly divided into M groups. For ease of description, the reference numerals in the figures are changed. Each gate terminal is represented by Gi, where i is a variable used to indicate the number of gate terminals. For example, the first gate terminal is G1, the second gate terminal is G2, and so on. Independent signal lines are represented by blockj, where j is a variable used to indicate the number of independent signal lines. For example, the first independent signal line is block1, the second independent signal line is block2, and so on. S1, S2, S3... in the figures all represent the number of columns of pixels.

[0026] Additionally, as attached Figure 1The electronic paper pixel structure circuit shown works as follows: when a positive voltage is applied to the gate, the TFT transistor 3a turns on, and the source signal is transmitted to the drain 4a, and then through the connection hole 6a to the pixel electrode 7a. The com electrode 5a is used as a storage capacitor with the pixel electrode 7a. Figure 1 The working principle of the traditional electronic paper pixel structure circuit is disclosed in detail in the patent document with application number CN201310386300.3, so it will not be elaborated on here. Therefore, the following principle section only describes how to use two independent first gate line 1 and second gate line 8 to open the first gate 1b and second gate 1c of TFT transistor 3 to realize the write signal.

[0027] Example 1:

[0028] This embodiment provides a wiring structure for an electronic paper pixel structure, as shown in the attached diagram. Figure 4 As shown, because the resolution is 800*600, the electronic paper has 800 rows of pixels, 800 first gate lines 1, and 800 second gate lines 8, with n rows of pixels distributed from top to bottom; each pixel in each row is as shown in the attached diagram. Figure 3The diagram includes a first gate 1b and a second gate 1c. In each row of pixels, the first gate 1b of all pixels is connected to one of the first gate lines 1, and the second gate 1c of all pixels in each row is connected to one of the second gate lines 8. In each row of pixels, the first gate line 1 is positioned above the second gate line 8, and 800 first gate lines 1 and 800 second gate lines 8 are distributed sequentially from top to bottom. Both the first gate lines 1 and the second gate lines 8 extend horizontally and are parallel to each other vertically. The diagram also includes 800 gate terminals Gi, namely G1, G2, G3...G800, and 4 independent signal lines blockj, namely block1, block2, block3, and block4. Each gate terminal Gi is connected via a... The IC is connected via a lead wire; each gate terminal Gi corresponds one-to-one with each first gate line 1. Odd-numbered gate terminals Gi are located to the left of their corresponding odd-numbered first gate lines 1, such as G1 to the left of the first first gate line 1, G3 to the left of the third first gate line 1, and so on; even-numbered gate terminals Gi are located to the right of their corresponding first gate lines 1, such as G2 to the right of the second first gate line 1, G4 to the right of the fourth first gate line 1, and so on; on both sides, gate terminals Gi located on the same side are evenly spaced in both vertical and horizontal directions; each first gate line 1 is connected to its corresponding gate terminal Gi, such as the first first gate line 1 connected to the left-hand G1, the second first gate line 1 connected to the right-hand G2, and so on.The independent signal line blockj and the second gate line 8 are divided into four groups. In the grouping of the second gate line 8, the first group consists of the first four odd-numbered second gate lines 8, the second group consists of the first four hundred even-numbered second gate lines 8, the third group consists of the last four hundred odd-numbered second gate lines 8, and the fourth group consists of the last four hundred even-numbered second gate lines 8. In the grouping of the independent signal line blockj, block1, block2, block3, and block4 each form a group. Block1 and block2 are located on the left side of the electronic paper, and block3 and block4 are located on the right side of the electronic paper. The second gate lines 8 in the first group are all collinearly connected to block1, the second gate lines 8 in the second group are all collinearly connected to block2, and the second gate lines 8 in the third group are all collinearly connected to block3. The second gate line 8 of the fourth group is connected collinearly with block 4; ultimately, the number of traces on both sides is reduced to 400+4. The gate signal is scanned pixel by pixel starting from G1. When scanning the first to the 400th row of pixels, the first to the 400th first gate line 1 receives a positive voltage through the IC, and the first to the 400th second gate line 8 receives a positive voltage through the corresponding independent signal line blockj. The remaining first gate line 1 receives a negative voltage through the IC, and the second gate line 8 receives a negative voltage signal through the corresponding independent signal line blockj. At this time, the first gate 1b and the second gate 1c of the TFT transistor 3 of the first to the 400th row of pixels are both turned on, and signals can be written. At this time, the first gate 1b and the second gate 1c of the TFT transistor 3 of the 401st to the 800th row of pixels are turned off, and signals cannot be written. Similarly, when scanning pixels from row 401 to row 800, the first gate lines 1 from row 401 to row 800 receive a positive voltage through the IC, and the second gate lines 8 from row 401 to row 800 receive a positive voltage through their corresponding independent signal lines (blockj). At this time, the first gate 1b and the second gate 1c of pixels from row 401 to row 800 are both open, allowing signals to be written; the first gate 1b and the second gate 1c of pixels from row 1 to row 400 are closed, preventing signals from being written.

[0029] Example 2:

[0030] The difference between this embodiment and Embodiment 1 is that there are 400 gate terminals Gi, namely G1, G2, G3...G400; the 800 first gate lines 1 are divided into two groups: the first group consists of lines 1 to 400, and the second group consists of lines 401 to 800. The odd-numbered first gate lines 1 in the first group correspond one-to-one with the odd-numbered first gate lines 1 in the second group, and the even-numbered first gate lines 1 in the first group correspond one-to-one with the even-numbered first gate lines 1 in the second group. Odd-numbered gate terminals Gi are located to the left of the odd-numbered first gate lines 1 in the first group, such as gate terminal G1 to the left of the first first gate line 1 in the first group, gate terminal G3 to the left of the third first gate line 1 in the first group, and so on; even-numbered gate terminals Gi are located to the right of the even-numbered first gate lines 1 in the first group. For example, gate terminal G2 is located to the right of the second first gate line 1 in the first group, and gate terminal G4 is located to the right of the first gate line 1 in the fourth row of the first group...; the first gate lines 1 in the first group are connected one by one to the corresponding gate terminals Gi on the left and right sides; in the first gate lines 1 of the second group, the odd number of first gate lines 1 are connected to the odd number of gate terminal Gi leads of the first group, such as the 401st first gate line 1 being connected to the lead of G1, the 403rd first gate line 1 being connected to the lead of G3...; in the first gate lines 1 of the second group, the even number of first gate lines 1 are connected to the even number of gate terminal Gi leads of the first group, such as the 402nd first gate line 1 being connected to the lead of G2, the 404th first gate line 1 being connected to the lead of G4... This can further reduce the number of terminal lead wires. The gate signal is scanned pixel by pixel starting from G1. When scanning the first to the 400th row of pixels, the first to the 400th first gate lines 1 are input with positive voltage through the IC, and the first to the 400th second gate lines 8 are input with positive voltage through the corresponding independent signal line blockj. The remaining first gate lines 1 are input with negative voltage through the IC, and the second gate lines 8 are all input with negative voltage signals through the corresponding independent signal line blockj. At this time, the first gate 1b and the second gate 1c of the TFT transistors 3 of the first to the 400th row of pixels are turned on, and signals can be written. At this time, the first gate 1b and the second gate 1c of the TFT transistors 3 of the 401st to the 800th row of pixels are turned off, and signals cannot be written.Similarly, when scanning pixels from row 401 to row 800, the first gate lines 1 from row 401 to row 800 receive a positive voltage through the IC, and the second gate lines 8 from row 401 to row 800 receive a positive voltage through their corresponding independent signal lines blockj. At this time, the first gate 1b and the second gate 1c of pixels from row 401 to row 800 are both open, allowing signals to be written. The first gate 1b and the second gate 1c of pixels from row 1 to row 400 are closed, preventing signals from being written.

[0031] Example 3:

[0032] The difference between this embodiment and Embodiment 2 is that there are 8 independent signal lines (blockj), namely block1, block2, block3, block4, block5, block6, block7, and block8. The 1st to 100th second gate lines (8) are connected to block1; the 101st to 200th second gate lines (8) are connected to block2; the 201st to 300th second gate lines (8) are connected to block3; the 301st to 400th second gate lines (8) are connected to block4; the 401st to 500th second gate lines (8) are connected to block5; the 501st to 600th second gate lines (8) are connected to block6; the 601st to 700th second gate lines (8) are connected to block7; and the 701st to 800th second gate lines (8) are connected to block8. Finally... The number of gate lines on both sides is reduced to 200+8. When the IC scans the pixels from row 1 to row 100, the first gate lines 1 from row 1 to row 100 receive a positive voltage input through the IC, and block 1 receives a positive voltage, turning on the first gate 1b and second gate 1c of the TFT transistors 3 of the pixels from row 1 to row 100, thus writing a signal. The remaining first gate lines 1 receive a negative voltage input through the IC, and the remaining 7 independent signal lines receive a negative voltage, preventing signal writing. When the IC scans the pixels from row 101 to row 200, the first gate lines 1 from row 101 to row 200 receive a positive voltage input through the IC, and block 2 receives a positive voltage, turning on the first gate 1b and second gate 1c of the TFT transistors 3 of the pixels from row 101 to row 200, thus writing a signal. The remaining first gate lines 1 receive a negative voltage input through the IC, and the remaining 7 independent signal lines receive a negative voltage, preventing signal writing. This process continues in this manner.

[0033] Example 4:

[0034] The difference between this embodiment and the previous embodiment is that when n is an odd number, n is taken as 799. If there are four independent signal lines blockj, divided into four groups: block1, block2, block3, and block4; the 799 second gate lines 8 are also divided into four groups: the first group consists of lines 1 to 200, the second group consists of lines 201 to 400, the third group consists of lines 401 to 600, and the fourth group consists of lines 601 to 799. In this case, the second gate line 8 in the fourth group is one less than the second gate line 8 in the other groups. The 799 first gate lines 1 are also divided into four groups: the first group consists of lines 1 to 200, the second group consists of lines 201 to 400, the third group consists of lines 401 to 600, and the fourth group consists of lines 601 to 799. There are 799 gate terminals Gi, namely G1, G2, ..., G799. Odd-numbered gate terminals Gi are positioned to the left of the odd-numbered first gate line 1 in the first group, such as gate terminal G1 to the left of the first gate line 1 in the first group, gate terminal G3 to the left of the third gate line 1 in the first group, and so on. Even-numbered gate terminals Gi are positioned to the right of the even-numbered first gate line 1 in the first group, such as gate terminal G2 to the right of the second gate line 1 in the first group, gate terminal G4 to the right of the first gate line 1 in the fourth row of the first group, and so on. The odd-numbered first gate line 1 is connected to the corresponding gate terminal Gi on its left, and the even-numbered first gate line 1 is connected to the corresponding gate terminal Gi on its right. The 1st to 200th second gate lines 8 are connected collinearly with block 1, the 201st to 400th second gate lines 8 are connected collinearly with block 2, the 401st to 600th second gate lines 8 are connected collinearly with block 3, and the 601st to 799th second gate lines 8 are connected collinearly with block 4.When the IC scans pixels from row 1 to row 200, the first gate lines 1 from row 1 to row 200 receive a positive voltage input through the IC, and block 1 receives a positive voltage, turning on the first gate 1b and second gate 1c of the TFT transistors 3 in rows 1 to 200, thus writing signals. The remaining first gate lines 1 receive a negative voltage input through the IC, and the remaining 7 independent signal lines receive a negative voltage, preventing signal writing. When the IC scans pixels from row 201 to row 400, the first gate lines 1 from row 201 to row 400 receive a positive voltage input through the IC, and block 2 receives a positive voltage, turning on the TFT transistors in rows 201 to 400. The first gate 1b and second gate 1c of transistor 3 are written with signals. The remaining first gate lines 1 are input with negative voltage through the IC, and the remaining 7 independent signal lines are input with negative voltage, so no signals can be written. This continues until the IC scans the pixels from row 601 to row 799. The first gate lines 1 from row 601 to row 799 are input with positive voltage through the IC, and block 2 is input with positive voltage. This turns on the first gate 1b and second gate 1c of TFT transistor 3 in the pixels from row 601 to row 799, and writes signals. The remaining first gate lines 1 are input with negative voltage through the IC, and the remaining 7 independent signal lines are input with negative voltage, so no signals can be written.

[0035] Example 5:

[0036] The difference between this embodiment and embodiment 4 is that when n is an odd number, n is taken as 801. If there are four independent signal lines blockj, and they are divided into four groups, namely block1, block2, block3, and block4; the 799 second gate lines 8 are also divided into four groups, the first group is line 1 to line 200, the second group is line 201 to line 400, the third group is line 401 to line 600, and the fourth group is line 601 to line 801. At this time, the second gate line 8 of the fourth group has one more second gate line 8 than the other groups. The signal writing method is the same as the above embodiment, and will not be repeated.

[0037] Example 6:

[0038] The difference between this embodiment and embodiments 4 and 5 is that when n is 802, if there are four independent signal lines blockj, and they are divided into four groups, namely block1, block2, block3, and block4; the 799 second gate lines 8 are also divided into four groups, the first group consists of lines 1 to 200, the second group consists of lines 201 to 400, the third group consists of lines 401 to 600, and the fourth group consists of lines 601 to 802. In this case, the second gate lines 8 of the fourth group have 2 more than the second gate lines 8 of the other groups. The signal writing method is the same as in the above embodiments and will not be repeated.

[0039] It should also be noted that the grouping method described in this invention can be used to address different resolutions.

[0040] While the disclosure is as stated above, its scope of protection is not limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of this disclosure, and all such changes and modifications will fall within the protection scope of this invention.

Claims

1. A wiring structure for an electronic paper pixel structure, wherein the electronic paper has n rows of pixels and n first gate lines (1) and n second gate lines (8), n≥1, and the n rows of pixels are distributed sequentially from top to bottom, characterized in that, The first gate (1b) of all pixels in each row is connected to one of the first gate lines (1), and the second gate (1c) of all pixels in each row is connected to one of the second gate lines (8). The electronic paper also includes several gate terminals (9) and N independent signal lines (10), where N is an even number. Each gate terminal (9) is connected to the IC by a lead wire. The first gate line (1) is connected to one of the gate terminals (9) or one of the lead wires. The N independent signal lines (10) are divided into M groups on average, and the n second gate lines (8) are also divided into M groups on average, where M is an even number. When the n second gate lines (8) cannot be divided into M groups on average, the number of second gate lines (8) in one group is several more or several fewer than the number of second gate lines (8) in the other groups. Each group of independent signal lines (10) is connected to one of the groups of second gate lines (8) on the same line. The independent signal lines (10) are used to receive positive and negative voltages. N / 2 of the independent signal lines (10) are located on the left side of the n rows of pixels, and the remaining independent signal lines (10) are located on the right side of the n rows of pixels. n is an even number, and the number of gate terminals (9) is an even number, and is n / 2; the n first gate lines (1) are divided into two groups, the first group is from the 1st to the n / 2nd, and the second group is from the n / 2+1th to the nth; the odd-numbered first gate lines (1) in the first group correspond one-to-one with the odd-numbered first gate lines (1) in the second group, and the even-numbered first gate lines (1) in the first group correspond one-to-one with the even-numbered first gate lines (1) in the second group; the gate terminal (9) is provided on the left side of the odd-numbered first gate line (1) in the first group, and the gate terminal (9) is provided on the right side of the even-numbered first gate line (1) in the first group. The first gate line (1) of the odd-numbered root in the first group is connected to the gate terminal (9) corresponding to the left; the first gate line (1) of the even-numbered root in the first group is connected to the gate terminal (9) corresponding to the right; the first gate line (1) of the odd-numbered root in the second group is connected in a collinear manner with the lead of the gate terminal (9) corresponding to the odd-numbered root in the first group on the left; the first gate line (1) of the even-numbered root in the second group is connected in a collinear manner with the lead of the gate terminal (9) corresponding to the even-numbered root in the first group on the right. 2.The routing structure of an electronic paper pixel structure according to claim 1, wherein, In each row of pixels, the first gate line (1) is disposed above the second gate line (8); all the first gate lines (1) and all the second gate lines (8) are distributed from top to bottom; the first gate lines (1) and the second gate lines (8) are both arranged in the left-right direction and are distributed in parallel vertically.

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