Flash memory device and data management method thereof

Abstract

The embodiment of the present application relates to the application field of storage devices, and discloses a flash memory device and a data management method thereof, the method comprising: establishing a mapping table of logical addresses to physical addresses, wherein the addressing granularity of the physical addresses = N * the addressing granularity of the logical addresses, N is a positive integer and N >= 2; dividing a cache module into a to-be-flushed data cache module and a to-be-combined data cache module; obtaining a write request sent by a host, and dividing write data into the to-be-flushed data cache module and / or the to-be-combined data cache module; flushing data in the to-be-flushed data cache module to a flash memory medium, or combining N minimum write units in the to-be-combined data cache module into a flushing unit, and flushing the flushing unit to the to-be-flushed data cache module or the flash memory medium. Through the addressing granularity of the physical addresses = N * the addressing granularity of the logical addresses, the present application can improve the performance of the flash memory device in a random write scenario and prolong the service life of the flash memory device.

Description

Technical Field

[0001] This application relates to the field of storage device applications, and in particular to a flash memory device and a data management method thereof. Background Technology

[0002] Flash memory devices, such as solid-state drives (SSDs), are hard drives made using arrays of solid-state electronic storage chips. SSDs include a control unit and storage units (FLASH memory chips or DRAM memory chips).

[0003] Because flash memory devices have unique data read / write characteristics, the operating system cannot directly manage them. A flash translation layer (FTL) is needed between the operating system and the flash memory device to map the host (or user) logical address space to the flash physical address space. However, the ever-increasing flash memory capacity causes the mapping table to grow larger and larger, while the memory space of the flash memory device does not increase proportionally with the flash memory capacity.

[0004] Existing technologies reduce the size of the mapping table by increasing the management granularity of the flash SSD. However, when the overall read / write length in the test scenario is less than the management granularity, it can lead to increased write amplification. Summary of the Invention

[0005] This application provides a flash memory device and its data management method, which can improve the performance of the flash memory device in random write scenarios and extend the life of the flash memory device.

[0006] The embodiments of this application provide the following technical solutions:

[0007] In a first aspect, embodiments of this application provide a data management method for a flash memory device, the flash memory device including a flash memory medium and a cache module, the method comprising:

[0008] Establish a mapping table from logical address to physical address, where the addressing granularity of physical address = N * addressing granularity of logical address, where N is a positive integer and N≥2;

[0009] The cache module is divided into a data cache module to be flushed and a data cache module to be combined. The data granularity of the data cache module to be combined is equal to the addressing granularity of the logical address, and the data granularity of the data cache module to be flushed is equal to the addressing granularity of the physical address.

[0010] Get the write request sent by the host, wherein the write request includes the write data of the host, wherein the write data includes several minimum write units;

[0011] Based on the size of the written data, the written data is divided into the data cache module to be flushed and / or the data cache module to be combined;

[0012] The data in the data cache module to be flushed is flushed to the flash memory medium, or the N smallest write units in the data cache module to be combined are combined into a flush unit and the flush unit is flushed to the data cache module to be flushed or the flash memory medium. The size of the flush unit is equal to the addressing granularity of the physical address.

[0013] Secondly, embodiments of this application provide a flash memory device, including:

[0014] At least one processor; and

[0015] A memory that is communicatively connected to at least one processor; wherein,

[0016] The memory stores instructions that can be executed by at least one processor, which enables the at least one processor to perform a data management method for a flash memory device as described in the first aspect.

[0017] Thirdly, embodiments of this application also provide a non-volatile computer-readable storage medium storing computer-executable instructions for enabling a flash memory device to perform a data management method for a flash memory device as described in the first aspect.

[0018] The beneficial effects of this application embodiment are as follows: Unlike the prior art, this application embodiment provides a data management method for a flash memory device. The flash memory device includes a flash memory medium and a cache module. The method includes: establishing a mapping table from logical addresses to physical addresses, wherein the addressing granularity of the physical address = N * the addressing granularity of the logical address, where N is a positive integer and N≥2; dividing the cache module into a data cache module to be flushed and a data cache module to be combined, wherein the data granularity of the data cache module to be combined is equal to the addressing granularity of the logical address, and the data granularity of the data cache module to be flushed is equal to the addressing granularity of the physical address. The addressing granularity of the physical address is determined; a write request sent by the host is obtained, wherein the write request includes the host's write data, wherein the write data includes several minimum write units; the write data is divided into a data cache module to be flushed and / or a data cache module to be combined, according to the size of the write data; the data in the data cache module to be flushed is flushed to the flash memory medium, or the N minimum write units in the data cache module to be combined are combined into a flush unit, and the flush unit is flushed to the data cache module to be flushed or the flash memory medium, wherein the size of the flush unit is equal to the addressing granularity of the physical address.

[0019] By using the addressing granularity of physical address = N * addressing granularity of logical address, where N is a positive integer and N≥2, the data granularity of the data cache module to be combined is equal to the addressing granularity of logical address, and the data granularity of the data cache module to be flushed is equal to the addressing granularity of physical address, this application can improve the performance of flash memory devices in random write scenarios. Furthermore, since it is not necessary to write data after reading the logical address, no additional write amplification is introduced, which can extend the lifespan of flash memory devices. Attached Figure Description

[0020] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0021] Figure 1 This is a schematic diagram of the structure of a flash memory device provided in an embodiment of this application;

[0022] Figure 2 This is a schematic diagram of a mapping table from logical address to physical address of a flash memory device provided in an embodiment of this application;

[0023] Figure 3 This is a schematic diagram illustrating the data distribution of a logical address according to an embodiment of this application;

[0024] Figure 4 This is a flowchart illustrating a data management method for a flash memory device provided in an embodiment of this application;

[0025] Figure 5 This is a schematic diagram of another logical address to physical address mapping table provided in an embodiment of this application;

[0026] Figure 6 This is a schematic diagram of another logical address to physical address mapping table provided in the embodiments of this application;

[0027] Figure 7 This is a schematic diagram of a caching module provided in an embodiment of this application;

[0028] Figure 8 yes Figure 4 Detailed flowchart of step S404 in the process;

[0029] Figure 9 yes Figure 8 Detailed flowchart of step S443 in the process;

[0030] Figure 10 This is a schematic diagram of a data cache set provided in an embodiment of this application;

[0031] Figure 11This is a schematic diagram illustrating the writing of data according to an embodiment of this application;

[0032] Figure 12 This is a schematic diagram illustrating the partitioning and writing of data provided in an embodiment of this application;

[0033] Figure 13 This is a schematic diagram of a data reading process provided in an embodiment of this application;

[0034] Figure 14 This is a schematic diagram of a waste recycling process provided in an embodiment of this application;

[0035] Figure 15 This is a schematic diagram of a mapping table from physical address to logical address provided in an embodiment of this application;

[0036] Figure 16 This is a schematic diagram of another physical address to logical address mapping table provided in an embodiment of this application;

[0037] Figure 17 This is a schematic diagram of another physical address to logical address mapping table provided in the embodiments of this application;

[0038] Figure 18 yes Figure 14 A detailed flowchart of step S142;

[0039] Figure 19 This is a detailed flowchart illustrating a method for finding valid data, as provided in an embodiment of this application.

[0040] Figure 20 This is a schematic diagram of a P2L table and an L2P table provided in an embodiment of this application;

[0041] Figure 21 This is a schematic diagram of a waste recycling method provided in an embodiment of this application;

[0042] Figure 22 This is a schematic diagram of another data cache set provided in an embodiment of this application;

[0043] Figure 23 This is a schematic diagram of the structure of a flash memory device provided in an embodiment of this application. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0045] It should be noted that, unless there is a conflict, the various features in the embodiments of this application can be combined with each other, all of which are within the protection scope of this application. Furthermore, although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than the module division in the device or the order in the flowchart. Moreover, the terms "first," "second," and "third" used in this application do not limit the data or execution order, but only distinguish identical or similar items with essentially the same function and effect.

[0046] The technical solution of this application will be described in detail below with reference to the accompanying drawings:

[0047] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of a flash memory device provided in an embodiment of this application;

[0048] like Figure 1 As shown, the flash memory device 100 includes a flash memory medium 110 and a controller 120 connected to the flash memory medium 110. The flash memory device 100 communicates with the host 200 via wired or wireless means to enable data exchange.

[0049] Flash memory medium 110, as the storage medium of flash memory device 100, is also called flash memory, Flash, Flash memory or Flash chip. It is a type of storage device and is a non-volatile memory that can retain data for a long time without a current supply. Its storage characteristics are equivalent to hard disk, which makes flash memory medium 110 the basis for the storage medium of various portable digital devices.

[0050] The controller 120 includes a data converter 121, a processor 122, a cache 123, a flash memory controller 124, and an interface 125.

[0051] Data converter 121, connected to processor 122 and flash memory controller 124 respectively, is used to convert binary data to hexadecimal data and vice versa. Specifically, when flash memory controller 124 writes data to flash memory medium 110, data converter 121 converts the binary data to be written into hexadecimal data before writing it to flash memory medium 110. When flash memory controller 124 reads data from flash memory medium 110, data converter 121 converts the hexadecimal data stored in flash memory medium 110 into binary data, and then reads the converted data from the binary data page register. Data converter 121 may include a binary data register and a hexadecimal data register. The binary data register can be used to store data converted from hexadecimal to binary, and the hexadecimal data register can be used to store data converted from binary to hexadecimal.

[0052] The processor 122 is connected to the data converter 121, the cache 123, the flash memory controller 124, and the interface 125, respectively. The processor 122 can be connected to the data converter 121, the cache 123, the flash memory controller 124, and the interface 125 via a bus or other means. The processor is used to run non-volatile software programs, instructions, and modules stored in the cache 123, thereby implementing any method embodiment of this application.

[0053] The buffer 123 is mainly used to buffer the read / write commands sent by the host 200 and the read or write data obtained from the flash memory medium 110 according to the read / write commands sent by the host 200.

[0054] The flash memory controller 124 is connected to the flash memory medium 110, the data converter 121, the processor 122, and the cache 123. It is used to access the back-end flash memory medium 110 and manage various parameters and data I / O of the flash memory medium 110; or, it is used to provide access interfaces and protocols, implement the corresponding SAS / SATA target protocol or NVMe protocol, obtain I / O instructions issued by the host 200, decode and generate internal private data results for execution; or, it is used to be responsible for the core processing of the flash translation layer (FTL).

[0055] Interface 125 connects host 200, data converter 121, processor 122, and buffer 123. It is used to receive data sent by host 200 or data sent by processor 122, so as to realize data transmission between host 200 and processor 122. Interface 125 can be a SATA-2 interface, SATA-3 interface, SAS interface, mSATA interface, PC IE interface, NGFF interface, CFast interface, SFF-8639 interface, and M.2 NVME / SATA protocol.

[0056] Currently, most enterprise-level flash memory devices cache the entire Logical to Physical (L2P) address mapping table, or L2P table, in Dynamic Random Access Memory (DRAM). Typically, 4 bytes are used as the size of each mapping unit, i.e., physical address. One mapping unit corresponds to 4K of data on the host (flash page size is 4K). If the flash memory capacity is 1TB, then the DRAM capacity required for the L2P table is 1GB. Similarly, if the flash memory capacity is 4TB / 8TB, then the DRAM capacity required for the L2P table is approximately 4GB / 8GB.

[0057] Please see Figure 2 , Figure 2 This is a schematic diagram of a mapping table from logical address to physical address of a flash memory device provided in an embodiment of this application;

[0058] like Figure 2 As shown, in the L2P table, the address number of a logical address (LMA) corresponds to the address number of a physical address (PMA). The address number of the physical address (PMA) can be found from the L2P table based on the address number of the logical address (LMA).

[0059] Currently, for flash memory devices with capacities of 8TB and below, the Logical Address (LMA) typically uses 4KB as its smallest address granularity, and the Physical Address (PMA) also uses 4KB as its smallest address granularity. Therefore, if 4 bytes represent the PMA address, the maximum address range it can represent is 4KB * 4Byte_NUM = 16TB. However, because 1 byte of the 32-bit physical address is used specifically in firmware design, the remaining 31 bytes can only identify a maximum flash memory capacity of 8TB. ​​Therefore, the maximum physical address range that 4 bytes can represent is generally only applicable to flash memory devices with capacities of 8TB and below. When the flash memory capacity exceeds 8TB, 4 bytes are insufficient to represent its entire physical address range.

[0060] Currently, enterprise-level flash memory devices typically employ large-granularity mapping to address the aforementioned issues. For example, if the addressing granularity of both the logical address (LMA) and physical address (PMA) is set to 8K, then 4 bytes can be used to represent the physical address range of a flash memory device with a capacity of 16TB. Similarly, if the addressing granularity of both the logical address (LMA) and physical address (PMA) is set to 16K, then 4 bytes can be used to represent the physical address range of a flash memory device with a capacity of 32TB.

[0061] It should be noted that the addressing granularity of the logical address (LMA) in this application can be 8K, 16K, 32K or other sizes. The following uses an 8K addressing granularity for the logical address (LMA) to illustrate the specific scheme of this large-granularity mapping:

[0062] When the addressing granularity of the Logical Address (LMA) in the firmware is 8K, the logical address space is actually divided into 8K granularities, requiring that the host data within each logical address (LMA) must be stored contiguously together. The host typically uses 4K (or 512B) as the smallest write unit.

[0063] When reading data, the address number corresponding to the Logical Block Address (LBA) is first converted into the address number of the Logical Address (LMA). Then, the Physical Address (PMA) is found through the L2P table. Finally, the address number corresponding to the Logical Block Address (LBA) is moduloed to determine the location of the data corresponding to the Logical Address (LMA) in the PMA.

[0064] In this context, if the flash memory device's capacity is a multiple of 4K, and the host's sector format (i.e., smallest write unit) is 4K, then the logical block address (LBA) is numbered from 1 to N; if the host's sector format (i.e., smallest write unit) is 512B, then the logical block address (LBA) is numbered from 0 to 8*N. If the addressing granularity of the logical block address (LBA) is 4K, then the address number corresponding to the logical block address (LBA) equals the address number of the logical address (LMA); if the addressing granularity of the logical block address (LBA) is 512B, then the address number of the logical address (LMA) equals the address number corresponding to the logical block address (LBA) divided by 8.

[0065] For example, if the addressing granularity of the Logical Block Address (LBA) is 4K, and the host reads data at address number 11 corresponding to the LBA, then the address number of the Logical Address (LMA) is equal to the address number corresponding to the LBA, which is also 11. The host then looks up the physical address (PMA) corresponding to LMA11 in the L2P table. Afterwards, it performs a modulo operation on the address number 11 corresponding to the LBA, dividing by 2 (2 = LMA addressing granularity 8K / LBA addressing granularity 4K), resulting in 1. 1 indicates that the data corresponding to the LMA is in the second position of the physical address (PMA). It's understandable that taking the remainder of any number with respect to 2 yields only two results: 0 and 1. 0 indicates that the data corresponding to the LMA is in the first position of the physical address (PMA), and 1 indicates that the data corresponding to the LMA is in the second position of the physical address (PMA).

[0066] Please see Figure 3 , Figure 3 This is a schematic diagram illustrating the data distribution of a logical address according to an embodiment of this application;

[0067] In this embodiment, the host uses 4K (or 512B) as the smallest write unit. Figure 3 Taking the host as an example, with 4K as the smallest write unit.

[0068] like Figure 3 As shown, when the addressing granularity of the logical address (LMA) is 8K and the host uses 4K as the smallest write unit, the host may write 4K of data at the logical address discretely. Logical address 0 (LMA0) and logical address 1 (LMA1) may only write data in the first 4K position, and there may be no data in the second 4K position. At this time, the data in LMA0 and LMA1 are not combined to form a continuous 8K as required, and the data cannot be written.

[0069] Therefore, it is necessary to first read the existing data corresponding to LMA0 and LMA1 from the flash memory medium, then combine a portion of the existing data with a portion of the new data to form a new 8K, write it to the flash memory medium, and update the L2P table. However, this method results in a read-write cycle within the firmware during random write scenarios, leading to reduced write performance and increased write amplification (4K more data is written relative to the actual amount written by the host), thereby shortening the lifespan of the flash memory device.

[0070] Based on this, embodiments of this application provide a data management method for a flash memory device to improve the performance of the flash memory device in random write scenarios. It does not require writing data after reading a logical address, thus avoiding the introduction of additional write amplification and extending the lifespan of the flash memory device.

[0071] Please see Figure 4 , Figure 4 This is a flowchart illustrating a data management method for a flash memory device provided in an embodiment of this application;

[0072] The data management method for the flash memory device is applied to the flash memory device, which includes a flash memory medium and a cache module.

[0073] like Figure 4 As shown, the data management method of the flash memory device includes:

[0074] Step S401: Establish a mapping table from logical address to physical address;

[0075] Specifically, the addressing granularity of a physical address = N * the addressing granularity of a logical address, where N is a positive integer and N ≥ 2. The addressing granularity of a logical address (LMA) is 4K, and the addressing granularity of a physical address (PMA) = N * 4K, for example: 8K, 16K...

[0076] In this embodiment of the application, the mapping table from logical address to physical address includes the mapping relationship between the address number of the logical address and the address number of the physical address. The address number of the logical address is, for example, LMA0, LMA1, etc., and the address number of the physical address is, for example, PMA0, PMA1, etc.

[0077] Please refer to the following: Figure 5 , Figure 5 This is a schematic diagram of another logical address to physical address mapping table provided in an embodiment of this application;

[0078] In the embodiments of this application, when the addressing granularity of the logical address (LMA) is 4K and the addressing granularity of the physical address (PMA) is 8K, in the mapping table from logical address to physical address, one physical address (PMA) will have two logical addresses (LMA) corresponding to it.

[0079] like Figure 5 As shown, LMA0 and LMA3 correspond to PMA0, LMA1 and LMA4 correspond to PMA2, ​​and LMA2 and LMA5 correspond to PMA1.

[0080] Please refer to the following: Figure 6 , Figure 6 This is a schematic diagram of another logical address to physical address mapping table provided in the embodiments of this application;

[0081] In the embodiments of this application, when the addressing granularity of the logical address (LMA) is 4K and the addressing granularity of the physical address (PMA) is 12K, in the mapping table from logical address to physical address, one physical address (PMA) will have three logical addresses (LMA) corresponding to it.

[0082] like Figure 6 As shown, LMA0, LMA2 and LMA4 correspond to PMA0, and LMA1, LMA3 and LMA5 correspond to PMA1.

[0083] Step S402: Divide the cache module into a cache module for data to be flushed and a cache module for data to be combined;

[0084] Specifically, the caching module is used to cache data written to the host. The data granularity of the caching module for combined data is equal to the addressing granularity of the logical address, and the data granularity of the caching module for data to be flushed is equal to the addressing granularity of the physical address. For example: if the addressing granularity of the logical address (LMA) is 4K, then the data granularity of the caching module for combined data is 4K; if the addressing granularity of the physical address (PMA) is 8K, then the data granularity of the caching module for data to be flushed is 8K; if the addressing granularity of the physical address (PMA) is 16K, then the data granularity of the caching module for data to be flushed is 16K.

[0085] Please refer to the following: Figure 7 , Figure 7 This is a schematic diagram of a caching module provided in an embodiment of this application;

[0086] like Figure 7 As shown, the caching module includes a data cache module for data to be flushed and a data cache module for data to be combined. In this embodiment, the caching module includes a cache memory.

[0087] Step S403: Obtain the write request sent by the host;

[0088] Specifically, the system retrieves write requests sent by the host via the Non-Volatile Memory Host Controller Interface (NVMe) protocol. NVMe is a logical device interface specification, a bus transmission protocol specification based on the device logical interface (equivalent to the application layer in communication protocols), used to access non-volatile memory media (such as solid-state drives using flash memory) attached via the PCI Express (PCIe) bus. The write request includes the host's write data, which comprises several minimum write units, with a data granularity of 4K or 512B.

[0089] Step S404: Based on the size of the written data, divide the written data into the data cache module to be flushed and / or the data cache module to be combined;

[0090] Specifically, the size of the data written = M * sector, where M is a positive integer and M≥1, and sector is the host sector format, i.e., the data granularity of the smallest write unit. The sector can be 4K or 512B. It is understandable that the data granularity of the smallest write unit, sector, can also include other values, such as 1K, 2K, etc.

[0091] In this embodiment, the written data is stored on storage media such as DRAM or SRAM in the firmware system. Dividing the written data into the data cache module to be flushed and / or the data cache module to be combined changes the mapping relationship of the written data ownership, and does not involve memory copying.

[0092] Please refer to the following: Figure 8 , Figure 8 yes Figure 4 Detailed flowchart of step S404 in the process;

[0093] like Figure 8 As shown, step S404: Based on the size of the written data, the written data is divided into the data cache module to be flushed and / or the data cache module to be combined, including:

[0094] Step S441: If the size of the written data is greater than the addressing granularity of the physical address, then the consecutive N integer multiples of the smallest write units in the written data are allocated to the data to be flushed cache module, and the remaining data in the written data are allocated to the data to be combined cache module.

[0095] Specifically, the addressing granularity of the physical address = N * the addressing granularity of the logical address, where N is a positive integer and N≥2. The data granularity of the data cache module to be combined is equal to the addressing granularity of the logical address, and the data granularity of the data cache module to be flushed is equal to the addressing granularity of the physical address.

[0096] For example: the data granularity of the smallest write unit is 4K, the addressing granularity of the logical address (LMA) is 4K, N=2, the addressing granularity of the physical address (PMA) is 8K, the data granularity of the data cache module to be combined is 4K, and the data granularity of the data cache module to be flushed is 8K. If the size of the written data is greater than the addressing granularity of the physical address (PMA) of 8K, then the consecutive integer multiples of 2 of the smallest write units, i.e., 8K data, in the written data will be allocated to the data cache module to be flushed, and the remaining data will be allocated to the data cache module to be combined.

[0097] Alternatively, the data granularity of the smallest write unit is 4K, the addressing granularity of the logical address (LMA) is 4K, N=3, the addressing granularity of the physical address (PMA) is 12K, the data granularity of the data cache module to be combined is 4K, and the data granularity of the data cache module to be flushed is 12K. If the size of the written data is greater than the addressing granularity of the physical address (PMA) of 12K, then the consecutive integer multiples of 3 smallest write units, i.e., 12K data, in the written data will be allocated to the data cache module to be flushed, and the remaining data will be allocated to the data cache module to be combined.

[0098] It should be noted that the addressing granularity of the physical address in this embodiment can also be 16K, 32K or other values, and the processing method is similar to that described above, so it will not be repeated here.

[0099] It is understandable that, since the data granularity corresponding to the data cache module to be flushed is N * the data granularity of the smallest write unit, in this embodiment of the application, dividing consecutive N integer multiples of the smallest write units in the written data into the data cache module to be flushed includes: according to the data order of the written data, taking N smallest write units as a unit, dividing the N integer multiples of the smallest write units in the written data into the data cache module to be flushed, so that the data size of each data in the data cache module to be flushed is N * the data granularity of the smallest write unit, wherein the data order of the written data is represented by the sequence number of the logical block.

[0100] Step S442: If the size of the written data is equal to the addressing granularity of the physical address, then the written data is allocated to the data to be flushed cache module;

[0101] Specifically, the data granularity of the data to be flushed cache module is equal to the addressing granularity of N * logical address. If the size of the data to be written is equal to the addressing granularity of N * logical address, where N is a positive integer and N≥2, then the data to be written will be allocated to the data to be flushed cache module.

[0102] For example: the addressing granularity of the logical address (LMA) is 4K, N=2, the addressing granularity of the physical address (PMA) is 8K, and the data granularity of the data to be flushed is 8K. If the size of the data to be written is equal to the addressing granularity of the physical address (PMA) of 8K, then the data to be written will be allocated to the data to be flushed.

[0103] Alternatively: The addressing granularity of the logical address (LMA) is 4K, N=3, the addressing granularity of the physical address (PMA) is 12K, and the data granularity of the data to be flushed is 12K. If the size of the written data is equal to the addressing granularity of the physical address (PMA) of 12K, then the written data will be allocated to the data to be flushed cache module.

[0104] Step S443: If the size of the data to be written is smaller than the addressing granularity of the physical address, then the data to be written is allocated to the data cache module to be combined.

[0105] For example: the addressing granularity of the logical address (LMA) is 4K, the data granularity of the data cache module to be combined is 4K, N=2, and the addressing granularity of the physical address (PMA) is 8K. If the size of the written data is smaller than the addressing granularity of the physical address (PMA) of 8K, then the written data will be allocated to the data cache module to be combined.

[0106] Alternatively: The addressing granularity of the logical address (LMA) is 4K, the data granularity of the data cache module to be combined is 4K, N=3, and the addressing granularity of the physical address (PMA) is 12K. If the size of the written data is smaller than the addressing granularity of the physical address (PMA) of 12K, then the written data will be allocated to the data cache module to be combined.

[0107] For details, please refer to [link / reference]. Figure 9 , Figure 9 yes Figure 8 Detailed flowchart of step S443 in the process;

[0108] In this embodiment of the application, the data cache module to be combined includes N data cache sets, each data cache set corresponding to a set number.

[0109] like Figure 9 As shown, step S443: If the size of the data to be written is smaller than the addressing granularity of the physical address, then the data to be written is divided into the data cache module to be combined, including:

[0110] Step S4431: If the size of the written data is smaller than the addressing granularity of the physical address, perform a modulo operation on the address number corresponding to each smallest written unit in the written data to obtain the modulo result of the address number corresponding to each written unit.

[0111] Specifically, the physical address addressing granularity = N * logical address addressing granularity, where N is a positive integer and N≥2. The remainder of the address number corresponding to each smallest write unit in the written data is obtained by performing a modulo operation, resulting in the remainder of the address number corresponding to each write unit, including:

[0112] The address number corresponding to each smallest write unit in the written data is moduloed by N to obtain the remainder result of the address number corresponding to each write unit. The value range of the remainder result is [0, N-1].

[0113] For example: if the size of the written data is less than the addressing granularity of N * logical address, take the remainder of the address number corresponding to each smallest written unit in the written data with respect to N, and obtain the remainder result of the address number corresponding to each written unit.

[0114] For example: the addressing granularity of the logical address (LMA) is 4K, N=2, the addressing granularity of the physical address (PMA) is 8K, and the size of the data to be written is smaller than the addressing granularity of the physical address (PMA) of 8K. If the address number corresponding to the smallest write unit in the data is LMA=1, then the remainder operation of 1 divided by 2 is performed, and the remainder result of the address number corresponding to the write unit is 1. If the address number corresponding to the smallest write unit in the data is LMA=4, then the remainder operation of 4 divided by 2 is performed, and the remainder result of the address number corresponding to the write unit is 0.

[0115] Alternatively, if the logical address (LMA) granularity is 4K and N=4, and the physical address (PMA) granularity is 16K, and the size of the data being written is smaller than the physical address (PMA) granularity of 16K, then if the address number corresponding to the smallest write unit in the data is LMA=1, then perform a modulo operation of 1 divided by 4 to obtain a remainder of 1 for the address number corresponding to that write unit; if the address number corresponding to the smallest write unit in the data is LMA=6, then perform a modulo operation of 6 divided by 4 to obtain a remainder of 2 for the address number corresponding to that write unit; if the address number corresponding to the smallest write unit in the data is LMA=2, then perform a modulo operation of 2 divided by 4 to obtain a remainder of 2 for the address number corresponding to that write unit.

[0116] Step S4432: Based on the remainder result, each smallest write unit in the written data is assigned to the data cache set.

[0117] Specifically, the remainder of the address number of each smallest write unit in the data cache set is equal to the set number. The number of data cache sets is N = physical address granularity / logical address granularity, where N is a positive integer and N≥2.

[0118] For example, if N=2, the data cache set includes two sets: set 0 and set 1. If the remainder is 1, the smallest write unit is assigned to set 1 of the data cache set; if the remainder is 0, the smallest write unit is assigned to set 0 of the data cache set.

[0119] Alternatively, N=3, the data cache set includes 3 sets: set 0, set 1 and set 2. If the remainder is 2, the smallest write unit is assigned to set 2 of the data cache set; if the remainder is 1, the smallest write unit is assigned to set 1 of the data cache set; if the remainder is 0, the smallest write unit is assigned to set 0 of the data cache set.

[0120] For example, if N=4, the data cache set includes 4 sets: set 0, set 1, set 2, and set 3. If the remainder is 3, the smallest write unit is assigned to set 3 of the data cache set; if the remainder is 2, the smallest write unit is assigned to set 2 of the data cache set; if the remainder is 1, the smallest write unit is assigned to set 1 of the data cache set; and if the remainder is 0, the smallest write unit is assigned to set 0 of the data cache set.

[0121] Please refer to the following: Figure 10 , Figure 10 This is a schematic diagram of a data cache set provided in an embodiment of this application;

[0122] In this embodiment of the application, the data cache set can be a linked list or any other distinguishable software data structure.

[0123] The following example, with N=4, illustrates the process of allocating the smallest write unit in the written data to the data cache set.

[0124] If N=4, the data granularity of the smallest write unit is 4K, the addressing granularity of the logical address (LMA) is 4K, and the addressing granularity of the physical address (PMA) is 16K. If the size of the written data is smaller than the addressing granularity of the physical address (PMA) of 16K, and the address number corresponding to the smallest write unit in the written data is LMA=1, then the remainder operation is performed by dividing 1 by 4. The remainder result of the address number corresponding to the write unit is 1. The smallest write unit is then assigned to set 1 of the data cache set, that is, the address number LMA1 corresponding to the smallest write unit is assigned to set 1 of the data cache set.

[0125] If the address number corresponding to the smallest write unit in the written data is LMA = 2, then perform the modulo operation of 2 divided by 4, and the modulo result of the address number corresponding to this write unit is 2. Divide this smallest write unit into set 2 of the data cache set, that is, divide the address number LMA2 corresponding to this smallest write unit into set 2 of the data cache set;

[0126] If the address number corresponding to the smallest write unit in the written data is LMA = 3, then perform the modulo operation of 3 divided by 4, and the modulo result of the address number corresponding to this write unit is 3. Divide this smallest write unit into set 3 of the data cache set, that is, divide the address number LMA3 corresponding to this smallest write unit into set 3 of the data cache set;

[0127] If the address number corresponding to the smallest write unit in the written data is LMA = 4, then perform the modulo operation of 4 divided by 4, and the modulo result of the address number corresponding to this write unit is 0. Divide this smallest write unit into set 0 of the data cache set, that is, divide the address number LMA4 corresponding to this smallest write unit into set 0 of the data cache set;

[0128] The process of dividing the smallest write units corresponding to different address numbers into the data cache set is the same as the above method and will not be elaborated here.

[0129] As Figure 10 shown, when N = 4, the data cache set includes 4 sets: set 0, set 1, set 2, and set 3. LMA4 and LMA8 belong to set 0, LMA1 and LMA5 belong to set 1, LMA2 and LMA6 belong to set 2, and LMA3 and LMA7 belong to set 3.

[0130] Please refer to Figure 11 , Figure 11 which is a schematic diagram of writing data provided by an embodiment of the present application;

[0131] As Figure 11 shown, when the size of the written data is greater than the addressing granularity of N * logical addresses, and the address number range of all the smallest write units corresponding to this written data is LMA_X to LMA_Y (X and Y are positive integers and X < Y), that is, logical address X to logical address Y, this written data can be divided into two parts. One part is composed of an integer multiple of N consecutive smallest write units, and the other part is composed of the remaining data.

[0132] For example: the data granularity of the smallest write unit is 4K, the addressing granularity of the logical address (LMA) is 4K, N=2, the addressing granularity of the physical address (PMA) is 8K, the data granularity of the data cache module to be combined is 4K, and the data granularity of the data cache module to be flushed is 8K. If the address number range corresponding to all the smallest write units of the written data is LMA110~LMA120, then in the smallest write units with address numbers ranging from LMA110 to LMA119, the granularity of the data composed of every two smallest write units is 8K, which is the same as the data granularity of the data cache module to be flushed. Therefore, the smallest write units with address numbers ranging from LMA110 to LMA119 can be assigned to the data cache module to be flushed, and the remaining smallest write unit with address number LMA120 can be assigned to the data cache module to be combined. Since LMA=120 modulo N=2, the remainder result is 0, so the smallest write unit with address number LMA120 is assigned to set 0 in the data cache module to be combined.

[0133] Please see Figure 12 , Figure 12 This is a schematic diagram illustrating the partitioning and writing of data provided in an embodiment of this application;

[0134] like Figure 12 As shown, the written data is divided into a data cache module to be flushed and a data cache module to be assembled within the cache module. These modules are identified by a node data structure. Each node identifies the location and length of the different data regions into which the written data is divided; specifically, the location and length of the data cache module to be flushed, and the location and length of the data cache module to be assembled. Nodes are linked together in a linked list, and each node points to a DRAM address corresponding to the written data divided into different data regions.

[0135] Similarly, the process of assigning each smallest write unit in the written data to the data cache set of the data cache module to be combined is also achieved through a node data structure.

[0136] It is understandable that dividing the written data into the data cache module to be flushed and the data cache module to be combined, as well as dividing each smallest write unit in the written data into the data cache set of the data cache module to be combined, does not involve copying memory. What changes is the mapping relationship of the written data ownership. Flushing or combining data is achieved by looking up the information of these nodes.

[0137] Step S405: Flush the data in the data cache module to be flushed to the flash memory medium, or combine the N smallest write units in the data cache module to be combined into a flush unit, and flush the flush unit to the data cache module to be flushed or the flash memory medium.

[0138] Specifically, the size of the down-flush unit is equal to the addressing granularity of the physical address, and the data granularity of the data cache module to be down-flush is also equal to the addressing granularity of the physical address. The data in the data cache module to be down-flush is down-flushed to the flash memory medium. Alternatively, the N smallest write units belonging to different data cache sets in the data cache module to be combined are combined into a down-flush unit, and the down-flush unit is down-flushed to the data cache module to be down-flush or the flash memory medium.

[0139] For example: the data granularity of the smallest write unit is 4K, the addressing granularity of the logical address (LMA) is 4K, N=2, the addressing granularity of the physical address (PMA) is 8K, the data granularity of the data cache module to be combined is 4K, the data granularity of the data cache module to be flushed is 8K, the data cache module to be combined includes set 0 and set 1, the 8K data in the data cache module to be flushed is flushed to the flash memory medium, or, take one smallest write unit from each of set 0 and set 1 in the data cache module to be combined to form a flush unit, the data granularity of the flush unit is 8K, and the flush unit is flushed to the data cache module to be flushed or the flash memory medium.

[0140] Alternatively, the data granularity of the smallest write unit is 4K, the addressing granularity of the logical address (LMA) is 4K, N=4, the addressing granularity of the physical address (PMA) is 16K, the data granularity of the data cache module to be combined is 4K, the data granularity of the data cache module to be flushed is 16K, and the data cache module to be combined includes set 0, set 1, set 2, and set 3. The 16K data in the data cache module to be flushed is flushed to the flash memory medium. Alternatively, one smallest write unit is taken from each of set 0, set 1, set 2, and set 3 in the data cache module to be combined to form a flush unit with a data granularity of 16K, and the flush unit is flushed to the data cache module to be flushed or the flash memory medium.

[0141] It is understandable that after the flash unit is flashed to the data cache module, the data cache module will then flash the flash unit to the flash memory medium.

[0142] In this embodiment, the method further includes combining N smallest write units in the data cache module to be combined into a brush unit, and brushing the brush unit to the data cache module to be brushed or the flash memory medium.

[0143] The data buffer module is divided into several data buffer units. The data buffer module then combines several data buffer units into the minimum data volume corresponding to the flash memory medium, so that several data buffer units can be flashed to the flash memory medium.

[0144] like Figure 7 As shown, in the data cache module to be combined, N smallest write units are combined into a brush unit, and the brush unit is assigned to the data cache module to be brushed. The data cache module to be brushed then brushes the brush unit to the flash memory medium.

[0145] Specifically, the minimum data size corresponding to the flash memory medium is related to the type of flash memory medium. For example, if the type of flash memory medium is TLC flash memory, the minimum data size corresponding to the flash memory medium is the data size of 3 data pages. In this case, several brush units need to be combined to form a minimum data size in order to brush the minimum data size into the flash memory medium.

[0146] Understandably, for some flash memory types, such as TLC flash memory, multiple data pages are typically required to be written together. Therefore, when data is flushed to the flash memory medium, the cache module to be flushed needs to gather enough data to meet the requirements of the flash memory medium before flushing. In other words, it is necessary to gather the data from multiple data pages.

[0147] In this embodiment of the application, the method further includes:

[0148] When data is written to the flash memory from the host, the mapping table from logical address to physical address is updated.

[0149] In the mapping table from logical address to physical address, N logical addresses correspond to one physical address.

[0150] It is understandable that, since the addressing granularity of physical address = N * addressing granularity of logical address, where N is a positive integer and N≥2, N logical addresses in the mapping table from logical address to physical address correspond to one physical address.

[0151] Please refer to the following: Figure 13 , Figure 13 This is a schematic diagram of a data reading process provided in an embodiment of this application;

[0152] like Figure 13 As shown, the data reading process includes:

[0153] Step S1301: Obtain the read request sent by the host;

[0154] Specifically, a read request includes the address number corresponding to the Logical Block Address (LBA). If the capacity of the flash memory device is N*4K (N is a positive integer and N≥2), if the sector format (i.e., the smallest write unit) is 4K, then the address number of the Logical Block Address (LBA) is 1 to N; if the sector format (i.e., the smallest write unit) is 512B, then the address number of the Logical Block Address (LBA) is 0 to 8*N.

[0155] Step S1302: Determine the address number of the logical address corresponding to the logical block address based on the address number corresponding to the logical block address;

[0156] Specifically, when the addressing granularity of the logical address (LMA) is 4K, if the addressing granularity of the logical block address (LBA) is also 4K, then the address number corresponding to the logical block address (LBA) is equal to the address number of the logical address (LMA); if the addressing granularity of the logical block address (LBA) is 512B, then the address number of the logical address (LMA) is equal to the address number corresponding to the logical block address (LBA) / 8.

[0157] For example: when the addressing granularity of the logical address (LMA) is 4K, the addressing granularity of the logical block address (LBA) is 4K, and the address number corresponding to the logical block address (LBA) is 11, the address number of the logical address (LMA) = the address number corresponding to the logical block address (LBA) = 11.

[0158] Step S1303: Based on the address number of the logical address, query the mapping table from logical address to physical address to determine the physical address corresponding to the logical address;

[0159] Specifically, the mapping table from logical address to physical address includes the mapping relationship between the address number of the logical address and the address number of the corresponding physical address.

[0160] For example, if the logical address (LMA) is numbered 11, we look up the mapping table from logical address to physical address to determine the physical address (PMA) corresponding to the logical address (LMA) with address number 11. Here, the addressing granularity of the physical address (PMA) = N * the addressing granularity of the logical address (LMA), where N is a positive integer and N ≥ 2. In other words, N logical address (LMA) address numbers correspond to one physical address (PMA) address number.

[0161] Step S1304: Perform a modulo operation on the address number of the logical address to determine the modulo result corresponding to the address number of the logical address;

[0162] Specifically, the address number of the logical address (LMA) is modulo N to determine the remainder result corresponding to the address number of the logical address. There are N possible remainder results corresponding to the address number of the logical address (LMA), where N = addressing granularity of physical address (PMA) / addressing granularity of logical address (LMA), and N is a positive integer and N≥2.

[0163] For example, the addressing granularity of a logical address (LMA) is 4K, N=2, and the addressing granularity of a physical address (PMA) is 8K. The remainder result has two possibilities: 0 and 1. If the address number of the logical address (LMA) is LMA=11, then performing a remainder operation with 11 divided by 2 yields a remainder of 1; if the address number of the logical address (LMA) is LMA=4, then performing a remainder operation with 4 divided by 2 yields a remainder of 0.

[0164] Alternatively, the addressing granularity of the logical address (LMA) is 4K, N=3, and the addressing granularity of the physical address (PMA) is 12K. The remainder result has three possibilities: 0, 1, and 2. If the address number of the logical address (LMA) is LMA=10, then taking the remainder of 10 divided by 3 yields a remainder of 1; if the address number of the logical address (LMA) is LMA=6, then taking the remainder of 6 divided by 3 yields a remainder of 0; if the address number of the logical address (LMA) is LMA=2, then taking the remainder of 2 divided by 3 yields a remainder of 2.

[0165] Alternatively, the addressing granularity of the logical address (LMA) is 4K, N=4, and the addressing granularity of the physical address (PMA) is 16K. The remainder result has four possible values: 0, 1, 2, and 3. If the address number of the logical address (LMA) is LMA=11, then taking the remainder of 11 divided by 4 yields a remainder of 3; if the address number of the logical address (LMA) is LMA=10, then taking the remainder of 10 divided by 4 yields a remainder of 2; if the address number of the logical address (LMA) is LMA=9, then taking the remainder of 9 divided by 4 yields a remainder of 1; and if the address number of the logical address (LMA) is LMA=8, then taking the remainder of 8 divided by 4 yields a remainder of 0.

[0166] Step S1305: Based on the remainder result corresponding to the address number of the logical address, determine the location of the data corresponding to the logical address in the physical address, so as to read the data corresponding to the logical address.

[0167] Specifically, since the addressing granularity of a physical address = N * the addressing granularity of a logical address, where N is a positive integer and N≥2, one physical address corresponds to N logical addresses. The order of the data corresponding to the logical address in the physical address is the same as the order of the remainder result of the address number of the logical address in all remainder results. For example, each position of the physical address corresponds to a 4K data.

[0168] For example: when the address granularity of the logical address (LMA) is 4K, N=2, and the address granularity of the physical address (PMA) is 8K, and the remainder result has two possibilities: 0 and 1, the address number of the logical address (LMA) is LMA=4, and the remainder result is 0, which is the first position in the order of all remainder results. Therefore, the data corresponding to LMA=4 is located in the first 4K position of the physical address. The address number of the logical address (LMA) is LMA=11, and the remainder result is 1, which is the second position in the order of all remainder results. Therefore, the data corresponding to LMA=11 is located in the second position of the physical address.

[0169] Alternatively, when the address granularity of the logical address (LMA) is 4K, N=3, and the address granularity of the physical address (PMA) is 12K, and the remainder result has three possibilities: 0, 1, and 2, the logical address (LMA) with address number LMA=6 has a remainder result of 0, which is the first position in the order of all remainder results, so the data corresponding to LMA=6 is in the first position in the physical address; the logical address (LMA) with address number LMA=10 has a remainder result of 1, which is the second position in the order of all remainder results, so the data corresponding to LMA=10 is in the second position in the physical address; and the logical address (LMA) with address number LMA=2 has a remainder result of 2, which is the third position in the order of all remainder results, so the data corresponding to LMA=2 is in the third position in the physical address.

[0170] Alternatively, when the address granularity of the logical address (LMA) is 4K, N=4, the address granularity of the physical address (PMA) is 16K, and the remainder result has four possible values: 0, 1, 2, and 3, the logical address (LMA) with address number LMA=8 has a remainder result of 0, which is the first position in the order of all remainder results, so the data corresponding to LMA=8 is in the first position of the physical address; the logical address (LMA) with address number LMA=9 has a remainder result of 1, which is the second position in the order of all remainder results, so the data corresponding to LMA=9 is in the second position of the physical address; the logical address (LMA) with address number LMA=10 has a remainder result of 2, which is the third position in the order of all remainder results, so the data corresponding to LMA=10 is in the third position of the physical address; and the logical address (LMA) with address number LMA=11 has a remainder result of 3, which is the fourth position in the order of all remainder results, so the data corresponding to LMA=11 is in the fourth position of the physical address.

[0171] Furthermore, after determining the location of the data corresponding to the logical address in the physical address, the data at that location in the physical address is read.

[0172] In this embodiment, by querying the mapping table from logical address to physical address based on the address number of the logical address, the physical address corresponding to the logical address is determined, and the position of the data corresponding to the logical address in the physical address is determined based on the remainder result corresponding to the address number of the logical address. This application can quickly read data and is more efficient.

[0173] Please refer to the following: Figure 14 , Figure 14 This is a schematic diagram of a waste recycling process provided in an embodiment of this application;

[0174] In this embodiment, since flash memory cannot be overwritten in its original location, when a user updates data, the firmware must find another flash memory space to write the new data. This causes the original flash memory space data to expire and become garbage. Therefore, garbage collection is needed to erase blocks so that the invalid space can be reused. Garbage collection is the process of reading out the valid data on a flash memory block, rewriting it, and then erasing the flash memory block to obtain a new usable flash memory block.

[0175] like Figure 14 As shown, the waste recycling process includes:

[0176] Step S141: Establish a mapping table from physical address to logical address;

[0177] Specifically, the Physical to Logical (P2L) mapping table is a table where one physical address (PMA) corresponds to N logical addresses (LMA). This P2L mapping table includes the mapping relationship between the address number of the physical address (PMA) and the address number of the corresponding logical address (LMA). This P2L mapping table is updated together with the logical address to physical address mapping table when data is written.

[0178] In this embodiment, the physical address to logical address mapping table is not fully cached in DRAM. After a flash memory block is full, the P2L table of that flash memory block is recorded in the "metadata area" of the flash memory medium. The "metadata area" can be a portion of the flash memory block's space that occupies the data, or it can be a physical area specifically partitioned from other flash memory media areas of the flash memory device.

[0179] Please refer to the following: Figure 15 , Figure 15 This is a schematic diagram of a mapping table from physical address to logical address provided in an embodiment of this application;

[0180] In the embodiments of this application, when the addressing granularity of the logical address (LMA) is 4K, N=2, and the addressing granularity of the physical address (PMA) is 8K, one physical address (PMA) in the mapping table from physical address to logical address corresponds to two logical addresses (LMA), that is, the address number of one physical address (PMA) corresponds to the address number of two logical addresses (LMA).

[0181] like Figure 15 As shown, physical address PMA0 with address number 0 corresponds to logical address LMA3 with address number 3 and logical address LMA0 with address number 0. Physical address PMA1 with address number 1 corresponds to logical address LMA2 with address number 2 and logical address LMA5 with address number 5. Physical address PMA2 with address number 2 corresponds to logical address LMA6 with address number 6 and logical address LMA9 with address number 9. The data corresponding to LMA0, LMA2, and LMA6 are located in the first position of PMA0, PMA1, and PMA2, ​​respectively, and the data corresponding to LMA3, LMA5, and LMA9 are located in the second position of PMA0, PMA1, and PMA2, ​​respectively.

[0182] Please refer to the following: Figure 16 , Figure 16 This is a schematic diagram of another physical address to logical address mapping table provided in an embodiment of this application;

[0183] In the embodiments of this application, when the addressing granularity of the logical address (LMA) is 4K, N=3, and the addressing granularity of the physical address (PMA) is 12K, one physical address (PMA) in the mapping table of physical to logical address (P2L) corresponds to three logical addresses (LMA), that is, the address number of one physical address (PMA) corresponds to the address number of three logical addresses (LMA).

[0184] like Figure 16 As shown, physical address PMA0 with address number 0 corresponds to logical address LMA0 with address number 0, logical address LMA4 with address number 4, and logical address LMA2 with address number 2. Physical address PMA1 with address number 1 corresponds to logical address LMA3 with address number 3, logical address LMA7 with address number 7, and logical address LMA5 with address number 5. Physical address PMA2 with address number 2 corresponds to logical address LMA6 with address number 6, logical address LMA10 with address number 10, and logical address LMA11 with address number 11.

[0185] Among them, the data corresponding to LMA0, LMA3, and LMA6 are located in the first position of PMA0, PMA1, and PMA2, ​​respectively; the data corresponding to LMA4, LMA7, and LMA10 are located in the second position of PMA0, PMA1, and PMA2, ​​respectively; and the data corresponding to LMA2, LMA5, and LMA11 are located in the third position of PMA0, PMA1, and PMA2, ​​respectively.

[0186] Please refer to the following: Figure 17 , Figure 17 This is a schematic diagram of another physical address to logical address mapping table provided in the embodiments of this application;

[0187] In the embodiments of this application, when the addressing granularity of the logical address (LMA) is 4K, N=4, and the addressing granularity of the physical address (PMA) is 16K, one physical address (PMA) in the mapping table of physical to logical address (P2L) corresponds to 4 logical addresses (LMA), that is, the address number of one physical address (PMA) corresponds to the address number of 4 logical addresses (LMA).

[0188] like Figure 17As shown, physical address PMA0 with address number 0 corresponds to logical address LMA0 with address number 0, logical address LMA1 with address number 1, logical address LMA2 with address number 2, and logical address LMA3 with address number 3. Physical address PMA1 with address number 1 corresponds to logical address LMA4 with address number 4, logical address LMA5 with address number 5, logical address LMA6 with address number 6, and logical address LMA7 with address number 7. Physical address PMA2 with address number 2 corresponds to logical address LMA8 with address number 8, logical address LMA9 with address number 9, logical address LMA10 with address number 10, and logical address LMA11 with address number 11.

[0189] Specifically, the data corresponding to LMA0, LMA4, and LMA8 are located in the first position of PMA0, PMA1, and PMA2, ​​respectively; the data corresponding to LMA1, LMA5, and LMA9 are located in the second position of PMA0, PMA1, and PMA2, ​​respectively; the data corresponding to LMA2, LMA6, and LMA10 are located in the third position of PMA0, PMA1, and PMA2, ​​respectively; and the data corresponding to LMA3, LMA7, and LMA11 are located in the fourth position of PMA0, PMA1, and PMA2, ​​respectively.

[0190] Step S142: Compare the mapping table from logical address to physical address with the mapping table from physical address to logical address to determine whether the data corresponding to the logical address is valid or invalid data;

[0191] Understandably, during garbage collection, there may be scenarios where some 4K data in a physical address (PMA) is valid. In this case, it is necessary to compare the mapping table from logical address to physical address with the mapping table from physical address to logical address to determine which 4K data in the physical address (PMA) is valid (not combined with other data and written to other locations).

[0192] For details, please refer to [link / reference]. Figure 18 , Figure 18 yes Figure 14 A detailed flowchart of step S142;

[0193] like Figure 18 As shown, step S142: Compare the mapping table from logical address to physical address with the mapping table from physical address to logical address to determine whether the data corresponding to the logical address is valid or invalid data, including:

[0194] Step S1421: Traverse the mapping table from physical address to logical address to obtain the first physical address;

[0195] Specifically, the first physical address corresponds to N logical addresses, where N satisfies: the addressing granularity of the physical address = N * the addressing granularity of the logical address, where N is a positive integer and N≥2.

[0196] Step S1422: Based on the mapping table from physical address to logical address, query each first logical address corresponding to the first physical address;

[0197] Specifically, if the addressing granularity of the logical address (LMA) is 4K and N=2, and the addressing granularity of the physical address (PMA) is 8K, then the first physical address PMA0 corresponds to 2 first logical addresses (LMA). Based on the mapping table from physical address to logical address, each first logical address corresponding to the first physical address is queried.

[0198] Alternatively, if the addressing granularity of the logical address (LMA) is 4K and N=3, and the addressing granularity of the physical address (PMA) is 12K, then the first physical address PMA0 corresponds to 3 first logical addresses (LMA). Based on the mapping table from physical address to logical address, each first logical address corresponding to the first physical address is queried.

[0199] Alternatively, if the addressing granularity of the logical address (LMA) is 4K and N=4, and the addressing granularity of the physical address (PMA) is 16K, then the first physical address PMA0 corresponds to 4 first logical addresses (LMA). Based on the mapping table from physical address to logical address, each first logical address corresponding to the first physical address is queried.

[0200] Step S1423: Based on each first logical address, query the mapping table from logical address to physical address to obtain the second physical address corresponding to each first logical address;

[0201] For example, the addressing granularity of logical address (LMA) is 4K, N=2, and the addressing granularity of physical address (PMA) is 8K. The first physical address PMA0 corresponds to two first logical addresses LMA0 and LMA3. By querying the mapping table from logical address to physical address, we can obtain the second physical address PMA0 corresponding to LMA0 and the second physical address PMA2 corresponding to LMA3.

[0202] Alternatively, the addressing granularity of the logical address (LMA) is 4K, N=3, and the addressing granularity of the physical address (PMA) is 12K. The first physical address PMA0 corresponds to three first logical addresses LMA0, LMA4 and LMA2. By querying the mapping table from logical address to physical address, we can obtain the second physical address PMA0 corresponding to LMA0, the second physical address PMA0 corresponding to LMA4, and the second physical address PMA0 corresponding to LMA2.

[0203] Alternatively, the addressing granularity of the logical address (LMA) is 4K, N=4, and the addressing granularity of the physical address (PMA) is 16K. The first physical address PMA0 corresponds to four first logical addresses LMA0, LMA1, LMA2 and LMA3. By querying the mapping table from logical address to physical address, we can obtain the second physical address PMA0 corresponding to LMA0, the second physical address PMA1 corresponding to LMA1, the second physical address PMA2 corresponding to LMA2, and the second physical address PMA3 corresponding to LMA3.

[0204] Step S1424: If the second physical address is the same as the first physical address, then determine that the data corresponding to the first logical address is valid data;

[0205] For example: the addressing granularity of logical address (LMA) is 4K, N=2, the addressing granularity of physical address (PMA) is 8K, the first physical address PMA0 corresponds to two first logical addresses LMA0 and LMA3, the second physical address corresponding to LMA0 is PMA0, and the second physical address PMA0 is the same as the first physical address PMA0, then the data corresponding to the first logical address LMA0 is determined to be valid data.

[0206] Alternatively, the addressing granularity of the logical address (LMA) is 4K, N=3, and the addressing granularity of the physical address (PMA) is 12K. The first physical address PMA0 corresponds to three first logical addresses LMA0, LMA4, and LMA2. The second physical address corresponding to LMA0 is PMA0, the second physical address corresponding to LMA4 is PMA0, and the second physical address corresponding to LMA2 is PMA0. The second physical address PMA0 corresponding to each logical address is the same as the first physical address PMA0. Therefore, the data corresponding to the first logical addresses LMA0, LMA4, and LMA2 are all valid data.

[0207] Alternatively, the addressing granularity of the logical address (LMA) is 4K, N=4, and the addressing granularity of the physical address (PMA) is 16K. The first physical address PMA0 corresponds to four first logical addresses LMA0, LMA1, LMA2 and LMA3. The second physical address corresponding to LMA0 is PMA0. If the second physical address PMA0 is the same as the first physical address PMA0, then the data corresponding to the first logical address LMA0 is determined to be valid data.

[0208] Step S1425: If the second physical address is different from the first physical address, then the data corresponding to the logical address is determined to be invalid data.

[0209] For example: the addressing granularity of logical address (LMA) is 4K, N=2, the addressing granularity of physical address (PMA) is 8K, the first physical address PMA0 corresponds to two first logical addresses LMA0 and LMA3, the second physical address corresponding to LMA3 is PMA2, ​​the second physical address PMA2 is different from the first physical address PMA0, then the data corresponding to the first logical address LMA3 is determined to be invalid data.

[0210] Alternatively, the addressing granularity of the logical address (LMA) is 4K, N=4, and the addressing granularity of the physical address (PMA) is 16K. The first physical address PMA0 corresponds to four first logical addresses LMA0, LMA1, LMA2, and LMA3. The second physical address corresponding to LMA1 is PMA1, the second physical address corresponding to LMA2 is PMA2, ​​and the second physical address corresponding to LMA3 is PMA3. Since the second physical addresses PMA1, PMA2, ​​and PMA3 are all different from the first physical address PMA0, it is determined that the data corresponding to the first logical addresses LMA1, LMA2, and LMA3 are all invalid data.

[0211] Please refer to the following: Figure 19 and Figure 20 , Figure 19 This is a detailed flowchart illustrating a method for finding valid data, as provided in an embodiment of this application. Figure 20 This is a schematic diagram of a P2L table and an L2P table provided in an embodiment of this application;

[0212] Specifically, Figure 19 This is a detailed flowchart for finding valid data when the addressing granularity of the logical address (LMA) is 4K, N=2, and the addressing granularity of the physical address (PMA) is 8K. In the diagram, X, Y, M, and N are aliases for address numbers, representing "a certain one".

[0213] like Figure 19 As shown, the detailed process for finding valid data includes:

[0214] Step S1901: Traverse the mapping table from physical address to logical address to obtain the first physical address PMA_X, i.e., the first physical address X;

[0215] Specifically, such as Figure 20 As shown, the first physical address PMA_X is PMA0.

[0216] Step S1902: Based on the mapping table from physical address to logical address, query the first logical address LMA_X and LMA_Y corresponding to the first physical address, that is, the first logical address X and the first logical address Y;

[0217] Specifically, such as Figure 20As shown in the P2L table, the first logical address LMA_X corresponding to the first physical address PMA0 is LMA3, and LMA_Y is LMA0.

[0218] Step S1903: Based on LMA_X and LMA_Y, query the mapping table from logical address to physical address to obtain the second physical addresses PMA_M and PMA_N corresponding to LMA_X and LMA_Y respectively;

[0219] Specifically, based on the first logical address X and the first logical address Y, the L2P table is queried to obtain the second physical address M (PMA_M) corresponding to the first logical address X (LMA_X) and the second physical address N (PMA_N) corresponding to the first logical address Y (LMA_Y).

[0220] Specifically, such as Figure 20 As shown in the L2P table, the second physical address PMA_M corresponding to LMA3 is PMA0, and the second physical address PMA_M corresponding to LMA0 is PMA5.

[0221] Step S1904: Determine whether PMA_M and PMA_X are the same;

[0222] Specifically, determine whether the second physical address M is the same as the first physical address X.

[0223] If so, proceed to step S1905: Determine that the data corresponding to LMA_X is valid data;

[0224] If not, proceed to step S1909: Determine that the data corresponding to LMA_X is invalid data;

[0225] Specifically, the second physical address PMA_M corresponding to LMA3 is PMA0, and the first physical address PMA_X is PMA0. Since they are the same, proceed to step S1905.

[0226] Step S1905: Determine that the data corresponding to LMA_X is valid data;

[0227] Specifically, the data corresponding to LMA3 is determined to be valid data.

[0228] Step S1906: Determine whether PMA_N and PMA_X are the same;

[0229] Specifically, determine whether the second physical address N (PMA_N) is the same as the first physical address PMA_X.

[0230] If so, proceed to step S1907: Determine that the data corresponding to LMA_Y is valid data;

[0231] If not, proceed to step S1910: Determine that the data corresponding to LMA_Y is invalid data;

[0232] Specifically, the second physical address PMA_M corresponding to LMA0 is PMA5, and the first physical address PMA_X is PMA0. Since the two are different, proceed to step S1909 to determine that the data corresponding to LMA0 is invalid data.

[0233] It is understandable that if the first physical address is different from the second physical address, it means that the data corresponding to that logical address has been written to another location and is not on the current flash memory block.

[0234] Step S1907: Determine that the data corresponding to LMA_Y is valid data;

[0235] Step S1908: Has the traversal ended?

[0236] Specifically, it determines whether to traverse each logical address and physical address corresponding to the P2L table in the current flash memory block.

[0237] If so, the process ends;

[0238] If not, proceed to step S1901: traverse the mapping table from physical address to logical address and obtain the first physical address PMA_X;

[0239] Specifically, obtain the next physical address from the mapping table of physical addresses to logical addresses, and perform similar operations as described above until the P2L table of the current flash block is traversed.

[0240] In this embodiment of the application, the flash memory device further includes a garbage collection cache module, and the method further includes:

[0241] Based on the addressing granularity of logical addresses and physical addresses, the garbage collection cache module is divided into a garbage collection data cache module and a data cache module with matching mapping granularity. The garbage collection data cache module includes N data cache sets, and each data cache set corresponds to a set number.

[0242] Specifically, the data granularity of the garbage collection data cache module is the same as the addressing granularity of the logical address, the data granularity of the matching mapping granularity data cache module is the same as the addressing granularity of the physical address, and the garbage collection data cache module has N data cache sets, where N satisfies: physical address addressing granularity = N * logical address addressing granularity, where N is a positive integer and N≥2.

[0243] Specifically, during the garbage collection process, the valid data read is first classified as discrete data into the garbage collection data cache module. This garbage collection data cache module includes N data cache sets, each of which corresponds to a set number. The valid data is classified by taking the remainder of N according to the address number of the logical address (LMA) corresponding to the valid data, and using the remainder result as the set number.

[0244] For example, when the addressing granularity of the logical address (LMA) is 4K and N=2, and the addressing granularity of the physical address (PMA) is 8K, the garbage collection data cache module includes two data cache sets, set 0 and set 1.

[0245] Alternatively, when the addressing granularity of the logical address (LMA) is 4K, N=4, and the addressing granularity of the physical address (PMA) is 16K, the garbage collection data cache module includes four data cache sets: set 0, set 1, set 2, and set 3.

[0246] In this embodiment, the method for partitioning the data cache set in the garbage collection data cache module is similar to the method for partitioning the data cache set in the data cache module to be combined described above, and will not be repeated here. The schematic diagram of the data cache set in the garbage collection data cache module is also similar to... Figure 10 The diagram is similar to the data cache set of the data cache module to be combined in the middle.

[0247] Step S143: If the data corresponding to the logical address is valid data, then move the valid data.

[0248] In this embodiment of the application, data transfer of valid data specifically includes:

[0249] Obtain a minimum write unit from each of the N data cache sets in the garbage collection data cache module, and combine the N minimum write units into a flush unit;

[0250] The brush unit is assigned to a data cache module with matching mapping granularity, and the data cache module with matching mapping granularity brushes the brush unit to the flash memory medium.

[0251] Specifically, the data granularity of the brush unit is the same as that of the data caching module that matches the mapping granularity.

[0252] Please refer to the following: Figure 21 , Figure 21 This is a schematic diagram of a waste recycling method provided in an embodiment of this application;

[0253] like Figure 21As shown, the garbage collection module includes a read data module, a write data module, and a garbage collection cache module. The garbage collection cache module includes a garbage collection data cache module and a data cache module that matches the mapping granularity.

[0254] The waste recycling process includes:

[0255] (1) The data read module reads data from the flash memory medium and stores the read data in the garbage collection cache module;

[0256] (2) The garbage collection data cache module in the garbage collection cache module obtains a minimum write unit for each of the N data cache sets and combines the N minimum write units into a flush unit;

[0257] (3) The garbage collection data cache module divides the flush unit into the data cache module with matching mapping granularity, and the data cache module with matching mapping granularity forwards the flush unit to the write data module;

[0258] (4) The write data module writes the brush unit to the flash memory medium.

[0259] Please refer to the following: Figure 22 , Figure 22 This is a schematic diagram of another data cache set provided in an embodiment of this application;

[0260] Assuming the logical address (LMA) addressing granularity is 4K, N=2, and the physical address (PMA) addressing granularity is 8K, then... Figure 22 As shown, the garbage collection data cache module includes two data cache sets, set 0 and set 1. It obtains a minimum write unit from set 0 and set 1 respectively. For example, it obtains the minimum write unit corresponding to logical address LMA4 from set 0 and the minimum write unit corresponding to logical address LMA1 from set 1. The two minimum write units are combined into a flush unit. The flush unit is assigned to the data cache module with matching mapping granularity. The data cache module with matching mapping granularity flushes the flush unit to the flash memory medium and updates the L2P table. The above steps are repeated to finally complete the garbage collection of the entire flash memory block.

[0261] It should be noted that the structure or function of the garbage collection data caching module is similar to the structure or function of the data caching module to be combined mentioned in the above embodiments, and the structure or function of the data caching module for matching mapping granularity is similar to the structure or function of the data caching module to be flushed mentioned in the above embodiments. For details, please refer to the data caching module to be combined or the data caching module to be flushed mentioned in the above embodiments, which will not be repeated here.

[0262] In this embodiment, the specific method for moving valid data during garbage collection is similar to the method described above of combining N smallest write units in the data cache module to be combined into a brush unit and brushing the brush unit to the flash memory medium, and will not be repeated here.

[0263] In this embodiment, valid data is divided into different sets of garbage collection data cache modules, and a minimum write unit is obtained from each of the N data cache sets of the garbage collection data cache module. The N minimum write units are combined into a flush unit. In the process of dividing the flush unit into data cache modules with matching mapping granularity, the only thing that is changed is the mapping relationship of the valid data, and memory copying is not involved.

[0264] Step S144: If the data corresponding to the logical address is invalid, then the invalid data will not be moved.

[0265] Specifically, if the data corresponding to the logical address is invalid, it means that the data has been written to another location and is not on the current flash memory block. In this case, the invalid data will not be moved.

[0266] In this embodiment, a data management method for a flash memory device is provided. The flash memory device includes a flash memory medium and a cache module. The method includes: establishing a mapping table from logical addresses to physical addresses, wherein the addressing granularity of the physical address = N * the addressing granularity of the logical address, where N is a positive integer and N≥2; dividing the cache module into a data cache module to be flushed and a data cache module to be combined, wherein the data granularity of the data cache module to be combined is equal to the addressing granularity of the logical address, and the data granularity of the data cache module to be flushed is equal to the addressing granularity of the physical address; obtaining a write request sent by the host, wherein the write request includes write data from the host, wherein the write data includes several minimum write units; dividing the write data into the data cache module to be flushed and / or the data cache module to be combined according to the size of the write data; flushing the data in the data cache module to be flushed to the flash memory medium, or combining the N minimum write units in the data cache module to be combined into a flush unit and flushing the flush unit to the flash memory medium, wherein the size of the flush unit is equal to the addressing granularity of the physical address.

[0267] By using the addressing granularity of physical address = N * addressing granularity of logical address, where N is a positive integer and N≥2, the data granularity of the data cache module to be combined is equal to the addressing granularity of logical address, and the data granularity of the data cache module to be flushed is equal to the addressing granularity of physical address, this application can improve the performance of flash memory devices in random write scenarios, without needing to write data after reading logical address, thus avoiding the introduction of additional write amplification and extending the lifespan of flash memory devices.

[0268] Please refer to the following: Figure 23 , Figure 23 This is a schematic diagram of the structure of a flash memory device provided in an embodiment of this application;

[0269] like Figure 23 As shown, the flash memory device 230 includes: one or more processors 231 and memory 232. Wherein, Figure 23 Take the 231 processor as an example.

[0270] The processor 231 and the memory 232 can be connected via a bus or other means. Figure 23 Taking the example of a connection between China and Israel via a bus.

[0271] The processor 231 is configured to provide computing and control capabilities to control the flash memory device 230 to perform corresponding tasks, such as controlling the flash memory device 230 to perform the data management method of the flash memory device in any of the above method embodiments.

[0272] Processor 231 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), a hardware chip, or any combination thereof; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The aforementioned PLD can be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a general-purpose array logic (GAL), or any combination thereof.

[0273] Memory 232, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer-executable programs, and modules, such as the program instructions / modules corresponding to the data management method of the flash memory device in the embodiments of this application. Processor 231 can implement the data management method of the flash memory device in any of the above method embodiments by running the non-transitory software programs, instructions, and modules stored in memory 232. Specifically, memory 232 may include volatile memory (VM), such as random access memory (RAM); memory 232 may also include non-volatile memory (NVM), such as read-only memory (ROM), flash memory, hard disk drive (HDD), solid-state drive (SSD), or other non-transitory solid-state storage devices; memory 232 may also include combinations of the above types of memory.

[0274] Memory 232 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 232 may optionally include memory remotely located relative to processor 231, and such remote memory may be connected to processor 231 via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0275] One or more modules are stored in memory 232. When executed by one or more processors 231, they perform the data management method of the flash memory device in any of the above method embodiments, for example, the method described above. Figure 4 The steps shown.

[0276] This application also provides a non-volatile computer storage medium storing computer-executable instructions that are executed by one or more processors. For example, the one or more processors can execute the data management method of the flash memory device in any of the above method embodiments, such as executing the data management method of the flash memory device in any of the above method embodiments, such as executing the steps described above.

[0277] The apparatus or device embodiments described above are merely illustrative. The unit modules described as separate components may or may not be physically separate, and the components shown as module units may or may not be physical units; that is, they may be located in one place or distributed across multiple network module units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0278] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented using software plus a general-purpose hardware platform, or of course, using hardware. Based on this understanding, the above technical solutions, in essence or the parts that contribute to the related technology, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., including several instructions for a computer device (which may be a personal computer, server, or network device, etc.) to execute the various embodiments or some parts of the embodiments.

[0279] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of this application as described above. For the sake of brevity, they are not provided in detail; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A data management method for a flash memory device, characterized in that, The flash memory device includes a flash memory medium and a cache module, and the method includes: Establish a mapping table from logical address to physical address, wherein the addressing granularity of the physical address = N * the addressing granularity of the logical address, where N is a positive integer and N≥2; The cache module is divided into a data cache module to be flushed and a data cache module to be combined. The data granularity of the data cache module to be combined is equal to the addressing granularity of the logical address, and the data granularity of the data cache module to be flushed is equal to the addressing granularity of the physical address. Obtain a write request sent by the host, wherein the write request includes the write data of the host, and the write data includes several minimum write units; Based on the size of the written data, the written data is divided into the data cache module to be flushed and / or the data cache module to be combined; The data in the data cache module to be flushed is flushed to the flash memory medium, or the N smallest write units in the data cache module to be combined are combined into a flush unit, and the flush unit is flushed to the data cache module to be flushed or the flash memory medium, wherein the size of the flush unit is equal to the addressing granularity of the physical address; The step of dividing the written data into the data cache module to be flushed and / or the data cache module to be combined, based on the size of the written data, includes: If the size of the written data is greater than the addressing granularity of the physical address, then the consecutive integer multiples of N of the smallest write units in the written data are allocated to the data to be flushed cache module, and the remaining data in the written data are allocated to the data to be combined cache module. If the size of the written data is equal to the addressing granularity of the physical address, then the written data is allocated to the data cache module to be flushed. If the size of the written data is smaller than the addressing granularity of the physical address, then the written data is allocated to the data cache module to be combined.

2. The method according to claim 1, characterized in that, The data cache module to be combined includes N data cache sets, each data cache set corresponding to a set number. If the size of the written data is smaller than the addressing granularity of the physical address, the written data is allocated to the data cache module to be combined, including: If the size of the written data is smaller than the addressing granularity of the physical address, perform a modulo operation on the address number corresponding to each smallest written unit in the written data to obtain the modulo result of the address number corresponding to each written unit. Based on the remainder result, each smallest write unit in the written data is assigned to the data cache set, wherein the remainder result of the address number of each smallest write unit assigned to the data cache set is equal to the set number.

3. The method according to claim 2, characterized in that, The step of performing a modulo operation on the address number corresponding to each smallest write unit in the written data to obtain the modulo result of the address number corresponding to each write unit includes: The address number corresponding to each smallest write unit in the written data is moduloed by N to obtain the remainder result of the address number corresponding to each write unit, wherein the value range of the remainder result is [0, N-1].

4. The method according to claim 1, characterized in that, The step of combining N smallest write units in the data cache module to be combined into a flush unit, and flushing the flush unit to the data cache module to be flushed or the flash memory medium, includes: The brush-down units are assigned to the data cache module to be brushed down. The data cache module then combines several brush-down units into the minimum data volume corresponding to the flash memory medium, so as to brush several brush-down units onto the flash memory medium.

5. The method according to any one of claims 1-4, characterized in that, The method further includes: When the data written by the host is brushed onto the flash memory medium, the mapping table from logical address to physical address is updated, wherein N logical addresses in the mapping table correspond to one physical address.

6. The method according to claim 5, characterized in that, The method further includes: Obtain a read request sent by the host, wherein the read request includes the address number corresponding to the logical block address; The address number of the logical address corresponding to the logical block address is determined based on the address number corresponding to the logical block address. Based on the address number of the logical address, query the mapping table from the logical address to the physical address to determine the physical address corresponding to the logical address; Perform a modulo operation on the address number of the logical address to determine the modulo result corresponding to the address number of the logical address; Based on the remainder result corresponding to the address number of the logical address, the position of the data corresponding to the logical address in the physical address is determined, so as to read the data corresponding to the logical address.

7. The method according to claim 1, characterized in that, The method further includes: Establish a mapping table from physical address to logical address, wherein one physical address in the mapping table corresponds to N logical addresses; By comparing the mapping table from logical address to physical address with the mapping table from physical address to logical address, it is determined whether the data corresponding to the logical address is valid or invalid data. If the data corresponding to the logical address is valid data, then the valid data is moved. If the data corresponding to the logical address is invalid, then the invalid data will not be moved.

8. The method according to claim 7, characterized in that, Determining whether the data corresponding to the logical address is valid or invalid includes: Traverse the mapping table from physical address to logical address to obtain the first physical address; Based on the mapping table from physical address to logical address, query each first logical address corresponding to the first physical address; Based on each of the first logical addresses, query the mapping table from the logical address to the physical address to obtain the second physical address corresponding to each of the first logical addresses; If the second physical address is the same as the first physical address, then the data corresponding to the first logical address is determined to be valid data; If the second physical address is different from the first physical address, then the data corresponding to the logical address is determined to be invalid data.

9. The method according to claim 7 or 8, characterized in that, The flash memory device further includes a garbage collection cache module, and the method further includes: Based on the addressing granularity of the logical address and the addressing granularity of the physical address, the garbage collection cache module is divided into a garbage collection data cache module and a data cache module with matching mapping granularity. The garbage collection data cache module includes N data cache sets, and each data cache set corresponds to a set number. The data transfer of the valid data specifically includes: Obtain a minimum write unit from each of the N data cache sets in the garbage collection data cache module, and combine the N minimum write units into a flush unit; The brush unit is assigned to the data cache module with matching mapping granularity, and the data cache module with matching mapping granularity brushes the brush unit to the flash memory medium.

10. A flash memory device, characterized in that, include: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform the data management method for a flash memory device as described in any one of claims 1-9.

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