Semiconductor memory devices

Abstract

The semiconductor memory device related to this invention includes: a memory cell array, forming a NOR-type memory cell array; an interleaved array having multiple columns and multiple rows, with variable resistor elements formed at the intersections of each column and each row; an entry gate disposed between the memory cell array and the interleaved array, connecting the selection bit lines of the memory cell array to the interleaved array based on a selection signal; and a row selection / signal processing unit. The row selection / signal processing unit includes: a row write unit for writing data read from the memory cell array to the selected row of the interleaved array; a row read unit for reading data from the selected row of the interleaved array; and a NOR write unit for writing at least the data read by the row read unit to the memory cell array. By including both a memory cell array and an interleaved array in the semiconductor memory device, the learning processing capability or efficiency can be improved.

Description

Technical Field

[0001] The present invention relates to a semiconductor memory device comprising an interleaved array and an array of NOR or NAND memory cells, and particularly to a semiconductor memory device that can be used as a neuromorphic device. Background Technology

[0002] Using variable resistance elements, synapses and neurons are structurally simulated, and interleaved arrays as AI (artificial intelligence) hardware are gradually becoming practical (e.g., Patent Document 1: JP 6818116 B1). Figure 1 This diagram illustrates an example of an interleaved array. The interleaved array includes: multiple column lines 1, multiple row lines 2, and variable resistor elements 3 connected at the intersections of the column lines 1 and row lines 2. The variable resistor elements 3 are non-volatile storage elements that store different resistance values ​​by applying voltage or current.

[0003] A synapse is a contact structure that develops between the output and input sides of a nerve to transmit information. It connects the axon terminal of the presynaptic cell to the dendrite of the postsynaptic cell. When the presynaptic and postsynaptic cells fire continuously at a high frequency, the transmission efficiency of the synapse increases. However, the binding strength changes simply by observing the firing time difference between the presynaptic and postsynaptic cells; this phenomenon is called "Spike Timing Dependent Plasticity" (STDP). When applying neural networks to interleaved arrays, STDP electrical signals can be written into variable resistive elements. For example, applying a surge signal Spre to a column line and a surge signal Spost to a row line results in the difference between the Spre / Spost signals generated by the presynaptic and postsynaptic cells being written into the variable resistive element, thus modulating the conductance of the variable resistive element (synaptic binding strength) (Patent Document 2: JP6899024B1).

[0004] When implementing neural networks using interleaved arrays, the resistance of the variable resistive elements in the interleaved array is adjusted according to the learning process. Figure 2 This is a block diagram illustrating the configuration of a synaptic array device with existing learning capabilities. The synaptic array device 10 includes: a flash memory 20 for storing learning data, an interleaved array 30, and a controller 40. The controller 40 reads learning data from the flash memory 20 and writes the read learning data into the interleaved array 30 to perform data learning on the variable resistor element. Additionally, the controller 40 reads learned data from the interleaved array 30 and writes the learned data into the flash memory 20.

[0005] In the existing synaptic array device 10, since data is read from flash memory and written to interleaved array 30, or learning data read from interleaved array 30 and written to flash memory 20, there is a problem of low data transmission efficiency and the AI ​​learning process is very time-consuming. Summary of the Invention

[0006] To address the problem of low data transmission efficiency in existing synaptic array devices, the present invention provides the following solution.

[0007] The present invention provides a semiconductor memory device, comprising: a memory cell array having a plurality of non-volatile memory cells arranged in rows and columns; an interleaved array having a plurality of columns and a plurality of rows, wherein variable resistor elements are formed at the intersections of each column and each row; a connection means disposed between the memory cell array and the interleaved array, connecting the selection bit line of the memory cell array to the interleaved array based on a selection signal; a row writing means for writing at least data read from the memory cell array to the selected row of the interleaved array; a row reading means for reading data from the selected row of the interleaved array; and a writing means for writing at least the data read by the row reading means to the memory cell array.

[0008] According to the present invention, by incorporating a memory cell array and an interleaved array into a semiconductor memory device, the learning processing capability or efficiency can be improved. Thus, a semiconductor memory device suitable for neuromorphic devices can be provided. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings:

[0010] Figure 1 This is a schematic diagram illustrating a typical example of an interleaved array.

[0011] Figure 2 This is a block diagram illustrating the structure of an existing synaptic array device.

[0012] Figure 3 This is a block diagram illustrating the configuration of a semiconductor memory device related to an embodiment of the present invention.

[0013] Figure 4 This is a schematic diagram illustrating the electrical connection relationship between the memory cell array and the interleaved array of a semiconductor memory device related to an embodiment of the present invention.

[0014] Figure 5 (A) and (B) are schematic diagrams illustrating the configuration of the row selection / signal processing unit in this embodiment.

[0015] Figure 6 (A) and (B) are schematic diagrams illustrating the configuration of the column selection / signal processing unit in this embodiment.

[0016] Figure 7 (A) and (B) are schematic diagrams illustrating the writing of an interleaved array through an embodiment of the present invention.

[0017] Figure 8 (A) and (B) are schematic diagrams illustrating the writing of an interleaved array through an embodiment of the present invention.

[0018] Figure 9 (A) and (B) are schematic diagrams illustrating the writing of a NOR memory cell array through an embodiment of the present invention.

[0019] Figure 10 This is a schematic diagram illustrating an example of an autoencoder that utilizes a neural network-like architecture.

[0020] Figure 11 This is a block diagram illustrating the configuration of the row writing unit related to the second embodiment of the present invention.

[0021] Figure 12 (A) and (B) are schematic diagrams illustrating a writing example of the row writing unit related to the second embodiment of the present invention.

[0022] Symbol explanation:

[0023] 1: Column line

[0024] 2: Line

[0025] 3: Variable resistor element

[0026] 10: Synaptic Array Device

[0027] 20: Flash memory

[0028] 30: Interleaved Array

[0029] 40: Controller

[0030] 100: Semiconductor memory devices

[0031] 110: NOR Memory Cell Array

[0032] 120: Address Buffer

[0033] 130:X Decoder

[0034] 140:Y decoder

[0035] 150: Input / output circuit

[0036] 160: Control Unit

[0037] 170: Entrance gate

[0038] 200: Interleaved Array

[0039] 210: Row Selection / Signal Processing Unit

[0040] 220: Column Selection / Signal Processing Unit

[0041] 230: Busbar

[0042] 300: NOR read unit

[0043] 310: Row Selection Unit

[0044] 320, 320A: Row Write Unit

[0045] 330: Line Reading Unit

[0046] 340: Data Selection Unit

[0047] 350: NOR write unit

[0048] 400: Column Selection Cell

[0049] 410: Column Write Unit

[0050] 420: Column Reading Unit

[0051] 430: Data Selection Unit

[0052] 500: Write pulse generation unit

[0053] 510: Surge signal generation unit

[0054] 512: Charging circuit

[0055] 514: Leakage circuit

[0056] 516: Output Circuit

[0057] 518: Reset Circuit

[0058] BL0~BLs: Bit lines

[0059] C0~Cn: Columns

[0060] GBL0~GBLm: Global Bit Line

[0061] Ma~Md: Storage unit

[0062] Q0~Q3: Select transistors

[0063] R0~Rn: column (row)

[0064] SEL: Selection signal

[0065] SL0~SLk: Source lines

[0066] VR, VR0~VR2: Variable resistive element

[0067] WL0~WLn: Word lines Detailed Implementation

[0068] The semiconductor memory device related to this invention relates to a non-volatile memory that combines a NOR-type or NAND-type flash memory with an interleaved array including variable resistive elements. In one embodiment, the semiconductor memory device comprises a stack between flash memory chips and interleaved array chips. In other embodiments, the semiconductor memory device stacks flash memory and interleaved array on the same chip.

[0069] The semiconductor memory device related to this invention can function as an AI memory or neuromorphic device with learning capabilities. A flash memory chip stores learning data, and the learning data read from the flash memory chip is written to an interleaved array chip. The interleaved array chip uses matrix calculations and other methods to write the learning data to a variable resistor element, thereby adjusting the resistance of the variable resistor element, i.e., learning the resistance. Furthermore, the data learned by the interleaved array chip is overwritten onto the flash memory chip, and the AI ​​controller uses the learning data overwritten on the flash memory chip.

[0070] Next, embodiments of the present invention will be described in detail with reference to the drawings. Figure 3 This is a block diagram illustrating the configuration of a semiconductor memory device 100 related to an embodiment of the present invention. The semiconductor memory device 100 of this embodiment includes: a NOR-type memory cell array 110; an address buffer 120 for holding addresses received by an input / output circuit 150; an X decoder 130 for selecting word lines of the memory cell array 110 based on column addresses; a Y decoder 140 for selecting bit lines and source lines of the memory cell array 110 based on row addresses; an input / output circuit 150 for receiving instructions, data, and addresses from the outside, or outputting data to the outside; a control unit 160 for controlling the overall operation of the device; an entry gate 170 disposed at the end of the memory cell array 110; an interleaved array 200 using variable resistor elements; a row selection / signal processing unit 210; a column selection / signal processing unit 220; and a bus 230.

[0071] A memory cell array 110, an address buffer 120, an X decoder 130, a Y decoder 140, an input / output circuit 150, a control unit, and an entry gate 170 constitute a NOR-type flash memory chip; an interleaved array 200, a row selection / signal processing unit 210, and a column selection / signal processing unit 220 constitute an interleaved array chip. In this embodiment, the interleaved array chip is stacked on the flash memory chip. The interleaved array 200 is configured on the memory cell array 110, the column selection / signal processing unit 220 is configured on the X decoder 130, and the row selection / signal processing unit 210 is configured on the Y decoder 140 and the entry gate 170. Signal transmission and reception between the two chips are performed through a bus 230. The storage capacity of the memory cell array 110 and the interleaved array 200 is not particularly limited; for example, the memory cell array 110 has 16MB, and the interleaved array 200 has 1MB.

[0072] Figure 4 This is a schematic diagram illustrating the electrical connections between a memory cell array and an interleaved array. The memory cell array 110 forms multiple memory cells in a row-column configuration. The drain regions of adjacent memory cells in the row direction are connected together, and these drain regions are connected to bit lines BL0, BL1, ..., BLr, BLs. Furthermore, the gates of each memory cell in the column direction are connected to word lines WL0, WL1, ..., WLn in the column direction, and the source regions of each memory cell in the column direction are connected to source lines SL0, SL1, ..., SLk in the column direction.

[0073] The memory cell includes a charge storage layer (e.g., oxide-nitride-oxide (ONO)) for storing charge, on which a conductive gate, such as polysilicon or metal, is located and connected to a word line. For example, when reading memory cell Ma, a positive voltage is applied to the select word line WL1, and the control unit 160 senses the current or voltage flowing between the select bit line BL0 and the select source line SL1. When writing (programming) memory cell Ma, a voltage is applied to the select word line WL1, and a voltage corresponding to the written data is applied to the select bit line BL0. Thermionic electrons flowing from the select bit line BL0 to the select source line SL1 are stored in the charge storage layer. However, the writing method can also be other than this; for example, by FN tunneling, the charge can be confined to the charge storage layer. Erasing memory cell Ma involves applying a voltage to the select word line WL1, for example, by injecting a thermionic hole into the charge storage layer, causing the charge stored in the charge storage layer to be discharged through FN tunneling. In addition, erasure can be performed on a segment basis rather than on a storage unit basis.

[0074] Each bit line of the memory cell array 110 is connected to the entry gate 170. The entry gate 170 is configured at the boundary between the memory cell array 110 and the row selection / signal processing unit 210 of the interleaved array chip. When accessing the interleaved array 200, the selection bit line BL of the memory cell array 110 is connected to the row selection / signal processing unit 210 through the global bit line GBL. Here, we assume that in the entry gate 170, the four bit lines of the memory cell array 110 are grouped together, and one of the four bit lines BL can be optionally connected to one global bit line GBL. For example, bit lines BL0, BL1, BL2, and BL3 are connected to one global bit line GBL through selection transistors Q0, Q1, Q2, and Q3. The selection transistors Q0, Q1, Q2, and Q3 can be optionally turned on by the selection signal SEL from the control unit 160 or the selection signal SEL generated by the row address.

[0075] Address buffer 120 receives addresses input from an external source and provides the received column and row addresses to X decoder 130 and Y decoder 140. X decoder 130 selects word lines based on the column address and applies the voltage corresponding to the operation (e.g., read, write, erase, etc.) to the selected word lines. Y decoder 140 selects bit lines and source lines based on the row address and applies the voltage corresponding to the operation (e.g., read, write, erase, etc.) to the selected bit lines and source lines.

[0076] The input / output circuit 150 receives instructions, addresses, data, etc. from the outside, or outputs data read from the storage unit array 110 to the outside. The instructions or data received by the input / output circuit 150 are provided to the control unit 160.

[0077] The control unit 160 controls the reading, writing, and erasing of the storage cell array 110 based on input instructions. Additionally, the control unit 160 corresponds to learning instructions used to instruct the interleaved array 200 to perform learning processing. When a learning instruction is input, based on the learning instruction, it writes data read from the storage cell array 110 to the interleaved array 200, or controls a write (programming) operation to write the data learned by the interleaved array 200 to the storage cell array 100.

[0078] The control unit 160 includes a sense amplifier SA, a write amplifier WA, a microcontroller, etc. The sense amplifier SA is used to sense data read from selected memory cells of the memory cell array 110, the write amplifier WA is used to write to the selected memory cells, and the microcontroller is used to control various operations. The microcontroller includes a ROM / RAM storing a program and a microprocessor that executes the program to control the operation of the semiconductor memory device 100.

[0079] Next, the interleaved array chip will be explained. Variable resistor elements VR are connected at the intersections of multiple columns R0, R1, ..., Rn and multiple rows C0, C1, ..., Cn in the interleaved array 200. The variable resistor elements VR store analog-level resistance values ​​based on the voltage or current applied to the selected column or row. For example, the variable resistor elements are made of transition metal oxides such as hafnium oxide (HfOx). When a write pulse is applied from one direction, the resistance is low; when a write pulse is applied from the opposite direction, the resistance is high. For example, if a write pulse is applied from row C0 to column R0, the resistance of the variable resistor element VR at that intersection will increase with the magnitude of the write pulse. If multiple write pulses are applied, the resistance will increase with the number of applications. Conversely, if a write pulse is applied from column R0 to row C0, the resistance of the variable resistor element VR at that intersection will decrease with the magnitude of the write pulse. In this way, the resistance of the variable resistor increases or decreases according to the polarity of the applied write pulse, and the resistance changes according to the applied energy. Alternatively, in other embodiments, the resistance of the variable resistor can also be varied by changing the number of write pulses applied and by changing the wave height of the write pulse applied to the variable resistor.

[0080] The row selection / signal processing unit 210 has a write function, which selects a row of the interleaved array 200, applies a write pulse to the selected row based on read data read from the selected storage cell of the storage cell array 110, or writes learning data read from the selected row to the selected storage cell of the storage cell array 110.

[0081] Figure 5 This is a schematic diagram illustrating the internal structure of the row selection / signal processing unit 210. The row selection / signal processing unit 210 includes: a NOR read unit 300, which reads data from selected memory cells in the memory cell array through an entry gate 170; a row selection unit 310, which selects rows in the interleaved array 200; a row write unit 320, which applies write pulses to the selected rows; a row read unit 330, which reads data output from the selected rows; a data selection unit 340, which selects input data from the row read unit 330 or the column read unit 420, and selects data output to the row write unit 320 or the NOR write unit 350; and a NOR write unit 350, which writes the read data output from the data selection unit 340 into selected memory cells in the memory cell array 110.

[0082] When accessing the interleaved array 200, for example, when read data read from the selected memory cell of the memory cell array 110 is written to the selected variable resistor element of the interleaved array 200, the entry gate 170 is enabled (any one of transistors Q1 to Q3 is turned on), and the selected bit line BL of the memory cell array 110 is connected to the NOR read unit 300 of the row selection / signal processing unit 210 through the selected global bit line GBL.

[0083] The NOR read unit 300 includes a sense amplifier that senses and holds the read data of the selected memory cells by selecting the global bit line GBL. For example, when memory cells Ma, Mb, Mc, and Md are selected, the entry gate 170 sequentially turns on transistors Q0, Q1, Q2, and Q3, and the NOR read unit 300 reads the 4 bits of read data stored in the four selected memory cells Ma, Mb, Mc, and Md through the bit lines BL0 to BL3.

[0084] The row selection unit 310 receives a row selection signal from the control unit 160 via the bus 230 and selects rows of the interleaved array 200 based on the row selection signal. The selected row is not limited to one row; multiple rows can be selected simultaneously.

[0085] The row write unit 320 includes a write amplifier that applies a write pulse to the row selected by the row selection unit 320 based on the read data held by the NOR read unit 300 or the read data output from the data selection unit 340. When a write pulse is applied to the row selected by the row write unit 320, the column write unit 410 of the column selection / signal processing unit 220 applies GND to the selected column. For example, if row C0 and column R0 are selected, and the read data is "0", the row write unit 320 applies a write pulse to row C0, and the column write unit 410 applies GND to column R0. Thus, a write pulse is applied to the variable resistor element VR at the intersection of row C0 and column R0, and the resistance increases with the magnitude of the write pulse. On the other hand, when the read data is "1", the row write unit 320 does not apply a write pulse, and the resistance of the variable resistor element VR does not change. Additionally, when writing to the column selected by the column write unit 410, the write sensor of the row write unit 320 applies GND to the selected row.

[0086] In one example, when the NOR read unit 300 sequentially receives 4 bits of read data from the selected global bit line GBL through the entry gate 170, the row write unit 320 applies write pulses to the selected row corresponding to the number of "0" bits in the 4-bit read data. If all 4 bits of read data are "0", the row write unit 320 applies 4 write pulses to the selected row; if 3 bits are "0", it applies 3 write pulses; if 2 bits are "0", it applies 2 write pulses; if 1 bit is "0", it applies 1 write pulse; if all 4 bits of read data are "1", the row write unit 320 does not apply any write pulses. In this way, the variable resistor element at the intersection of the selected row and the selected column stores the sum of the 4 bits of read data.

[0087] In other embodiments, the row write unit 320, in addition to changing the resistance of the variable resistor element according to the number of write pulses applied, also includes, for example, a DA converter that converts multiple bits of data output from the NOR read unit 300 or the data selection unit 340 into analog levels, and applies write pulses with a peak value of the converted analog level to the selected row. For example, if the read data is 4 bits, the DA converter generates 16 peak values ​​of write pulses and applies them to the variable resistor element. In this case, if all the read data is "0", the write pulse with the highest peak value is generated; or if all the read data is "1", a write pulse with a peak value of 0 is applied, or no write pulse is applied.

[0088] The row read unit 330 senses the read data output from the row selected by the row selection unit 310 and maintains the sensed read data. When reading the row selected by the row read unit 330, the column read unit 420 of the column selection / signal processing unit 220 applies a read voltage to the selected column. For example, when row C0 and column R0 are selected, the column read unit 420 applies a read voltage to column R0, and the row read unit 330 senses the read voltage or read current flowing through the variable resistor element at the intersection of column R0 and row C0. Additionally, when reading the column selected by the column read unit 420, the row read unit 330 applies a read voltage to the selected row.

[0089] The row read unit 330 includes an AD converter, which is used to convert analog level read voltage or read current into m-bit (m is an integer greater than or equal to 2) digital data. For example, the row read unit 330 converts read current or read voltage into 4-bit read data and decomposes the resistance of the variable resistor element into 16 levels.

[0090] The data selection unit 340, based on the selection signal from the control unit 160, inputs the read data from the row read unit 330 or the read data selected by the data selection unit 430 of the column selection / signal processing unit 220, and provides either the input read data to the row write unit 320 or the NOR write unit 350.

[0091] Figure 5 (B) illustrates an example of data selection for the input / output of the data selection unit 340. When the 2-bit selection signal is "00", the data selection unit 340 inputs the read data from the row read unit 330 to the row write unit 320, thereby writing the data read from the selected row to other selected rows. When the selection signal is "01", the data selection unit 340 outputs the read data from the row read unit 330 to the NOR write unit 350, thereby writing the data read from the selected row to the selected memory cell of the memory cell array 110. When the selection signal is "10", the data selection unit 340 outputs the read data from the column read unit 420 to the row write unit 320, thereby writing the data read from the selected column to the selected row. When the selection signal is "11", the data selection unit 340 outputs the read data from the column read unit 420 to the NOR write unit 350, thereby writing the data read from the selected column to the selected memory cell of the memory cell array 110.

[0092] The NOR write unit 350 writes the read data output from the data selection unit 340 into the selected memory cells of the memory cell array 110 through the entry gate 170. For example, when writing 4 bits of read data into the selected memory cells Ma, Mb, Mc, and Md, the entry gate 170 sequentially turns on transistors Q0 to Q3, and the NOR write unit 350 sequentially applies the write voltage corresponding to the read data to the bit lines BL0, BL1, BL2, and BL3 through the global bit line GBL0. At this time, a write voltage is applied to the word line WL1, and GND is applied to the source line SL1. The non-selected word line, non-selected bit line, and non-selected source line are in a floating state. In this way, the data stored in the selected variable resistor element, that is, the data modulated through learning, will be overwritten in the selected memory cells Ma, Mb, Mc, and Md.

[0093] The column selection / signal processing unit 220 selects a column of the interleaved array 200, reads the data of the selected column, and writes the data into the selected column.

[0094] Figure 6This is a schematic diagram illustrating the internal structure of the column selection / signal processing unit 220. The column selection / signal processing unit 220 includes: a column selection unit 400 for selecting columns of the interleaved array 200; a column writing unit 410 for applying write pulses to the selected columns; a column reading unit 420 for reading data from the selected columns; and a data selection unit 430 for outputting the read data input from the column reading unit 420 to the data selection unit 340 of the column writing unit 410 or the row selection / signal processing unit 210.

[0095] The column selection unit 400 receives a column selection signal from the control unit 160 via the bus 230, and selects columns of the interleaved array 200 based on the column selection signal. The selected column is not limited to one column, and multiple columns can be selected simultaneously.

[0096] The column write unit 410 and column read unit 420 are configured similarly to the row write unit 320 and row read unit 330 of the row selection / signal processing unit 210. The column write unit 410 applies a write pulse to the selected column based on the read data output from the data selection unit 430. When the column write unit 410 applies a write pulse to the selected column, the row write unit 320 applies GND to the selected row. For example, if column R1 is selected, row C1 is selected, and the data is "0", the column write unit 410 applies a write pulse to column R1, and the row write unit 320 applies GND to row C1. This applies a write pulse to the variable resistor element VR at the intersection of column R1 and row C1, and the resistance decreases with the magnitude of the write pulse. On the other hand, when the input data is "1", the column write unit 410 does not apply a write pulse, and the resistance of the variable resistor element VR does not change.

[0097] The column read unit 420 senses the read data output from the selected column via the column selection unit 400. When reading via the column read unit 420, the row read unit 300 applies a read voltage to the selected row. For example, when column R1 and row C1 are selected, the row read unit 300 applies a read voltage to row C1, and the column read unit 420 senses the read voltage or read current flowing through the variable resistor element at the intersection of row C1 and column R1.

[0098] The column read unit 420 includes an AD converter, which is used to convert analog level read voltage or read current into m-bit (m is an integer greater than or equal to 2) digital data. For example, the column read unit 420 converts read current or read voltage into 4-bit read data and decomposes the resistance of the variable resistor element into 16 levels.

[0099] Based on the selection signal from the control unit 160, the data selection unit 430 outputs the read data input from the column read unit 420 to the column write unit 410 or the data selection unit 340 of the row selection / signal processing unit 210.

[0100] Figure 6 (B) illustrates the input and output data of the data selection unit 430. When the 1-bit selection signal is "0", the data selection unit 430 outputs the read data input from the column read unit 420 to the column write unit 410, thereby enabling the data read from the selected column to be written to other selected columns. When the selection signal is "1", the data selection unit 430 outputs the read data input from the column read unit 420 to the NOR write unit 350, thereby enabling the data read from the selected column to be written to the selected memory cell of the memory cell array 110.

[0101] Next, the operation of the semiconductor memory device 100 in this embodiment will be described.

[0102] [Read operation]

[0103] When a read command and address are input from external terminals, the X decoder 130 selects the word line based on the column address, and the Y decoder 140 selects the bit line and source line based on the row address. The control unit 160 applies a positive voltage to the selected word line, a read voltage to the selected bit line, and GND to the selected source line according to the read command. The control unit 160 disables the entry gate 170 (turns off all transistors Q0-Q3) only during the operation of the memory cell array 110, thus separating the interleaved array 200 from the memory cell array 110.

[0104] For example, choosing Figure 4 When the memory cell Ma is activated, a positive voltage is applied to the select word line WL1, a read voltage is applied to the select bit line BL0, and GND is applied to the select source line SL1. The memory cell Ma is turned on and off according to the stored data, and the sensing amplifier of the control unit 160 senses the voltage or current of the bit line BL0.

[0105] [Write operation]

[0106] When a write command and address are input from external terminals, the X decoder 130 selects the word line based on the column address, and the Y decoder 140 selects the bit line and source line based on the row address. The non-selected bit lines are in a floating state. The control unit 160 applies a write voltage to the selected word line, applies the write voltage corresponding to the data to the selected bit line, and applies GND to the source line according to the write command.

[0107] For example, when writing the data "0" to the memory cell Ma, a write voltage is applied to the select word line WL1, a write voltage corresponding to the data "0" is applied to the select bit line BL0, and GND is applied to the select source line SL1.

[0108] [Erase Operation]

[0109] When the erase command and address are input from external terminals, the X decoder 130 selects the word line based on the column address, and the Y decoder 140 selects the bit line and source line based on the row address. The control unit 160, according to the erase command, applies GND to the selected word line, making the selected bit line float, and applies an erase voltage to the selected source line. A high voltage is applied between the gate and source of the selected memory cell, causing electrons in the selected memory cell to detach from the source side, becoming data "1". Alternatively, multiple memory cells within a segment can be erased at once.

[0110] Next, the read or write operations performed on the interleaved array 200 will be described.

[0111] [Write operations performed on an interleaved array]

[0112] The control unit 160 performs a write operation, writing data read from a selected memory cell of the memory cell array 110 into the interleaved array 200 according to the instructions and addresses input from external terminals. Writing to the interleaved array 200 can be a combination of multiple instructions or addresses. For example, after inputting the read instruction and address for the memory cell array 110, the write instruction and address for the interleaved array 200 can be input.

[0113] For example, such as Figure 7 As shown in (A), the operation of writing data read from the four memory cells Ma, Mb, Mc, and Md connected to the select word line WL1 into the variable resistor element VR0 at the intersection of row C0 and column R0 of the interleaved array 200 will be described. When writing data read from the memory cells into the interleaved array 200, the control unit 160 disables the sense amplifier on the memory cell array side and enables the NOR read unit 300 of the row selection / signal processing unit 210.

[0114] When the memory cell Ma is selected based on the read command and address from the outside, the entry gate 170 turns on the transistor Q0 (and turns off the other transistors) based on the selection signal SEL, and connects the bit line BL0 to the NOR read unit 300 through the global bit line GBL0. The NOR read unit 300 then reads the data from the memory cell Ma.

[0115] Next, the row write unit 320 receives the read data held by the NOR read unit 330 according to the write command and address from the external interleaved array. The row selection unit 310 selects row C0 based on the input row address, and the column selection unit 400 selects column R0 based on the input column address. The row write unit 320 applies a write pulse corresponding to the read data to row C0, and the column write unit 410 applies GND to column R0. For example, if the read data is "0", a write pulse is applied to row C0; if the read data is "1", no write pulse is applied to row C0.

[0116] Next, when selecting memory cell Mb based on the read command and address from the outside, the entry gate 170 turns on transistor Q1 based on the selection signal SEL, and connects bit line BL1 to NOR read unit 300 through global bit line GBL0. NOR read unit 300 reads the data of memory cell Mb. Then, based on the write command and address from the outside for the interleaved array, similarly, row write unit 320 applies a write pulse to row C0 based on the data read by NOR read unit 300. Similarly, when reading data from memory cells Mc and Md, row write unit 320 applies the corresponding write pulse to row C0. If all four bits of data in memory cells Ma, Mb, Mc, and Md are "0", four write pulses are applied to the variable resistor element VR0 at the intersection of row C0 and column R0. The sum of the four bits of data in memory cells Ma, Mb, Mc, and Md is written to the variable resistor element VR0.

[0117] The above method inputs the instruction and address each time memory cells Ma, Mb, Mc, and Md are read, but it is not limited to this; multiple memory cells on the same word line can also be burst-read with a single instruction. Alternatively, it can be configured to perform interleaved array writing with a single instruction. In this case, the NOR read unit 300 holds the 4 bits of data burst-read, and the row write unit 320 applies a write pulse based on the 4 bits of data held by the NOR read unit 300. Alternatively, the row write unit 320 can also use a DA converter to convert the 4 bits of data into a write pulse with an analog level waveform, applying a single write pulse to the variable resistor element.

[0118] Furthermore, although an embodiment is illustrated in which 4 bits of read data from memory cells Ma, Mb, Mc, and Md are written into the variable resistor element VR0, this is only one example. It is also possible to write read data from any address and any number of memory cells into any address and any number of variable resistor elements, depending on the input address.

[0119] For example, one can select eight memory cells on the same word line and write the sum of the eight bits of data in the selected memory cells to a variable resistor element. Additionally, as... Figure 7 As shown in (B), multiple rows C0 and C1 can also be selected by row selection unit 310 to simultaneously write the 4-bit data of storage units Ma, Mb, Mc, and Md into variable resistor elements VR0 and VR1.

[0120] In addition, such as Figure 8 As shown in (A), storage units Ma, Mb, Mc, and Md of different bit lines WL0, WL1, WL2, and WL3 can also be selected to write the sum of these 4 bits of data into the variable resistor element VR0. Additionally, as... Figure 8 As shown in (B), you can also select the storage cells Ma, Mb, Mc, and Md on the same word line BL0 of different bit lines WL0, WL1, WL2, and WL3, and write the sum of these 4 bits of data into the variable resistor element VR0.

[0121] Additionally, row write unit 320, such as Figure 5 As shown in (A) and (B), data read from the row reading unit 330 or the column reading unit 420, output from the data selection unit 340, can be written to the selected row.

[0122] [Write operation performed on NOR array]

[0123] The control unit 160 performs a write operation, writing data read from the interleaved array 200 to selected memory cells of the memory cell array 110 according to externally input instructions and addresses. Writing to the memory cell array 110 can be a combination of multiple instructions or addresses. For example, after inputting the read instruction and address for the interleaved array 200, the write instruction and address for the memory cell array 110 can be input.

[0124] For example, such as Figure 9 As shown in Figure (A), an embodiment is described where data read from the variable resistor VR2 connected at the intersection of row C2 and column R2 is written to four memory cells Ma, Mb, Mc, and Md connected to the select word line WL1. Furthermore, we assume that the analog data of the variable resistor VR2 is converted to 4 bits. Additionally, we assume that memory cells Ma, Mb, Mc, and Md are in an erased state (data "1").

[0125] When reading data from the interleaved array 200 is written to the memory cell array 110, the control unit 160 disables the write amplifier on the memory cell array side and enables the NOR write unit 350 of the row selection / signal processing unit 210.

[0126] When the variable resistor element VR is selected according to the read command from the outside and the address, the column read unit 420 applies a read voltage to the column R2 selected by the column selection unit 400, and the row read unit 330 receives the read voltage or read current of the row C2 selected by the row selection unit 310, converts it into 4-bit data through the AD converter, and holds it.

[0127] Next, based on the write command and address from the outside, the entry gate 170 turns on transistor Q0 (while turning off other transistors) based on the selection signal SEL, and selects bit line BL0 through the global bit line GBL0. A write voltage is applied to the select word line WL1, and GND is applied to the select source line SL1. The NOR write unit 350 writes one bit of the read data from the four bits of data held by the row read unit 330 into the memory unit Ma through the select bit line BL0.

[0128] Next, based on the write command and address from the outside, the entry gate 170 turns on transistor Q1 (while turning off other transistors) based on the selection signal SEL, and selects bit line BL1 through the global bit line GBL0. A write voltage is applied to the selection word line WL1, and GND is applied to the selection source line SL1. The NOR write unit 350 writes one bit of the 4-bit data held by the row read unit 330 into the memory cell Mb through the selection bit line BL1. Similarly, memory cells Mc and Md are written. Thus, memory cells Ma, Mb, Mc, and Md store the learning data of the variable resistor element VR2.

[0129] Additionally, the NOR write unit 350, such as Figure 9 As shown in (B), the read data read by the column read unit 420 can be written to the storage units Ma, Mb, Mc, and Md of the storage unit array 110. In this example, the storage units Ma, Mb, Mc, and Md are connected to different word lines WL0, WL1, WL2, and WL3.

[0130] In the above embodiment, 4 bits of read data are written to storage cells Ma, Mb, Mc, and Md. However, this is only one example. The number of storage cells selected can also be determined based on the decomposition capability (number of bits) of the AD converter. The AD converter converts the analog data stored in the variable resistor element into digital data. For example, if the AD converter generates 8 bits of data, then the 8 bits of data will be written to 8 storage cells respectively. Furthermore, if the storage cells can store multi-value data, then the corresponding number of storage cells is selected. Additionally, data from the variable resistor element at any position in the interleaved array 200 can be read according to the input address, and read data can also be written to any storage cell at any position according to the input address.

[0131] Figure 10 This illustration shows an example of an autoencoder utilizing a neural network-like architecture. The autoencoder comprises multiple encoder layers and multiple decoder layers, located between the input and output, and adjusts the weights or symbols of the encoders and decoders through learning. An interleaved array 200, positioned between the input and output, performs processing for each layer of the encoder and decoder. In other words, data read from storage unit 110 is processed by the i-th layer, and its output signal is input to the (i+1)-th layer. The output signal processed by the (i+1)-th layer is then input to the (i+2)-th layer, and this process is repeated sequentially.

[0132] In addition, the data learned by the interleaved array 200 is written (written back) to the storage cell array 110, and the storage cell array 110 keeps the learned data. The external controller can then use the learned data to perform various processing tasks (e.g., image processing, estimation processing, natural language processing, etc.).

[0133] According to this embodiment, by constructing a semiconductor memory device including a flash memory array and an interleaved array, it can be used as a neuromorphic chip with AI learning capabilities. Furthermore, by performing calculations on the learning data stored in the flash memory array within the interleaved array, the efficiency and speed of the calculation processing can be improved. Additionally, by configuring row selection / signal processing units on the row side and column selection / signal processing units on the column side of the interleaved array, losses caused by signal transmission can be suppressed, while matrix calculations of the interleaved array can be performed with high efficiency.

[0134] Next, a second embodiment of the present invention will be described. In the first embodiment, it was illustrated that a write pulse was applied according to the read data "0" and "1", while in the second embodiment, the row write unit and the column write unit will write the surge signal of STDP suitable for neural networks.

[0135] Figure 11 The configuration of the row writing unit in the second embodiment is illustrated. Since the column writing unit has the same configuration as the row writing unit, its description is omitted here. The row writing unit 320A of this embodiment includes: a write pulse generation unit 500 that generates write pulses based on read data; and a surge signal generation unit 510 that generates surge signals based on the write pulses.

[0136] For example, the write pulse generation unit 500 generates a write pulse with a certain pulse width when the read data from the NOR read unit 300 is "0" and outputs it to the surge signal generation unit 510. When the read data is "1", no write pulse is output.

[0137] The surge signal generation unit 510 simulates the synaptic signals generated by neurons. The surge signal generation unit 510 includes: a charging circuit 512 that charges a capacitor in response to a write pulse from the write pulse generation unit 500; a leakage circuit 514 that allows the charge in the capacitor to leak or discharge over time; an output circuit 516 that outputs a surge signal Sp when the charge in the capacitor reaches a critical value; and a reset circuit 518 that resets the charge in the capacitor when the surge signal Sp is output.

[0138] When a write pulse is applied, the charging circuit 512 charges the capacitor during the pulse width of the write pulse. The leakage circuit 514, for example, includes a resistor connected in parallel with the capacitor, through which the charge charged to the capacitor is discharged. By adjusting the resistor, the discharge rate of the charge can be changed. The charging circuit 512 causes charge to accumulate in the capacitor according to the application of the write pulse; on the other hand, the leakage circuit 514 discharges the charge charged to the capacitor. If the time between the next applied write pulse is long, the discharge of the capacitor correspondingly increases. The function of the leakage circuit 514 is analogous to the forgetting process in the human mind, and it can generate a surge signal Sp of STDP.

[0139] The output circuit 516 compares the capacitor voltage generated by the capacitor's charge with a threshold value. When the capacitor voltage exceeds the threshold value, it outputs a surge signal Sp. The surge signal Sp is applied to the row selected by the row selection unit 310.

[0140] Figure 12 This illustrates a write example of row write unit 320A. Here, we assume that 8 bits of data from rows A and B of memory cell array 110 are read and written to the select column of the interleaved array. For example... Figure 12 As shown in (A), the NOR read unit 300 reads 8 bits of data from row A and provides this read data to the row write unit 320A. The write pulse generation unit 500 generates a write pulse in response to 6 bits of "0" in the 8 bits of read data. In other words, 6 write pulses are sequentially output to the surge signal generation unit 510. The charging circuit 512 charges the capacitor in response to the 6 write pulses. When the capacitor voltage reaches the critical value at the 6th write pulse, the output circuit 516 outputs a surge signal Sp. At the same time, the reset circuit 518 discharges the capacitor charge to GND.

[0141] On the other hand, NOR read unit 300, such as Figure 12As shown in (B), when reading 8 bits of data from row B, the write pulse generation unit 500 generates a write pulse in response to 4 bits of "0" in the 8 bits of read data. The charging circuit 512 responds to 4 write pulses, charging the capacitor. However, since the capacitor voltage has not reached the critical value, the surge signal Sp is not output from the output circuit 516. Because no surge signal Sp is output, the reset circuit 518 does not reset, and the charge remains in the capacitor. Over time, the charge leaks through the leakage circuit 514. If the leaked charge is large, even if two more write pulses are applied, the capacitor voltage will not reach the critical value, and no surge signal Sp will be output.

[0142] According to this embodiment, a surge signal of STDP is generated, thus enabling the provision of a neuromorphic device that optimizes the binding strength of synapses.

[0143] In the above embodiments, a row selection / signal processing unit 210 is illustrated to perform row-side processing of the interleaved array 200, and a column selection / signal processing unit 220 is illustrated to perform column-side processing. However, the present invention is not limited to this configuration, and the reading or writing from the column side of the interleaved array 200 may be omitted, and only the reading or writing from the row side of the interleaved array 200 may be performed. In this case, the row selection / signal processing unit 210 writes data read from the storage cell array 110 from the row side to the interleaved array 200, and writes data read from the row side of the interleaved array 200 to the storage cell array 110. The column side of the interleaved array 200 selects columns based on column addresses. For example, the row selection / signal processing unit 210 repeatedly writes multiple data read from the storage cell array 110 to a selected variable resistor element of the interleaved array 200 to change the resistance of the variable resistor element (i.e., to make it learn). Then, it reads the learning data of the variable resistor element and writes the read data to the storage cell array 110.

[0144] In addition, the above embodiments illustrate the use of an interleaved array on a NOR flash memory, but the NOR type can also be replaced by an interleaved array on a NAND flash memory.

[0145] The preferred embodiments of the present invention have been described in detail, but the present invention is not limited to specific embodiments. Various modifications and alterations can be made within the scope of the spirit of the present invention as described in the claims.

Claims

1. A semiconductor memory device, characterized in that, The semiconductor memory device includes: A storage cell array, which consists of multiple non-volatile storage cells arranged in rows and columns; An interleaved array has multiple columns and multiple rows, with variable resistive elements formed at the intersections of the columns and rows; A connection device, configured between the memory cell array and the interleaved array, connects the selection bit line of the memory cell array to the interleaved array based on a selection signal; The row writing device writes at least the data read from the storage cell array to a selected row of the interleaved array; The row reading device reads data from selected rows of the interleaved array; The writing device writes at least the data read by the row reading device into the storage cell array; The column reading device reads data from selected columns of the interleaved array; as well as The column writing device writes at least the data read by the column reading device into the selected column of the interleaved array.

2. The semiconductor memory device as claimed in claim 1, characterized in that, The semiconductor memory device further includes: The row-side selection device provides the data read by the row reading device or the data read by the column reading device to the row writing device or the writing device.

3. The semiconductor memory device as claimed in claim 2, characterized in that, The semiconductor memory device further includes: The column-side selection device provides the data read by the column reading device to the column writing device or the row-side selection device.

4. The semiconductor memory device as claimed in claim 1, characterized in that, The semiconductor memory device further includes: Row selection device, selecting rows of the interleaved array based on address information; and A column selection device selects a column of the interleaved array based on the address information; The row writing device writes the row selected by the row selection device, and the row reading device reads the row selected by the row selection device. The column writing device writes the column selected by the column selection device, and the column reading device reads the column selected by the column selection device.

5. The semiconductor memory device as claimed in claim 1, characterized in that, The row writing device applies a write pulse to the row selected based on the read data.

6. The semiconductor memory device as claimed in claim 1, characterized in that, The column writing device applies a write pulse to the column selected based on the read data.

7. The semiconductor memory device as claimed in claim 4, characterized in that, The row selection device selects multiple rows, and the row writing device writes to the selected multiple rows simultaneously.

8. The semiconductor memory device as claimed in claim 4, characterized in that, The column selection device selects multiple columns, and the column writing device writes to the selected multiple columns simultaneously.

9. The semiconductor memory device as claimed in claim 1, characterized in that, The writing device includes an AD conversion device to convert analog data read from the interleaved array into m-bit digital data; The writing device writes m bits of data into m selected storage cells in the storage cell array.

10. The semiconductor memory device as claimed in claim 1, characterized in that, The writing device includes a DA converter, which converts m bits of digital data read from the storage cell array into analog data; The writing device writes the analog data into a selected row of the interleaved array.

11. The semiconductor memory device according to any one of claims 1 to 10, characterized in that, The row writing device, the row reading device, the writing device, the row-side selection device, and the row selection device are configured on the row side of the interleaved array; The column writing device, column reading device, column-side selection device, and column selection device are configured on the column side of the interleaved array. The interleaved array is stacked on the memory cell array, or the memory cell array is stacked on the interleaved array.

12. The semiconductor memory device according to any one of claims 1 to 10, characterized in that, The storage cell array is a NOR or NAND type storage cell array.

13. The semiconductor memory device according to any one of claims 1 to 10, characterized in that, The storage unit array stores data used for AI learning; The interleaved array performs matrix calculations on the AI ​​learning data read from the storage cell array and writes the calculated data into the storage cell array.

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